F2010 552 Project Description
F2010 552 Project Description
F2010 552 Project Description
WISC-F10 has a register file, a 3-bit FLAG register, and sixteen instructions. The register file comprises
sixteen 16-bit registers. Register $0 is hardwired to 0x0000. Register $15 has a special purpose. Register
$15 serves as a Return Address register for JAL instruction. The FLAG register contains three bits: Zero
(Z), Overflow (V), and Sign bit (N).
WISC-F10’s instructions can be categorized into four major classes: Arithmetic, Memory, Load Immediate
and Control.
Eight arithmetic and logical instructions belong to this category. They are ADD, SUB, AND, OR, SLL, SRL,
SRA, and RL.
The ADD, SUB, AND, and OR instructions have a three address format. The assembly level syntax for
these instructions is
Opcode rd, rs, rt
The two operands are (rs) and (rt) and the destination is register rd.
The ADD and SUB instructions respectively add and subtract the two operands in two’s-complement
representation and save the result in register rd.
The AND and OR instructions respectively perform bitwise AND, and bitwise OR operation on the two
operands and save the result in register rd.
The SLL, SRL, SRA, and RL instructions have the following assembly level syntax.
Opcode rd, rs, imm
The imm field is a 4-bit immediate operand in unsigned representation for the SLL, SRL, SRA, and RL
instructions.
SLL, SRL, SRA and RL shift (rs) by number of bits specified in the imm field and saves the result in
register rd. SRA is shift right arithmetic, SRL is shift right logical, SLL is shift left logical, and RL is rotate
left.
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ECE/CS 552 Project Description Fall 2010
There are four instructions which belong to this category: B, JAL, JR, and EXEC.
The B (Branch) instruction conditionally jumps to the address obtained by adding the 8-bit immediate
(signed) offset to the contents of the program counter. Assume that the value of the program counter
used in this addition is the address of the next instruction (i.e., address of Branch instruction + 1).
The eight possible conditions are Equal (EQ), Not Equal (NE), Greater Than (GT), Less Than (LT), Greater
or Equal (GEQ), Less or Equal, Overflow, and True. Many of these conditions are determined based on
the 3-bit flag N, V, and Z which should be set by an ADD, SUB, AND or OR instruction executed prior to
the conditional branch instruction.
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ECE/CS 552 Project Description Fall 2010
The True condition corresponds to an unconditional branch. The status of the condition is obtained from
the FLAG register (definition of each flag is in section 3.3). The assembly level syntax for this instruction
is
B cond, offset
The machine level encoding for this instruction is
Opcode 0ccc iiii iiii
where ccc specifies the condition as in Table 1 and iiiiiiii represents the 8-bit signed offset in twos-
complement representation.
The JAL (jump and link) instruction saves the contents of the program counter (address of the Call
instruction + 1) to the Return Address register ($15) and jumps to the procedure whose starting address is
partly specified in the instruction. The assembly level syntax for this instruction is
JAL target
The machine level encoding for this instruction is
Opcode gggg gggg gggg
where gggg gggg gggg specifies a 12-bit signed immediate offset that is added to the current PC (which is
PC+1 relative to the branch instruction PC) to form the target jump address.
The JR (jump register) instruction jumps to the address specified by (rt). When rt == $15, JR is used as
return-from-procedure-call instruction. The assembly level syntax for this instruction is
JR rt
The machine level encoding for this instruction is (tttt encodes the name of register rt)
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ECE/CS 552 Project Description Fall 2010
2. Memory System
The address space of the WISC-F10 processor is 16 bits. Each memory location is 16 bits in size (word-
addressable), so the total memory capacity is 216x16 bits = 220 bits = 1 Mbit = 128 Kbytes.
For the first stage of the project, the processor will have separate instruction and data memories. The
instruction memory has a 16-bit address input and a 16-bit data output with no control signals, while the
data memory has a 16-bit address input, a 16-bit data input, a 16-bit data output, and an active-low write
signal for specifying a write operation. If the write signal is low, the memory will write the data input
bits to the address specified by the address. The read operation is always active for both instruction and
data memories and will return data from the location specified by the address. The access time for both
memories is one cycle.
Verilog modules will be provided for both memories.
For the second stage of the project, the instruction and data memories will be replaced with cache
memories backed up by a slower main memory. Details of the timing and information of the cache and
memory system will be announced later this semester.
3. Implementation
3.1 Pipelining
Your design must use a five stage pipeline (IF, ID, EX, MEM, WB) similar to that in the text. The design
should follow the Quartus II design problems presented in the homework assignments during the course
of the semester. You must implement hazard detection so that your pipeline correctly handles all data
and control dependences.
WISC-F09 has a Reset input. Instructions are executed when Reset input is low. If the Reset input goes
high for one clock cycle, the contents of the program counter and register file are cleared.
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ECE/CS 552 Project Description Fall 2010
3.3 Flags
Flag bits are stored in the FLAG register and are used in conditional jump. There are three bits in the
FLAG register: Zero (Z), Overflow (V), and Sign bit (N). Only four instructions can change the FLAG
register: ADD, SUB, AND, OR.
The Z flag is set if and only if the output of the operation is zero.
The V flag is set by the ADD and SUB instructions if and only if the operation results in an overflow.
Overflow must be set based on treating the arithmetic values as 16-bit signed integers. The AND and OR
instructions always clear the V flag.
The N flag is set if and only if the result of the ADD and SUB instruction is negative. Note that N flag
should be implemented as (sign-bit XOR overflow). The AND and OR instructions always clear the N
flag.
Other Instructions, including shift/rotate instructions, load/store instructions and control instructions,
do not change the contents of the FLAG register.
Make sure you discuss any extra features with the TA and instructor before proceeding.
4. Submission Requirements
First Stage Project Report
The project should be done in a group of three. The first stage project report should include the following
parts:
1) A brief description of or an introduction to your project. Report its special features, any particular
effort you have made to optimize the design, and any major problems you encountered in
implementing the design.
2) A statement indicating whether or not your design meets all the requirements specified in this
document.
3) Include schematic printouts or Verilog listings of major blocks.
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ECE/CS 552 Project Description Fall 2010
4) The simulation results for test programs (will be provided later) in “list” form.
5) A detailed description of the methodology you used to test the correctness of your design. Include a
well commented copy of the key programs you used to create test inputs and/or verify the outputs
from the various blocks. A significant part of your project grade will be based on the testing
methodology you used.
6) If your project implements extra features (forwarding, etc.) to further enhance performance, provide
a short paragraph highlighting the extra features. Also, provide an estimate of performance
enhancement due to these extra features for the testing program. Bonus point will not be considered
if the design is incorrect.
Note that there will be additional documentation requirements for the stage 2 memory system design
which will be specified later.
Project Demonstration
Each group will be asked to demonstrate their project on Sunday December 12, 2010. All team members
must be present at the demo and must be prepared to answer detailed questions about the design. The
demonstration will be used to primarily evaluate the following.
• Verification methodology: Designs tested with well thought out systematic procedures will get
higher scores. You will be asked to show the test programs you have used to create test inputs
and/or verify the outputs from the various blocks.
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