MICRO PROGRAMMED CONTROL

Topics to cover
• Control memory
• Address sequencing
• Micro program example
• Design of control unit
Control Memory
• Control Unit
Function: To initiate sequences of micro operations
Control signal specifies micro operations
Two major types of control unit:

1) Hardware control:
 When these control signals are generated by hardware, the control unit is hardwired
The control logic is implemented with gates, flip flops, decoder, multiplexer and other
digital circuits.
Fast operation
Wiring change is difficult.
2) Micro programmed control:
When these control signals originate in data stored in a special unit and constitute a program on the
small scale, the control unit is micro programmed .
 The control memory is programmed to initiate the require sequence of micro operation for an
instruction.
 Update can be easy
 Slow micro operation.

 Control Word
 The control function specifying a microoperation is a binary variable whose active state could be
either 1 or 0.
 In the variable ’s active state, the microoperation is executed.
 The string of control variables which control the sequence of microoperations is called a control
word.
 Micro instruction
 The micro operations specified in a control word is called a microinstruction.
 It specifies one or more micro operation for the system.

 Micro Program
It is sequence of micro instruction just like as program is a sequence of program. It is of two type
which are as follows:
Dynamic microprogramming(RAM)
Ram can be used for writing
Static micro programming(ROM)
Control word in rom are made permanent during hardware production.
Micro programmed control organization
• In a micro programmed processor, the control unit consists of:

–Control address register – contains the address of the next

microinstruction to be executed.

–Control data register – contains the microinstruction to be

executed. Allows the execution of the micro instruction specified by
the control word simultaneously with the generation of the next
microinstruction.

–The sequencer – determines the next address from within control

memory

–Control memory – A memory that is part of a control unit is referred as

control memory.
–where microinstructions are stored.
Sequencer:
• The next address generator
• It determines the address sequence that is read from control
memory.
Functions: incrementing the control address register by one,
 loading into control address register an address from control
memory,
Transferring an external address,
loading an initial address to start the control operations.
Address sequencing
• Microinstructions are usually stored in groups where each group specifies a
routine, where each routine specifies how to carry out an instruction.
• Each routine must be able to branch to the next routine in the sequence.
• The hardware that controls the address sequencing of the control memory
must be capable of sequencing the microinstructions within a routine and be
able to branch from one routine to another
• Steps the control must undergo during the execution of a
single computer Instruction:
o Load an initial address into the CAR when power is turned on in the computer. This
address is usually the address of the first microinstruction that activates the instruction
fetch routine – IR holds instruction
o The control memory then goes through the routine to determine the effective address of
the operand – AR holds operand address
o The next step is to generate the micro operations that execute the instruction by
considering the opcode and applying a mapping
o After execution, control must return to the fetch routine by executing an unconditional
branch
STEP 1:
 An initial address is loaded into the control address register
when power is turned on in the computer.
 This address is usually the address of the first
microinstruction that activates the instruction fetch routine.
 The fetch routine may be sequenced by incrementing the
control address register through the rest of its
microinstructions.
 At the end of the fetch routine, the instruction is in the
instruction register of the computer.
STEP 2:
• The control memory next must go through the routine that
determines the effective address of the operand.
• The effective address computation routine in control memory
can be reached through a branch microinstruction, which is
conditioned on the status of the mode bits of the instruction.
• When the effective address computation routine is completed,
the address of the operand is available in the memory address
register.
STEP 3:
• The next step is to generate the microoperations that execute
the instruction fetched from memory.
• The transformation from the instruction code bits to an
address in control memory where the routine is located is
referred to as a mapping process.
• A mapping procedure is a rule that transforms the instruction
code into a control memory address.
STEP 4:
• Once the required routine is reached, the microinstructions that
execute the instruction may be sequenced by incrementing the
control address register.
• Micro-programs that employ subroutines will require an external
register for storing the return address.
• When the execution of the instruction is completed, control must
return to the fetch routine.
• This is accomplished by executing an unconditional branch
microinstruction to the first address of the fetch routine.
• Addressing sequencing capabilities of control memory include:
–Incrementing the CAR
–Unconditional and conditional branching (depending on status bit).
–Mapping instruction bits into control memory addresses
–Handling subroutine calls and returns.
Mapping Instruction
• The mapping process converts the 4-bit opcode to a 7-bit address for
control memory
• This mapping consists of placing a 0 in the most significant bit of the
address, transferring the four operation code bits, and clearing the two
least significant bits of the control address register.
MACHINE INSTRUCTION FORMAT
Machine instruction format
15 14 11 10 0
I Opcode Address

Sample machine instructions

Symbol OP-code Description
EA is the effective address
ADD 0000 AC  AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC  EA)
STORE 0010 M[EA]  AC
EXCHANGE 0011 AC  M[EA], M[EA]  AC

Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD

F1, F2, F3: Microoperation fields

CD: Condition for branching
BR: Branch field
AD: Address field
MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3

F1 Microoperation Symbol
000 None NOP F2 Microoperation Symbol
001 AC  AC + DR ADD 000 None NOP
010 AC  0 CLRAC 001 AC  AC - DR SUB
011 AC  AC + 1 INCAC 010 AC  AC  DR OR
100 AC  DR DRTAC 011 AC  AC  DR AND
101 AR  DR(0-10) DRTAR 100 DR  M[AR] READ
110 AR  PC PCTAR 101 DR  AC ACTDR
111 M[AR]  DR WRITE 110 DR  DR + 1 INCDR
111 DR(0-10)  PC PCTDR

F3 Microoperation Symbol
000 None NOP
001 AC  AC  DR XOR
010 AC  AC’ COM
011 AC  shl AC SHL
100 AC  shr AC SHR
101 PC  PC + 1 INCPC
110 PC  AR ARTPC
111 Reserved
MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR

CD Condition Symbol Comments

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0
SYMBOLIC MICROINSTRUCTIONS
 Symbols are used in microinstructions as in assembly language
 A symbolic microprogram can be translated into its binary equivalent by a
microprogram assembler.
Sample Format
five fields:label; micro-ops; CD; BR; AD
1) Label: may be empty or may specify a symbolic address terminated with a colon
2) Micro-ops: consists of one, two, or three symbols separated by commas
3) CD: one of {U, I, S, Z}, where U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC
4) BR: one of {JMP, CALL, RET, MAP}
5) AD: one of {Symbolic address, NEXT, empty}
SYMBOLIC MICROPROGRAM - FETCH ROUTINE

During FETCH, Read an instruction from memory

and decode the instruction and update PC

Sequence of microoperations in the fetch cycle:

AR  PC
DR  M[AR], PC  PC + 1
AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0

Symbolic microprogram for the fetch cycle:

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP

Binary equivalents translated by an assembler

Binary
address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000
Design Of Control Unit
 The bits of microinstruction are usually divided into fields, with each
field defining a distinct, separate function.
 The various field encountered in instruction format provide control
bits to initiate microoperation in the system, special bit to specify the
way the next address is to be evaluated, an address field for branching.
 The nine bits of the micro operation fields are divided into three
subfield of three bits each.
 The control memory out put of each sub filed must be decoded to
provide the distinct micro operation.
Design of control unit
• When f1=101(5), the next clock pulse transition transfer the
content of DR(0-10) to AR.
• When f1=110(6),there is transfer from PC to AR.
• As shown in fig output 5 and 6 of decoder F1 are connected to the
load input of AR so that when either one of the output is active,
information from the mux is transferred to AR.
• The mux selects the information from DR when output 5 is active
and from PC when output 5 is inactive.
• The transfer into AR occurs with a clock pulse transition only
when output 5 or output 6 of the decoder are active.
• The other output of the decoders that initiate transfer between two
register must be connected in a similar fashion.
Micro program sequencer
• The basic component of micro programmed control unit are
control memory and the circuits that selects the next address.
• The address selection part is called a micro program
sequencer.
• The purpose of micro programmed sequencer is to present an
address to control memory so that a micro instruction may be
read and executed.
• There are two mux in the circuit.
• The first mux selects the address from one of four sources and
routes it into a control address register(CAR).
• The second mux tests the value of selected status bit and result of
test is applied to an input logic circuit.
• The output from CAR provides the address for control memory.
• The content of CAR is incremented and applied to one of the mux
input and to the subroutine register SBR.
• The other three input to multiplexer 1 come from adress field of
present microinstruction, from the output of SBR, from an external
source that maps the instruction.
• CD: it selects one of the status bits in second mux.
• If selected bit is equal to 1,the T variable is equal to 1, otherwise 0.
• The T value together with BR goes into logic unit which determines
the types of operation that are available in the unit.
• The logic circuit has three inputs, I0, I1 and T. Also three output
S0,S1 and L.
• Variable S0 and S1 selects one of the source address for CAR.
• Variable L enables the load input in SBR.
• The binary values of the two selection variables determine the path
in the mux.