SP5655

2·7GHz Bidirectional I2C Bus Controlled Synthesiser

Advance Information
Supersedes July 1996 version, DS3743-4.3 DS3743 - 5.0 June 1998

The SP5655 is a single chip frequency synthesiser designed

for TV tuning systems. Control data is entered in the standard
I2C BUS format. The device contains 2 addressable current
limited outputs and 4 addressable bidirectional open-collector CHARGE PUMP 1 16 DRIVE OUTPUT
ports, one of which is a 3-bit ADC. The information on these CRYSTAL Q1 2 15 VEE
ports can be read via the I2C BUS. the device has one fixed CRYSTAL Q2 3 14 RF INPUT
I 2 C BUS address and 3 programmable addresses,
SDA 4 13 RF INPUT
programmed by applying a specific input voltage to one of the SP5655
current limited outputs. This enables two or more synthesisers SCL 5 12 VCC
to be used in a system. † I/O PORT P7 6 11 P0 OUTPUT PORT
* I/O PORT P6 7 10 P3 OUTPUT PORT/
ADD SELECT
† I/O PORT P5 8 9 I/O PORT P4 †
FEATURES
MP16
■ Complete 2·7GHz Single Chip System
† = Logic level I/O port
■ High Sensitivity RF Inputs * = 3-bit ADC input
■ Programmable via I2C BUS
■ Low Power Consumption (5V, 30mA)
Fig. 1 Pin connections – top view
■ Low Radiation
■ Phase Lock Detector
■ Varactor Drive Amp Disable
■ 6 Controllable Outputs, 4 Bidirectional
APPLICATIONS
■ 5-Level ADC
■ Satellite TV
■ Variable I2C BUS Address for Multi-tuner Applications
■ High IF Cable Tuning Systems
■ ESD Protection: 4kV, Mil-Std-883C, Method 3015 (1)
■ Switchable 4512/1024 Reference Divider THERMAL DATA
uJC = 41°C/W
■ Pin and Function Compatible with SP5055S (2)
uJA = 111°C/W
(1) Normal ESD handling precautions should be observed.
ORDERING INFORMATION
(2) The SP5055S does not have a switchable reference SP5655 KG/MPAS (Tubes)
division ratio. SP5655S KG/MPAD (Tape and reel)
SP5655

ELECTRICAL CHARACTERISTICS
TAMB = 220°C to 180°C, VCC = 14·5V to 15·5V, reference frequency = 4MHz.
These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage ranges unless otherwise stated.

Value
Characteristic Pin Units Conditions
Min. Typ. Max.

Supply current 12 30 40 mA VCC = 4·5V to 5·5V (note 1)

Prescaler input voltage 13,14 50 300 mVrms 120MHz to 2·7GHz sinewave,
see Fig. 5
Prescaler input impedance 13,14 50 Ω
Prescaler input capacitance 13, 14 2 pF
SDA, SCL
Input high voltage 4,5 3 5·5 V
Input low voltage 4,5 0 1·5 V
Input high current 4,5 10 µA Input voltage = VCC
Input low current 4,5 210 µA Input voltage = 0V
Leakage current 4,5 10 µA When VCC = 0V
SDA
Output voltage 4 0·4 V Sink current = 3mA
Charge pump current low 1 650 µA Byte 4, bit 2 = 0, pin 1 = 2V
Charge pump current high 1 6170 µA Byte 4, bit 2 = 1, pin 1 = 2V
Charge pump output leakage current 1 65 nA Byte 4, bit 4 = 1, pin 1 = 2V
Charge pump drive output current 16 500 µA V pin 16 = 0·7V
Charge pump amplifier gain 6400
Recommended crystal series resistance 10 200 Ω Parallel resonant crystal (note 2)
Crystal oscillator drive level 2 80 mV p-p
Crystal oscillator negative resistance 2 750 1000 Ω
External reference input frequency 2 2 8 MHz AC coupled sinewave
External reference input amplitude 2 70 200 mVrms AC coupled sinewave
Output Ports
P0, P3 sink current 11, 10 0·7 1 1·5 mA VOUT = 12V
P0, P3 leakage current 11, 10 10 µA VOUT = 13·2V
P4-P7 sink current 9-6 10 mA VOUT = 0·7V
P4-P7 leakage current 9-6 10 µA VOUT = 13·2V
Input Ports
P3 input current high 10 110 µA V pin 10 = VCC
P3 input current low 10 210 µA V pin 10 = 0V
P4, P5, P7 input voltage low 9,8,6 0·8 V
P4, P5, P7 input voltage high 9,8,6 2·7 V
P6 input current high 7 110 µA See Table 3 for ADC levels
P6 input current low 7 210 µA

NOTES
1. Maximum power consumption is 220mW with VCC = 5·5V and all ports off.
2. Resistance specified is maximum under all conditions.

2
 SP5655

ABSOLUTE MAXIMUM RATINGS

All voltages are referred to VEE and pin 3 at 0V
Value
Parameter Pin Units Conditions
Min. Max.

Supply voltage 12 20·3 7 V

RF input voltage 13,14 2·5 V p-p
Port voltage 6-11 20·3 14 V Port in off state
6-9 20·3 6 V Port in on state
10, 11 20·3 14 V Port in on state
Total port output current 6-9 50 mA
Address select voltage 10 20·3 VCC10·3 V
RF input DC offset 13-14 20·3 VCC10·3 V
Charge pump DC offset 1 20·3 VCC10·3 V
Drive output DC offset 16 20·3 VCC10·3 V
Crystal oscillator DC offset 2 20·3 VCC10·3 V
SDA, SCL input voltage 4,5 20·3 6 V
Storage temperature 255 1150 °C
Junction temperature 1150 °C

PREAMP OSC
13 2
15-BIT FPD PHASE FCOMP Q1
PRESCALER DIVIDER
RF IN PROGRAMMABLE COMP CRYSTAL
14 416 DIVIDER 4512/1024 3
F Q2
LOCK
DET 1
CHARGE PUMP
POWER 15-BIT LATCH
ON DET DIVIDE RATIO
DN
POR CHARGE 16 DRIVE/
PUMP VARICAP OUT
UP
5 FL
SCL
I 2C BUS CONTROL DATA
4 TRANSCEIVER LATCHES
SDA CP TO OS
AND
CONTROL LOGIC

LEVEL 6-BIT LATCH 4

ADDRESS 3-BIT 3 TTL PORT INFO
SELECT ADC COMP
2 4

PORT OUTPUT DRIVERS VCC

15
VEE

11 10 9 8 7 6

P0 P3 P4 P5 P6 P7

Fig. 2 Block diagram

3
SP5655

FUNCTIONAL DESCRIPTION
The SP5655 is programmed from an I2C Bus. Data and from 512 to 1024, and is controlled by bit 7 of byte 4 (TS0); a
Clock are fed in on the SDA and SCL lines respectively, as logic 1 to 512, a logic 0 for 1024. The SP5655 differs from the
defined by the I2C Bus format. The synthesiser can either SP5055 in this respect, only 512 being available on the
accept new data (write mode) or send data (read mode). The SP5055. Note that the comparison frequency is 7·8125kHz
LSB of the address byte (R/W) sets the device into write mode when a 4MHz reference is used, and divide by 512 is selected.
if it is low and read mode if it is high. The Tables in Fig. 3 Bit 2 of byte 4 of the programming data (CP) controls the
illustrate the format of the data. The device can be pro- current in the charge pump circuit, a logic 1 for ±170µA and a
grammed to respond to several addresses, which enables the logic 0 for ±50µA, allowing compensation for the variable
use of more than one synthesiser in an I2C Bus system. tuning slope of the tuner and also to enable fast channel
Table 4 shows how the address is selected by applying a changes over the full band. When the device is frequency
voltage to P3. locked, the charge pump current is internally set to ±50µA
When the device receives a correct address byte, it pulls regardless of CP.
the SDA line low during the acknowledge period, and during Bit 4 of byte 4 (T0) disables the charge pump when it is set
following acknowledge periods after further data bytes are to a logic 1.
programmed. When the device is programmed into the read Bit 8 of byte 4 (OS) switches the charge pump drive
mode, the controller accepting the data must pull the SDA line amplifier’s output off when it is set to a logic 1.
low during all status byte acknowledge periods to read an- Bit 3 of byte 4 (T1) enables various test modes when set
other status byte. If the controller fails to pull the SDA line low high. These modes are selected by bits 5, 6 and 7 of byte 4
during this period, the device generates an internal STOP (TS2, and TS1, TS0) as detailed in Table 5. When T1 is set
condition, which inhibits further reading. low, TS2 and TS1 are assigned a ‘don’t care’ condition, and
TS0 selects the reference divider ratio as previously de-
WRITE Mode (Frequency Synthesis) scribed.
When the device is in write mode bytes 2 and 3 select the Byte 5 programs the output ports P0 and P3 to P7; a logic
synthesised frequency, while bytes 4 and 5 control the output 0 for a high impedance output and a logic 1 for low impedance
port states, charge pump, reference divider ratio and various (on).
test modes.
Once the correct address is received and acknowledged, READ Mode
the first bit of the next byte determines whether that byte is When the device is in read mode the status byte read from
interpreted as byte 2 or 4; a logic 0 for frequency information the device on the SDA line takes the form shown in Table 2.
and a logic 1 for control and output port information. When Bit 1 (POR) is the power-on reset indicator and is set to a
byte 2 is received the device always expects byte 3 next. logic 1 if the VCC supply to the device has dropped below 3V
Similarly, when byte 4 is received the device expects byte 5 (at 25˚C), for example, when the device is initially turned on.
next. Additional data bytes can be entered without the need The POR is reset to 0 when the read sequence is terminated
to readdress the device until an I2C stop condition is recog- by a stop command. When POR is set high (at low VCC), the
nised. This allows a smooth frequency sweep for fine tuning programmed information is lost and the output ports are all set
or AFC purposes. to high impedance.
If the transmission of data is stopped mid-byte (for exam- Bit 2 (FL) indicates whether the device is phase locked, a
ple, by another device on the bus) then the previously pro- logic 1 is present if the device is locked, and a logic 0 if the
grammed byte is maintained. device is unlocked.
Frequency data from bytes 2 and 3 are stored in a 15-bit register Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports
and used to control the division ratio of the 15-bit programmable P7, P5 and P4 respectively. A logic 0 indicates a low level and
divider. This is preceded by a divide-by-16 prescaler and amplifier to a logic 1 a high level. If the ports are to be used as inputs they
give excellent sensitivity at the local oscillator input, see Fig. 5. The should be programmed to a high impedance state (logic 1).
input impedance is shown in Fig. 7. These inputs will then respond to data complying with TTL
The programmed frequency can be calculated by multiply- type voltage levels.
ing the programmed division ratio by 16 times the comparison Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of
frequency FCOMP. When frequency data is entered, the phase the 5-level ADC. The ADC can be used to feed AFC informa-
comparator, via a charge pump and varicap drive amplifier, tion to the microprocessor from the IF section of the receiver,
adjusts the local oscillator control voltage until the output of as illustrated in the typical application circuit.
the programmable divider is frequency and phased locked to
the comparison frequency. APPLICATION
The reference frequency may be generated by an external A typical application is shown in Fig. 4. All input/output
source capacitively coupled into pin 2, or provided by an on- interface circuits are shown in Fig. 6. The SP5655 is function and
chip crystal controlled oscillator. The comparison frequency pin equivalent to the SP5055 device apart from the switchable
FCOMP is derived from the reference frequency via the refer- reference divider, and has much lower power dissipation, im-
ence divider. The reference divider division ratio is switchable proved RF sensitivity and better ESD performance.

4
 SP5655

MSB LSB
Address 1 1 0 0 0 MA1 MA0 0 A Byte 1
14 13 12 11 10 9 8
Programmable divider 0 2 2 2 2 2 2 2 A Byte 2
Programmable divider 2 7
26 25 24 23 22 21 2 0
A Byte 3
Charge pump and test bits 1 CP T1 T0 TS2 TS1 TS0 OS A Byte 4
I/O port control bits P7 P6 P5 P4 P3 X X P0 A Byte 5
Table 1 Write data format (MSB transmitted first)

Address 1 1 0 0 0 MA1 MA0 1 A Byte 1

Status byte POR FL I2 I1 I0 A2 A1 A0 A Byte 2
Table 2 Read data format

A2 A1 A0 Voltage input to P6
1 0 0 0·6VCC to 13·2V MA1 MA0 Address select input voltage
0 1 1 0·45VCC to 0·6VCC 0 0 0V to 0·2VCC
0 1 0 0·3VCC to 0·45VCC 0 1 Always valid
0 0 1 0·15VCC to 0·3VCC 1 0 0·3VCC to 0·7VCC
0 0 0 0V to 0·15VCC 1 1 0·8VCC to 13·2V
Table 3 ADC levels Table 4 Address selection

T1 TS2 TS1 TS0 Operation mode description

0 X X 0 Normal operation, test modes disabled, reference divider ratio = 1024
0 X X 1 Normal operation, test modes disabled, reference divider ratio = 512
1 0 0 X Charge pump source (down). Status bit FL set to 0
1 0 1 X Charge pump sink (up). Status bit FL set to 1
1 1 0 0 Ports P4, P5, P6, P7set to state X
1 1 0 1 Port P7 = FPD/2; P4, P5, P6 set to state X
1 1 1 X Port P7 = FPD; P6 = FCOMP; P4, P5 set to state X

Table 5 Operation modes

NOTES
X = don’t care
For further details of test modes, see Table 6

A : Acknowledge bit
MA1, MA0 : Variable address bits (see Table 4)
CP : Charge Pump current select
T1 : Test mode selection
T0 : Charge pump disable
TS2, TS1, TS0 : Operation mode control bits (see Table 5)
OS : Varactor drive Output disable Switch
P7, P6, P5, P4, P3, P0 : Control output port states
POR : Power On Reset indicator
FL : Phase lock detect flag
I2, I1, I0 : Digital information from ports P7, P5 and P4 respectively
A2, A1, A0 : 5-level ADC data from P6 (see Table 3)
X : Don’t care

Fig. 3 Data formats

5
SP5655

112V 112V

IF SIGNAL
IF SECTION
AFC OUT

P4
9 8 P5
P6
P3 10 7
15V
SATELLITE P0 11 6 P7
TUNER 15V SCL
12 5
1n CONTROL
0·1µ SP5655 I 2C BUS SDA
OSCILLATOR 13 4 MICRO
OUTPUT
14 3 4MHz
1n CRYSTAL
15 2
130V
18p
16 1

22k 39n

47k 10k VT 180n

VARICAP
INPUT
22k
10n

BCW31

Fig. 4 Typical application

300
VIN (mV RMS INTO 50 Ω )

150

OPERATING
WINDOW

100

50

120 1000 2000 2700 3000 3500

FREQUENCY (MHz)

Fig. 5 Typical input sensitivity

6
 SP5655

VREF VCC

CHARGE
400 400 PUMP

RF INPUTS
150
DRIVE
OUTPUT
OS
(O/P DISABLE)

RF input Loop amplifier

VCC
VCC

67k

3k
SCL/SDA

CRYSTAL Q1
* ACK

CRYSTAL Q2
* ON SDA ONLY
Reference oscillator SCL and SDA inputs

VCC VCC

PORT P3
ONLY

3k
PORT
3k
PORT 12k

Ports P7-P4 Ports P0-P3

Fig. 6 SP5655 input/output interface circuits

7
SP5655

j1

j 0.5 j2

j 0.2
j5

0 0.2 0.5 1 2 5
2·6GHz

2j 5
2j 0.2

2j 2
S11:ZO = 50Ω 2j 0.5
NORMALISED TO 50Ω FREQUENCY MARKER STEP = 500MHz
2j 1

Fig. 7 Typical input impedance,

APPLICATION NOTES
An application note, AN168, is available for designing with The board can be used for the following purposes:
synthesisers such as the SP5655. It covers aspects such as loop (A) Measuring RF sensitivity perfomance
filter design, decoupling and I2C bus radiation problems. (B) Indicating port function
The application note is published in the Mitel Semiconductor (C) Synthesising a voltage controlled oscillator
Media IC Handbook. A generic test/demonstration board has (D)Testing external reference sources
been produced, which can be used for the SP5655. A circuit The programming codes relevant to these tests are given in
diagram and layout for the board are shown in Figs. 8 and 9. Table 6.

EXTERNAL 15V 130V 112V

REFERENCE P2
15V SK2
C7 C8 C9
100n 100n 100n
R11 3k C3 47n
S1 C6 10n C2 R8 22k
(NOT FITTED, 220n
SEE NOTE)
S2 R9 10k R10 47k P3
R7 22k VAR

R12 1k X1 C1 TR1 C14 10n GND

1 16
4MHz 18p 2N3904
2 15
C5 1n SK1
TP1 3 14 RFINPUT
C4 1n 112V
DATA/SDA 4 13 15V R14 22k
C12 100p SP5655
5 12
C10 1n R13 12k
TR2
6 11 2N3906
CLOCK/SCL
C13 100p 7 10

8 9

ENABLE/ADDRESS SEL
P1
P4
NOTE
R1 4·7k

R2 4·7k

R3 4·7k

R4 4·7k

R5 4·7k

R6 4·7k

To use an external reference,

capacitor C6 must be fitted
and capacitor C1 removed
from the board. D1 D2 D3 D4 D5 D6 112V
PIN NO. 6 7 8 9 10 11
C11
1n

Fig. 8 Test board circuit

8
 SP5655

TP1 = PIN 3 DC BIAS

Top view (ground plane)

Underside (surface mounted components side)

NOTES
1. CIRCUIT SCHEMATIC IS SHOWN IN FIG. 8
2. ALL SUFACE MOUNT COMPONENTS ARE
MOUNTED ON UNDERSIDE OF BOARD

Fig. 9 Test board layout

9
SP5655

TEST MODES
As explained in the functional description, The SP5655 can NOTE:
be programmed into a numb er of test modes. These are invoked When looking at FPD or FCOMP signals from ports P7 and P6. byte
by programming Hex codes into byte 4, those most commonly should be sent twice, first to set the desired reference division
used being shown in Table 6. ratio then to switch on the chosen test mode.
Other codes will also apply due to don’t care conditions, which The pulses can then be measured by simply connecting an
are assumed to be 1 in the Table. oscilloscope or counter to the relevant output pin on the test board.

Hex code (byte 4)

Operation mode description
CP high mode CP low mode
Normal operation, reference divider ratio = 1024 CC 8C
Normal operation, reference divider ratio = 512 CE 8E
Charge pump source (down), FL set to 0 E2 A2
Charge pump sink (up), FL set to 1 E6 A6
Port P7 = FPD/2 EA AA
Port P7 = FPD, P6 = FCOMP EE AE
Charge pump disable, reference divider ratio = 512 DE 9E
Varactor line disable, reference divider ratio = 512 CF 8F
Charge pump and varactor line disable, reference divider ratio = 512 DF 9F

Table 5 Operation modes

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