Iot Based Irrigation System

INDEX
ABSTRACT
CHAPTER1. INTRODUCTION
1.1 Introduction
1.2 Block Diagram
CHAPTER2. DESCRIPTION OF HARDWARE COMPONENTS
2.1 LPC2103
2.1.1 Introduction
2.1.2 Features
2.1.3 Applications
2.1.4 Architectural Overview
2.1.5 Block Diagram
2.1.6 Pin Description Of LPC2103
2.1.7 GPIO
2.2 POWER SUPPLY

2.2.1 Introduction
2.2.2 Transformer
2.2.3 Rectifier
2.2.4 Regulator
2.3 LCD
2.4 SOIL SENSOR
2.5 RELAY
2.6 MOTOR
2.7 ESP8266
CHAPTER3. CIRCUITS AND THEIR OPERATION

CHAPTER4. SOFTWARE DEVELOPMENT
4.1 Introduction
4.1 Tools used
4.1 C51 Compiler & A51 macro assembler
4.1 Start µ vision
CHAPTER 5. SOURCE CODE

5.1 Source code
IOT BASED IRRIGATION SYSTEM
ABSTRACT
In the field of agriculture, use of proper method of irrigation is important because the main
reason is the lack of rains & scarcity of land reservoir water. The continuous extraction of water from
earth is reducing the water level due to which lot of land is coming slowly in the zones of un-irrigated
land. Another very important reason of this is due to unplanned use of water due to which a significant
amount of water goes waste. For this purpose; we use this automatic plant irrigation system. The
system derives power from solar energy through photo-voltaic cells. Hence, dependency on erratic
commercial power is not required.
In this project we use solar energy which is used to operate the irrigation pump. The circuit
comprises of sensor parts built using op-amp IC. Op-amp’s are configured here as a comparator. Two
stiff copper wires are inserted in the soil to sense whether the soil is wet or dry. A microcontroller is
used to control the whole system by monitoring the sensors and when sensors sense dry condition of
soil, then the microcontroller will send command to relay driver IC the contacts of which are used to
switch on the motor and it will switch off the motor when the soil is in wet condition. The
microcontroller does the above job as it receives the signal from the sensors through the output of the
comparator, and these signals operate under the control of software which is stored in ROM of the
microcontroller. The condition of the pump i.e., ON/OFF is displayed on a 16X2 LCD which is
interfaced to the microcontroller. Further the project can be enhanced by interfacing it with a GSM
modem to gain control over the switching operation of the motor.
CHAPTER1. INTRODUCTION
1.1 INTRODUCTION
1.1 .1 EMBEDDED SYSTEMS

Embedded systems are designed to do some specific task, rather than be a general-purpose
computer for multiple tasks. Some also have real time performance constraints that must be met, for
reason such as safety and usability; others may have low or no performance requirements, allowing
the system hardware to be simplified to reduce costs.
An embedded system is not always a separate block - very often it is physically built-in to
the device it is controlling. The software written for embedded systems is often called firmware, and is
stored in read-only memory or flash convector chips rather than a disk drive. It often runs with limited
computer hardware resources: small or no keyboard, screen, and little memory.
Wireless communication has become an important feature for commercial products and a
popular research topic within the last ten years. There are now more mobile phone subscriptions than
wired-line subscriptions. Lately, one area of commercial interest has been low-cost, low-power, and
short-distance wireless communication used for \personal wireless networks." Technology
advancements are providing smaller and more cost effective devices for integrating computational
processing, wireless communication, and a host of other functionalities. These embedded
communications devices will be integrated into applications ranging from homeland security to
industry automation and monitoring. They will also enable custom tailored engineering solutions,
creating a revolutionary way of disseminating and processing information. With new technologies and
devices come new business activities, and the need for employees in these technological areas.
Engineers who have knowledge of embedded systems and wireless communications will be in high
demand. Unfortunately, there are few adorable environments available for development and classroom
use, so students often do not learn about these technologies during hands-on lab exercises. The
communication mediums were twisted pair, optical fiber, infrared, and generally wireless radio.
1.1.2 OBJECTIVE OF THE PROJECT:

1.2 BLOCK DIAGRAM
LCD
SOIL SENSOR
Lpc2103
RELAY MOTOR
ESP8266
HARDWARE REQUIREMENTS: SOFTWARE REQUIREMENTS:

8051 series Microcontroller, Op-Amp, Keil compiler
LCD, Relay, Motor, Voltage Regulator,
Diodes, Capacitors, Resistors, LED, Languages: Embedded C or Assembly
Crystal, Transistors.
CHAPTER2
DESCRIPTION OF HARDWARE COMPONENTS
2.1 LPC2103
1. General description
The LPC2101/2102/2103 microcontrollers are based on a 16-bit/32-bit

ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 8 kB,
16 kB or 32 kB of embedded high-speed ßash memory. A 128-bit wide memory interface
and a unique accelerator architecture enable 32-bit code execution at the maximum clock
rate. For critical performance in interrupt service routines and DSP algorithms, this increases
performance up to 30 % over Thumb mode. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance
penalty.
Due to their tiny size and low power consumption, the LPC2101/2102/2103 are ideal
for applications where miniaturization is a key requirement. A blend of serial communications
interfaces ranging from multiple UARTs, SPI to SSP and two I 2C-buses, combined with on-
chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication
gateways and protocol converters. The superior performance also makes these devices suitable
for use as math coprocessors. Various 32-bit and 16-bit timers, an improved 10-bit ADC,
PWM features through output match on all timers, and 32 fast GPIO lines with up to nine edge
or level sensitive external interrupt pins make these microcontrollers particularly suitable for
industrial control and medical systems.
2. Features
Key features
 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP48 package.
 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip ßash program
memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.
 ISP/IAP via on-chip bootloader software. Single ßash sector or full chip erase in
100 ms and programming of 256 bytes in 1 ms.
 EmbeddedICE RT offers real-time debugging with the on-chip RealMonitor software.
 The 10-bit A/D converter provides eight analog inputs, with conversion times as low as
2.44 s per channel and dedicated result registers to minimize interrupt overhead.
 Two 32-bit timers/external event counters with combined seven capture and seven
compare channels.
 Two 16-bit timers/external event counters with combined three capture and seven
compare channels.
 Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz
clock input.
 Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses
(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.
 Vectored interrupt controller with conÞgurable priorities and vector

addresses.
 Up to thirty-two 5 V tolerant fast general purpose I/O pins.
 Up to 13 edge or level sensitive external interrupt pins available.
 70 MHz maximum CPU clock available from programmable on-chip PLL with a possible
input frequency of 10 MHz to 25 MHz and a settling time of 100 s.
 On-chip integrated oscillator operates with an external crystal in the range from 1 MHz to
25 MHz.
 Power saving modes include Idle mode, Power-down mode with RTC active, and Power-
down mode.
 Individual enable/disable of peripheral functions as well as peripheral clock scaling for

additional power optimization.
 Processor wake-up from Power-down mode via external interrupt or RTC.

2.Ordering information
Table 1: Ordering information

Type number Package
Name Description Version
plastic low proÞle quad ßat package;
LPC2101FBD48 LQFP48 48 leads; SOT313-2
body 7  7  1.4 mm

body 7  7  1.4 mm

body 7  7  1.4 mm
LPC2103FA44 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
3.1 Ordering options
Table 2: Ordering options

Type number Flash RAM ADC Temperature
memory range (C)
LPC2101FBD48 8 kB 2 kB 8 inputs 40 to +85
LPC2103FA44 32 kB 8 kB 8 inputs 40 to +85

4. Block diagram
XTAL2 V V
TMS TDI DD(3V3) DD(1V8)
V
TRST TCK TDO XTAL1 RST SS
LPC2101/2102/2103 TEST/DEBUG
INTERFACE
HIGH SPEED SYSTEM
P0[31:0] GENERAL 8 kB PLL FUNCTIONS
PURPOSE I/O BOOT ROM ARM7TDMI-S
system
AHB BRIDGE clock
INTERRUPT
VECTORED
ARM7 local bus CONTROLLER
AMBA AHB
(Advanced High-performance Bus)
INTERNAL
SRAM
MEMORY
ACCELERATOR
CONTROLLER
2 kB/4 kB/ 8 kB/16 kB/ AHB TO APB

8 kB SRAM 32 kB FLASH BRIDGE
APB (ARM
peripheral bus) 2 (1)
EINT2 to EXTERNAL I C-BUS SERIAL SCL0, SCL1
(1)
EINT0 INTERRUPTS INTERFACES 0 AND 1 (1)
(1) SDA0, SDA1
3  CAP0
(1)
4  CAP1
(1) CAPTURE/COMPARE (1)
3  CAP2 SCK0, SCK1
3  MAT0
(1) EXTERNAL COUNTER SPI AND SSP (1)
(1) TIMER 0/TIMER 1/ MOSI0, MOSI1
4  MAT1 SERIAL INTERFACES
(1) TIMER 2/TIMER 3 (1)
3  MAT2 MISO0, MISO1
(1)
4  MAT3 (1)
SSEL0, SSEL1
(1)
AD0[7:0] ADC UART0/UART1 TXD0, TXD1
(1)
RXD0, RXD1
DSR1, CTS1,
RTS1, DTR1
DCD1, RI1
GENERAL RTXC1
P0[31:0] REAL-TIME CLOCK RTXC2
PURPOSE I/O
VBAT
WATCHDOG
SYSTEM CONTROL
TIMER
002aab814
5.2 Pin description
Table 3:Pin description
Symbol LQFP48 PLCC44 Type Description
P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction
controls for each bit. A total of 31 pins of the Port 0 can be
used as general purpose bidirectional digital I/Os while P0.31
is an output only pin. The operation of port 0 pins depends
upon the pin function selected via the pin connect block.
P0.0/TXD0/ 13 [1] 18 [1] I/O P0.0 Ñ General purpose Input/output digital pin (GPIO).
MAT3.1 O TXD0 Ñ Transmitter output for UART0.
O MAT3.1 Ñ PWM output 1 for Timer 3.
P0.1/RXD0/ 14 [2] 19 [2] I/O P0.1 Ñ General purpose Input/output digital pin (GPIO).
MAT3.2 I RXD0 Ñ Receiver input for UART0.
P0.2/SCL0/ 18 [3] 22 [3] I/O P0.2 Ñ General purpose Input/output digital pin (GPIO).
2
CAP0.0 I/O SCL0 Ñ I C0 clock Input/output. Open-drain output (for
2
I C-bus compliance).
I CAP0.0 Ñ Capture input for Timer 0, channel 0.
P0.3/SDA0/ 21 [3] 25 [3] I/O P0.3 Ñ General purpose Input/output digital pin (GPIO).
2
MAT0.0 I/O SDA0 Ñ I C0 data input/output. Open-drain output (for
2
O MAT0.0 Ñ PWM output for Timer 0, channel 0.
P0.4/SCK0/ 22 [4] 26 [4] I/O P0.4 Ñ General purpose Input/output digital pin (GPIO).
CAP0.1 I/O SCK0 Ñ Serial clock for SPI0. SPI clock output from master
or input to slave.
P0.5/MISO0/ 23 [4] 27 [4] I/O P0.5 Ñ General purpose Input/output digital pin (GPIO).
MAT0.1 I/O MISO0 Ñ Master In Slave OUT for SPI0. Data input to SPI
master or data output from SPI slave.
P0.6/MOSI0/ 24 [4] 28 [4] I/O P0.6 Ñ General purpose Input/output digital pin (GPIO).
CAP0.2 I/O MOSI0 Ñ Master Out Slave In for SPI0. Data output from SPI
master or data input to SPI slave.
P0.7/SSEL0/ 28 [2] 31 [2] I/O P0.7 Ñ General purpose Input/output digital pin (GPIO).
MAT2.0 I SSEL0 Ñ Slave Select for SPI0. Selects the SPI interface as
a slave.
P0.8/TXD1/ 29 [4] 32 [4] I/O P0.8 Ñ General purpose Input/output digital pin (GPIO).
MAT2.1 O TXD1 Ñ Transmitter output for UART1.
P0.9/RXD1/ 30 [2] 33 [2] I/O P0.9 Ñ General purpose Input/output digital pin (GPIO).
MAT2.2 I RXD1 Ñ Receiver input for UART1.
P0.10/RTS1/ 35 [4] 38 [4] I/O P0.10 Ñ General purpose Input/output digital pin (GPIO).
CAP1.0/AD0.3 O RTS1 Ñ Request to Send output for UART1.
I AD0.3 Ñ ADC 0, input 3.
P0.11/CTS1/ 36 [3] 39 [3] I/O P0.11 Ñ General purpose Input/output digital pin (GPIO).
CAP1.1/AD0.4 I CTS1 Ñ Clear to Send input for UART1.
P0.12/DSR1/ 37 [4] 40 [4] I/O P0.12 Ñ General purpose Input/output digital pin (GPIO).
MAT1.0/AD0.5 I DSR1 Ñ Data Set Ready input for UART1.
P0.13/DTR1/ 41 [4] 43 [4] I/O P0.13 Ñ General purpose Input/output digital pin (GPIO).
MAT1.1 O DTR1 Ñ Data Terminal Ready output for UART1.
P0.14/DCD1/ 44 [3] 2 [3] I/O P0.14 Ñ General purpose Input/output digital pin (GPIO).
SCK1/EINT1 I DCD1 Ñ Data Carrier Detect input for UART1.
I/O SCK1 Ñ Serial Clock for SPI1. SPI clock output from master
or input to slave.
I EINT1 Ñ External interrupt 1 input.
P0.15/RI1/ 45 [4] 3 [4] I/O P0.15 Ñ General purpose Input/output digital pin (GPIO).
EINT2 I RI1 Ñ Ring Indicator input for UART1.
I EINT2 Ñ External interrupt 2 input.
P0.16/EINT0/ 46 [2] 4 [2] I/O P0.16 Ñ General purpose Input/output digital pin (GPIO).
MAT0.2 I EINT0 Ñ External interrupt 0 input.
P0.17/CAP1.2/ 47 [1] 5 [1] I/O P0.17 Ñ General purpose Input/output digital pin (GPIO).
SCL1 I CAP1.2 Ñ Capture input for Timer 1, channel 2.
2
I/O SCL1 Ñ I C1 clock Input/output. Open-drain output (for
2
P0.18/CAP1.3/ 48 [1] 6 [1] I/O P0.18 Ñ General purpose Input/output digital pin (GPIO).
SDA1 I CAP1.3 Ñ Capture input for Timer 1, channel 3.
2
I/O SDA1 Ñ I C1 data Input/output. Open-drain output (for
2
P0.19/MAT1.2/ 1 [1] 7 [1] I/O P0.19 Ñ General purpose Input/output digital pin (GPIO).
MISO1 O MAT1.2 Ñ PWM output for Timer 1, channel 2.
I/O MISO1 Ñ Master In Slave Out for SSP. Data input to SPI
master or data output from SSP slave.
P0.20/MAT1.3/ 2 [2] 8 [2] I/O P0.20 Ñ General purpose Input/output digital pin (GPIO).
MOSI1 O MAT1.3 Ñ PWM output for Timer 1, channel 3.
I/O MOSI1 Ñ Master Out Slave for SSP. Data output from SSP
master or data input to SSP slave.
P0.21/SSEL1/ 3 [4] 9 [4] I/O P0.21 Ñ General purpose Input/output digital pin (GPIO).
MAT3.0 I SSEL1 Ñ Slave Select for SPI1. Selects the SPI interface as
a slave.
P0.22/AD0.0 32 [4] 35 [4] I/O P0.22 Ñ General purpose Input/output digital pin (GPIO).
P0.26/AD0.7 39 [1] n.c. I/O P0.26 Ñ General purpose Input/output digital pin (GPIO).
P0.27/TRST/ 8 [4] 13 [4] I/O P0.27 Ñ General purpose Input/output digital pin (GPIO).
CAP2.0 I TRST Ñ Test Reset for JTAG interface.

P0.28/TMS/ 9 [4] 14 [4] I/O P0.28 Ñ General purpose Input/output digital pin (GPIO).
CAP2.1 I TMS Ñ Test Mode Select for JTAG interface.

P0.29/TCK/ 10 [4] 15 [4] I/O P0.29 Ñ General purpose Input/output digital pin (GPIO).
CAP2.2 I TCK Ñ Test Clock for JTAG interface.

P0.30/TDI/ 15 [4] 20 [4] I/O P0.30 Ñ General purpose Input/output digital pin (GPIO).
MAT3.3 I TDI Ñ Test Data In for JTAG interface.

P0.31/TDO 16 [4] 21 [4] O P0.31 Ñ General purpose output only digital pin (GPIO).
O TDO Ñ Test Data Out for JTAG interface.
RTXC1 20 [5] 24 [5] I Input to the RTC oscillator circuit.
RTXC2 25 [5] 29 [5] O Output from the RTC oscillator circuit.
RTCK 26 [5] n.c. I/O Returned test clock output: Extra signal added to the JTAG
port. Assists debugger synchronization when processor
frequency varies. Bidirectional pin with internal pull-up.
X1 11 16 I Input to the oscillator circuit and internal clock generator
circuits.
X2 12 17 O Output from the oscillator ampliÞer.
DBGSEL 27 30 I Debug select: When LOW, the part operates normally. When
HIGH, debug mode is entered. Input with internal pull-down.
RST 6 11 I External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states and processor execution to begin at address 0. TTL
with hysteresis, 5 V tolerant.
V
SS 7, 19, 43 1, 12, 23 I Ground: 0 V reference.
Table 3: Pin description
V
SSA 31 34 I Analog ground: 0 V reference. This should be nominally the
same voltage as VSS but should be isolated to minimize noise
and error.
V
DDA 42 44 I Analog 3.3 V power supply: This should be nominally the
same voltage as VDD(3V3) but should be isolated to minimize
noise and error. This voltage is used to power the on-chip
PLL. This pin also provides a voltage reference level for the
ADC.
V
DD(1V8) 5 10 I 1.8 V core power supply: This is the power supply voltage for
internal circuitry.
V
DD(3V3) 17, 40 42 I 3.3 V pad power supply: This is the power supply voltage for
the I/O ports.
VBAT 4 n.c. I RTC power supply: 3.3 V on this pin supplies the power to
the RTC.
[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate
control.
[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew
rate control. If conÞgured for an input function, this pad utilizes built-in glitch Þlter that blocks
pulses shorter than 3 ns.
[3] Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz speciÞcation compatible pad. It requires
external pull-up to provide an output functionality.
[4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control)
and analog input function. If conÞgured for an input function, this pad utilizes built-in glitch Þlter
that blocks pulses shorter than 3 ns. When conÞgured as an ADC input, digital section of the pad
is disabled.
[5] Pad provides special analog functionality.
6. Functional description
Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on Reduced
Instruction Set Computer (RISC) principles, and the instruction set and related decode
mechanism are much simpler than those of microprogrammed Complex Instruction Set
Computers (CISC). This simplicity results in a high instruction throughput and impressive
real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and
memory systems can operate continuously. Typically, while one instruction is being
executed, its successor is being decoded, and a third instruction is being fetched from
memory.
The ARM7TDMI-S processor also employs a unique architectural
strategy known as Thumb, which makes it ideally suited to high-volume applications with
memory restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set.
Essentially, the ARM7TDMI-S processor has two instruction sets:
 The standard 32-bit ARM set.

 A 16-bit Thumb set.
The Thumb setÕs 16-bit instruction length allows it to approach twice the
density of standard ARM code while retaining most of the ARMÕs performance advantage
over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160
% of the performance of an equivalent ARM processor connected to a 16-bit memory system.
The particular ßash implementation in the LPC2101/2102/2103 allows for
full speed execution also in ARM mode. It is recommended to program performance critical
and short code sections in ARM mode. The impact on the overall code size will be minimal
but the speed can be increased by 30 % over Thumb mode.
6.2 On-chip ßash program memory

The LPC2101/2102/2103 incorporate a 8 kB, 16 kB or 32 kB ßash memory system
respectively. This memory may be used for both code and data storage. Programming of the
ßash memory may be accomplished in several ways. It may be programmed In System via
the serial port. The application program may also erase and/or program the ßash while the
application is running, allowing a great degree of ßexibility for data storage Þeld Þrmware
upgrades, etc. The entire ßash memory is available for user code as the bootloader
6.3 On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed
as 8-bits, 16-bits, and 32-bits. The LPC2101/2102/2103 provide 2 kB, 4 kB or 8 kB of static
RAM.
6.4 Memory map
The LPC2101/2102/2103 memory map incorporates several distinct regions, as shown in
Figure 4. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside
in either ßash memory (the default) or on-chip static RAM.
4.0 GB 0xFFFF FFFF

AHB PERIPHERALS
3.75 GB 0xF000 0000
APB PERIPHERALS
3.5 GB 0xE000 0000
3.0 GB 0xC000 0000
RESERVED ADDRESS SPACE
0x8000 0000 0x7FFF FFFF

2.0 GB
BOOT BLOCK 0x7FFF E000 0x7FFF DFFF
0x4000 2000
RESERVED ADDRESS SPACE 0x4000 1FFF
0x4000 1000
0x4000 0FFF
8 kB ON-CHIP STATIC RAM (LPC2103)
0x4000 0800
0x4000 07FF
0x4000 0000
1.0 GB 0x0000 8000
RESERVED ADDRESS SPACE 0x0000 7FFF
0x0000 4000
32 kB ON-CHIP NON-VOLATILE MEMORY (LPC2103) 0x0000 3FFF
16 kB ON-CHIP NON-VOLATILE MEMORY (LPC2102)
0x0000 2000
8 kB ON-CHIP NON-VOLATILE MEMORY 0x0000 1FFF
(LPC2101)
0.0 GB 0x0000 0000
6.5 Interrupt controller
The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored
IRQ, and non-vectored IRQ as deÞned by programmable settings. The programmable
assignment scheme means that priorities of interrupts from the various peripherals can be
dynamically assigned and adjusted.
FIQ has the highest priority. If more than one request is assigned to FIQ, the
VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classiÞed as FIQ, because then the
FIQ service routine does not need to branch into the interrupt service routine but can run
from the interrupt vector location. If more than one request is assigned to the FIQ class, the
FIQ service routine will read a word from the VIC that identiÞes which FIQ source(s) is (are)
requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can
be assigned to this category. Any of the interrupt requests can be assigned to any of the 16
vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-
vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can
start by reading a register from the VIC and jumping there. If any of the vectored IRQs are
pending, the VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.
Interrupt sources
Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller,
but may have several internal interrupt ßags. Individual interrupt ßags may also represent
more than one interrupt source.
Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one
function. ConÞguration registers control the multiplexers to allow connection between the pin
and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to
being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled
peripheral function that is not mapped to a related pin should be considered undeÞned.The Pin
Control Module with its pin select registers deÞnes the functionality of the microcontroller in a
given hardware environment.
After reset all pins of Port 0 are conÞgured as input with the following
exceptions: If debug is enabled, the JTAG pins will assume their JTAG functionality. The pins
associated with the I2C0 interface are open-drain
6.7 Fast general purpose parallel I/O
Device pins that are not connected to a speciÞc peripheral function are controlled by the GPIO
registers. Pins may be dynamically conÞgured as inputs or outputs. Separate registers allow
setting or clearing any number of outputs simultaneously. The value of the output register may
be read back, as well as the current state of the port pins.
 LPC2101/2102/2103 introduce accelerated GPIO functions over prior LPC2000 devices:
 GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.
 Mask registers allow treating sets of port bits as a group, leaving other bits unchanged.
 All GPIO registers are byte addressable.
 Entire port value can be written in one instruction.
Features
 Bit-level set and clear registers allow a single instruction set or clear of any number
of bits in one port.
 Direction control of individual bits.
 Separate control of output set and clear.
 All I/O default to inputs after reset.
10-bit A/D converter

The LPC2101/2102/2103 contain one analog to digital converter. It is a single 10-bit
successive approximation analog to digital converter with eight channels.
Features
 Measurement range of 0 V to 3.3 V.
 Each converter capable of performing more than 400,000 10-bit samples per second.
 Burst conversion mode for single or multiple inputs.
 Optional conversion on transition on input pin or Timer Match signal.
 Every analog input has a dedicated result register to reduce interrupt overhead.
UARTs
The LPC2101/2102/2103 each contain two UARTs. In addition to standard transmit and
receive data lines, UART1 also provides a full modem control handshake
interface.Compared to previous LPC2000 microcontrollers, UARTs in LPC2101/2102/2103
include a fractional baud rate generator for both UARTs. Standard baud rates such as
115200 can be achieved with any crystal frequency above 2 MHz.
Built-in fractional baud rate generator covering wide range of baud rates without a need for
external crystals of particular values.
Transmission FIFO control enables implementation of software (XON/XOFF) ßow control

on both UARTs.
UART1 is equipped with standard modem interface signals. This module also provides
full support for hardware ßow control (auto-CTS/RTS).
2
I C-bus serial I/O controllers
The LPC2101/2102/2103 each contain two I2C-bus controllers.
The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line
(SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and can
operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the capability
to both receive and send information such as serial memory. Transmitters and/or receivers
can operate in either master or slave mode, depending on whether the chip has to initiate a
data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be controlled by
more than one bus master connected to it.
The I2C-bus implemented in LPC2101/2102/2103 supports bit rates up to 400 kbit/s (Fast
I2C).
Features
o Compliant with standard I2C-bus interface.

o Easy to conÞgure as Master, Slave, or Master/Slave.
o Programmable clocks allow versatile rate control.
o Bidirectional data transfer between masters and slaves.
o Multi-master bus (no central master).
o Arbitration between simultaneously transmitting masters without corruption of serial data

on the bus.
o Serial clock synchronization allows devices with different bit rates to communicate via one
serial bus.
o Serial clock synchronization can be used as a handshake mechanism to suspend and resume
serial transfer.
o The I2C-bus can also be used for test and diagnostic purposes.
SPI serial I/O controller

The LPC2101/2102/2103 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only a
single master and a single slave can communicate on the interface during a given data transfer.
During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the
slave always sends 8 bits to 16 bits of data to the master.
SSP serial I/O controller

The LPC2101/2102/2103 each contain one SSP. The SSP controller is capable of operation on
a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the
bus. However, only a single master and a single slave can communicate on the bus during a
given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to 16 bits
ßowing from the master to the slave and from the slave to the master. Often only one of these
data streams carries meaningful data.
Features
o Compatible with Motorola SPI, 4-wire TIÕs SSI and National SemiconductorÕs
Microwire buses.
o Synchronous Serial Communication.
o Master or slave operation.
o 8-frame FIFOs for both transmit and receive.
o Four bits to 16 bits per frame.
General purpose 32-bit timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally
supplied clock and optionally generate interrupts or perform other actions at speciÞed timer
values, based on four match registers. It also includes four capture inputs to trap the timer
value when an input signal transitions, optionally generating an interrupt. Multiple pins can be
selected to perform a single capture or match function, providing an application with ÔorÕ
and ÔandÕ, as well as ÔbroadcastÕ functions among them.
The LPC2101/2102/2103 can count external events on one of the capture inputs if the
minimum external pulse is equal or longer than a period of the PCLK. In this conÞguration,
unused capture lines can be selected as regular timer capture inputs or used as external
interrupts.
Features
o A 32-bit timer/counter with a programmable 32-bit prescaler.
o External event counter or timer operation.
o Four 32-bit capture channels per timer/counter that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an interrupt.
o Four 32-bit match registers that allow:
 Continuous operation with optional interrupt generation on match.
 Stop timer on match with optional interrupt generation.

 Reset timer on match with optional interrupt generation.
o Four external outputs per timer/counter corresponding to match registers, with the
following capabilities:
 Set LOW on match.
General purpose 16-bit timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally
supplied clock and optionally generate interrupts or perform other actions at speciÞed timer
values, based on four match registers. It also includes three capture inputs to trap the timer value
when an input signal transitions, optionally generating an interrupt. Multiple pins can be
selected to perform a single capture or match function, providing an application with ÔorÕ and
ÔandÕ, as well as ÔbroadcastÕ functions among them.
The LPC2101/2102/2103 can count external events on one of the capture inputs if
the minimum external pulse is equal or longer than a period of the PCLK. In this conÞguration,
unused capture lines can be selected as regular timer capture inputs or used as external
interrupts.
Features
o Two 16-bit timer/counters with a programmable 16-bit prescaler.
o External event counter or timer operation.
o Three 16-bit capture channels that can take a snapshot of the timer value when an input
signal transitions. A capture event may also optionally generate an interrupt.
o Four 16-bit match registers that allow:
 Continuous operation with optional interrupt generation on match.
 Stop timer on match with optional interrupt generation.
 Reset timer on match with optional interrupt generation.
o Four external outputs per timer/counter corresponding to match registers, with the
following capabilities:
 Set LOW on match.
 Set HIGH on match.
 Toggle on match.
 Do nothing on match.
Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system reset
if the user program fails to ÔfeedÕ (or reload) the watchdog within a predetermined amount
of time.
o Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
o Flag to indicate watchdog reset.
o Programmable 32-bit timer with internal pre-scaler.
o Selectable time period from (TPCLK  256  4) to (TPCLK  232  4) in multiples of
 TPCLK  4.
Real-time clock
The Real-Time Clock (RTC) is designed to provide a set of counters to measure time when
normal or idle operating mode is selected. The RTC has been designed to use little power,
making it suitable for battery powered systems where the CPU is not running continuously
(Idle mode).
Features
o Measures the passage of time to maintain a calendar and clock.
o Ultra-low power design to support battery powered systems.
o Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of
Year.
o Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the
external crystal/oscillator input at XTAL1. Programmable Reference Clock Divider allows
Þne adjustment of the RTC.
o Dedicated power supply pin can be connected to a battery or the main 3.3 V.
Crystal oscillator
On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz. The
oscillator output frequency is called fosc and the ARM processor clock frequency is referred to
as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL
is running and connected. Refer to Section 6.17.2 ÒPLLÓ for additional information.
PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 70 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there
is an additional divider in the loop to keep the CCO within its frequency range while the PLL
is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or
16 to produce the output clock. Since the minimum output divider value is 2, it is insured that
the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip
reset and may be enabled by software. The program must conÞgure and activate the PLL, wait
for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100
s.
Reset and wake-up timer

Reset has two sources on the LPC2101/2102/2103: the RESET pin and watchdog reset. The
RESET pin is a Schmitt trigger input pin with an additional glitch Þlter. Assertion of chip
reset by any source starts the wake-up timer (see wake-up timer description below), causing
the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is
running, a Þxed number of clocks have passed, and the on-chip ßash controller has completed
its initialization.
When the internal reset is removed, the processor begins executing at

address 0, which is the reset vector. At that point, all of the processor and peripheral registers
have been initialized to predetermined reset values.
The wake-up timer ensures that the oscillator and other analog functions
required for chip operation are fully functional before the processor is allowed to execute
instructions. This is important at power on, all types of reset, and whenever any of the
aforementioned functions are turned off for any reason. Since the oscillator and other functions
are turned off during Power-down mode, any wake-up of the processor from Power-down
mode makes use of the wake-up timer.
The wake-up timer monitors the crystal oscillator as the means of

checking whether it is safe to begin code execution. When power is applied to the chip, or
some event caused the chip to exit Power-down mode, some time is required for the oscillator
to produce a signal of sufÞcient amplitude to drive the clock logic. The amount of time
depends on many factors, including the rate of V DD ramp (in the case of power on), the type
of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other
external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the
existing ambient conditions.
Code security
This feature of the LPC2101/2102/2103 allow an application to control whether it can be
debugged or protected from observation.
If after reset on-chip bootloader detects a valid checksum in ßash and reads 0x8765 4321 from
address 0x1FC in ßash, debugging will be disabled and thus the code in ßash will be protected
from observation. Once debugging is disabled, it can only be enabled by performing a full chip
erase using the ISP.
External interrupt inputs

The LPC2101/2102/2103 include up to three edge or level sensitive External Interrupt Inputs
as selectable pin functions. When the pins are combined, external events can be processed as
three independent interrupt signals. The External Interrupt Inputs can optionally be used to
wake-up the processor from Power-down mode.
Additionally all 10 capture input pins can also be used as external interrupts without the
option to wake the device up from Power-down mode.
Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
ßash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
Power control
The LPC2101/2102/2103 supports two reduced power modes: Idle
mode and Power-down mode.
In Idle mode, execution of instructions is suspended until either a reset or

interrupt occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates power used by the
processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no
internal clocks. The processor state and registers, peripheral registers, and internal SRAM
values are preserved throughout Power-down mode and the logic levels of chip output pins
remain static. The Power-down mode can be terminated and normal operation resumed by
either a reset or certain speciÞc interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
Selecting an external 32 kHz clock instead of the PCLK as a clock-source for

the on-chip RTC will enable the microcontroller to have the RTC active during Power-down
mode. Power-down current is increased with RTC active. However, it is signiÞcantly lower
than in Idle mode.
A Power Control for Peripherals feature allows individual peripherals to be

turned off if they are not needed in the application, resulting in additional power savings
during active and Idle mode.
APB bus
The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The Þrst is to
provide peripherals with the desired PCLK via APB bus so that they can operate at the speed
chosen for the ARM processor. In order to achieve this, the APB bus may be slowed down to
1
2 to 14 of the processor clock rate. Because the APB bus must work properly at power-up
(and its timing cannot be altered if it does not work since the APB divider control registers
reside on the APB bus), the default condition at reset is for the APB bus to run at 14 of the
processor clock rate. The second purpose of the APB divider is to allow power savings when
an application does not require any peripherals to run at the full processor rate. Because the
APB divider is connected to the PLL output, the PLL remains active (if it was running) during
Idle mode.
7. Limiting values
Table 4: Limiting values

Symbol Parameter Conditions Min Max Unit
V [2]
DD(1V8) supply voltage (1.8 V) 0.5 +2.5 V
V [3]
DD(3V3) supply voltage (3.3 V) 0.5 +3.6 V
V
DDA analog 3.3 V pad supply voltage 0.5 4.6 V
V
i(VBAT) input voltage on pin VBAT for the RTC 0.5 4.6 V
V [4]
IA analog input voltage 0.5 5.1 V
[5] [6]
VI input voltage 5 V tolerant I/O 0.5 6.0 V
pins
[5] [7]
other I/O pins 0.5 VDD + 0.5 V
I [8] [9]
DD supply current - 100 mA
I [10] [9]
SS ground current - 100 mA
T [11]
stg storage temperature 40 125 C
P
tot(pack) total power dissipation (per package) based on package - 1.5 W
heat transfer, not
device power
consumption
[1] The following applies to the Limiting values:

a) This product includes circuitry speciÞcally designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise speciÞed. All voltages are with respect to V SS
unless otherwise noted.
[2] Core and internal rail.
[3] External rail.
[4] On ADC related pins.
[5] Including voltage on outputs in 3-state mode.
[6] Only valid when the VDD(3V3) supply voltage is present.
[7] Not to exceed 4.6 V.
[8] Per supply pin.
[9] The peak current is limited to 25 times the corresponding maximum current.
[10] Per ground pin.
[11] Dependent on package type.
8. Static characteristics
Static
Table 5: characteristics
Symbol Parameter Conditions Min Typ [1] Max Unit

V [2] 1.65 1.8 1.95 V
DD(1V8) supply voltage (1.8 V)
V [3]
DD(3V3) supply voltage (3.3 V)
V
DDA analog 3.3 V pad supply 3.0 3.3 3.6 V
voltage
V [4]
input voltage on pin VBAT
i(VBAT) 2.0 3.3 3.6 V
3.0 3.3 3.6 V
Standard port pins, RESET, RTCK
I
IL LOW-state input current VI = 0 V; no pull-up - - 3 A
I
IH HIGH-state input current VI = VDD(3V3); no pull-down - - 3 A
I
OZ OFF-state output current VO = 0 V, VO = VDD(3V3); no - - 3 A
pull-up/down
I
latch I/O latch-up current (0.5VDD(3V3)) < V < - - 100 mA
(1.5V )
DD(3V3)
Tj < 125 C
[5] [6] 0 - 5.5 V
VI input voltage pin conÞgured to provide a [7]
digital function
V
VO output voltage output active 0 - DD(3V3) V
V
IH HIGH-state input voltage 2.0 - - V
V
IL LOW-state input voltage - - 0.8 V
V
hys hysteresis voltage - 0.4 - V
V V
OH HIGH-state output voltage IOH = 4 mA [8] DD(3V3)  - - V
0.4
V [8] - - 0.4 V
OL LOW-state output voltage IOL = 4 mA
I V =V 0.4 V [8] 4 - - mA
OH HIGH-state output current OH DD(3V3) 
I [8] 4 - - mA
OL LOW-state output current VOL = 0.4 V
I [9] - - 45 mA
OHS HIGH-state short-circuit VOH = 0 V
output current
I V =V [9] - - 50 mA
OLS LOW-state short-circuit OL DDA
output current
I [10]
pd pull-down current VI = 5 V 10 50
I [11] 15 50 85
150 A
pu pull-up current VI = 0 V
V <V <5V [10]
DD(3V3) I 0 0 A
I
DD(act) active mode supply VDD(1V8) = 1.8 V, Ta = 25 C, 0
current code
while(1){}
executed from ßash, no active
peripherals
CCLK = 10 MHz <tbd> 7 <tbd> mA
CCLK = 70 MHz <tbd> 41 <tbd> mA
(other parameters as above)
I
DD(pd) Power-down mode supply VDD(1V8) = 1.8 V, Ta = +25 C <tbd> 7 <tbd> A
current
VDD(1V8) = 1.8 V, Ta = +85 C <tbd> <tbd> <tbd> A
2.2POWER SUPPLY
All digital circuits require regulated power supply. In this article we are going to learn how to get a
regulated positive supply from the mains supply.

Figure 1 shows the basic block diagram of a fixed regulated power supply. Let us go through each block.
TRANSFORMER
A transformer consists of two coils also called as “WINDINGS” namely PRIMARY & SECONDARY.
They are linked together through inductively coupled electrical conductors also called as CORE. A
changing current in the primary causes a change in the Magnetic Field in the core & this in turn induces an
alternating voltage in the secondary coil. If load is applied to the secondary then an alternating current will
flow through the load. If we consider an ideal condition then all the energy from the primary circuit will be
transferred to the secondary circuit through the magnetic field.
So

The secondary voltage of the transformer depends on the number of turns in the Primary as well as in the second
Rectifier
A rectifier is a device that converts an AC signal into DC signal. For rectification purpose we use a diode, a
diode is a device that allows current to pass only in one direction i.e. when the anode of the diode is
positive with respect to the cathode also called as forward biased condition & blocks current in the reversed
biased condition.

Rectifier can be classified as follows:
1) Half Wave rectifier.
This is the simplest type of rectifier as you can see in the diagram a half wave rectifier consists of only one
diode. When an AC signal is applied to it during the positive half cycle the diode is forward biased &
current flows through it. But during the negative half cycle diode is reverse biased & no current flows
through it. Since only one half of the input reaches the output, it is very inefficient to be used in power
supplies.
2) Full wave rectifier.
Half wave rectifier is quite simple but it is very inefficient, for greater efficiency we would like to use both
the half cycles of the AC signal. This can be achieved by using a center tapped transformer i.e. we would
have to double the size of secondary winding & provide connection to the center. So during the positive
half cycle diode D1 conducts & D2 is in reverse biased condition. During the negative half cycle diode D2
conducts & D1 is reverse biased. Thus we get both the half cycles across the load.
One of the disadvantages of Full Wave Rectifier design is the necessity of using a center tapped
transformer, thus increasing the size & cost of the circuit. This can be avoided by using the Full Wave
Bridge Rectifier.
3) Bridge Rectifier.
As the name suggests it converts the full wave i.e. both the positive & the negative half cycle into DC thus
it is much more efficient than Half Wave Rectifier & that too without using a center tapped transformer
thus much more cost effective than Full Wave Rectifier.
Full Bridge Wave Rectifier consists of four diodes namely D1, D2, D3 and D4. During the positive half
cycle diodes D1 & D4 conduct whereas in the negative half cycle diodes D2 & D3 conduct thus the diodes
keep switching the transformer connections so we get positive half cycles in the output.
If we use a center tapped transformer for a bridge rectifier we can get both positive & negative half cycles
which can thus be used for generating fixed positive & fixed negative voltages.
FILTER CAPACITOR
Even though half wave & full wave rectifier give DC output, none of them provides a constant output
voltage. For this we require to smoothen the waveform received from the rectifier. This can be done by
using a capacitor at the output of the rectifier this capacitor is also called as “FILTER CAPACITOR” or
“SMOOTHING CAPACITOR” or “RESERVOIR CAPACITOR”. Even after using this capacitor a small
amount of ripple will remain.
We place the Filter Capacitor at the output of the rectifier the capacitor will charge to the peak voltage during eac
cycle then will discharge its stored energy slowly through the load while the rectified voltage drops to zero, thus
to keep the voltage as constant as possible.
If we go on increasing the value of the filter capacitor then the Ripple will decrease. But then the costing will inc
The value of the Filter capacitor depends on the current consumed by the circuit, the frequency of the waveform
accepted ripple.

Where,
Vr= accepted ripple voltage.( should not be more than 10% of the voltage)
I= current consumed by the circuit in Amperes.
F= frequency of the waveform. A half wave rectifier has only one peak in one cycle so F=25hz
Whereas a full wave rectifier has Two peaks in one cycle so F=100hz.
VOLTAGE REGULATOR
A Voltage regulator is a device which converts varying input voltage into a constant regulated output
voltage. Voltage regulator can be of two types
1) Linear Voltage Regulator

Also called as Resistive Voltage regulator because they dissipate the excessive voltage resistively as
heat.
2) Switching Regulators.
They regulate the output voltage by switching the Current ON/OFF very rapidly. Since their output is
either ON or OFF it dissipates very low power thus achieving higher efficiency as compared to linear
voltage regulators. But they are more complex & generate high noise due to their switching action. For low
level of output power switching regulators tend to be costly but for higher output wattage they are much
cheaper than linear regulators.
The most commonly available Linear Positive Voltage Regulators are the 78XX series where the XX
indicates the output voltage. And 79XX series is for Negative Voltage Regulators.
After filtering the rectifier output the signal is given to a voltage regulator. The maximum input voltage
that can be applied at the input is 35V.Normally there is a 2-3 Volts drop across the regulator so the input
voltage should be at least 2-3 Volts higher than the output voltage. If the input voltage gets below the Vmin
of the regulator due to the ripple voltage or due to any other reason the voltage regulator will not be able to
produce the correct regulated voltage.
3 Circuit diagram:
Fig 2.3. Circuit Diagram of power supply
IC 7805:
7805 is an integrated three-terminal positive fixed linear voltage regulator. It supports an input voltage of
10 volts to 35 volts and output voltage of 5 volts. It has a current rating of 1 amp although lower current
models are available. Its output voltage is fixed at 5.0V. The 7805 also has a built-in current limiter as a
safety feature. 7805 is manufactured by many companies, including National Semiconductors and Fairchild
Semiconductors.
The 7805 will automatically reduce output current if it gets too hot.The last two digits represent the
voltage; for instance, the 7812 is a 12-volt regulator. The 78xx series of regulators is designed to work in
complement with the 79xx series of negative voltage regulators in systems that provide both positive and
negative regulated voltages, since the 78xx series can't regulate negative voltages in such a system.
The 7805 & 78 is one of the most common and well-known of the 78xx series regulators, as it's small
component count and medium-power regulated 5V make it useful for powering TTL devices.
Table 2.1. Specifications of IC7805

SPECIFICATIONS IC 7805
Vout 5V
Vein - Vout Difference 5V - 20V
Operation Ambient Temp 0 - 125°C
Output Imax 1A
2.3 LCD MODULE
To display interactive messages we are using LCD Module. We examine an intelligent LCD display
of two lines,16 characters per line that is interfaced to the controllers. The protocol (handshaking) for the
display is as shown. Whereas D0 to D7th bit is the Data lines, RS, RW and EN pins are the control pins
and remaining pins are +5V, -5V and GND to provide supply. Where RS is the Register Select, RW is the
Read Write and EN is the Enable pin.
The display contains two internal byte-wide registers, one for commands (RS=0) and the second
for characters to be displayed (RS=1). It also contains a user-programmed RAM area (the character RAM)
that can be programmed to generate any desired character that can be formed using a dot matrix. To
distinguish between these two data areas, the hex command byte 80 will be used to signify that the display
RAM address 00h will be chosen.Port1 is used to furnish the command or data type, and ports 3.2 to3.4
furnish register select and read/write levels.
The display takes varying amounts of time to accomplish the functions as listed. LCD bit 7 is monitored for
logic high (busy) to ensure the display is overwritten.
Liquid Crystal Display also called as LCD is very helpful in providing user interface as well as for
debugging purpose. The most common type of LCD controller is HITACHI 44780 which provides a simple
interface between the controller & an LCD. These LCD's are very simple to interface with the controller as
well as are cost effective.
2x16 Line Alphanumeric LCD Display

The most commonly used ALPHANUMERIC displays are 1x16 (Single Line & 16 characters), 2x16
(Double Line & 16 character per line) & 4x20 (four lines & Twenty characters per line).
The LCD requires 3 control lines (RS, R/W & EN) & 8 (or 4) data lines. The number on data lines depends
on the mode of operation. If operated in 8-bit mode then 8 data lines + 3 control lines i.e. total 11 lines are
required. And if operated in 4-bit mode then 4 data lines + 3 control lines i.e. 7 lines are required. How do
we decide which mode to use? It’s simple if you have sufficient data lines you can go for 8 bit mode & if
there is a time constrain i.e. display should be faster then we have to use 8-bit mode because basically 4-bit
mode takes twice as more time as compared to 8-bit mode.
Pin Symbol Function
1 Vss Ground
2 Vdd Supply Voltage
3 Vo Contrast Setting
4 RS Register Select
5 R/W Read/Write Select
6 En Chip Enable Signal
7-14 DB0-DB7 Data Lines
15 A/Vee Gnd for the backlight
16 K Vcc for backlight
When RS is low (0), the data is to be treated as a command. When RS is high (1), the data being sent
is considered as text data which should be displayed on the screen.
When R/W is low (0), the information on the data bus is being written to the LCD. When RW is high (1),
the program is effectively reading from the LCD. Most of the times there is no need to read from the LCD
so this line can directly be connected to Gnd thus saving one controller line.
The ENABLE pin is used to latch the data present on the data pins. A HIGH - LOW signal is required to
latch the data. The LCD interprets and executes our command at the instant the EN line is brought low. If
you never bring EN low, your instruction will never be executed.
COMMANDS USED IN LCD
2.4 SOIL SENSOR (LM 358)

LM 358
Features:
 Internally Frequency Compensated for Unity Gain

 Large DC Voltage Gain: 100dB
 Wide Power Supply Range:
 LM358:
Singal supply:3V~32V
Or dual supply: ±1.5V~ 16V
 Input Common Mode Voltage Range Includes Ground
 Large Output Voltage Swing: 0V DC to Vcc -1.5V DC
 Power Drain Suitable for Battery Operation.
 Available in 8-Bump micro SMD chip sized package,
 Wide bandwidth (unity gain): 1 MHz (temperature compensated).
 Very low supply current drain (500 μA) essentially independent of supply voltage.
 Low input offset voltage: 2 mV.
 Differential input voltage range equal to the power supply voltage.
Dual Operational Amplifiers:

These devices consist of two independent, high-gain, frequency-compensated Operational
Amplifiers designed to operate from a single supply over a wide range of voltages. Operation from split
supplies also is possible if the difference between the two supplies is 3 V to 32 V (3 V to 26 V for the
LM2904 , and VCC is at least 1.5 V more positive than the input common-mode voltage. The low supply-
current drain is independent of the magnitude of the supply voltage.
Applications include transducer Amplifiers dc amplification blocks, and all the conventional
Operational Amplifier circuits that now CAN be implemented more easily in single-supply-voltage
systems. For example, these devices CAN be operated directly from the standard 5-V supply used in digital
systems and easily provide the required Interface electronics without additional 5-V supplies.
Complete LM358 datasheet specifications. The LM358 series consists of two independent,
high gain, internally frequency compensated operational amplifiers which were designed specifically to
operate from a single power supply over a wide range of voltages. Operation from split power supplies is
also possible and the low power supply current drain is independent of the magnitude of the power supply
voltage.
Description:
LM 358 consist of two independent, high gain, internally frequency compensated operational amplifiers
which were designed specifically to operate from a single power supply over a wide range of voltage.
Operation from split power supplies is also possible and the low power supply current drain is independent
of the magnitude of the power supply voltage.
Application areas include transducer amplifier, DC gain blocks and all the conventional OP-AMP circuits
which now can be easily implemented in single power supply systems.
PIN DIAGRAM
INTERNAL DIAGRAM:
2.5 RELAY
RELAYS SPDT
Overview OF Relays
A relay is an electrically operated switch used to isolate one electrical circuit from another. In its simplest
form, a relay consists of a coil used as an electromagnet to open and close switch contacts. Since the two
circuits are isolated from one another, a lower voltage circuit can be used to trip a relay, which will control
a separate circuit that requires a higher voltage or amperage. Relays can be found in early telephone
exchange equipment, in industrial control circuits, in car audio systems, in automobiles, on water pumps, in
high-power audio amplifiers and as protection devices.
Relay Switch Contacts

The switch contacts on a relay can be "normally open" (NO) or "normally closed" (NC)--that is, when the
coil is at rest and not energized (no current flowing through it), the switch contacts are given the
designation of being NO or NC. In an open circuit, no current flows, such as a wall light switch in your
home in a position that the light is off. In a closed circuit, metal switch contacts touch each other to
complete a circuit, and current flows, similar to turning a light switch to the "on" position. In the
accompanying schematic diagram, points A and B connect to the coil. Points C and D connect to the
switch. When you apply a voltage across the coil at points A and B, you create an electromagnetic field,
which attracts a lever in the switch, causing it to make or break contact in the circuit at points C and D
(depending if the design is NO or NC). The switch contacts remain in this state until you remove the
voltage to the coil. Relays come in different switch configurations. The switches may have more than one
"pole," or switch contact. The diagram shows a "single pole single throw" configuration, referred to as
SPST. This is similar to a wall light switch in your home. With a single "throw" of the switch, you close
the circuit.
The Single Pole Double Throw Relay

A single pole double throw (SPDT) relay configuration switches one common pole to two other poles,
flipping between them. As shown in the schematic diagram, the common point E completes a circuit with
C when the relay coil is at rest, that is, no voltage is applied to it.
This circuit is "closed." A gap between the contacts of point E and D creates an "open" circuit. When you
apply power to the coil, a metal level is pulled down, closing the circuit between points E and D and
opening the circuit between E and C. A single pole double throw relay can be used to alternate which
circuit a voltage or signal will be sent to.
SPDT Relay:
(Single Pole Double Throw Relay) an electromagnetic switch, consist of a coil (terminals 85 & 86), 1
common terminal (30), 1 normally closed terminal (87a), and one normally open terminal (87) (Figure 1).
When the coil of an SPDT relay (Figure 1) is at rest (not energized), the common terminal (30) and the
normally closed terminal (87a) have continuity. When the coil is energized, the common terminal (30) and
the normally open terminal (87) have continuity.
The diagram below center (Figure 2) shows an SPDT relay at rest, with the coil not energized. The diagram
below right (Figure 3) shows the relay with the coil energized. As you can see, the coil is an electromagnet
that causes the arm that is always connected to the common (30) to pivot when energized whereby contact
is broken from the normally closed terminal (87a) and made with the normally open terminal (87).
When energizing the coil of a relay, polarity of the coil does not matter unless there is a diode across the
coil. If a diode is not present, you may attach positive voltage to either terminal of the coil and negative
voltage to the other, otherwise you must connect positive to the side of the coil that the cathode side (side
with stripe) of the diode is connected and negative to side of the coil that the anode side of the diode is
connected.
Why do I want to use a relay and do I really need to?

Anytime you want to switch a device which draws more current than is provided by an output of a switch
or component you'll need to use a relay. The coil of an SPDT or an SPST relay that we most commonly
use draws very little current (less than 200 milliamps) and the amount of current that you can pass through
a relay's common, normally closed, and normally open contacts will handle up to 30 or 40 amps. This
allows you to switch devices such as headlights, parking lights, horns, etc., with low amperage outputs
such as those found on keyless entry and alarm systems, and other components. In some cases you may
need to switch multiple things at the same time using one output. A single output connected to multiple
relays will allow you to open continuity and/or close continuity simultaneously on multiple wires.
There are far too many applications to list that require the use of a relay, but we do show many of the most
popular applications in the pages that follow and many more in our Relay Diagrams - Quick Reference
application. If you are still unclear about what a relay does or if you should use one after you browse
through the rest of this section, please post a question in the12volt's install bay. (We recommend Tyco
(formerly Bosch) or Potter & Brumfield relays for all of the SPDT and SPST relay applications shown on
this site.)
2.6 DC MOTOR
DC motors are configured in many types and sizes, including brush less, servo, and gear motor
types. A motor consists of a rotor and a permanent magnetic field stator. The magnetic field is
maintained using either permanent magnets or electromagnetic windings. DC motors are most
commonly used in variable speed and torque.
Motion and controls cover a wide range of components that in some way are used to
generate and/or control motion. Areas within this category include bearings and bushings, clutches and
brakes, controls and drives, drive components, encoders and resolves, Integrated motion control, limit
switches, linear actuators, linear and rotary motion components, linear position sensing, motors (both
AC and DC motors), orientation position sensing, pneumatics and pneumatic components, positioning
stages, slides and guides, power transmission (mechanical), seals, slip rings, solenoids, springs.
Motors are the devices that provide the actual speed and torque in a drive system. This
family includes AC motor types (single and multiphase motors, universal, servo motors, induction,
synchronous, and gear motor) and DC motors (brush less, servo motor, and gear motor) as well as linear,
stepper and air motors, and motor contactors and starters.
In any electric motor, operation is based on simple electromagnetism. A current-

carrying conductor generates a magnetic field; when this is then placed in an external magnetic field, it
will experience a force proportional to the current in the conductor, and to the strength of the external
magnetic field. As you are well aware of from playing with magnets as a kid, opposite (North and
South) polarities attract, while like polarities (North and North, South and South) repel. The internal
configuration of a DC motor is designed to harness the magnetic interaction between a current-carrying
conductor and an external magnetic field to generate rotational motion.
Let's start by looking at a simple 2-pole DC electric motor (here red represents a magnet or winding
with a "North" polarization, while green represents a magnet or winding with a "South" polarization).
Every DC motor has six basic parts -- axle, rotor (a.k.a., armature), stator, commutator, field magnet(s),
and brushes. In most common DC motors (and all that Beamers will see), the external magnetic field is
produced by high-strength permanent magnets1. The stator is the stationary part of the motor -- this
includes the motor casing, as well as two or more permanent magnet pole pieces. The rotor (together
with the axle and attached commutator) rotates with respect to the stator. The rotor consists of windings
(generally on a core), the windings being electrically connected to the commutator. The above diagram
shows a common motor layout -- with the rotor inside the stator (field) magnets.
The geometry of the brushes, commutator contacts, and rotor windings are such that
when power is applied, the polarities of the energized winding and the stator magnet(s) are
misaligned, and the rotor will rotate until it is almost aligned with the stator's field magnets. As the
rotor reaches alignment, the brushes move to the next commutator contacts, and energize the next
winding. Given our example two-pole motor, the rotation reverses the direction of current through the
rotor winding, leading to a "flip" of the rotor's magnetic field, and driving it to continue rotating.
In real life, though, DC motors will always have more than two poles (three is a very common
number). In particular, this avoids "dead spots" in the commutator. You can imagine how with our
example two-pole motor, if the rotor is exactly at the middle of its rotation (perfectly aligned with the
field magnets), it will get "stuck" there. Meanwhile, with a two-pole motor, there is a moment where the
commutator shorts out the power supply (i.e., both brushes touch both commutator contacts
simultaneously). This would be bad for the power supply, waste energy, and damage motor components
as well. Yet another disadvantage of such a simple motor is that it would exhibit a high amount of
torque” ripple" (the amount of torque it could produce is cyclic with the position of the rotor).
So since most small DC motors are of a three-pole design, let's tinker with the workings of one via an
interactive animation (JavaScript required):
You'll notice a few things from this -- namely, one pole is fully energized at a time (but two
others are "partially" energized). As each brush transitions from one commutator contact to the next, one
coil's field will rapidly collapse, as the next coil's field will rapidly charge up (this occurs within a few
microsecond). We'll see more about the effects of this later, but in the meantime you can see that this is a
direct result of the coil windings' series wiring:
There's probably no better way to see how an average dc motor is put together, than by just
opening one up. Unfortunately this is tedious work, as well as requiring the destruction of a perfectly good
motor.
2.7
ESP 8266:
ESP8266 Features
 802.11 b/g/n protocol

 Wi-Fi Direct (P2P), soft-AP
 Integrated TCP/IP protocol stack
 Integrated TR switch, balun, LNA, power amplifier and matching network
 Integrated PLL, regulators, and power management units
 +19.5dBm output power in 802.11b mode
 Integrated temperature sensor
 Supports antenna diversity
 Power down leakage current of < 10uA
 Integrated low power 32-bit CPU could be used as application processor
 SDIO 2.0, SPI, UART
 STBC, 1×1 MIMO, 2×1 MIMO
 A-MPDU & A-MSDU aggregation & 0.4µs guard interval
 Wake up and transmit packets in < 2ms
 Standby power consumption of < 1.0mW (DTIM3)
The ESP8266 is a low-cost Wi-Fi chip with full TCP/IP stack and MCU (Micro Controller Unit) capability
produced by Shanghai-based Chinese manufacturer,
The chip first came to the attention of western makers in August 2014 with the ESP-01 module, made by a
third-party manufacturer, AI-Thinker. This small module allows microcontrollers to connect to a Wi-Fi
network and make simple TCP/IP connections using Hayes-style commands. However, at the time there
was almost no English-language documentation on the chip and the commands it accepted. The very low
price and the fact that there were very few external components on the module which suggests that it could
eventually be very inexpensive in volume, attracted many hackers to explore the module, chip, and the
software on it, as well as to translate the Chinese documentation.
The ESP8285 is an ESP8266 with 1 MB of built-in flash, allowing for single-chip devices capable of
connecting to Wi-Fi.
The successor to these module(s) is ESP32.
This is the series of ESP8266-based modules made by Espressif.
Active Form Dimensions

Name Pitch LEDs Antenna Shielded? Notes
pins factor (mm)
ESP- PCB FCC ID 2AC7Z-
18 0.1" 2×9 DIL No Yes 18 × 20
WROOM-02 trace ESPWROOM02
In the table above (and the two tables which follow), "Active pins" include the GPIO and ADC pins with
which you can attach external devices to the ESP8266 MCU. The "Pitch" is the space between pins on the
ESP8266 module, which is important to know if you are going to breadboard the device. The "Form factor"
also describes the module packaging as "2 x 9 DIL", meaning two rows of 9 pins arranged "Dual In Line",
like the pins of DIP ICs. Many ESP-xx modules include a small on-board LED which can be programmed
to blink and thereby indicate activity. There are several antenna options for ESP-xx boards including a
trace antenna, an on-board ceramic antenna, and an external connector which allows you to attach an
external Wi-Fi antenna. Since Wi-Fi communications generates a lot of RFI (Radio Frequency
Interference), governmental bodies like the FCC like shielded electronics to minimize interference with
other devices. Some of the ESP-xx modules come housed within a metal box with an FCC seal of approval
stamped on it. First and second world markets will likely demand FCC approval and shielded Wi-Fi
devices.
AI-Thinker modules
ESP-01 module
These are the first series of modules made with the ESP8266 by the third-party manufacturer AI-Thinker
and remain the most widely available. They are collectively referred to as "ESP-xx modules". To form a
workable development system they require additional components, especially a serial TTL-to-USB adapter
(sometimes called a USB-to-UART bridge) and an external 3.3 Volt power supply. Novice ESP-8266
developers are encouraged to consider larger ESP8266 Wi-Fi development boards like the Node MCU
which includes the USB-to-UART bridge and a Micro-USB connector coupled with a 3.3 Volt power
regulator already built into the board. When project development is complete, you may not need these
components and can consider using these cheaper ESP-xx modules as a lower power, smaller footprint
option for your production runs.
This is the series of ESP8266-based modules made by Espressif.
Active Form Dimensions

Name Pitch LEDs Antenna Shielded? Notes
pins factor (mm)
ESP- PCB FCC ID 2AC7Z-
18 0.1" 2×9 DIL No Yes 18 × 20
WROOM-02 trace ESPWROOM02
In the table above (and the two tables which follow), "Active pins" include the GPIO and ADC pins with
which you can attach external devices to the ESP8266 MCU. The "Pitch" is the space between pins on the
ESP8266 module, which is important to know if you are going to breadboard the device. The "Form factor"
also describes the module packaging as "2 x 9 DIL", meaning two rows of 9 pins arranged "Dual In Line",
like the pins of DIP ICs. Many ESP-xx modules include a small on-board LED which can be programmed
to blink and thereby indicate activity. There are several antenna options for ESP-xx boards including a
trace antenna, an on-board ceramic antenna, and an external connector which allows you to attach an
external Wi-Fi antenna. Since Wi-Fi communications generates a lot of RFI (Radio Frequency
Interference), governmental bodies like the FCC like shielded electronics to minimize interference with
other devices. Some of the ESP-xx modules come housed within a metal box with an FCC seal of approval
stamped on it. First and second world markets will likely demand FCC approval and shielded Wi-Fi
devices.
AI-Thinker modules
ESP-01 module
These are the first series of modules made with the ESP8266 by the third-party manufacturer AI-Thinker
and remain the most widely available. They are collectively referred to as "ESP-xx modules". To form a
workable development system they require additional components, especially a serial TTL-to-USB adapter
(sometimes called a USB-to-UART bridge) and an external 3.3 Volt power supply. Novice ESP-8266
developers are encouraged to consider larger ESP8266 Wi-Fi development boards like the Node MCU
which includes the USB-to-UART bridge and a Micro-USB connector coupled with a 3.3 Volt power
regulator already built into the board. When project development is complete, you may not need these
components and can consider using these cheaper ESP-xx modules as a lower power, smaller footprint
option for your production runs.
ESP8266 offers a complete and self-contained Wi-Fi networking solution, allowing it to either host the
application or to offload all Wi-Fi networking functions from another application processor.
When ESP8266 hosts the application, and when it is the only application processor in the device, it is able
to boot up directly from an external flash. It has integrated cache to improve the performance of the system
in such applications, and to minimize the memory requirements.
Alternately, serving as a Wi-Fi adapter, wireless internet access can be added to any microcontroller-based
design with simple connectivity through UART interface or the CPU AHB bridge interface.
The popularity of many of these "other boards" over the earlier ESP-xx modules is the inclusion of an on-
board USB-to-UART bridge (like the Silicon Labs' CP2102 or the WCH CH340G) and a Micro-USB
connector coupled with a 3.3 Volt regulator to provide both power to the board and connectivity to the host
(software development) computer commonly referred to as the console. With earlier ESP-xx modules,
these two items (the USB-to-Serial adaptor and a 3.3 Volt regulator) had to be purchased separately and be
wired into the ESP-xx circuit. Modern ESP8266 boards like the Node MCU boards are a lot less painful
and offer more GPIO pins to play with. Most of these "other boards" are based on the ESP-12E module, but
new modules are being introduced seemingly every few months.
CHAPTER3
SOFTWARE DEVELOPMENT:
4.1 Introduction:
In this chapter the software used and the language in which the program code is defined is mentioned and the
program code dumping tools are explained. The chapter also documents the development of the program for the
application. This program has been termed as “Source code”. Before we look at the source code we define the two
header files that we have used in the code.
4.2 Tools Used:
Figure 4.1 Keil Software- internal stages
Keil development tools for the 8051 Microcontroller Architecture support every level of software
developer from the professional applications
Step1: open the NEW Uversion project which is in the project option in the tool bar.
Step2: save the project with the required name and click save button
Step:3 select the device from NXP options the window which comes after saving the
project.
Step 4: select the LPC 2148 from the NXP options
Step 5: click yes in the startup code of LPC 2148 window

Step 6: select the new file from the file options to write the C code
Step 7: a new text file will open which we have to write the following code
Step 8 : write the code require for ur applications
Step 9:save the text file as .C file

Step 10: Add the saved .C file p by right clicking the Source Group Option1 and u will get
drop down window in that select Add Files to Group
Step 11: select the saved .c file from the window which is showing to add the file by
clicking the add tab.
Step 12: thus .C file is added to the Source Group is clearly seen
Step 13: press the icon that shows Rebuilt Target which proceeds for the Linking if the .C
file.
Step 14:Re-built All Target files for complete process of assembling->Compiling ->linking->
generating .hex file
Step 15: press the start/stop debug icon for debugging of the code which written.
Following are debugging windows press F11 for step by step debug
Window:1
Window2
CHAPTER 5. SOURCE CODE
5.1Source code
Source code:
#include<LPC2103.H>
#include<string.h>
#define GPIO_Port0s_IODIR IODIR

#define Set_Port0s IOSET
#define Clear_Port0s IOCLR
#define Port0_Set IOPIN
#define Logic_Low 0
#define Port0 0
#define Port1 1
/******************************************************************/
#define Motor (1<<29)
#define Outputs (Motor)

/******************************************************************/
/******************************************************************/
#define Soil (1<<5)
#define Inputs (Soil|Tank1|Tank2)

/******************************************************************/
#include "LCD.c"
#include "Serial_Uart0.c"
#include "GSM.c"
#include "adc0.c"
#include "App.c"
int PinStatus_Port(unsigned char ,unsigned int);

void Multichannel_Data_Display(void);
void LCD_Lable_display(void);
unsigned char x;
main()
{
GPIO_Port0s_IODIR = ~(Inputs);
GPIO_Port0s_IODIR = (LCD_Data|RS|EN|Outputs); //output=1
// input=0
while(1)
{
Get_ADC_Data();
ADC_Data_Dispaly();
Check_Sensors();
}
}
PinStatus_Port(unsigned char port,unsigned int pin)

{
if(port==0)
{
x=(Port0_Set& (1<<pin))?1:0;
}
void Project_Title(void)
{
Lcd_Data_Str(1,1,"iot Based ");
Lcd_Data_Str(2,1,"Irrigation System");
Delay(500);
Lcd_Data_Chr(0,0,0,LCD_CLEAR);
Lcd_Data_Str(2,1,"Soil:");
void Enable_UART0_Interrupt(void);
void Disable_UART0_Interrupt(void);
void Project_Title(void);
void LCD_Lable_display(void);
void Misscall_Message_Sending(void);
void Sending_Message_Structure(void);
void Data_For_Sending_Message(void);
void Multichannel_GetData(void);
void clear_mess_buffer(void);
void String_Compare(void);
unsigned char *GPS_Data_Link(void);
unsigned char mess[20],

mess_phone[16],s[5],misscall_phone[16],sim_reg[4],Message_string[13];
//misscall_phone="+919866200201"
unsigned char i,j,k=0,l,ptr,ptr1,cnt,cnt1;
unsigned char LCD_CLEAR=0X01,Misscall_flag,Message_Read_flag;
unsigned char *mmess_cpy;
unsigned char gps_link[4];
unsigned char Reg_Phno_flag;
//--------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----
/
*---------------------------------------------------------------------
-----------------------------
GSM Modem Initing functions
----------------------------------------------------------------------
----------------------------*/
void GSM_S900(void)
{
GSM_Modem_Init();
Sim_Registering();
Message_Deleting();
Registering_Mobile_NO();
}
/
*---------------------------------------------------------------------
-----------------------------
Modem Initing functions
----------------------------------------------------------------------
----------------------------*/
void GSM_Modem_Init(void)
{
Lcd_Data_Str(1,1,"GSM Initng ");
Lcd_Data_Str(1,1,"GSM Inited ");
Delay(gsm_delay);
Lcd_Data_Str(1,1,"SIM Chkng ");
}
/
*---------------------------------------------------------------------
-----------------------------
SIM Registering....
----------------------------------------------------------------------
----------------------------*/
void Sim_Registering(void)
{
UART0_TX_Str("AT+CREG?");
for(j=0;j<4;j++)
{
sim_reg[j]=UART0_RX_Chr();
}
for(j=0;j<4;j++)
{
Lcd_Data_Chr(1,2,ptr++,sim_reg[j]);
}
if(sim_reg[3]==0x31)
{
Lcd_Data_Str(1,1,"GSM Inited ");
Lcd_Data_Str(2,1,"SIM Registered ");
Delay(500);
Enable_UART0_Interrupt();
}
else
{
Lcd_Data_Str(2,1,"SIM Registering");
Delay(700);
Lcd_Data_Str(2,1," ");
goto start;
}
}
/
*---------------------------------------------------------------------
-----------------------------
Phone_No_Registering........
----------------------------------------------------------------------
----------------------------*/
void Registering_Mobile_NO(void)
{
Project_Title();
Delay(300);
Give_Misscall(Restg);
while(1)
{
if(Reg_Phno_flag==1)
{
Ph_no_Reg_Message_Sending();
Give_Misscall(Restd);
}
}
}
void Ph_no_Reg_Message_Sending(void)
{
Lcd_Data_Str(1,1," ");
Lcd_Data_Str(1,1,"Misscall ");
for(j=0;j<15;j++)
{
misscall_phone[j]=UART0_RX_Chr();
}
Lcd_Data_Str(2,1,"message sending");
UART0_TX_Str ("AT\r\n");
Delay(gsm_delay);
UART0_TX_Str ("AT+CMGS=");
UART0_TX_Str(misscall_phone);
UART0_TX_Chr(0x0D);
UART0_TX_Chr(0x0A);
while(UART0_RX_Chr()!='>');
UART0_TX_Str ("Your Phone No:");
UART0_TX_Str("Is Feeded Sucessfully");
while(UART0_RX_Chr()!='O');
while(UART0_RX_Chr()!='K');
Lcd_Data_Str(2,1," message sent ");
}
void Give_Misscall(unsigned char ph)
{
if(!ph)
{
Lcd_Data_Str(1,1,"Give Miscal ");
Lcd_Data_Str(2,1,"To Reg Phone No ");
}
if(ph)
{
Lcd_Data_Str(1,1,"Ur Ph No ");
Lcd_Data_Str(2,1,"Reg Successfully");
Delay(300);
}
}
/
*---------------------------------------------------------------------
-----------------------------
Chk_for_MissCall--->Cut_Call--->Send_Messg
----------------------------------------------------------------------
----------------------------*/
void Misscall_Detect()//unsigned char *mmess)
{
Disable_UART0_Interrupt();
Lcd_Data_Str(1,1," Misscall ");
Delay(500);
UART0_TX_Str("ATH");
for(j=0;j<15;j++)
{
misscall_phone[j]=UART0_RX_Chr();
}
Misscall_Message_Send(GPS_Data_Link());
void Sending_Message(unsigned char *mess,unsigned char *Gpslink)

{
Delay(gsm_delay);
UART0_TX_Chr(0x0D);
UART0_TX_Chr(0x0A);
UART0_TX_Str(mess);
UART0_TX_Str(Gpslink);
Delay(gsm_delay);
UART0_TX_Chr(0x1a);
}
/
*---------------------------------------------------------------------
-------------------------------------
MissCall_Sending_Message_Structure
----------------------------------------------------------------------
-------------------------------------*/
void Misscall_Message_Send(unsigned char *mmdata)

{
Delay(gsm_delay);
UART0_TX_Chr(0x0D);
UART0_TX_Chr(0x0A);
UART0_TX_Str(mmdata);
UART0_TX_Chr(0x1a);
}
/
*---------------------------------------------------------------------
-----------------------------
*****************************************************/
void Project_Title(void);
int PinStatus_Port(unsigned char ,unsigned int);
void Check_Sensors(void);
unsigned char TEmt_flag=1,TFull_flag=1,TankWater;
void Check_Sensors(void)
{
if(PinStatus_Port(0,5)==0)
{
Lcd_Data_Str(2,6,"Wet");
Clear_Port0s=Motor;
Misscall_Message_Send("GSM Based Irrigation System\r\n Soil Wet
Condition");
}
if((PinStatus_Port(0,5)==1))
{
Lcd_Data_Str(2,6,"Dry");
if((TankWater==1))
{
if(Volt_Nok==0)
{
Set_Port0s=Motor;
}
if(Volt_Nok==1)
{
Clear_Port0s=Motor;
}
}
Misscall_Message_Send("GSM Based Irrigation System\r\n Soil Dry
Condition");
}
/* Water Tank Condition */
if(PinStatus_Port(0,6)==0&&PinStatus_Port(0,7)==0)
{
Lcd_Data_Str(2,10,"WTank:F");
if(TFull_flag==1)
{
Condition");
}
}
{
Lcd_Data_Str(2,10,"WTank:M");
}
{
TankWater=0;
Lcd_Data_Str(2,10,"WTank:E");
Clear_Port0s=Motor;
Condition");
}
#define LCD_Data (0xFF)<<16
#define RS (0xFFFFFFFF)<<31
#define EN (1<<30)
unsigned char LCD_C=0,LCD_D=1,Wr_Data=1;
int Delay(unsigned int );
void Lcd_Init(void);
int Lcd_Data_Chr(unsigned char ,unsigned char ,unsigned char
,unsigned char);
int Lcd_Data_Str(unsigned char ,unsigned char ,unsigned char temp[]);
int Lcd_Wr(unsigned char );
/*********************************************************************
************
Lcd_Data_(0-cmd:1-data,line no,position,char to disp on LCD);
**********************************************************************
***********/
void Lcd_Init(void)
{
unsigned char LCD_2_LINE=0x38;

unsigned char LCD_CLEAR=0X01;
unsigned char DISPLAY_ON=0X0E;
unsigned char LCD_CURSOR_OFF=0x0C;
Lcd_Data_Chr(0,0,0,LCD_2_LINE);
Lcd_Data_Chr(0,0,0,DISPLAY_ON);
Lcd_Data_Chr(0,0,0,LCD_CURSOR_OFF);
Lcd_Data_Chr(0,0,0,LCD_CLEAR);
Lcd_Data_Chr(unsigned char RS1 ,unsigned char line,unsigned char

position,unsigned char temp1)
{
unsigned char x;
if(RS1==0)
{
Set_Port0s= (temp1<<16)&LCD_Data;
Lcd_Wr(LCD_C);
if(RS1==1)
{
if(line==1)
{
x=0x7f+position;
Set_Port0s= (x<<16)&LCD_Data;
Lcd_Wr(LCD_C);
if(line==2)
{
x=0xbf+position;
Set_Port0s= (x<<16)&LCD_Data;
Lcd_Wr(LCD_C);
}
Set_Port0s= (temp1<<16)&LCD_Data;
Lcd_Wr(LCD_D);
Delay(5);
}
Lcd_Data_Str(unsigned char line1,unsigned char position,unsigned char

temp[])
{
unsigned int p;
unsigned char t;
if(line1==1)
{
p=0x7f+position;
Lcd_Data_Chr(0,0,0,(Set_Port0s=(p<<16)&LCD_Data));
if(line1==2)
{
p=0xbf+position;
Lcd_Data_Chr(0,0,0,(Set_Port0s=(p<<16)&LCD_Data));
}
while(temp[t]!='\0')
{
Set_Port0s= (temp[t]<<16)&LCD_Data;
Lcd_Wr(LCD_D);
t++;
}
Lcd_Wr(unsigned char r)
{
if(r==1)
{
Set_Port0s= RS;
Set_Port0s= EN;
Delay(1);
Clear_Port0s= EN;
}
if(r==0)
{
Clear_Port0s= RS;
Set_Port0s= EN;
Delay(1);
Clear_Port0s= EN;
Delay(unsigned int time)

{
unsigned int i,j;
for(i=0;i<time;i++)
for(j=0;j<25000;j++);
}
CONCLUSION
The project “IOT BASED IRRIGATION SYSTEM” has been successfully

designed and tested. Integrating features of all the hardware components used have
developed it. Presence of every module has been reasoned out and placed carefully thus
contributing to the best working of the unit. Secondly, using highly advanced IC’s and
with the help of growing technology the project has been successfully implemented.
CHAPTER 7. BIBILOGRAPHY, REFERENCES
BIBILOGRAPHY
1. WWW.MITEL.DATABOOK.COM
2. WWW.ATMEL.DATABOOK.COM
3. WWW.FRANKLIN.COM
4. WWW.KEIL.COM
en.wikipedia.org/wiki/ZigBee
WWW .ZIGBEE .ORG /
www.nxp.com/documents/user_manual/UM1 http://www.futurlec.com/GPS.shtml013
HTTP :// EN .WIKIPEDIA .ORG /WIKI /G LOBAL _P OSITIONING _S YSTEM9. PDF
http://electronics.howstuffworks.com/gadgets/travel/gps.htm
http://en.wikipedia.org/wiki/GSM
http://burnsidetelecom.com/whitepapers/gsm.pdf
http://www.itu.int/osg/spu/ni/3G/casestudies/GSM-FINAL.pdf
REFERENCES
1. ARM-systemonchip-architecture by Steve furber.
2. ARM-user manual UM10114.
3. ARM System Developers Guide by Andrew N.SLOSS
4. "Power Electronics” by M D Singh and K B Khanchandan
5. "Linear Integrated Circuits” by D Roy Choudary & Shail Jain
6. "Electrical Machines” by S K Bhattacharya
7. "Electrical Machines II” by B L Thereja
8. www.8051freeprojectsinfo.com

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INDEX

CHAPTER2. DESCRIPTION OF HARDWARE COMPONENTS

2.2 POWER SUPPLY

CHAPTER3. CIRCUITS AND THEIR OPERATION

CHAPTER 5. SOURCE CODE

IOT BASED IRRIGATION SYSTEM

1.1 .1 EMBEDDED SYSTEMS

1.1.2 OBJECTIVE OF THE PROJECT:

HARDWARE REQUIREMENTS: SOFTWARE REQUIREMENTS:

DESCRIPTION OF HARDWARE COMPONENTS

The LPC2101/2102/2103 microcontrollers are based on a 16-bit/32-bit

 EmbeddedICE RT offers real-time debugging with the on-chip RealMonitor software.

 Vectored interrupt controller with conÞgurable priorities and vector

 Up to thirty-two 5 V tolerant fast general purpose I/O pins.

 Up to 13 edge or level sensitive external interrupt pins available.

 Individual enable/disable of peripheral functions as well as peripheral clock scaling for

 Processor wake-up from Power-down mode via external interrupt or RTC.

Table 1: Ordering information

plastic low proÞle quad ßat package;

plastic low proÞle quad ßat package;

LPC2103FA44 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2

3.1 Ordering options

Table 2: Ordering options

LPC2102FBD48 16 kB 4 kB 8 inputs 40 to +85

LPC2103FBD48 32 kB 8 kB 8 inputs 40 to +85

LPC2103FA44 32 kB 8 kB 8 inputs 40 to +85

HIGH SPEED SYSTEM

P0[31:0] GENERAL 8 kB PLL FUNCTIONS

PURPOSE I/O BOOT ROM ARM7TDMI-S

AHB BRIDGE clock

ARM7 local bus CONTROLLER

(Advanced High-performance Bus)

2 kB/4 kB/ 8 kB/16 kB/ AHB TO APB

I CAP2.0 Ñ Capture input for Timer 2, channel 0.

I CAP2.1 Ñ Capture input for Timer 2, channel 1.

I CAP2.2 Ñ Capture input for Timer 2, channel 2.

O MAT3.3 Ñ PWM output 3 for Timer 3.

 The standard 32-bit ARM set.

6.2 On-chip ßash program memory

6.3 On-chip static RAM

4.0 GB 0xFFFF FFFF

3.0 GB 0xC000 0000

RESERVED ADDRESS SPACE

0x8000 0000 0x7FFF FFFF

Non-vectored IRQs have the lowest priority.

Pin connect block

6.7 Fast general purpose parallel I/O

 LPC2101/2102/2103 introduce accelerated GPIO functions over prior LPC2000 devices:

 All GPIO registers are byte addressable.

 Entire port value can be written in one instruction.

 Direction control of individual bits.

 Separate control of output set and clear.

 All I/O default to inputs after reset.

10-bit A/D converter

 Optional conversion on transition on input pin or Timer Match signal.

Transmission FIFO control enables implementation of software (XON/XOFF) ßow control

The LPC2101/2102/2103 each contain two I2C-bus controllers.

o Compliant with standard I2C-bus interface.

o Programmable clocks allow versatile rate control.

o Bidirectional data transfer between masters and slaves.

o Multi-master bus (no central master).

o Arbitration between simultaneously transmitting masters without corruption of serial data