(SSUET/QR/111)

SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY

ELECTRONIC ENGINEERING DEPARTMENT
B.SC. ELECTRONIC ENGINEERING TECHNOLOGY PROGRAM

COURSE INFORMATION SHEET

Session: Fall2021
Course Title: Electronic Devices and Technology
Course Code: ELT-224L
Credit Hours: 1
Semester: 3rd
Pre-Requisites: Basic Electronics
Instructor Name: Engr.Bilal Ahmed Bhatti
Email and Contact Information: babhatti@ssuet.edu.pk
Whats App Group
Office Hours: 9:00am to 05:00p.m
Mode of Teaching: Synchronous/Asynchronous/ Hybrid/Blended

COURSE OBJECTIVE:
This lab emphasizes to perform experiment on different types of transistors (BJT/FET/Op-
Amp/Oscillators) that shows the behavior of Electronic devices & circuits. The student will be able to
analyze the AC / DC behavior of BJTS / FETS using different Biasing techniques.

COURSE OUTLINE:
Small signal analysis of BJTs and FETs along with their different configurations. Transistor modeling
(Hybrid equivalent model, re model).Frequency response of transistors.Darlington connection and various
classes of BJT amplifiers, Introduction to Op-Amps, Various types of operational amplifier circuits and
topologies, Open and close loop gains, Non-linear applications of Op-amp: Comparator, Schmitt trigger,
Window comparator, Precision rectifier, Clamper, peak detector Sample and hold circuit, ADC and DAC,
Oscillators and its various types

COURSELEARNING OUTCOMES (CLOs) and its mapping with Program Learning Outcomes
(PLOs):

CLO Bloom’s
Course Learning Outcomes (CLOs) PLOs
No. Taxonomy
Assemble the circuits in order to understand PLO_3
P4
1 methodology and operation behind Electronic (Design/development of
(Mechanism)
Devices and Circuits. solution)

2
Explain the basic principles behind PLO_10 A4
Electronic Devices and Circuits. (Communication) (Organization)

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 (SSUET/QR/111)
SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
ELECTRONIC ENGINEERING DEPARTMENT
B.SC. ELECTRONIC ENGINEERING TECHNOLOGY PROGRAM

BROAD ENGINEERING TECHNOLOGY ACTIVITY:

Broad Engineering Technology Included: Yes
Activity Nature and details of Broad Engineering Technology
Activity (BTA):
It will be given as Subject Project assigned to 2-4
students in a group.
(BTA) will be based on CLO_1. To investigate the
problem, students have to use in-depth knowledge of
combinational and sequential circuits and diverse
resources are required

RELATIONSHIP BETWEEN ASSESSMENT TOOLS AND CLOS:

Assessment Tools CLO-1(40) CLO-2(10)

Lab Manual 37.5% (15) -

Viva/Demonstration 30% (12) 30% (03)

Lab Exam 32.5% (13) 70% (07)

GRADING POLICY:

Assessment Tools Percentage Marks

Lab Manual 30% 15
Viva/Demonstration 30% 15
Lab Exam 40% 20
TOTAL 100% 50

Recommended Book:
● Robert Boylestad, Electronic Devices & Circuits, 11th Edition, Publication year 2017,
ISBN: 9002-34867564-21
Reference Books:
● Floyd, Electronic Devices, 4th Edition
● S. Salivahana, Electronic Devices & Circuits, 2nd Edition

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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
ELECTRONIC ENGINEERING DEPARTMENT
B.SC. ELECTRONIC ENGINEERING TECHNOLOGY PROGRAM

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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
ELECTRONIC ENGINEERING DEPARTMENT
B.SC. ELECTRONIC ENGINEERING TECHNOLOGY PROGRAM

COURSE BREAKDOWN WITH LAB SYNCHRONIZATION:

- Both sides same Colours: Lab is synchronized with the topic
- Red Color: Lab is not synchronized (conducted before theory)
- No Color: Lab is to introduce new hardware or software skill /
Open Ended Lab / Lab is relevant to a topic taught in
Pre-requisite and required for upcoming labs.
Week Topics
No. Laboratory Synchronization
1 Introduction to transistor, applications
,advantages and disadvantages of transistors,
To follow the process to identify
Important parameters of a two port system, Transistor
the type of transistor (NPN & PNP)
Modeling, re Transistor model (CE configuration, CB
& find its correct pin configuration
configuration & CC configuration, BJT small
signal analysis, Fixed bias configuration,
2 CE Emitter stabilized bias (bypassed & un bypassed), To reproduce BJT circuit as a
Voltage Divider bias(bypassed and un- bypassed switch
3 Emitter Follower bias, Common base configuration,
Effect of RS& RL using System Approach: Two Port To follow common emitter
System, Effect of Load Impedance (RL), AC Load configuration of BJT
Line, Effect of Source Impedance (Rs) , Combined
Effect of RS and RL
4 Hybrid equivalent model and h-parameters, Reproduce the BJT Fixed biased
Approximate Hybrid equivalent model, Fixed bias configuration in order to perform
configuration, DC analysis

5 Voltage Divider configuration, Emitter Follower

bias, Common base configuration, Fixed bias, Reproduce the BJT emitter
Emitter stabilized bias (bypassed and Un- bypassed), stabilized biased configuration in
Field Effect Transistor, Construction and order to perform DC analysis
characteristics of JFET, Transfer characteristics.
6 Depletion type MOSFET, Enhancement type
MOSFET , FET DC Biasing, Fixed bias
Reproduce the BJT feedback
configuration, Self bias configuration, Voltage
biased configuration in order to
Divider bias, FET Amplifier, FET small signal
perform DC analysis
model, Mathematical model of gm, Plotting gm VS
VGS, FET input impedance, FET output impedance
7 FET AC equivalent circuit, JFET Fixed bias Open Ended Lab
configuration, JFET Self bias configuration with
Un bypassed Rs, JFET Voltage Divider
configuration, JFET Source Follower (Common
Drain) configuration
8 Midterm
9 JFET Common Gate Configuration, Designing FET
Amplifier networks configuration, Sketch Transfer Characteristic of
N-channel JFET

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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
ELECTRONIC ENGINEERING DEPARTMENT
B.SC. ELECTRONIC ENGINEERING TECHNOLOGY PROGRAM

10 BJT and JFET Frequency Response, Logarithms,

Decibels, General Frequency consideration Low Display the output of DC analysis
Frequency analysis----Bode plot, Low Frequency of self-bias configuration of N-
response of BJT Amplifier, Low channel JFET
Frequency response of FET Amplifier
11 Miller Effect Capacitance, High Frequency Measure the quantities ID, VGS, VDS
response of BJT Amplifier, High Frequency be able to do DC analysis of
response of FET Amplifier, Multistage common source, voltage divider
Frequency Effects bias JFET amplifier.
12 Power Amplifiers, Amplifier types, Amplifier types,
Amplifier efficiency
Measure the quantities ID, VGS, VDS
be able to do DC analysis of
common drain (source
follower) N-channel JFET amplifier

13 Series fed class A Amplifier, Transformer coupled

class A Amplifier, Class B Amplifier operation, Follow the circuit of common
Class B Amplifier circuits (Transformer coupled emitter BJT amplifier to find the
Push-Pull circuits, Complementary-Symmetry frequency response.
circuits, Quasi- Trace the Lower critical frequency
Complementary Push-Pull Amplifier and Upper critical frequency

14 Amplifier distortion, Class C Amplifier, Class D Reproduce two stage BJT

Amplifier transistor amplifiers and trace the
AC analysis at both stages of
cascaded transistor.
15 Compound Configurations: Cascade
connections, Darlington connection (AC Equivalent
Open Ended Lab
Circuit), AC input impedance, AC
Voltage gain, AC Current gain.
16 Differential Amplifiers (DC bias, AC operation, Final Viva
Single ended AC Voltage gain, double ended AC
voltage gain and common mode AC voltage
gain

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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
ELECTRONIC ENGINEERING DEPARTMENT
B.SC. ELECTRONIC ENGINEERING TECHNOLOGY PROGRAM

LAB PLAN
Course Title: Electronic Devices and Technology
Course Code: ELT-224L

Week Lab No. Objective Required Corresponding

No. Reading CLO and PLO
1 12-10-2021 To follow the process to identify the type
to of transistor (NPN & PNP) & find its
16-10-2021 correct pin configuration
2 18-10-2021
to To reproduce BJT circuit as a switch
23-10-2021
3 25-10-2021 To follow common emitter configuration
to of BJT
30-10-2021
01-11-2021 Reproduce the BJT Fixed biased
to configuration in order to perform DC
4 06-11-2021 analysis

5 08-11-2021 Reproduce the BJT emitter feedback

to biased configuration in order to perform
13-11-2021 DC analysis
6 15-11-2021 Reproduce the BJT feedback biased
to configuration in order to perform DC
20-11-2021 analysis
7 22-11-2021 Open Ended Lab
to
27-11-2021
8 Mid Term Examination
(29-11-2021 to 04-12-2021)
9 06-12-2021
Sketch Transfer Characteristic of N-
to
11-12-2021 channel JFET
10 13-12-2021
Display the output of DC analysis of self-
to
18-12-2021 bias configuration of N-channel JFET
11 20-12-2021 Measure the quantities ID, VGS, VDS be
to able to do DC analysis of common source,
25-12-2021 voltage divider bias JFET amplifier.
12 27-12-2021 Measure the quantities ID, VGS, VDS be
to able to do DC analysis of common drain
01-01-2022 (source
follower) N-channel JFET amplifier
13 03-01-2022 Follow the circuit of common emitter BJT

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 (SSUET/QR/111)
SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
ELECTRONIC ENGINEERING DEPARTMENT
B.SC. ELECTRONIC ENGINEERING TECHNOLOGY PROGRAM

to amplifier to find the frequency response.

08-01-2022 Trace the Lower critical frequency and Upper
critical frequency
14 10-01-2022 Reproduce two stage BJT transistor
to amplifiers and trace the AC analysis at both
15-01-2022 stages of cascaded transistor.
15 Make Up
Lab may be
adjusted Open Ended Lab
before
Midterm
16 Lab Examination
(17-01-2022 to 22-01-2022)

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