Accellera-SystemC-Tutorial-2014 - Case Study
Accellera-SystemC-Tutorial-2014 - Case Study
Accellera-SystemC-Tutorial-2014 - Case Study
sc_vector
sc_event_or_list
sc_writer_policy
reset_signal_is
reset() and kill()
Child(sc_module_name n)
: port_vec("port_vec", 4) Elements are named Vector-of-ports
{ ...
struct Top: sc_module
{
sc_vector< sc_signal<int> > sig_vec;
Child* c;
Top(sc_module_name n)
: sig_vec("sig_vec", 4) Size passed to ctor
{
c = new Child("c");
c->port_vec.bind(sig_vec); Vector-to-vector bind
}
...
3 © 2014 Doulos March 3, 2014
sc_vector of Modules
struct Child: sc_module Module
Module
{ m2
Module
m2
Module
sc_out<int> p; m2
Module
m2
Module
... m2
Module
struct Top: sc_module m2
m2
Child
{
Anything derived from sc_object
Top(sc_module_name n)
: mod_vec("mod_vec")
, sig_vec("sig_vec") Elements are named
{
mod_vec.init(4);
sig_vec.init(4); Size deferred
for (int i = 0; i < 4; i++)
mod_vec[i].p.bind(sig_vec[i]);
}
...
4 © 2014 Doulos March 3, 2014
sc_vector methods sc_object
name()
kind()
struct M: sc_module
{
sc_vector< sc_signal<int> > vec; sc_vector_base
size()
M(sc_module_name n) get_elements()
: vec("vec", 4) {
SC_THREAD(proc)
} T
sc_vector
void proc() {
sc_vector(nm, N)
for (unsigned int i = 0; i < vec.size(); i++) init(N)
vec[i].write(i); ~sc_vector()
wait(SC_ZERO_TIME); begin()
end()
T& operator[]()
sc_vector< sc_signal<int> >::iterator it; T& at()
for (it = vec.begin(); it != vec.end(); it++)
cout << it->read() << endl; bind()
...
it = m1->port_vec.bind( m3->export_vec.begin(),
m3->export_vec.end(),
it );
1st unbound element Start binding here
6 © 2014 Doulos March 3, 2014
Constructor Arguments
struct Child: sc_module
{
Child(sc_module_name n, int a, bool b); Module ctor has args
...
sc_vector<Child> child_vec;
child_vec.init(4, creator_func);
sc_vector
sc_event_or_list
sc_writer_policy
reset_signal_is
reset() and kill()
sc_vector
sc_event_or_list
sc_writer_policy
reset_signal_is
reset() and kill()
M(sc_module_name n) : interrupt("interrupt", 4) {
SC_HAS_PROCESS(M);
SC_THREAD(proc1);
SC_THREAD(proc2);
}
sc_vector
sc_event_or_list
sc_writer_policy
reset_signal_is
reset() and kill()
sc_spawn_options opt;
opt.reset_signal_is(reset, active_level);
opt.async_reset_signal_is(reset, true);
handle.reset();
handle.sync_reset_on();
...
handle.sync_reset_off();
sc_vector
sc_event_or_list
sc_writer_policy
reset_signal_is
reset() and kill()
}
...
17 © 2014 Doulos March 3, 2014
Unwinding the Call Stack
void target()
{
q = 0;
while (1)
{
try {
wait(ev); reset() kill()
++q;
}
catch (const sc_unwind_exception& e)
{
sc_assert( sc_is_unwinding() );
if (e.is_reset()) cout << "target was reset";
else cout << "target was killed";
}
...
18 © 2014 Doulos March 3, 2014
Unwinding the Call Stack
void target()
{
q = 0;
while (1)
{
try {
wait(ev); reset() kill()
++q;
}
catch (const sc_unwind_exception& e)
{
sc_assert( sc_is_unwinding() );
if (e.is_reset()) cout << "target was reset";
else cout << "target was killed";
proc_handle.reset();
Resets some other process
throw e;
}
... Must be re-thrown
SC_METHOD(reset_handler);
dont_initialize();
sensitive << t.reset_event();
SC_METHOD(kill_handler);
dont_initialize();
sensitive << t.terminated_event(); void target()
{
...
void calling() while (1)
{ {
wait(10, SC_NS); wait(ev);
t.reset(); ...
wait(10, SC_NS); }
t.kill(); }
...
20 © 2014 Doulos March 3, 2014
For Further Information
http://www.doulos.com/knowhow/systemc/
http://www.accellera.org/community/systemc/
http://www.accellera.org/downloads/standards/
http://standards.ieee.org/getieee/1666/download/1666-2011.pdf
2G 3G 4G
Hardware Software
System-On-Chip System-On-Board
Baseband, Radio, and Radio Unit and Digital Unit
Control SoCs
System-In-Cabinet
RBS 6000 series of multi-standard base stations
System
HW IP cores D&V
IP
Hardware Software
HW Chip D&V
HW Board D&V
THE DESIGN
PROCESS AS A SW TOOLS
FLOW OF
ACTIVITIES
Platform & App
POTENTIAL ADVANTAGES
8 © 2014 Ericsson AB March 3, 2014
Board
Functional
LT model AT model RTL model
model
(SystemC) (SystemC) (VHDL/…)
(C++)
HW emulation
Platform SW dev.
Virtual prototyping Prototype ver.
SW Tools
Appl. SW dev. (RANs)
Platform SW Application SW
(C/C++) (C/C++)
Projects
Methodology project – Apollo 2010
Pilot project TLM for early SW development – Helios 2010
Pilot project TLM for Architectural exploration – Vulcan 2011
Sharp project TLM for early SW development – Ghost 2012
Sharp project TLM for early HW verification – Atom 2012
Master thesis
Accuracy of AT TLM models. How to compare RTL and TLM.
TLM for virtual platforms
TLM for verification
SW statistics collection from TLM for HW exploration and dimensioning
Today…
Ericsson uses a TLM-2.0
LT based virtual platform
for SW development
- Hundreds of users
- SW operates many months
before chip and board is
ready
- Replaced legacy Virtual
platform
DspTools Core
TCP/IP socket
Debug Attribute Execute Factory
QSim
Legacy
Virtual platform
SVPIF server
SVPIF client
In-house CCI framework
p p
e
e
r ASIC r
i ASIC i
p ASIC p
h
h
e
(TLM2) e
r r
a a
l l
Test framework I/O
s s
support
FPGA (TLM2)
SVPIF server
Today…
TLM-2.0 AT models used for
HW IP level performance
exploration
TLM-2.0 LT models used at
system-level to acquire SW
load models
Evaluation
Performance Evaluation is purpose
to quantify the services
given by the system as a
function of scenarios Exploration Dimensioning
- Quantifying services = Metric or
performance metric
- Scenarios = Stimuli or load Stimuli Performance evaluation Metric
Goals are:
Performance dimensioning
- Assure the selected system meets
performance goals.
- Metric high accuracy HW SW HW/SW
Performance exploration
- Performance evaluation of multiple
HW IP System-On-Chip System-On-Board System-In-Cabinet
systems that are then compared.
- Metric medium accuracy (Relative
comparison)
0.8
0.6
0.4
0.2
0
AT Model vs. Original RTL
0 20 40 60 80 100
0.4
0.2
0
0 20 40 60 80 100
Today…
TLM-2.0 LT models are
used as references at HW
IP level
TLM-2.0 LT models used
as development platform
for chip level verification
Advantages
- TLM available early and used as stable development platform for SW driven
test cases.
- Develop and run design loop is fast.
27 © 2014 Ericsson AB March 3, 2014
TLM in chip level verification
Software driven Verification
Same verification platform for all abstractions, TLM, RTL, Emulation and HW.
This setup allows us as well to verify and debug software.
TLM model used for test software development in this setup
The verification environment supports both test software development and design verification.
Possibilities to run real software will improve our confidence and pave the wave for a smooth software integration.
Regressions are run on all abstractions
SoC SoC
SoC SoC
HW HW
TLM RTL
Emulation Prototype
Loosely
Timed For
Timing
Abstraction Level
How can we move the REF model to low abstraction level for
achieving the verification goal?
How can we maximize the model reusability?
Abstraction Level
32 © 2014 Ericsson AB March 3, 2014
Summarize LT and AT
APP PLATFORM
LT adds value to several user LT SW SW
DEV DEV
groups in HW and SW.
100
LT -
Verification requires refined LT 1000 HW
VERIFIERS
but not AT users
Introduction
Language standard overview
AMS models of computation
Dynamic and reactive extensions in SystemC AMS 2.0
Example: DC motor control with Pulse Width Modulator
Conclusions
2
SystemC AMS objectives
3
SystemC AMS applications
Image courtesy of STMicroelectronics
Automotive systems
4
SystemC AMS – History
1999: Open SystemC Initiative (OSCI)
announced
2000: SystemC 1.0 released ~2000: First C-based AMS initiatives
(sourceforge.net) (AVSL, MixSigC)
2002: OSCI SystemC 1.0.2 2002: SystemC-AMS study group started
2005: IEEE Std 1666-2005 LRM 2005: First SystemC-AMS PoC
released by Fraunhofer
2005: SystemC Transaction level
modeling (TLM) 1.0 released 2006: OSCI AMSWG installed
2007: SystemC 2.2 released
2008: SystemC AMS Draft 1 LRM
2009: SystemC TLM 2.0 standard
2010: SystemC AMS 1.0 LRM standard
2009: SystemC Synthesizable Subset
Draft 1.3 2010: SystemC AMS 1.0 PoC released
by Fraunhofer IIS/EAS
2011: IEEE Std 1666-2011 LRM
2012: SystemC AMS 2.0 draft standard
2012: SystemC 2.3 PoC released by
2013: SystemC AMS 2.0 LRM standard
Accellera Systems Initiative
2013: SystemC AMS 2.0 PoC test version
Specification
RF
SoC
Functional AMS
Digital
Interface
6
Example: Communication System
Receiver
Serial Modulator/
ADC Host
Interface demod.
processor
DSP
Antenna
Calibration & Control Micro-
front-end
controller Imaging
Memory
DSP
Transmitter
DAC
to all blocks
High
Power Audio Speed
RF Temp. Oscillator Clock Manage- DSP Serial
detector sensor Generator ment Interface
7
Industry requirements and needs
8
SystemC AMS advantages
Model abstractions
Discrete-time Continuous-time
static non-linear dynamic linear
Modeling formalism
Electrical Linear
Timed Data Flow (TDF) Linear Signal Flow (LSF)
Networks (ELN)
10
AMS models in Virtual Prototypes realistic?
Yes, as long as you use the right language and abstraction method
SystemC AMS
ELN LSF TDF
extensions
Verilog-AMS, electrical
signal real-
VHDL-AMS flow number
virtual
Verilog-A electrical
prototyping
top-level
Fast-spice electrical verification
circuit/block
Spice verification
[1] M. Barnasconi, SystemC AMS Extensions: Solving the Need for Speed,
http://www.accellera.org/community/articles/amsspeed/
11
SystemC AMS extensions LRM
12
SystemC AMS User’s Guide
13
SystemC AMS language features
Mixed-Signal Virtual Prototypes
written by the end user
14
SystemC AMS methodology elements
Support design refinement using different models of computation
- Timed Data Flow (TDF) - efficient simulation of discrete-time behavior
- Linear Signal Flow (LSF) - simulation of continuous-time behavior
- Electrical Linear Networks (ELN) - simulation of network topology & primitives
Using namespaces
- Clearly identify the used model of computation
- Unified and common set of predefined classes, (converter) ports and signals
Examples
- Module sca_tdf::sca_module sca_lsf::sca_module
- Input port sca_tdf::sca_in sca_lsf::sca_in
- Output port sca_tdf::sca_out sca_lsf::sca_out
- Signals sca_tdf::sca_signal sca_lsf::sca_signal
- Nodes (electrical only) sca_eln::sca_node
- Terminal (in/output port, electrical only) sca_eln::sca_terminal
15
Timed Data Flow (TDF)
V(t)
t
A B outC
16
Linear Signal Flow (LSF)
LSF port LSF module LSF signal LSF equation system
d
x(t) k1 k y(t)
dt
x(t)
k2
t
17
Electrical Linear Networks (ELN)
ELN equation system ELN node ELN terminal
va C vb
18
Dynamic Timed Data Flow modeling
This requires a dynamic and reactive Timed Data Flow modeling style
- Basically introduce variable time step instead of fixed/constant time step
19
Example: DC motor control
difference PI controller PWM Driver + DC motor
iref k vdrv
kp + i out
s
h0
imeas s
1+
ω0
20
DC motor control loop behavior
10
imeas (t) iref
8
2 3
6
2 1 4 1
t_ramp
0 t_duty t/sec
0 0.01 0.02 0.03 0.04 0.05t_period
0.06 0.07 0.08 0.09 0.1
vdrv (t) 1
0.5
0 t/sec
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
21
Example of Pulse Width Modulator (1)
// pwm_dynamic.h
#include <cmath>
#include <systemc-ams>
SCA_TDF_MODULE(pwm) // for dynamic TDF, we can use the same helper macro to define the module class
{
sca_tdf::sca_in<double> in;
sca_tdf::sca_out<double> out;
void set_attributes()
{
does_attribute_changes(); // module allowed to make changes to TDF attributes
accept_attribute_changes(); // module allows attribute changes made by other modules
}
22
Example of Pulse Width Modulator (2)
if ( t_pos < t_ramp ) {
// rising edge
request_next_activation( t_ramp - t_pos, sc_core::SC_SEC );
1
} else if ( t_pos < t_ramp + t_duty ) {
// plateau
request_next_activation( ( t_ramp + t_duty ) - t_pos, sc_core::SC_SEC ); 2
} else if ( t_pos < t_ramp + t_duty + t_ramp ) {
// falling edge
request_next_activation( ( t_ramp + t_duty + t_ramp ) - t_pos, sc_core::SC_SEC ); 3
} else {
// return to initial value
request_next_activation( t_period - t_pos, sc_core::SC_SEC ); 4
}
}
2 3
void processing()
{
... // PWM behavior
1 4 1
}
t_ramp
t_duty
private:
t_period
... // member variables
};
23
TDF vs. Dynamic TDF comparison
TDF model of t_step t_ramp t_period Time accuracy #activations
computation variant (ms) (ms) (ms) (ms) per period
0.01
Conventional TDF 0.05 5.0 0.01 ( = t_step) 500
(fixed)
defined by
Dynamic TDF variable 0.05 5.0 4
sc_set_time_resolution()
24
Summary and outlook
www.accellera.org
www.accellera.org/downloads/standards/systemc/ams
www.accellera.org/community/articles/amsspeed
www.accellera.org/community/articles/amsdynamictdf
www.systemc-ams.org
26
Thank you
Case Studies in SystemC
What is UVM-Connect?
UVM-Connect primer
Summary
2 March 3, 2014 © 2014 Mentor Graphics Corp.
The case for hybrid testbenches
Mounting use of TLM 2 as the common interconnect for multi-language HVL
testbench environments:
- TLM-2 standard is already “baked in” to IEEE 1666 SystemC and SV-UVM standards
- Open-source public donations for “cross language connectivity fabric” are TLM-2
based and are already out there:
- UVM-Connect - from Mentor Graphics
- UVM-ML - from Accellera MLWG
Cable Box TV
HDMI
SV/UVM SystemC
6 March 3, 2014 © 2014 Mentor Graphics Corp.
What is UVM-Connect?
Trans-language TLM connections
• Connect SysC & SV-UVM models using
standard TLM1, TLM2 interface ports TLM1
SysC SV-UVM
• TLM GP handled automatically
• Access and control UVM from SystemC
via command API
• Messaging, configuration, and factory TLM2
methods supported SysC SV-UVM
• Synchronize SystemC to UVM phases
• Standards based, available today
• Vendor-independent
UVM
• Fully open-sourced, Apache licensed SysC Command
SV-UVM
package just like the UVM 1.1b base C / C++
package is
Can obtain from Mentor’s Verification Academy here:
http://verificationacademy.com/verification-methodology/uvm-connect
SV SC
import uvm_pkg::*;
import uvmc_pkg::*; SC-to-SV
scoreboard
`include "producer.sv"
`include "scoreboard.sv" compare bar
SV
TestbenchEnv
Scoreboard apbUvc Agent APB Master Top
Compare
actualQ == ApbTalker TlmDriver APB
ApbCover APB Master Master
expectQ Monitor Driver DPI Xactor
DpiDriver
APB Bus
APB
APB Slave
UVM-Connect’ions DPI Slave
DpiDriver
Xactor
APB
APB Monitor Monitor
DPI
TlmDriver Xactor
SystemC Testbench
TestbenchEnv
Scoreboard apbUvc Agent APB Master Top
Compare
actualQ == ApbTalker TlmDriver APB
ApbCover APB Master Master
expectQ Monitor Driver DPI Xactor
DpiDriver
APB Bus
class APB {
Testbench : public sc_module
// UVM-Connect’ed SV-UVM uvm_driver “initiator” APB Slave
UVM-Connect’ions DPI
ApbMasterTlmDriver Slave
*apbMaster;
class ApbBusMasterDriver DpiDriver
Testbench( sc_module_nameXactor
name );
extends uvm_driver };
#( uvm_tlm_generic_payload ); // {
class ApbMasterTlmDriver : public sc_module,
`uvm_component_utils(ApbBusMasterDriver) public virtual tlm::tlm_fw_transport_if<>
protected string peerId; // UVM-Connect ID { tlm::tlm_target_socket<32>APB
socket;
uvm_tlm_b_initiator_socket #(uvm_tlm_generic_payload)
initiatorSocket;
ApbMasterTlmDriver(
APB Monitor Monitor
DPI name, const char
sc_module_name *transactorPath );
TlmDriver Xactor
void b_transport(
function new( string name, uvm_component parent );
SystemC Testbench
tlm::tlm_generic_payload &trans,
sc_time &delay );
function void connect_phase( uvm_phase phase ); }
APB Bus
APB){
const svBitVecVal *monitorRecord
class ApbBusMonitor APB Slave
Slave
DPI*me = (ApbMonitorTlmDriver
extends uvm_subscriber UVM-Connect’ions
ApbMonitorTlmDriver *)
DpiDriver
svGetUserData( svGetScope(),
#(uvm_tlm_generic_payload); // { Xactor
(void *)(&ApbMonitorWrite) );
`uvm_component_utils(ApbBusMonitor) me->write( monitorRecord );
}
protected string peerId; // UVM-Connect ID
uvm_analysis_port #( uvm_tlm_generic_payload ) APB
analysisPort;
APB Monitor Monitor
DPI
TlmDriver Xactor
function new(string name, uvm_component parent);
SystemC Testbench
function void connect_phase( uvm_phase phase );
::b_transport()
::nb_transport_fw() = UVM-Connect “hidden”
TLM conduit infrastructure
UartTargetTransactor has 4
::nb_transport_bw() interchangeable initiator clients:
::nb_transport_bw()
::b_transport() SV-UVM TLM 2 test sequence client
::nb_transport_fw()
UartFileIo
SV-UVM TLM 2 file i/o client
Client SystemC TLM-2.0 xterm client
(SV/UVM) SystemC TLM-2.0 file i/o client
::b_transport()
::nb_transport_bw()
::nb_transport_fw()
UartFileIo
Client
(SysC)
::b_transport()
::nb_transport_bw() ::nb_transport_fw()
UartXterm UartTarget
Client Transactor
(SysC)
AXI Bus
Pipes
SystemC Testbench
TLM-2 ports SysC+Tlm AXI Slave
are unused AXI Slave Xactor
Memory Memory
Driver DPI
Xactor
In this case the TLM-2 port in both the SV-UVM driver = TLM analysis port -> subscribers
and the slave memory (back-door port) are unused
16 March 3, 2014 © 2014 Mentor Graphics Corp.
Dual use UVM drivers Sequencer port
is unused
SV-UVM Testbench
TestbenchEnv
SystemC Top
Testbench
AxiUvc
FrontBack “Front-door”
Tester AXI DPI AXI Master
Master path
Xactor
Driver SCE-MI 2
AXI Bus
Pipes
“masterSocket” UVM-Connect’ion
“Back-door”
path
= TLM-2 fabric
This configuration demonstrates a dual use
= TLM-2.0 initiator -> target socket
SV-UVM driver equipped with both a
sequencer port and a TLM-2 port = TLM analysis port -> subscribers
AxiTalker
AxiCover
soc_dut_wrapper
Monitor Driver
SV-UVM
Coverage Harness
AXI “Agent”
axi_dut_wrapper
AXI Master clocks, reset
Driver+Xactor Clock & Reset
AXI Generation
Bridge AXI_IF
Tlm2Rtl AXI Slave
Graphics
Driver+Xactor Subsystem
Interrupt
Monitor
SystemC
ARM FastModel TBX
Virtual Platform Co-model
Channel (DPI)
The TLM 1 and 2 standards are well supported by both SV-UVM and
SystemC methodologies
- There are now open-source "cross-language" TLM connectivity packages
readily available - and being considered for standardization