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93L34 8-Bit Addressable Latch

June 1989

93L34
8-Bit Addressable Latch
General Description Features
The 93L34 is an 8-bit addressable latch designed for gener- Y Serial to parallel capability
al purpose storage applications in digital systems. It is a Y Eight bits of storage with output of each bit available
multifunctional device capable of storing single line data in Y Random (addressable) data entry
eight addressable latches, and being a one-of-eight decoder Y Active high demultiplexing or decoding capability
and demultiplexer with active level HIGH outputs. The de- Y Easily expandable
vice also incorporates an active LOW common clear for re- Y Common conditional clear
setting all latches, as well as, an active LOW enable.

Connection Diagram Logic Symbol

Dual-In-Line Package

TL/F/10201 – 2
VCC e Pin 16
GND e Pin 8
TL/F/10201 – 1
Order Number 93L34DMQB or 93L34FMQB
See NS Package Number J16A or W16A

Pin Names Description

A0–A3 Address Inputs
D Data Input
E Enable Input (Active LOW)
CL Clear Input (Active LOW)
Q0–Q7 Parallel Latch Outputs

C1995 National Semiconductor Corporation TL/F/10201 RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required, Note: The ‘‘Absolute Maximum Ratings’’ are those values
please contact the National Semiconductor Sales beyond which the safety of the device cannot be guaran-
Office/Distributors for availability and specifications. teed. The device should not be operated at these limits. The
Supply Voltage 7V parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
Input Voltage 5.5V
The ‘‘Recommended Operating Conditions’’ table will define
Operating Free Air Temperature Range the conditions for actual device operation.
Military b 55§ C to a 125§ C
Storage Temperature Range b 65§ C to a 150§ C

Recommended Operating Conditions

93L34 (Mil)
Symbol Parameter Units
Min Nom Max
VCC Supply Voltage 4.5 5 5.5 V
VIH High Level Input Voltage 2 V
VIL Low Level Input Voltage 0.7 V
IOH High Level Output Voltage b 400 mA
IOL Low Level Output Current 4.8 mA
TA Free Air Operating Temperature b 55 125 §C
ts (H) Setup Time HIGH, D to E 45 ns
th (H) Hold Time HIGH, D to E b5 ns
ts (L) Setup Time LOW, D to E 45 ns
th (L) Hold Time LOW, D to E b7 ns
ts (H) Setup Time HIGH or LOW 10
ns
ts (L) An to E 10
tw (L) E Pulse Width LOW 26 ns
tw (L) CL Pulse Width LOW 35 ns

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 1)
VI Input Clamp Voltage VCC e Min, II e b10 mA b 1.5 V
VOH High Level Output Voltage VCC e Min, IOH e Max,
2.4 V
VIL e Max, VIH e Min
VOL Low Level Output Voltage VCC e Min, IOL e Max,
0.3 V
VIH e Min, VIL e Max
II Input Current @ Max VCC e Max, VI e 5.5V
1 mA
Input Voltage
IIH High Level Input Current VCC e Max, VI e 2.4V Inputs 20
mA
E 30
IIL Low Level Input Current VCC e Max, VI e 0.3V Inputs b 0.4
mA
E b 0.6

IOS Short Circuit VCC e Max (Note 2)

b 2.5 b 25 mA
Output Current
ICC Supply Current VCC e Max (Note 3) 21 mA
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open and all inputs grounded.

2
Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 1 for Test Waveforms and Output Load)
CL e 15 pF
Symbol Parameter Units
Min Max
tPLH Propagation Delay 45
ns
tPHL E to Qn 42
tPLH Propagation Delay 65
ns
tPHL D to Qn 45
tPLH Propagation Delay 66
ns
tPHL An to Qn 66
tPHL Propagation Delay
55 ns
CL to Qn

Functional Description
The 93L34 has four modes of operation which are shown in Mode Select Table
the Mode Select Table. In the addressable latch mode, data
on the data line (D) is written into the addressed latch. The E CL Mode
addressed latch will follow the Data input with all non-ad- L H Addressable Latch
dressed latches remaining in their previous states. In the H H Memory
memory mode, all latches remain in their previous state and
L L Active HIGH 8-Channel Demultiplexer
are unaffected by the data or address inputs. To eliminate
H L Clear
the possibility of entering erroneous data into the latches,
the Enable should be held HIGH while the Address lines are
changing. In the 1-of-8 decoding or demultiplexing mode,
the addressed output will follow the state of the D input with
all other outputs in the LOW state. In the clear mode all
outputs are LOW and unaffected by the address and data
inputs. When operating the 93L34 as an addressable latch,
changing more than one bit of the address could impose a
transient wrong address. Therefore, this should only be
done while in the memory mode.

3
Truth Table
Inputs Outputs
Mode
CL E A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L H X X X L L L L L L L L Clear
L L L L L D L L L L L L L Demultiplex
L L H L L L D L L L L L L
L L L H L L L D L L L L L
# # # # # # # # # # # # #
# # # # # # # # # # # # #
L L H H H L L L L L L L L
H H X X X Qt–1 Qt–1 Qt–1 Qt – 1 Qt – 1 Qt – 1 Qt – 1 Qt – 1 Memory
H L L L L D Qt–1 Qt– 1 Qt – 1 Qt – 1 Qt – 1 Qt – 1 Qt – 1 Addressable
H L H L L Qt–1 D Qt–1 Qt – 1 Qt – 1 Qt – 1 Qt – 1 Qt – 1 Latch
H L L H L Qt – 1 Qt – 1 D Qt –1 Qt –1 Qt –1 Qt –1 Qt –1
# # # # # # # # # # # # #
# # # # # # # # # # # # #
H L H H H Qt – 1 Qt – 1 Qt – 1 Qt –1 Qt –1 Qt –1 Qt –1 D
H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Qt–1 e Previous Output State

4
Logic Diagram

TL/F/10201 – 3

5
6
Physical Dimensions inches (millimeters)

16-Lead Ceramic Dual-In-Line Package (J)

Order Number 93L34DMQB
NS Package Number J16A

7
93L34 8-Bit Addressable Latch

Physical Dimensions inches (millimeters) (Continued)

16-Lead Ceramic Flat Package (W)

Order Number 93L34FMQB
NS Package Number W16A

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failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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