Tps 2033

TPS2030, TPS2031
TPS2032, TPS2033, TPS2034

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SLVS190C – DECEMBER 1998 – REVISED OCTOBER 2007
POWER-DISTRIBUTION SWITCHES
1FEATURES
• 33-mΩ (5-V Input) High-Side MOSFET Switch • Ambient Temperature Range, –40°C to 85°C
• Short-Circuit and Thermal Protection • 2-kV Human-Body-Model, 200-V
• Overcurrent Logic Output Machine-Model ESD Protection
• Operating Range: 2.7 V to 5.5 V • UL Listed– File No. E169910
• Logic-Level Enable Input D OR P PACKAGE
• Typical Rise Time: 6.1 ms (TOP VIEW)
• Undervoltage Lockout
GND 1 8 OUT
• Maximum Standby Supply Current: 10 μA IN 2 7 OUT
• No Drain-Source Back-Gate Diode IN 3 6 OUT
• Available in 8-pin SOIC and PDIP Packages EN 4 5 OC
DESCRIPTION
The TPS203x family of power distribution switches is intended for applications where heavy capacitive loads and
short circuits are likely to be encountered. These devices are 50-mΩ N-channel MOSFET high-side power
switches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive is
provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The charge pump requires no external components and allows operation from
supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS203x limits the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low.
When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a
thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present.
The TPS203x devices differ only in short-circuit current threshold. The TPS2030 limits at 0.3-A load, the
TPS2031 at 0.9-A load, the TPS2032 at 1.5-A load, the TPS2033 at 2.2-A load, and the TPS2034 at 3-A load
(see Available Options). The TPS203x is available in an 8-pin small-outline integrated-circuit (SOIC) package
and in an 8-pin dual-in-line (DIP) package and operates over a junction temperature range of –40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas Copyright © 1998–2007, Texas Instruments Incorporated
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS2030, TPS2031
TPS2032, TPS2033, TPS2034 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
RECOMMENDED MAXIMUM PACKAGED DEVICES (1)
TYPICAL SHORT-CIRCUIT
CONTINUOUS LOAD
TA ENABLE CURRENT LIMIT AT 25°C SMALL OUTLINE PLASTIC DIP
CURRENT
(A) (D) (2) (P)
(A)
0.2 0.3 TPS2030D TPS2030P
0.6 0.9 TPS2031D TPS2031P
–40°C to 85°C Active high 1 1.5 TPS2032D TPS2032P
1.5 2.2 TPS2033D TPS2033P
2 3 TPS2034D TPS2034P
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2030DR)
TPS2030 FUNCTIONAL BLOCK DIAGRAM

Power Switch
†
IN CS OUT
Charge
Pump
Current
EN Driver
Limit
OC
UVLO
Thermal
GND Sense
†Current Sense
TERMINAL FUNCTIONS
TERMINAL
NO. I/O DESCRIPTION
NAME
D OR P
EN 4 I Enable input. Logic high turns on power switch.
GND 1 I Ground
IN 2, 3 I Input voltage
OC 5 O Overcurrent. Logic output active low
OUT 6, 7, 8 O Power-switch output
2 Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034

TPS2030, TPS2031
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TPS2032, TPS2033, TPS2034
DETAILED DESCRIPTION
POWER SWITCH
The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 mΩ (VI(IN) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled.
CHARGE PUMP
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
DRIVER
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range.
ENABLE (EN)
The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce the
supply current to less than 10 μA when a logic low is present on EN . A logic high input on EN restores bias to
the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS
logic levels.
OVERCURRENT (OC)
The OC open drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
CURRENT SENSE
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant while
varying the voltage on the load.
THERMAL SENSE
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to approximately
140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled approximately 20°C, the
switch turns back on. The switch continues to cycle off and on until the fault is removed.
UNDERVOLTAGE LOCKOUT
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback 3

TPS2030, TPS2031
ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)
VALUE UNIT
VI(IN) (2) Input voltage range –0.3 to 6 V
VO(OUT) (2) Output voltage range –0.3 to VI(IN) + 0.3 V
VI(EN) Input voltage range –0.3 to 6 V
IO(OUT) Continuous output current Internally limited
Continuous total power dissipation See Dissipation Rating Table
TJ Operating virtual junction temperature range –40 to 125 °C
Tstg Storage temperature range –65 to 150 °C
Human body model 2 kV
ESD Electrostatic discharge protection: Machine model 200 V
Charged device model (CDM) 750 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
DISSIPATION RATING TABLE

TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING
D 725 mW 5.8 mW°C 464 mW 377 mW
P 1175 mW 9.4 mW°C 752 mW 611 mW
RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
VI(IN) 2.7 5.5 V
Input voltage
VI(EN) 0 5.5 V
TPS2030 0 0.2
TPS2031 0 0.6
IO Continuous output current TPS2032 0 1 A
TPS2033 0 1.5
TPS2034 0 2
TJ Operating virtual junction temperature –40 125 °C

TPS2030, TPS2031
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TPS2032, TPS2033, TPS2034
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 5 V (unless otherwise noted)
POWER SWITCH
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
VI(IN) = 5 V, TJ = 25°C, IO = 1.8 A 33 36
VI(IN) = 5 V, TJ = 85°C, IO = 1.8 A 38 46
VI(IN) = 5 V, TJ = 125°C, IO = 1.8 A 44 50
VI(IN) = 3.3 V, TJ = 25°C, IO = 1.8 A 37 41
VI(IN) = 3.3 V, TJ = 85°C, IO = 1.8 A 43 52
VI(IN) = 3.3 V, TJ = 125°C, IO = 1.8 A 51 61
rDS(on) Static drain-source on-state resistance mΩ
VI(IN) = 5 V, TJ = 25°C, IO = 0.18 A 30 34
VI(IN) = 5 V, TJ = 85°C, IO = 0.18 A 35 41
VI(IN) = 5 V, TJ = 125°C, IO = 0.18 A 39 47
VI(IN) = 3.3 V, TJ = 25°C, IO = 0.18 A 33 37
VI(IN) = 3.3 V, TJ = 85°C, IO = 0.18 A 39 46
VI(IN) = 3.3 V, TJ = 125°C, IO = 0.18 A 44 56
VI(IN) = 5.5 V, TJ = 25°C,
6.1
CL = 1 μF, RL = 10 Ω
tr Rise time, output ms
VI(IN) = 2.7 V, TJ = 25°C,
8.6
CL = 1 μF, RL = 10 Ω
VI(IN) = 5.5 V, TJ = 25°C,
3.4
CL = 1 μF, RL = 10 Ω
tf Fall time, output ms
VI(IN) = 2.7 V, TJ = 25°C,
3
CL = 1 μF, RL = 10 Ω
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
ENABLE INPUT (EN)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH high-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V 2 V
4.5 V ≤ VI(IN) ≤ 5.5 V 0.8
VIL Low-level input voltage V
2.7 V ≤ VI(IN) ≤ 4.5 V 0.5
II Input current EN = 0 V or EN = VI(IN) –0.5 0.5 μA
ton Turnon time CL = 100 μF, RL = 10 Ω 20
ms
toff Turnoff time CL = 100 μF, RL = 10 Ω 40
CURRENT LIMIT
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
TPS2030 0.22 0.3 0.4
TPS2031 0.66 0.9 1.1
TJ = 25°C, VI = 5.5 V, OUT connected to GND,
IOS Short-circuit output current TPS2032 1.1 1.5 1.8 A
Device enable into short circuit
TPS2033 1.65 2.2 2.7
TPS2034 2.2 3 3.8
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.

TPS2030, TPS2031
ELECTRICAL CHARACTERISTICS (Continued)

over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 5 V (unless otherwise noted)
SUPPLY CURRENT
TJ = 25°C 0.3 1
Supply current, low-level output No Load on OUT EN = 0 μA
40°C ≤ TJ ≤ 125°C 10
TJ = 25°C 58 75
Supply current, high-level output No Load on OUT EN = VI(IN) μA
40°C ≤ TJ ≤ 125°C 75 100
Leakage current OUT connected to ground EN = 0 40°C ≤ TJ ≤ 125°C 10 μA
Low-level input voltage 2 2.5 V
Hysteresis TJ = 25°C 100 mV
OVERCURRENT (OC)
Output low voltage IO = 10 mA, VOL(OC) 0.4 V
Off-state current (1) VO = 5 V, VO = 3.3 V 1 μA
(1) Specified by design, not production tested.

TPS2030, TPS2031
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TPS2032, TPS2033, TPS2034
PARAMETER MEASUREMENT INFORMATION

OUT
tr tf
RL CL
VO(OUT) 90% 90%
10% 10%
TEST CIRCUIT
VI(EN) 50% 50%
ton toff
VO(OUT) 90%
10%
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
TABLE OF TIMING DIAGRAMS

FIGURE
Turnon Delay and Rise Time 2
Turnoff Delay and Fall Time 3
Turnon Delay and Rise Time with 1-μF Load 4
Turnoff Delay and Rise TIME with 1-μF Load 5
Device Enabled Into Short 6
TPS2030, TPS2031, TPS2032, TPS2033, and TPS2034, Ramped Load on Enabled Device 7, 8, 9, 10, 11
TPS2034, Inrush Current 12
7.9-Ω Load Connected to an Enabled TPS2030 Device 13

TPS2030, TPS2031
VI(EN) (5 V/div) VI(EN) (5 V/div)

VI(EN) VI(EN)
VI(IN) = 5 V
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div) VO(OUT) (2 V/div)
VIN = 5 V
VO(OUT) RL = 27 Ω VO(OUT)
TA = 25°C
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
t − Time − ms t − Time − ms
Figure 2. Turnon Delay and Rise Time Figure 3. Turnoff Delay and Fall Time
VI(EN) (5 V/div) VI(EN) (5 V/div)

VI(EN) VI(EN)
VO(OUT) (2 V/div) VO(OUT) (2 V/div)
VI(IN) = 5 V VI(IN) = 5 V
CL = 1 µF CL = 1 µF
VO(OUT) RL = 27 Ω VO(OUT) RL = 27 Ω
TA = 25°C TA = 25°C
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
Figure 4. Turnon Delay and Rise Time With 1-µF Load Figure 5. Turnoff Delay and Fall Time With 1-μF Load

TPS2030, TPS2031
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TPS2032, TPS2033, TPS2034
VO(OC) (5 V/div)
VI(EN)
VI(EN) (5 V/div)
VO(OC)
TA = 25°C TA = 25°C
TPS2034
TPS2033
TPS2032 IO(OUT) (500 mA/div)
TPS2031
TPS2030
IO(OUT) IO(OUT)
IO(OUT) (1 A/div)
0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 140 160 180 200

Figure 6. Device Enabled Into Short Figure 7. TPS2030, Ramped Load on Enabled Device
VO(OC) (5 V/div) VO(OC) (5 V/div)
VO(OC) VO(OC)
TA = 25°C TA = 25°C
IO(OUT) (1 A/div)
IO(OUT) (1 A/div)
IO(OUT) IO(OUT)
0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200
Figure 8. TPS2031, Ramped Load on Enabled Device Figure 9. TPS2032, Ramped Load on Enabled Device

TPS2030, TPS2031
VO(OC) VO(OC)
VI(IN) = 5 V
VI(IN) = 5 V TA = 25°C
TA = 25°C
IO(OUT) (1 A/div) IO(OUT) (1 A/div)
IO(OUT) IO(OUT)
0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200
Figure 10. TPS2033, Ramped Load on Enabled Device Figure 11. TPS2034, Ramped Load on Enabled Device
VI(EN)
VO(OC) (5 V/div)
VI(EN) (5 V/div)
VO(OC)
IO(OUT) (200 mA/div)
470 µF
150 µF II(IN) (500 mA/div)
VI(IN) = 5 V
II(IN) RL = 10 Ω IO(OUT) RL = 7.9 Ω
47 µF TA = 25°C
TA = 25°C
0 1 2 3 4 5 6 7 8 9 10 0 200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − ms t − Time − µs
Figure 12. TPS2034, Inrush Current Figure 13. 7.9-Ω Load Connected to an
Enabled TPS2030 Device

TPS2030, TPS2031
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TPS2032, TPS2033, TPS2034

VO(OC) VO(OC)
RL = 3.7 Ω RL = 3.7 Ω
TA = 25°C TA = 25°C
IO(OUT) (500 mA/div)

IO(OUT) (1 A/div)
IO(OUT) IO(OUT)
0 50 100 150 200 250 300 350 400 450 500 0 200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − µs t − Time − µs
Figure 14. 3.7-Ω Load Connected to an Figure 15. 3.7-Ω Load Connected to an
Enabled TPS2030 Device Enabled TPS2031 Device
VO(OC)
VO(OC)
RL = 2.6 Ω RL = 2.6 Ω
TA = 25°C TA = 25°C
IO(OUT) IO(OUT)
0 50 100 150 200 250 300 350 400 450 500 0 200 400 600 800 1000 1200 1400 1600 1800 2000

TPS2030, TPS2031

VO(OC) VO(OC)
VI(IN) = 5 V
RL = 1.2 Ω
TA = 25°C
VI(IN) = 5 V
IO(OUT) IO(OUT) RL = 1.2 Ω
TA = 25°C
0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000

VO(OC) VO(OC)
RL = 0.9 Ω RL = 0.9 Ω
TA = 25°C TA = 25°C
IO(OUT) (2 A/div)
IO(OUT) (5 A/div)
IO(OUT) IO(OUT)
0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000

TPS2030, TPS2031
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TPS2032, TPS2033, TPS2034
VO(OC) (5 V/div)
VO(OC)
VI(IN) = 5 V
RL = 0.5 Ω
TA = 25°C
IO(OUT) (5 A/div)
IO(OUT)
0 50 100 150 200 250 300 350 400 450 500

t − Time − µs
Figure 22. 0.5-Ω Load Connected to an
Enabled TPS2034 Device
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
td(on) Turnon delay time vs Output voltage 23
td(off) Turnoff delay time vs Input voltage 24
tr Rise time vs Load current 25
tf Fall time vs Load current 26
Supply current (enabled) vs Junction temperature 27
Supply current (disabled) vs Junction temperature 28
Supply current (enabled) vs Input voltage 29
Supply current (disabled) vs Input voltage 30
vs Input voltage 31
IOS Short-circuit current limit
vs Junction temperature 32
vs Input voltage 33
rDS(on) Static drain-source on-state resistance
vs Input voltage 35
VI Input voltage Undervoltage lockout 37

TPS2030, TPS2031
TURNON DELAY TIME TURNOFF DELAY TIME

vs vs
OUTPUT VOLTAGE INPUT VOLTAGE
7.5 18
TA = 25°C TA = 25°C
7 CL = 1 µF CL = 1 µF
− Turn-off Delay Time − ms

t d(on) − Turn-on Delay Time − ms
6.5 17.5
5.5 17
t d(off)
4.5 16.5
3.5 16
2.5 3 3.5 4 4.5 5 5.5 6 2.5 3 3.5 4 4.5 5 5.5 6
VI − Input Voltage − V VI − Input Voltage − V
Figure 23. Figure 24.
RISE TIME FALL TIME

vs vs
LOAD CURRENT LOAD CURRENT
6.5 3.5
TA = 25°C
TA = 25°C
CL = 1 µF
CL = 1 µF
3.25
6
t f − Fall Time − ms
t r − Rise Time − ms
5.5
2.75
5 2.5
0 0.5 1 1.5 2 0 0.5 1 1.5 2
IL − Load Current − A IL − Load Current − A

TPS2030, TPS2031
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TPS2032, TPS2033, TPS2034
SUPPLY CURRENT (ENABLED) SUPPLY CURRENT (DISABLED)

vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
75 5
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 5.5 V 4
Supply Current (Disabled) − µ A

Supply Current (Enabled) − µ A
65
VI(IN) = 5 V
3
55 2
VI(IN) = 4 V
1
VI(IN) = 4 V
45
VI(IN) = 3.3 V VI(IN) = 3.3 V
0
VI(IN) = 2.7 V VI(IN) = 2.7 V
35 −1
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ − Junction Temperature − °C TJ − Junction Temperature − °C
SUPPLY CURRENT (ENABLED) SUPPLY CURRENT (DISABLED)

vs vs
INPUT VOLTAGE INPUT VOLTAGE
75 5
TJ = 125°C
TJ = 85°C 4 TJ = 125°C
Supply Current (Disabled) − µ A
Supply Current (Enabled) − µ A
65
55 TJ = 85°C
2
1 TJ = 25°C
45 TJ = 25°C
TJ = 0°C 0
TJ = 0°C
TJ = −40°C TJ = −40°C
35 −1
2.5 3 3.5 4 4.5 5 5.5 6 2.5 3 3.5 4 4.5 5 5.5 6
VI − Input Voltage − V VI − Input Voltage − V

TPS2030, TPS2031
SHORT-CIRCUIT CURRENT LIMIT SHORT-CIRCUIT CURRENT LIMIT

vs vs
INPUT VOLTAGE JUNCTION TEMPERATURE
3.5 3.5
TA = 25°C TPS2034 TPS2034
I OS − Short-Circuit Current Limit − A
I OS − Short-Circuit Current Limit − A

3 3
2.5 2.5
TPS2033
TPS2033
2 2
TPS2032 TPS2032
1.5 1.5
1 TPS2031 1 TPS2031
TPS2030
0.5 TPS2030 0.5
0 0
2 3 4 5 6 −50 −25 0 25 50 75 100
VI − Input Voltage − V TJ − Junction Temperature − °C
STATIC DRAIN-SOURCE ON-STATE RESISTANCE STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs vs
r DS(on) − Static Drain-Source On-State Resistance − m Ω
− Static Drain-Source On-State Resistance − m Ω
60
60
IO = 0.18 A
IO = 0.18 A
50
50
TJ = 125°C VI = 2.7 V
40
40
VI = 3.3 V
TJ = 25°C 30
30 VI = 5.5 V
TJ = −40°C
DS(on)
20
20 −50 −25 0 25 50 75 100 125 150
2.5 3 3.5 4 4.5 5 5.5 6
TJ − Junction Temperature − °C
r
VI − Input Voltage − V

TPS2030, TPS2031
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TPS2032, TPS2033, TPS2034
STATIC DRAIN-SOURCE ON-STATE RESISTANCE STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs vs

60
60
IO = 1.8 A
IO = 1.8 A
50
TJ = 125°C 50
VI = 3.3 V
VI = 4 V
40 VI = 5.5 V
40
TJ = 25°C
30 TJ = −40°C
30
DS(on)
20
DS(on)
20
3 3.5 4 4.5 5 5.5 6
−50 −25 0 25 50 75 100 125 150
TJ − Junction Temperature − °C
r
r
2.5
2.4
Start Threshold
2.3
2.2 Stop Threshold
2.1
2
−50 0 50 100 150
TJ − Temperature − °C
Figure 37.

TPS2030, TPS2031
APPLICATION INFORMATION
TPS2034
Power Supply 2,3

IN
2.7 V to 5.5 V 6,7,8
0.1 µF OUT Load
10 kΩ
0.1 µF 22 µF
5
OC
4
EN
GND
1
Figure 38. Typical Application
POWER SUPPLY CONSIDERATIONS

A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output and input pins is recommended when the output load is
heavy. This precaution reduces power supply transients that may cause ringing on the input. Additionally,
bypassing the output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to
short-circuit transients.
OVERCURRENT
A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the
series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant
output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present
long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 6). The TPS203x senses the short and
immediately switches into a constant-current output.
In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive load
occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figure 13
through Figure 22). After the current-limit circuit has tripped (reached the overcurrent trip threshold) the device
switches into constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 7 through Figure 11). The TPS203x is capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
OC RESPONSE
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. An RC filter can be connected
to the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic capacitors on the output lowers
the inrush current flow through the device during hot-plug events by providing a low impedance energy source,
thereby reducing erroneous overcurrent reporting.

TPS2030, TPS2031
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TPS2032, TPS2033, TPS2034
TPS203x TPS203x
V+
GND OUT V+ GND OUT
IN OUT Rpullup
Rpullup IN OUT
IN OUT IN OUT
Rfilter
EN OC EN OC
Cfilter
Figure 39. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses
POWER DISSIPATION AND JUNCTION TEMPERATURE

The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it is
good design practice to check power dissipation and junction temperature. The first step is to find rDS(on) at the
input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of
interest and read rDS(on) from Figure 33 through Figure 36. Next, calculate the power dissipation using:
P +r I2
D DS(on) (1)
Finally, calculate the junction temperature:
T +P R )T
J D qJA A (2)
Where:
TA = Ambient Temperature °C
RθJA = Thermal resistance SOIC = 172°C/W, PDIP = 106°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get an acceptable answer.
THERMAL PROTECTION
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS203x into constant current mode, which causes the voltage
across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to
the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection
circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense
circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues
to cycle in this manner until the load fault or input power is removed.
UNDERVOLTAGE LOCKOUT (UVLO)

An undervoltage lockout ensures that the power switch is in the off state at powerup. Whenever the input voltage
falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion
systems where it is not possible to turn off the power switch before input power is removed. The UVLO also
keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is
enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce EMI and
voltage overshoots.

TPS2030, TPS2031
GENERIC HOT-PLUG APPLICATIONS (Figure 40)

In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Because of the controlled rise times and fall times of the TPS203x series, these devices can
be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of
the TPS203x also ensures the switch will be off after the card has been removed, and the switch will be off
during the next insertion. The UVLO feature ensures a soft start with a controlled rise time for every insertion of
the card or module.
PC Board
Power TPS2034 Block of
Supply GND OUT Circuitry
2.7 V to 5.5 V IN OUT
1000 µF 0.1 µF
IN OUT
Optimum
EN OC
Overcurrent Response
Figure 40. Typical Hot-Plug Implementation
By placing the TPS203x between the VCC input and the rest of the circuitry, the input power will reach this device
first after insertion. The typical rise time of the switch is approximately 9 ms, providing a slow voltage ramp at the
output of the device. This implementation controls system surge currents and provides a hot-plugging
mechanism for any device.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPS2030D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2030
TPS2030DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2030
TPS2030DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2030
TPS2030P ACTIVE PDIP P 8 50 RoHS & NIPDAU N / A for Pkg Type -40 to 85 TPS2030P
Non-Green
TPS2031DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2031
Non-Green
TPS2034DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2034
Non-Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2030, TPS2032 :
• Automotive: TPS2030-Q1, TPS2032-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Type Drawing Diameter Width (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2030DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2031DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2032DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2033DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2034DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2030DR SOIC D 8 2500 340.5 338.1 20.6
TPS2031DR SOIC D 8 2500 340.5 338.1 20.6
TPS2032DR SOIC D 8 2500 340.5 338.1 20.6
TPS2033DR SOIC D 8 2500 340.5 338.1 20.6
TPS2034DR SOIC D 8 2500 340.5 338.1 20.6
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated

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TPS2030, TPS2031

TPS2032, TPS2033, TPS2034

PRODUCTION DATA information is current as of publication date.

TPS2030 FUNCTIONAL BLOCK DIAGRAM

2 Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated

Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034

Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback 3

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATING TABLE

RECOMMENDED OPERATING CONDITIONS

4 Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated

Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034

Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback 5

ELECTRICAL CHARACTERISTICS (Continued)

(1) Specified by design, not production tested.

6 Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated

Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034

PARAMETER MEASUREMENT INFORMATION

VI(EN) 50% 50%

Figure 1. Test Circuit and Voltage Waveforms

TABLE OF TIMING DIAGRAMS

Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback 7

VI(EN) (5 V/div) VI(EN) (5 V/div)

VO(OUT) (2 V/div) VO(OUT) (2 V/div)

VI(EN) (5 V/div) VI(EN) (5 V/div)

VO(OUT) (2 V/div) VO(OUT) (2 V/div)

8 Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated

Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034

0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 140 160 180 200

VO(OC) (5 V/div) VO(OC) (5 V/div)

Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback 9

VO(OC) (5 V/div) VO(OC) (5 V/div)

IO(OUT) (1 A/div) IO(OUT) (1 A/div)

IO(OUT) (200 mA/div)

150 µF II(IN) (500 mA/div)

10 Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated

Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034

VO(OC) (5 V/div) VO(OC) (5 V/div)

IO(OUT) (500 mA/div)

IO(OUT) (1 A/div) IO(OUT) (1 A/div)

Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback 11

VO(OC) (5 V/div) VO(OC) (5 V/div)

IO(OUT) (1 A/div) IO(OUT) (2 A/div)

VO(OC) (5 V/div) VO(OC) (5 V/div)

12 Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated

Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034

0 50 100 150 200 250 300 350 400 450 500

Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback 13

TURNON DELAY TIME TURNOFF DELAY TIME

− Turn-off Delay Time − ms

RISE TIME FALL TIME

14 Submit Documentation Feedback Copyright © 1998–2007, Texas Instruments Incorporated

Product Folder Link(s): TPS2030 TPS2031 TPS2032 TPS2033 TPS2034

SUPPLY CURRENT (ENABLED) SUPPLY CURRENT (DISABLED)

Supply Current (Disabled) − µ A

SUPPLY CURRENT (ENABLED) SUPPLY CURRENT (DISABLED)

Copyright © 1998–2007, Texas Instruments Incorporated Submit Documentation Feedback 15

SHORT-CIRCUIT CURRENT LIMIT SHORT-CIRCUIT CURRENT LIMIT

I OS − Short-Circuit Current Limit − A

STATIC DRAIN-SOURCE ON-STATE RESISTANCE STATIC DRAIN-SOURCE ON-STATE RESISTANCE