EECE2412 Final Exam

with Solutions
Prof. Charles A. DiMarzio
Department of Electrical and Computer Engineering
Northeastern University

Fall Semester 2010

My file 11480/exams/final

General Instructions:

1. You may use a calculator.

2. You may use one page of notes (both sides).

3. Do not ask the proctor questions. Make your best guess, and explain
it in writing on the exam.

4. Place phones, laptops, other electronic devices out of sight.

5. Use the workspaces provided by the vertical bar. You may use the back
of the paper if needed. Write your answer on the line provided.

6. The appearance of academic dishonesty will be dealt in accordance with

University policies described in the Student Handbook.

Note that the transistor is different in the two FET problems. Don’t expect
your answers in Problem 3 to match the parameters in Problem 4.
1 Short Answer Questions
The following questions relate to topics discussed in lectures. You should
be able to answer each of them with a few words. No equations or long
discussions are needed.

1.1 BJT Amplifiers

In which mode of operation is a BJT used for an amplifier? (Cutoff, Satura-
tion, Active, Passive, Triode, or Pentode)

Active
What type of BJT amplifier is the best choice to produce a large voltage
gain?

Common Emitter.
Why is it good practice to keep the AC base–emitter voltage below 10 mV
in an amplifier circuit?

To prevent non–linear behavior.

What is the ideal gain of a common–collector amplifier?

1.
Is it possible to design a DC–coupled amplifier using a single BJT? Why or
why not?

No. The base, emitter, and collector must be at different voltages.

1.2 FET DC Analysis

On which terminal of an FET is the arrow in the symbol we used in class?

The source.
Which terminal of a FET carries no current?

The gate.

2
In a current mirror, two or more identical FETs are used. The circuit controls
the current in the first, and the remaining ones all produce the same current.
If we want to change the current in one of the “mirror” transistors, which
parameter would we change?

Width, W .
Analyzing a particular FET circuit with the triode equation, we obtain two
solutions, one with VDS = 2.8 V and the other with with VDS = 1.2 V.
Which one is valid? Why?

The second, with the smaller VDS . The higher one will be beyond the bound-
ary and thus into the triode region.

1.3 FET Amplifiers

In which mode of operation is a FET used for an amplifier? (Cutoff, Satu-
ration, Active, Passive, Triode, or Pentode)

Saturation
A depletion FET is an attractive choice for a DC–coupled voltage amplifier.
Why?

The gate and drain can be at the same DC levels while the transistor is in
saturation.

3
In the circuit shown in this figure,M 1 is the amplifier transistor. The input
is on the gate, and the output is on the drain.

What type of amplifier is this?

Common source.
What parameters of the circuit determines the output resistance? Hint:
There are two.

The r0 of M 2.

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1.4 Logic
Here is a typical CMOS logic inverter.

What is the current at the current marker in this circuit when the input, V 2,
is high? What is it when the input is low?

Zero, Zero.
What is the voltage at the output voltage marker in this circuit circuit when
the input, V 2, is high? What is it when the input is low?

Zero, 5V.

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2 High–Voltage Piezoelectric Driver
A piezoelectric transducer is a device which can move objects through small
distances up to hundreds of micrometers, with the distance being propor-
tional to an applied voltage. However, several hundred volts may be required.
We would like to amplify a low–voltage control signal to provide voltage for
the piezoelectric transducer. Fortunately the transducer has a relatively high
resistance, so we can probably use just a voltage amplifier. Also fortunately,
transistors capable of working with these high voltages are available. Other-
wise these drivers would have to use vacuum tubes and I would have to find
another exam problem.
Let’s build an amplifier using the circuit below, with the piezoelectric trans-
ducer connected to the collector. We would like a voltage gain of |AV | = 100.
so that, as the input swings through 10 V the output swings through 1000 V.
The supply voltage is 1000 V, and we would like 2.5 mA of DC collector cur-
rent at the nominal operating point with a 500 V output on the collector.
(DC)
We will use VB = 5 V as the nominal input voltage. For this transistor
β = 55. (2.1)

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2.1 Resistor Selection
Determine the values for the two resistors.

1000 V − 500 V
RC = = 200 kΩ (2.2)
2.5 mA
The gain of the amplifier is nominally
RC
AV = − , (2.3)
RE
so
RE = 2 kΩ. (2.4)

2.2 Currents and Powers

What is the base current at the operating point?

Use KVL,
(DC)
5 V − 0.7 V = (β + 1) iB RE (2.5)
(DC)
iB = 38 µA. (2.6)

How much power is dissipated in each resistor at the operating point?

(DC)
PC = IC RC = (2.5 mA) × 200 kΩ = 1.25 W. (2.7)

(DC)
PE = IC RE = (2.5 mA) × 200 kΩ = 12.5 mW. (2.8)

A SPICE analysis is shown below.

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2.3 Transfer Function
What are the maximum and minimum input voltages required to cover the
full 1000 V range of output voltages? Draw the transfer curve carefully.

Minimum is 0.7V. Maximum is 10.7V.

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9
3 FET DC Analysis
Here we see the characteristic curves of an actual 3–micron N–channel FET
at a temperature of 297.5K (a balmy 24.35C or 75.83F). The first figure
shows the usual iD –vs.–vDS curves for different gate voltages. These values
are different from most of the FETs we used in class.

The next plot shows the current for different values of vDS , from 1 Volt to 4
Volts in 1–Volt steps, as a function of vGS .

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3.1 DC Parameters
Determine the numerical value of the threshold voltage.

0.75 Volts
Determine the numerical value of µn Cox W/L.

At
(DC)
VGS = 4 V, (3.1)
³ ´2
(DC)
W V GS − VT hr
(DC)
ID = µn Cox (1 + λVDS ) . (3.2)
L 2
(DC)
Extrapolating back to VDS = 0,
(DC)
W 2ID
µn Cox =³ ´2 . (3.3)
L (DC)
VGS − VT hr

W 120 µA 2
µn Cox =2 2 = 22.7 µA/V . (3.4)
L (4 V − 0.75 V)

Estimate the numerical value of the Early Voltage. How accurately can you
determine it from this graph?

iD
VA = (3.5)
λ
172 µA − 130 µA
λ= = 14 µA/V. (3.6)
4 V−1 V
VA = 8.6 V. (3.7)

3.2 DC Circuit
Now consider this transistor in the following circuit. Use the curves instead
of equations where possible. The equations are simple enough but a bit
time–consuming.

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 (DC)
What is the numerical value of VG ?

(DC) 180 kΩ
VG =5 V× . (3.8)
120 kΩ + 180 kΩ
(DC)
VG = 3.0 V. (3.9)

If I want to operate at VGS = 2 V, what is the voltage on the source?

(DC) (DC) (DC)

VS = VG − VGS =1V (3.10)

What is the value of RD ?

(DC)
From the curves, VDS = 0.3 V, so
(DC) (DC)
VD = VS + 0.3 V = 1.3 V. (3.11)

The current is 80 µA, so

5 V − 1.3 V
RD = = 46 kΩ. (3.12)
80 × 10−6 A

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Is the transistor is in saturation or triode?

Triode, from the curves.

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4 FET Amplifier
Consider the following circuit. In this case, µn Cox = 20 µA/V2 , L = 2 µm
and W = 10 µm, Vthr = 2 V, and VA = 150 V.

4.1 Small–Signal Parameters

Compute the small–signal parameters, gm and r0 , using the equations we
used in class.

r
(DC) W
gm = 2ID µn Cox (4.1)
L
gm = 440 µA/V (4.2)

VA
r0 = (DC)
(4.3)
ID
r0 = 150 kΩ. (4.4)

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4.2 Amplifier
The input is on the gate, and the output is on the drain. What is the voltage
gain of this amplifier?

AV = −gm (RC k r0 ) (4.5)

AV = −8 (4.6)

What is the output impedance?

Rout = (RC k r0 ) = 17 kΩ. (4.7)

How large can the input signal be before the transistor leaves the saturation
region?

We need to find the operating point. The drain voltage is

(DC) (DC)
VD = VDD − ID RD = 8 V. (4.8)

The AC output must be much less than 8 V. Thus the input must be
¯ ¯ 8V
¯ (AC) ¯
¯ in ¯ ¿
v = 1 V. (4.9)
|Av |

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