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1.fault Modeling

The document discusses fault modeling, fault grading, test coverage, and fault coverage in integrated circuit testing. It defines different types of fault models including stuck-at, transition, IDDQ, bridging, path delay, and small path delay faults. It also defines fault grading as determining what percentage of manufacturing defects will be detected by a test, and test coverage as the percentage of detectable faults that a test can detect. Fault coverage is calculated as the percentage of total faults, both testable and untestable, that a test detects.

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sharath A
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© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
71 views

1.fault Modeling

The document discusses fault modeling, fault grading, test coverage, and fault coverage in integrated circuit testing. It defines different types of fault models including stuck-at, transition, IDDQ, bridging, path delay, and small path delay faults. It also defines fault grading as determining what percentage of manufacturing defects will be detected by a test, and test coverage as the percentage of detectable faults that a test can detect. Fault coverage is calculated as the percentage of total faults, both testable and untestable, that a test detects.

Uploaded by

sharath A
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1. Fault modeling
2. Fault grading
3. Test coverage
4. Fault coverage
5. Atpg efficiency

1.Scan insertion flow & pre requisites


2.Pre DFT DRC-Violations
3.Post DFT DRC violations

1.Fault Modeling:
A fault Modeling is a representation of something that could go wrong in the
production, development, or operation of a piece of equipment or product. From this
model the user efficiency and importance of particular fault.
or
Fault
Modeling the effects of physical defects on the logic function and timing.

Corresponding to the type of fault which we are targeting, different type of fault models
is used. Following are some commonly used fault models.

a) Stuck at Fault.
b) Transition Fault.
c) IDDQ Fault.
d) Bridging Fault.
e) Path Delay Fault.
f) Small Delay Fault.
a) Stuck at fault:
The node module is stuck at some value 0 or 1 depending on what we are
targeting.

b) Transition fault:
There is any delay in the right time or fault time of a signal is called transition
fault model.
The transition fault model also slow to rise & slow to fall.

c) IDDQ Fault:
Leakage current in the circuit is called IDDQ fault.

Advantages
Covers most bridge faults
Covers some open faults
Higher defect coverage than stuck-at tests
Disadvantages
Circuit must be designed with low IDDQ
Test application slow Some open faults escape IDDQ tests
Some timing faults escape IDDQ tests
Current threshold has to be empirically established.

d) Bridging Fault:
Short circuit between two adjacent signal lines.
Two unconnected signal nets electrically connected due to extra material.
e) Path delay fault model:

The path delay fault model captures small extra delay such that each one by itself will
not cause the circuit fail but their cumulative effect along a path from input to output
can result in a faulty behavior.

Distributed delay in combinational path.


Propagation delays of all paths in a circuit must be less than one clock cycle.
Path delay fault model defects in circuit path.
Testing the combined delay through all gates of specific path.

f) Small Path Delay:


longest path is used to detect @ speed testing.
Timing Data from prime time.
A-D Path for SDD.
2) Fault Grading:
Fault grading is an implemented using ATPG and Fault simulation flow to fault grade the
functional test vectors.
Or
Logic fault grading is the process of determining what percentage of list of particular
manufacturing defects (faults) will be detected if you run a test or series of test on a
device. Fault grading does not verify that a device meets a design specification, only that
the device was manufactured according to the instructions used to manufacture the
device.

3) Test Coverage:

Test coverage = detected faults/total faults - untestable faults (total testable faults)
*100

              Detected faults: Detected by implication


                                                  pins in the scan chain data path
                                                  shift clock distributions to scan cells
                                                  set/reset distributions to scan cells
                                           Detected by simulation.
           Untestable faults: 1. unused
                                              2. Tied
                                              3. Blocked
                                                4. Redundant.

4) Fault Coverage:
      Fault Coverage = detected faults/Total no of faults *100

   Detected faults: Detected by implication


Total faults = testable + Untestable faults.

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