Electronic Warfare Signal Generation: Technologies and Methods
Electronic Warfare Signal Generation: Technologies and Methods
Electronic Warfare Signal Generation: Technologies and Methods
Electronic Warfare
Signal Generation:
Technologies and Methods
Introduction
Productive and efficient engineering of electronic warfare (EW) systems requires the generation
of test signals that accurately and repeatably represent the EW environment. Simulation of
multi-emitter environments is vital to ensure realistic testing.
This application note summarizes the technological approaches for EW signal and environment
simulation and the latest progress in flexible, high-fidelity solutions. For example, recent
innovations in digital-to-analog converters (DACs) have brought direct digital synthesis (DDS)
signal generation into EW applications through advances in both bandwidth and signal quality.
This paper also covers DDS solutions and other innovations in agile frequency and power
control so you can improve your design phase EW engineering accuracy and productivity.
The cost of test is as important as test realism, as the relationship between cost and test
fidelity is exponential. As test equipment becomes more cost-effective and capable, more
EW testing can be performed on the ground — in a lab or chamber — rather than in flight.
Even though flight testing can add test capability, it does so at a high cost. It is typically done
later in the program lifecycle, adding risk and further expense to the program through missed
deadlines if the system under test (SUT) fails. It is far better to test early in a lab environment
with as much realism as possible, where tests are easily repeated to identify iteratively and to
resolve issues.
Acquisition, GCI
Fire control
Early warning
VHF UHF L S C X Ku K Ka
A B C D E F G H I J K
Figure 1. A general representation of the threat density vs. frequency band in a typical operational environment. The
full RF/microwave environment would be a combination of the threat and commercial wireless environments.
In EW design, the multiplicity and density of the environment — and often the bandwidth —
make it impractical to use a single source or a small number of sources to simulate a single
emitter or a small number of emitters. Cost, space, and complexity considerations rule out
these approaches.
The only practical solution is to simulate many emitters with a single source, and to employ
multiple sources — each typically simulating many emitters — when required to produce the
needed signal density or to simulate specific phenomena such as angle-of-arrival (AoA).
The ability to simulate multiple emitters at multiple frequencies depends on the following: pulse
repetition frequency; duty cycle; number of emitters; and the capability of the source to switch
between frequency, amplitude, and modulation quickly.
A limiting factor in the use of a single signal generator to simulate multiple emitters is pulse
collisions. Figures 2 and 3 show the number of pulse collisions expected for the cases of low
and high pulse repetition frequency (PRF).
1000 emitters
80
70
512 emitters
60
50
40 256 emitters
30
20 128 emitters
10
36 emitters
0
0 1 1 2 2 3 3 4
Millions of pulses per second
Figure 2. As the number of emitters grows, the number of pulse collisions grows even when all emitters use low PRF.
80
70
60 2 emitters
50
40
30
20
10
1 emitter
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Millions of pulses per second
Figure 3. The percentage of pulse collisions climbs very quickly as high-PRF emitters are added to a simulation.
A source’s agility is a factor in its ability to simulate multiple emitters. Source frequency, phase,
and amplitude settling time (whichever is greater) is the transition time between playing one
pulse descriptor word (PDW) and the next.
Figure 4 shows that the total pulse density for a single source is limited by the sum of the
transition time, the width of the transmitted pulses, and the lockout period parameter. The
lockout period must be as short as possible, so the source settling times are as brief.
Pulse width
Frequency switching time
Transition time
Lockout period
Figure 4. The ability to simulate multiple emitters depends on the emitter parameters like PRF and pulse width. It also
includes the frequency, phase, and amplitude switching speeds and settling times of the signal source used to synthesize
the emitters. If the source is switching, it cannot play a pulse. If it is playing a pulse, it cannot switch. The source is
unavailable to simulate a different threat during the lockout period.
To simulate high pulse density and the possibility of some overlapping pulses, it is often
necessary to combine multiple sources. As more sources are added to the test configuration,
pulse density should scale quickly and seamlessly, reaching the desired tradeoff of satisfactory
simulation realism and cost.
Value
Legacy simulation
technology Modern
simulation technology
Fidelity
Figure 5. Simulation fidelity and cost increase exponentially. System integrators and evaluators must determine the level
of cost versus fidelity to ensure system performance. New simulation technologies enable more simulation realism and
fidelity at a lower cost.
In the past, simulations have generally been created with a separate component for each
emulation function, such as signal generation, modulation/pulsing, attenuation or amplification,
and phase shift. The same PDW would be sent to each functional component to provide output
on a pulse-to-pulse basis. For instance, a synthesizer would generate the output frequency,
while a separate modulator would create pulsed modulation or AM/FM/PM modulation.
Amplifiers and attenuators would adjust the signal to the desired output power level. Figure 6 is
an example of the system’s topology.
Synchronization
Figure 6. In the traditional approach, PDW control parameters are sent in parallel to multiple functional
elements, on a pulse-to-pulse basis, to generate and modify the desired signal. This approach results in a
complex system, demanding precise synchronization.
1. Philip Kazserman, “Frequency of pulse coincidence given in n radars of different pulse widths and PRFs,”
IEEE Trans. Aerospace and Electronic Systems, Vol. AES-6, p. 657-662, September 1970.
This approach can be scaled directly to create multiple coordinated channels, as shown in
Figure 7. However, systems configured in this way require a large footprint — occupying more
rack space — and cost escalates quickly.
Figure 7. A signal generation approach using separate functional elements can be scaled up to increase pulse
density and generate a more realistic environment. The cost and space requirements scale up rapidly as well.1
The controller in Figure 7 would route PDWs to channels based on emitter parameters, such
as frequency, amplitude, and pulse repetition frequency, and the availability of each channel to
implement the PDW. Because a channel cannot execute the parameters of two different PDWs at
the same time, one could be shunted to a backup channel or dropped according to its priority.
EW receivers must be able to handle 8 to 10 million pulses per second, where most of the pulse
density occurs at X-band. EW receivers must be able to handle pulses arriving at the same
time at different frequencies from different angles. Creating pulses that are coincident with one
another in the time domain should be a goal of simulation to increase simulation realism.
Though Figure 7 describes a very capable system, the system elements are not highly integrated.
Recent developments in analog and digital signal generation technologies
are enabling a higher degree of integration and solutions which are more cost- and space-
efficient, as described in the section, “Increasing Integration in EW Test Solutions.”
There are several methods of controlling simulations, depending on test objectives. Figure
7 shows systems with a traditional, distributed architecture. The synchronization of an agile
local oscillator (LO) with functions such as pulse modulation, frequency/phase modulation,
and amplitude control is a considerable challenge. In an integrated EW test solution such
as the UXG, this synchronization is automatic, provided by the test equipment itself. By
simplifying hardware and system complexity, this integrated approach promises to improve both
performance and reliability.
1. Reproduced by permission from David Adamy, EW 101: A First Course in Electronic Warfare, Norwood,
MA: Artech House, Inc., 2001. © 2001 by Artech House, Inc.
For example, there is often a need to switch between one simulated threat mode to another in response
to identification and jamming by the SUT. For long scenario lengths with fast control over scenario
changes, PDWs can be streamed over the LAN to the signal generation system operating in an agile
controller mode. In this case, simulation software generates batches of PDWs according to simulation
kinematic granularity and streams them ahead of their desired playtime.
The goals are to stress the SUT with increasing pulse density, depending on the number of simulation
channels available and the parameters of the threats to be simulated. As pulse density increases,
PDWs can be dropped according to a priority scheme as they increasingly collide in the time domain,
and there are insufficient signal generation channels to play them.
Creating AoA
In addition to creating emitters with the desired fidelity and density, it is also important to match
the geometry and kinematics of EW scenarios. This is because the AoA of a radar threat to the
EW system changes slowly compared to other parameters, such as center frequency and pulse
repetition frequency.
EW systems measure AoA and estimate distance using amplitude comparison, differential Doppler,
interferometry (phase difference), and time difference of arrival (TDoA). Precise AoA measurements
enable precise localization of radar threats. New stand-off jamming systems use active electronically
scanned arrays capable of precise beamforming to minimize loss of jamming power due to beam
spreading toward a threat. EW receivers with better AoA capability reduce the need for pulse
de-interleaving and sorting. Consequently, AoA is an increasingly important test requirement.
As an alternative, and depending on their architecture, sources can be linked together to create
phase-coherent output, allowing for exceptional control over creating phase fronts to the SUT.
Similarly, amplitude control at the source can be used to create appropriate amplitude differences at
SUT receive channels.
The ability to control AoA to meet modern test requirements depends on the architecture of
the source. At a minimum, it should be possible to lock the LOs of multiple sources together so
that they all share the same phase. Often, calibration is required to align the phase and timing
between sources.
Creating small, accurate, and repeatable differences in phase or frequency between channels is
the next challenge. Sources based on a direct digital synthesis (DDS) architecture allow AoA to be
controlled digitally in a numerically controlled oscillator. Phase alignment in a DDS source is then
a matter of sharing reference clocks. Calibrations to provide accuracy and repeatability can be
uploaded to a table to be applied in real time.
In addition to wide frequency coverage, sources for EW test must have fast frequency, phase,
and amplitude switching speeds to simulate different radars operating in different modes in
various frequency bands.
The required control loop filtering in PLLs results in a significant settling or loop response
time. This looping limits the ability of the synthesizer to switch frequency quickly. Due to their
comparatively high transition time, these sources are limited in their ability to simulate multiple
radar threats out of a single channel, even if they have the necessary broadband frequency
coverage and frequency resolution. They also lack phase-repeatable switching capability.
Since the switches and arithmetic operators used in the DAS approach operate very quickly
and do not need loop filtering, these synthesizers have very high-frequency agility. They are a
typical architecture for traditional EW test solutions.
However, DAS technology has several drawbacks. First, numerous stages are required to
achieve the desired frequency resolution. Switching parallel and series multiplication, division,
and mixing stages requires more hardware than PLLs and reduces reliability. Second, circuit
noise from each stage is cascaded, and phase noise is multiplied through the stages.
Finally, each stage adds components that increase size, weight, and cost.
On the positive side for EW applications, DAS has the potential for limited phase-repeatable
frequency switching. All frequencies are usually derived from the same reference, but divider
ambiguities generally preclude full phase-coherent switching.
Fast sample rates are needed to produce outputs with very wide bandwidth, so that a minimum
of multiplying stages can be used to create the desired output frequencies. The use of either
many multiplying stages or a DAC of insufficient purity would limit the effective spurious-free
dynamic range (SFDR) of the EW synthesizer.
Phase Phase-to-
∆Φ Phase Φ(t)
Frequency increment amplitude To DAC
accumulator
calculator converter
In frequency synthesis, a frequency control word — a delta phase — is sent to the phase
accumulator along with the digital reference clock. For each clock cycle, this delta phase is
added in the phase accumulator with high precision. The phase value generated by the
accumulator is then converted to a sinusoidal amplitude in the phase-to-amplitude converter.
The digital sine wave is sent to the DAC and output at a frequency given by the DDS tuning
equation, where N is the number of bits in the frequency control word:1
∆phase
fout = fclk
2N
This equation demonstrates that greater DAC clock frequencies achieve higher output
frequencies while the resolution is controlled by the number of bits in the frequency control
word and phase accumulators. The numerically controlled oscillator behaves as a divider to the
reference clock to provide frequencies with high resolution according to the bit depths of the
phase register and frequency control word. Note that transitions to new frequencies happen in
one clock cycle.
1. David Buchanan, “Choosing DACs for direct digital synthesis,” Analog Devices Application Note 237,
Available:(http://application-notes.digchip.com/013/13-14876.pdf)
–– Digital control of extremely fine frequency and phase tuning increments within a single
clock cycle. In the Keysight UXG agile signal generator, the frequency resolution is one
millihertz and phase resolution is sub-degree. Fractional-N techniques can provide
microhertz resolution, but frequency changes are much slower due to PLL filtering. DAS
techniques provide rapid frequency switching, but at a cost in frequency resolution.
–– Get fast frequency hopping with phase continuity and phase repeatability to simulate
multiple pulse-Doppler radars at different frequencies while maintaining their original
phase. This combination of phase control and hopping speed is unique to the Keysight UXG
agile signal generator.
DAS techniques offer hop speed and frequency/phase repeatability only under limited
conditions. Modulation is created in the digital domain, providing numerical precision and
repeatability.
There are other advantages to using DDS that are of interest to the EW engineer. Many DDSs
employ a digital modulator for amplitude, frequency, and phase modulation for the creation of
digitally modulated signals in the numerically controlled oscillator. Linear frequency modulated
(LFM) chirps and Barker codes can also be directly synthesized using the numerically controlled
oscillator. Chirp bandwidth depends on the bandwidth of the bandpass filters after each
multiplication stage and whether the signal is crossing a band.
Recent DAC innovations from Keysight provide an example of a DAC and DDS suitable for
EW test applications. The DAC has been designed for RF applications, with a combination
of high bit depth and excellent purity, including spurious-free dynamic range and low
phase noise. The high sample rate of the DAC supports a wide bandwidth DDS that allows
microwave frequencies to be synthesized with a low number of multiplication stages. Limiting
multiplication stages restricts the phase noise and spurious signals present in microwave
output.
EW testing also requires precise signal amplitudes over a wide range of power levels. These
power levels must be switched as fast as frequencies are changed, without signal distortion
from attenuator settling. As with the DAC, these demands have led Keysight to develop a new
series of field effect transistor (FET) switches to implement a solid-state attenuator with high
agility, low distortion, and an amplitude range of 120 dB. The agile amplitude range of the
attenuator is 80 dB anywhere in the 0 dBm to -120 dBm output range.
The architecture of a true DDS-based, agile microwave signal generator utilizing developments
in DAC and FET switching technology is shown in Figure 10.
Freq
Amplifier
doublers
Numerically Digital to Electronic & Analog out
controlled analog x2n mechanical 0.01-40 GHz
oscillator converter attenuators
Signal generation begins with a DDS optimized for very low spurious output, as spurs increase
for each doubling stage. A sequence of doubler circuits is then used as needed to create signals
up to 40 GHz. Each multiplication stage employs bandpass filters to remove unwanted signals
from the multipliers.
The FET-based agile attenuator is then used to produce the desired output levels. This
attenuator provides fast settling, matched to frequency switching speed so that the source can
implement open loop power control with high accuracy and no loss in switching time.
You cannot create some threat scenarios, such as AoA, with a single-channel source. Those
scenarios depend on properly synchronizing the outputs of two or more sources. By precisely
controlling the amplitude, phase, and time delay of each source output, you can simulate the
direction of a radar wavefront as it reaches the multiple antennas of an EW SUT. Accomplishing
this feat with multiple signal generators scales up the costs, often resulting in redundant
hardware — adding size, weight, power consumption, and complexity.
The Keysight UXG agile vector adapter works in conjunction with the UXG agile signal
generator. Figure 11 shows the block diagram.
6 GHz reference
8 - 18 GHz LO
1.8 GHz
1.6 GHz BW
.05 - 40 GHz
PDWs
Proprietary DAC
Figure 11. High level block diagram of the UXG agile vector adapter
Minimizing Distortion
Traditional analog I/Q baseband systems must be carefully tuned to minimize signal distortion
caused by phenomenon such as IQ gain imbalance (where the gain in the I and Q channels
is slightly different) and IQ skew (where the I and Q paths are not precisely in quadrature).
Figure 12 (left image) shows how these imperfections create in-band distortion. Because these
distortion products occur within the signal bandwidth, they cannot be filtered out.
A digital baseband architecture mathematically shifts the I and Q channels by 90 degrees and
digitally sums them before conversion to an analog IF signal. This technique greatly reduces
the amount of in-band distortion. Figure 12 (right image) shows how this technique provides a
higher fidelity signal.
This level of performance may impose severe limits on the threat scenario, which could require
a higher, agile dynamic range. Moreover, the DAC technique for amplitude control cannot
attenuate any spurious signals created further down the signal chain. The EW receiver under
test must perform additional signal processing to determine if the detected signal is a genuine
threat signal or a spurious one that can be ignored.
An agile electronic attenuator provides a better way to scale the threat signal. If we position the
electronic attenuator at the end of the signal chain, just before the RF output, it will attenuate
the threat signal and spur equally, as shown in Figure 13. Using an electronic attenuator in
combination with DAC bits can provide up to 120 dB of agile amplitude control.
Threat signal power reduction using DAC bits alone does not decrease
corresponding spur level (the absolute level remains constant)
The agile attenuator attenuates the threat signal along with its Spurs
and Harmonics by the same amount
If the scenario requires large numbers of pulses at multiple frequencies with minimal dropped
pulses, you might select the 4-channel, 1-port configurations in Figure 14. The outputs of each
analog or vector source are combined to a single RF port.
Analog Vector
If the threat scenario calls for AoA measurements, you need a different configuration. Figure 15
shows two different 1-channel, 4-port test configurations. All four sources are tuned to the
same frequency. But the amplitude, phase, and time delay of each RF output are individually
controlled to simulate the direction of the threat.
Analog Vector
The UXG meets important functional and performance requirements for EW test by combining
a DDS-based agile source and a matching agile attenuator to create a high level of functional
integration:
–– Fast frequency, amplitude, and phase switching for quick transitions between multiple
emitters
–– High dynamic range to match the dynamic range of modern EW receivers
–– Simulates multiple threats with accurate power levels and a large, agile amplitude range
that can switch amplitude as quickly as frequency
–– Low noise floor to test receiver sensitivity as channels are combined
–– Pulse modulation with a high on/off ratio and fast settling with low distortion
–– Intrapulse modulation capability for pulse compression such as Barker codes and linear
frequency modulation
–– Scalable to multi-channel and multi-port threat simulation to easily increase pulse density
and realism
–– Wide frequency range from near DC to 40 GHz to keep pace with modern threat simulation
requirements
–– BCD frequency control interface for backward compatibility with legacy sources previously
used as LOs
–– LAN and LVDS interfaces to allow high-rate PDW streaming
EW simulation sources need a fast, full-featured interface for streaming complete PDWs at a
high rate rather than frequency-only control.
Recent innovations in core hardware such as DACs and FPGAs have enabled new solutions
with the hardware simplicity and reliability of traditional test equipment. These solutions
will provide dramatic improvements in solution cost and size, bringing high-fidelity EW
environment simulation to a much earlier phase in the design process. Using realistic
EW environment simulation at the optimization and pre-verification stages of design will
improve performance, speed the design process, and reduce overall costs.