Department of Electrical Engineering

Faculty Member: _ Dated : _

Semester: _______________ Section: ________________

EE313: ELECTRONIC CIRCUIT DESIGN

Lab 6: BJT Current Mirror Circuits
(Widlar Current Source)

Name Reg. No Viva Analysis Modern Ethics Individual

of data in Tool and and Team
Lab Usage Safety Work
Report

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks

BJT Current Mirror Circuits

(Widlar Current Source)

EE313: Electronic Circuit Design Page 1

Introduction

1. This laboratory execise is meant to enble the students to design and understand the basic working of
current mirrors. For this, current mirrors with different configurations are implemented and the current
voltage relationships and output resistance of the circuits are studied thoroughly. In the end, a conclusion is
drawn on the basis of comparative study.

Objective

2. This laboratory will enable the students to achieve the following:

2.1. To design a Widlar Current Source

Conduct of Lab

3. The students have to perform this experiment using Pspice.Hardware implentation is also required.
4. The students are required to work in groups of three to four; each student must attempt to understand the
the use of a simple set up for measuring the parameters of the given transistor.In case some aspect of the
lab experiment is not understood the students are advised to seek help from the teacher, the lab
technicians or the Lab engineer.

Theory and Background

5. A current mirror is a circuit which can provide a copy of a current from a single reference current source to
one or more circuit elements which require current biasing. This allows for distribution from a single
reference by minimizing direct connections to the reference current source. In addition the current steering
circuits can be added to allow for the reference current to be distributed to many circuits that require
biasing constant currents.
6. The Widlar current source, shown in Figure 2, is a variant of the current mirror that includes a resistor
connected between the emitter of Q2 and ground. In this design, Re acts to reduce Vbe on Q2, which
reduces Ib and thus Ic.
7. The basic PSpice models and symbols are given in table-1. These will be used in the exercise.

Table-1: PSpice Symbols used in exercise

EE313: Electronic Circuit Design Page 2

 PSpice Symbol PSpice Symbol
Name
Name

0 L1
1 2
10uH
L

R1 V1
1Vac
0V dc

R 1K Vac
For Frequency Response only

Q1
C1
1u
Q 2N 2222
C Q2N2222

V1 = 0 V3
V2 = 1
TD = 0 V1
TR = 1 n 5Vdc
TF = 1 n
P W = 20m
P E R = 40m

VPULSE VDC
For Bias Point and DC Sweep
For Transient Response only
Analysis

INSTRUCTIONS FOR LAB REPORT

This handout will be used as part of Lab Report which is to be submitted by each group. Wherever a
measurement value is to recorded, or a calculation has to annotate, it will be done in student’s own
handwriting.
The required curves and graphs that have been asked in the handout will be attached with this handout. It is
important that correct labeling of graphs is done and referred to in the appropriate place of the handout.
Wherever a question requires an explanation, it will be written in the students own handwriting.

The finished lab report will be given before the commencement of the next lab.

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 PART 1 – Simple Current Mirror (Simulate Only)

R1

V1 V2
5V dc Q1 1V dc
Q 2N 2222
Q2
Q 2N 2222
0 0

Fig. 1: Simple Current Mirror

1. Simple Current Mirror

1.1. Calculate the value of resistor R1 to generate IREF equal to 1 mA.

R1 ____________________________

1.2. Now setup the circuit in PSPICE as shown in (Fig-1) and use the “Bias Point” analysis mode of PSpice
to show that the collector current in Q2 is nearly the same as IREF. In addition save the circuit by using
print screen option.
The percentage difference ___________________________

1.3. Now alter the voltage V2 as shown in following table and record the values of IO at Q2 :

V2 DC Supply 1V 2V 3V 4V 5V

IO at Q2

1.4. What would be the value of R1 in Fig. 1, if IO at Q2 is required to be 10 µA.

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 PART 2 – The Widlar Current Source

R1

V1 I V2
5V dc 3V dc

Q1
0 0
Q 2N 2222
Q Q2
2
I
Q 2N 2222

R2

Fig. 2: Widlar Current Source

2. The WIDLAR Current Source

2.1. (a) Calculate the value of resistor R1 (figure-2) to generate IREF of 1 mA.

R1 ____________________________

2.2. What would be the value of R2 if IO at Q2 is required to be 10 uAmp?

R2____________________________

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 2.3. Now setup the circuit in PSpice as shown in (Fig-2) and use the “Bias Point” analysis type to show
that the collector current in Q2 is nearly 10uAmperes. In addition save the DC bias voltage results by
using print screen option.

The percentage difference ___________________________

2.4. Comparing the value of resistance in section 2.2 and section 1.5, which approach is better to be
implemented from integrated circuit design point of view?

2.5. Now calculate the output resistance of the circuit. This can be done by selecting the “DC Sweep”
analysis type and sweeping the voltage V2 with Start Value=0, End Value=5 and Increment=0.01. The
output resistance is the slope of the IV-curve generated. In addition save the graph by using print
screen option.

Output Resistance___________________________

2.6. Now patch the circuit, as shown in (Fig-2), on Breadboard and verify your simulation results.
Note: You may have to use a Load resistance for practical part to avoid possible thermal runaway e.g. 1K
resistor at collector of Q2

Io=___________________________

The percentage difference ___________________________

2.7. Now alter the voltage V2 as shown in following table and record the values of IO at Q2 : Draw an I vs V
Graph.
V2 DC Supply 1V 2V 3V 4V 5V

IO at Q2

Now calculate the output resistance of the circuit. This can be done by calculating the slope of the I-V
graph in linear region and taking the inverse of slope.

Output Resistance___________________________

EE313: Electronic Circuit Design Page 6