Infineon-CY8CKIT-062S2-43012 PSoC 62S2 Wi-Fi BT Pioneer Kit Guide-UserManual-v01 00-EN

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CY8CKIT-062S2-43012
PSoC 62S2 Wi-Fi BT Pioneer Kit Guide
Doc. # 002-28109 Rev. *G
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
www.cypress.com
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CY8CKIT-062S2-43012 PSoC 62S2 Wi-Fi BT Pioneer Kit Guide, Doc. # 002-28109 Rev. *G 2
Contents
Safety and Regulatory Compliance Information 5
1. Introduction 7
1.1 Kit Contents .................................................................................................................8
1.2 Getting Started.............................................................................................................9
1.3 Board Details ...............................................................................................................9
1.4 Additional Learning Resources..................................................................................15
1.5 Technical Support......................................................................................................15
1.6 Documentation Conventions......................................................................................15
1.7 Acronyms...................................................................................................................16
2. Kit Operation 18
2.1 Theory of Operation...................................................................................................18
2.2 KitProg3: On-Board Programmer/Debugger..............................................................23
2.2.1 Programming and Debugging using ModusToolbox ......................................23
2.2.2 USB-UART Bridge..........................................................................................27
2.2.3 USB-I2C Bridge..............................................................................................28
3. Hardware 29
3.1 Schematics ................................................................................................................29
3.2 Hardware Functional Description...............................................................................29
3.2.1 CY8CMOD-062S2-43012 (MOD1).................................................................29
3.2.2 PSoC 5LP-based KitProg3 (U2).....................................................................34
3.2.3 Serial Interconnection between PSoC 5LP and PSoC 6 MCU ......................35
3.2.4 Serial Interconnection Between PSoC 5LP and CYW43012 .........................36
3.2.5 Power Supply System ....................................................................................36
3.2.6 I/O Headers....................................................................................................39
3.2.7 CapSense Circuit ...........................................................................................40
3.2.8 LEDs ..............................................................................................................41
3.2.9 Push Buttons..................................................................................................42
3.2.10 Cypress Quad SPI NOR Flash.......................................................................42
3.2.11 Cypress Quad SPI F-RAM .............................................................................43
3.2.12 microSD card section .....................................................................................43
3.2.13 PSoC 6 USB Section .....................................................................................44
3.2.14 Potentiometer Section....................................................................................44
3.3 PSoC 62S2 Wi-Fi BT Pioneer Kit Rework .................................................................45
3.3.1 CapSense Shield ...........................................................................................45
3.3.2 ETM Trace Header.........................................................................................45
3.3.3 microSD Card Detect Multiplexing .................................................................45
3.3.4 microSD Card SPI Multiplexing......................................................................46
3.3.5 U.FL (UMCC) Connector for External Antenna ..............................................46
3.3.6 U.FL (UMCC) Connector for Antenna Diversity..............................................46
Contents
3.4 Bill of Materials ..........................................................................................................47

3.5 Frequently Asked Questions......................................................................................47
Revision History 49
Safety and Regulatory Compliance
Information
Regulatory Compliance Information

Contains Transmitter Module FCC ID: VPYLBEE59B1LV and IC: 772C-LBEE59B1LV
This kit is intended to use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR
EVALUATION PURPOSES ONLY and is not considered by Cypress Semiconductor to be a finished
end product fit for general consumer use. It generates, uses, and can radiate radio frequency energy
and has not been tested for compliance with the limits of computing devices pursuant to part 15 of
FCC or ICES-003 rules, which are designed to provide reasonable protection against radio
frequency interference. Operation of the equipment may cause interference with radio
communications, in which case the user at his own expense will be required to take whatever
measures may be required to correct this interference.
The kit contains Murata’s Type 1LV (LBEE59B1LV) certified module. Due to change in the antenna
pattern/type used in CY8CKIT-062S2-43012 PSoC® 62S2 Wi-Fi BT Pioneer Kit, class II permissive
changes are required to recertify this kit. The radiated emission tests must be performed again to
obtain a new FCC ID for this host kit. Most conducted RF test results may still be reused. Customer
also needs to take their product through other FCC/ISED testing such as unintentional radiators
(FCC sub part 15B) and any other required regional product certifications including but not limited to
EU directives. Refer FCC Regulatory Certification Guide by Murata on information on pre-certified
and reference certified module concepts and information on what additional test are required for
FCC certification. Customer should consult a Telecommunication Certification Body (TCB) lab for
guidance on other requirements for the device certification.
For more details on Murata Type 1LV module refer https://wireless.murata.com/type-1lv.html.
PSoC 62S2 Wi-Fi BT Pioneer Boards contain electrostatic discharge

(ESD)- sensitive devices. Electrostatic charges readily accumulate on
the human body and any equipment, which can cause a discharge
without detection. Permanent damage may occur on devices
subjected to high-energy discharges. Proper ESD precautions are
recommended to avoid performance degradation or loss of
functionality. Store unused PSoC 62S2 Wi-Fi BT Pioneer Boards in the
protective shipping package.
End-of-Life/Product Recycling
The end-of-life cycle for this kit is five years from the date of
manufacture mentioned on the back of the box. Contact your nearest
recycler to discard the kit.
General Safety Instructions
ESD Protection
ESD can damage boards and associated components. Cypress recommends that you perform
procedures only at an ESD workstation. If an ESD workstation is unavailable, use appropriate ESD
protection by wearing an anti-static wrist strap attached to a grounded metal object.
Handling Boards
CY8CKIT-062S2-43012 PSoC 62S2 Wi-Fi BT Pioneer Kit is sensitive to ESD. Hold the board only by
its edges. After removing the board from its box, place it on a grounded, static-free surface. Use a
conductive foam pad, if available. Do not slide the board over any surface.
1. Introduction
Thank you for your interest in the CY8CKIT-062S2-43012 PSoC 62S2 Wi-Fi BT Pioneer Kit. The
PSoC 62S2 Wi-Fi BT Pioneer Kit enables you to evaluate and develop your applications using the
PSoC 62 Series MCU (hereafter called “PSoC 6 MCU”) and CYW43012 WICED Wi-Fi/BT combo
device.
PSoC 6 MCU is Cypress’ latest, ultra-low-power PSoC specifically designed for wearables and IoT
products. PSoC 6 MCU is a true programmable embedded system-on-chip, integrating a 150-MHz
Arm® Cortex®-M4 as the primary application processor, a 100-MHz Arm Cortex-M0+ that supports
low-power operations, up to 2 MB Flash and 1 MB SRAM, Secure Digital Host Controller (SDHC)
supporting SD/SDIO/eMMC interfaces, CapSense® touch-sensing, and programmable analog and
digital peripherals that allow higher flexibility, in-field tuning of the design, and faster time-to-market.
The PSoC 6 BLE Pioneer Board offers compatibility with Arduino™ shields. The board features a
PSoC 6 MCU, and a CYW43012 Wi-Fi/Bluetooth combo module. Cypress CYW43012 is a 28-nm,
ultra-low-power device that supports single-stream, dual-band IEEE 802.11n-compliant Wi-Fi MAC/
baseband/radio and Bluetooth 5.0 BR/EDR/LE. The WLAN section supports SDIO interface to the
host MCU (PSoC 6 MCU), and the Bluetooth section supports high-speed 4-wire UART interface to
the host MCU. In addition, the board features an onboard programmer/debugger (KitProg3), a
512-Mbit Quad SPI NOR flash, a 4-Mbit Quad SPI F-RAM, a micro-B connector for USB device
interface, a 5-segment CapSense slider, two CapSense buttons, a microSD card holder, an RGB
LED, two user LEDs, one potentiometer, and two push buttons. The board supports operating
voltages from 1.8 V to 3.3 V for PSoC 6 MCU.
You can use ModusToolbox™ to develop and debug your PSoC 6 MCU projects. ModusToolbox
software is a set of tools that enable you to integrate Cypress devices into your existing development
methodology.
If you are new to PSoC 6 MCU and ModusToolbox IDE, refer to the application note AN221774 -
Getting Started with PSoC 6 MCU to help you familiarize with the PSoC 6 MCU and help you create
your own design using the ModusToolbox IDE.
Introduction
1.1 Kit Contents

The CY8CKIT-062S2-43012 PSoC 62S2 Wi-Fi BT Pioneer Kit has the following contents, as shown
in Figure 1-1.
■ PSoC 62S2 Wi-Fi BT Pioneer Board
■ USB Type-A to Micro-B cable
■ Four jumper wires (4 inches each)
■ Two jumper wires (5 inches each)
■ Quick Start Guide
Figure 1-1. Kit Contents
Inspect the contents of the kit; if you find any part missing, contact your nearest Cypress sales office
for help: www.cypress.com/support.
Introduction
1.2 Getting Started

This guide will help you get acquainted with the PSoC 62S2 Wi-Fi BT Pioneer Kit:
■ The Kit Operation chapter on page 18 describes the major features of the PSoC 62S2 Wi-Fi BT
Pioneer Kit and functionalities such as programming, debugging, and the USB-UART and USB-
I2C bridges.
■ The Hardware chapter on page 29 provides a detailed hardware description, methods to use the
onboard NOR flash, kit schematics, and the bill of materials (BOM).
■ Application development using PSoC 62S2 Wi-Fi BT Pioneer Kit is supported in various
development ecosystems such as ModusToolbox and Mbed OS. For the latest software support
for this development kit including the different development ecosystems, refer to the kit webpage.
❐ ModusToolbox software is a free development ecosystem that includes the ModusToolbox
IDE. Using ModusToolbox IDE, you can enable and configure device resources, middleware
libraries, and program and debug the device. You can download the software from the
ModusToolbox home page. See the ModusToolbox User Guide for additional information.
❐ Mbed OS: Visit Cypress’ Mbed OS page on instructions to develop applications on Cypress’
target board on the Mbed OS platform.
■ There are wide range of code examples to evaluate the PSoC 62S2 Wi-Fi BT Pioneer board.
These examples help you familiarize PSoC 6 MCU and create your own design. These examples
are available in various development ecosystems such as ModusToolbox IDE and Mbed OS.
Visit Cypress’ code example page to access examples for the following development
ecosystems:
❐ ModusToolbox based examples
❐ Mbed OS based examples
1.3 Board Details

The PSoC 62S2 Wi-Fi BT Pioneer Board that has the following features:
■ CY8CMOD-062S2-43012 carrier module that contains
❐ PSoC 6 MCU (CY8C624ABZI-S2D44)
❐ Murata 1LV ultra-small 2.4/5.0-GHz WLAN and Bluetooth functionality module based on
CYW43012
■ 512-Mbit external Quad SPI NOR Flash that provides a fast, expandable memory for data and
code
■ 4-Mbit Quad SPI ferroelectric random-access memory (F-RAM)
■ KitProg3 onboard SWD programmer/debugger with USB-UART and USB-I2C bridge functionality
■ CapSense touch-sensing slider (5 elements), two buttons, based on self-capacitance (CSD) and
mutual-capacitance (CSX) sensing
■ A micro-B connector for USB device interface for PSoC 6 MCU
■ 1.8 V and 3.3 V operation of PSoC 6 MCU is supported
■ Two user LEDs, an RGB LED, two user buttons, and a reset button for PSoC 6 MCU
■ A potentiometer
■ One Mode selection button and one Status LED for KitProg3
■ A microSD Card holder
Introduction
Figure 1-2 shows the pinout of the Pioneer Board.

Figure 1-2. Pioneer Board Pinout
P6_0/SCL
P6_1/SDA
VREF/AREF
GND/GND
P12_2/D13
P12_1/D12
P12_0/D11
P12_3/D10
P7_6/D9
P7_5/D8
P1_4
P0_4
P7_4
NC
NC
NC NC
VTRAG/IOREF NC
XRES/RESET NC
V 3.3/3.3V NC
V 5.0/5V NC
GND/GND
GND/GND
VIN/Vin NC
P13_5
P13_4
P8_0
P13_6
P10_0/A0 P9_0 P1_3
P10_1/A1 P9_1 P0_3
P10_2/A2 P9_2 P0_2
P10_3/A3 P9_3
P10_4/A4 P9_4 P5_7/D7
P10_5/A5 P9_5 P5_6/D6
P10_6 P9_6 P5_5/D5
P10_7 P9_7 P5_4/D4
P5_3/D3
P5_2/D2
BT_UART_RXD BT_I2S_CLK P5_1/D1
BT_UART_TXD BT_I2S_WS P5_0/D0
BT_UART_CTS BT_I2S_DO
BT_UART_RTS BT_I2S_DI
WL_UART_RX BT_IO2
WL_UART_TX BT_IO3
WL_IO1 BT_IO4
WL_IO2 BT_IO5
P7_3 NC
LEGEND P0_5 P11_1
Arduino Uno R3 P1_1 P1_5
PSoC 6 I/Os
WL/BT I/Os
Table 1-1. Pioneer Board Pinout

Primary On-board Secondary On-board
Pin Connection details
Function Function
PSoC 6 MCU Pins
XRES Hardware Reset – –
P0[2] GPIO on non-Arduino – –
header IO0 (J22.1)
header IO1 (J22.2)
P0[4] User button with GPIO on non-Arduino –
Hibernate wakeup header (J21.9)
capability
P0[5] RGB green LED GPIO on non-Arduino –
(LED5) header (J24.3)
Introduction
Table 1-1. Pioneer Board Pinout (continued)

Function Function
P1[0] CapSense RX for GPIO on non-Arduino Remove R33 to disconnect from CapSense.
buttons and header IO7 (J22.8) Populate R145 to connect to GPIO on non-
CapSense TX for Arduino header.
sliders
P1[1] RGB red LED (LED5) GPIO on non-Arduino –
header (J24.1)
P1[2] USB Host Enable – –
header J22.3
P1[4] User button with GPIO on non-Arduino –
Hibernate wakeup header (J21.10)
capability
P1[5] Orange user LED GPIO on non-Arduino –
P5[0] UART_RX Arduino D0 (J4.1) Remove R21 to disconnect from KitProg3.
P5[1] UART_TX Arduino D1 (J4.2) Remove R61 to disconnect from KitProg3.
P5[2] UART_RTS Arduino D2 (J4.3) Remove R19 to disconnect from KitProg3.
P5[3] UART_CTS Arduino D3 (J4.4) Remove R18 to disconnect from KitProg3.
P5[4] Arduino D4 (J4.5) – –
P5[5] Arduino D5 (J4.6) – –
P5[6] Arduino D6 (J4.7) – –
P5[7] Arduino D7 (J4.8) – –
P6[0] I2C SCL Arduino (J3.10) Remove R58 to disconnect from KitProg3.
P6[1] I2C SDA Arduino (J3.9) Remove R59 to disconnect from KitProg3.
P6[2] USB VBUS Detect – –
P6[3] USB Interrupt – –
P6[4] PSoC 6 MCU JTAG – –
TDO/SWD SWO
TDI
TMS/SWD SWDIO
TCK/SWD SWCLK
P7[0] ETM Clock – –
P7[1] CapSense CINTA – –
P7[2] CapSense CINTB – –
P7[3] RGB blue LED GPIO on non-Arduino –
Introduction

Function Function
P7[4] GPIO on non-Arduino CapSense Shield Remove R155 to disconnect from IO15
header IO15 (J21.8) (J21.8).
Populate R38 to connect to CapSense
Shield.
P7[5] Arduino D8 (J3.1) – –
P7[6] Arduino D9 (J3.2) – –
P7[7] CapSense CMOD – –
header (J22.5)
P8[1] CapSense Button0 GPIO on non-Arduino Remove R24 to disconnect from CapSense.
TX header IO8 (J21.1) Populate R144 to connect to GPIO on non-
Arduino header.
P8[2] CapSense Button1 GPIO on non-Arduino Remove R25 to disconnect from CapSense.
TX header IO9 (J21.2) Populate R143 to connect to GPIO on non-
Arduino header.
P8[3] CapSense Slider0 GPIO on non-Arduino Remove R28 to disconnect from CapSense.
RX header IO10 (J21.3) Populate R142 to connect to GPIO on non-
Arduino header.
Arduino header.
Arduino header.
Arduino header.
Arduino header.
P9[0] Extended Arduino A8 ETM TRACEDATA[3] Remove R125 to disconnect from J2
(J2.2) header.
Populate R126 to connect to ETM Trace
header.
P9[1] Extended Arduino A9 ETM TRACEDATA[2] Remove R124 to disconnect from J2
(J2.4) header.
header.
P9[2] Extended Arduino ETM TRACEDATA[1] Remove R123 to disconnect from J2
A10 (J2.6) header.
header.
Introduction

Function Function
P9[3] Extended Arduino ETM TRACEDATA[0] Remove R117 to disconnect from J2 header.
A11 (J2.8) Populate R129 to connect to ETM Trace
header.
P9[4] Extended Arduino – –
A12 (J2.10)
A13 (J2.12)
A14 (J2.14)
A15 (J2.16)
P10[0] Arduino A0 (J2.1) – –
P10[1] Arduino A1 (J2.3) – –
P10[2] Arduino A2 (J2.5) – –
P10[3] Arduino A3 (J2.7) – –
P10[4] Arduino A4 (J2.9) – –
P10[5] Arduino A5 (J2.11) – –
P10[6] Potentiometer output Extended Arduino A6 Remove R51 to disconnect from
(J2.13) potentiometer.
P10[7] Extended Arduino A7 – –
(J2.15)
P11[0] QSPI F-RAM CS – –
P11[1] Red user LED GPIO on non-Arduino –
P11[2] QSPI Flash CS – –
P11[3:6] QSPI Flash IO[3:0] – –
P11[7] QSPI Flash CLK – –
P12[0] Arduino header D11 – –
(J3.4)
(J3.5)
(J3.6)
(J3.3)
P12[4] microSD card CMD – Remove R168 to disconnect from microSD
card connector.
P12[5] microSD card CLK – Remove R166 to disconnect from microSD
card connector.
P12[6] ECO Crystal XIN – –
P12[7] ECO Crystal XOUT – –
Introduction

Function Function
P13[0] microSD card DAT0 microSD card MOSI Remove R164 to disconnect from microSD
port (J20.7).
Populate R169 to connect to microSD
(J20.3).
P13[1] microSD card DAT1 microSD card MISO Remove R163 to disconnect from microSD
port (J20.8).
(J20.7).
P13[2] microSD card DAT2 microSD card SPI CLK Remove R162 to disconnect from microSD
port (J20.1)
(J20.5)
P13[3] microSD card DAT3 microSD card SPI –
SSEL
header IO5 (J22.6)
header IO6 (J22.7)
header IO3 (J22.4)
P13[7] microSD card chip GPIO on non-Arduino Remove R161 to disconnect from microSD
detect header IO16 (J24.6) card detect
Populate R160 to connect to IO16 (J24.6)
CYW43012 Pins
BT_UART_TXD UART interface with – –
Host MCU (PSoC 6
MCU)
BT_UART_RXD UART interface with – –
Host MCU (PSoC 6
MCU)
BT_UART_CTS UART interface with – –
Host MCU (PSoC 6
MCU)
BT_UART_RTS UART interface with – –
Host MCU (PSoC 6
MCU)
BT_I2S_CLK I2S serial clock – –
BT_I2S_WS I2S serial word select – –
BT_I2S_DO I2S serial data out – –
BT_I2S_DI I2S serial data in – –
BT_IO_2 Bluetooth general- – –
purpose I/Os
purpose I/Os
Introduction

Function Function
purpose I/Os
purpose I/Os
WL_UART_RX Wi-Fi debug UART – –
Rx pin
WL_UART_TX Wi-Fi debug UART – –
Tx Pin
WL_GPIO_1 Programable GPIO – –
WL_GPIO_2 Programable GPIO – –
1.4 Additional Learning Resources

Cypress provides a wealth of data at www.cypress.com/psoc6 to help you to select the right PSoC
device for your design and to help you to quickly and effectively integrate the device into your
design.
1.5 Technical Support

For assistance, visit Cypress Support or contact customer support at +1(800) 541-4736 Ext. 3 (in the
USA) or +1 (408) 943-2600 Ext. 3 (International).
You can also use the following support resources if you need quick assistance:
■ Self-help (Technical Documents).
■ Local Sales Office Locations.
1.6 Documentation Conventions

Table 1-2. Document Conventions for Guides
Convention Usage
Courier New Displays file locations, user entered text, and source code:
C:\...cd\icc\
Italics Displays file names and reference documentation:
Read about the sourcefile.hex file in the PSoC Creator User Guide.
File > Open Represents menu paths:
File > Open > New Project
Bold Displays commands, menu paths, and icon names in procedures:
Click the File icon and then click Open.
Times New Roman Displays an equation:
2+2=4
Text in gray boxes Describes cautions or unique functionality of the product.
Introduction
1.7 Acronyms
Table 1-3. Acronyms Used in this Document
Acronym Definition
ADC Analog-to-Digital Converter
BLE Bluetooth Low Energy
BOM Bill of Materials
BT Bluetooth
CINT Integration Capacitor
CMOD Modulator Capacitor
CPU Central Processing Unit
CSD CapSense Sigma Delta
CSX CapSense Crosspoint
DC Direct Current
Del-Sig Delta-Sigma
DMA Direct Memory Access
ECO External Crystal Oscillator
ESD Electrostatic Discharge
GPIO General-Purpose Input/Output
HID Human Interface Device
I2C Inter-Integrated Circuit
I2S Inter-IC Sound
IC Integrated Circuit
IDE Integrated Development Environment
IoT Internet of Things
LED Light-emitting Diode
LPO Low Power Oscillator
PC Personal Computer
PDM Pulse Density Modulation
PSoC Programmable System-on-Chip
PWM Pulse Width Modulation
QSPI Quad Serial Peripheral Interface
SAR Successive Approximation Register
SDHC Secure Digital Host Controller
SDIO Secure Digital Input Output
SMIF Serial Memory Interface
SPI Serial Peripheral Interface
SRAM Serial Random Access Memory
Introduction
Table 1-3. Acronyms Used in this Document (continued)

Acronym Definition
SWD Serial Wire Debug
UART Universal Asynchronous Receiver Transmitter
USB Universal Serial Bus
WCO Watch Crystal Oscillator
2. Kit Operation
This chapter introduces you to various features of the PSoC 62S2 Wi-Fi BT Pioneer Board, including
the theory of operation and the onboard KitProg3 programming and debugging functionality,
USB-UART and USB-I2C bridges.
2.1 Theory of Operation

The PSoC 62S2 Wi-Fi BT Pioneer Board is built around a PSoC 6 MCU. Figure 2-1 shows the block
diagram of the PSoC 6 MCU device used on the board. For details of device features, see the device
datasheet.
Figure 2-2 shows the block diagram of the CYW9-BASE-01 Pioneer Board (modified for CY8CKIT-
062S2-43012).
Figure 2-1. PSoC 6 MCU Block Diagram
CPU Subsystem
PSoC 62
CY8C62X8, SWJ/ETM/ITM/CTI SWJ/MTB/CTI
CY8C62XA
SONOS CRYPTO
29 Channel
29 Channel
SRAM0 SRAM1 SRAM2 ROM
4 Channel
Cortex M4 FLASH Cortex M0+
DMA
DW0
DW1
AES,SHA,CRC,
512 KB 256 KB 256 KB 100 MHz (1.1V) 64 KB
150 MHz (1.1V) 2048+32 KB TRNG,RSA,ECC
25 MHz (0.9V)
50 MHz (0.9V)
System Resources 8 KB $ 8 KB $
FPU, NVIC, MPU SRAM Controller SRAM Controller SRAM Controller Initiator/MMIO MUL, NVIC, MPU ROM Controller
FLASH Controller
Power
Sleep Control
POR BOD
OVP LVD System Interconnect (Multi Layer AHB, IPC, MPU/SMPU)
REF
PWRSYS-LP/ULP
DMA
Buck PCLK Peripheral Interconnect (MMIO,PPU) MMIO
Clock
Clock Control
Serial Memory Interface (QSPI)

ILO WDT Prog. Audio
IMO ECO Analog Subsystem
Low Power Comparator
TIMER,CTR,QD, PWM
SD/SDIO/eMMC
FLL 2xPLL
Energy Profiler
2x SDHC
32x TCPWM
2x LPCOMP
SAR
Host + Device
I2C,SPI,UART
SMIF
ADC
I2C, UART
1x SCB
8x SCB
4x SCB
CapSense
EFUSE
1024 bit
I2C,SPI
Reset
CSD
USB-FS
LCD
IOSS GPIO
(12-bit)
Reset Control
XRES
PDM/PCM
2x I2S
Test
TestMode Entry x1
Digital DFT
Analog DFT
Backup SARMUX
Backup Control
BREG
RTC
WCO FS/LS
PHY
Power Modes High Speed I/O Matrix, Smart I/O, Boundary Scan
Active/Sleep
2x Smart IO
LowePowerActive/Sleep
DeepSleep 98x GPIO Enh, 6x GPIO OVT
Hibernate
Backup IO Subsystem
Kit Operation
Figure 2-2. Block Diagram of Pioneer Board

CYW9‐BASE‐01 Architecture Block Diagram
Cypress Device
KitProg3 Mode 10‐pin SWD/ 20‐Pin ETM Reset

Switch & LED JTAG header header Button VDDA Potentiometer No Load
1.8~3.3V SWD SWD

VTARG_REF JTAG VBACKUP Loaded Device
JTAG 1.8~3.3V 2 x User
P5LP_VDD VTARG_REF TRACE VDDD
SWD buttons
I2C/UART_RX/UART_TX
User LEDs
P5LP_VDD
USB
VTARG VTARG (RGB, Red,
Level Orange)
(Micro‐B) UART_RTS
Translator
KitProg3 UART_CTS
QSPI NOR
(PSoC 5LP) VDDIO_0 Flash
P5LP_VDD WL_VDDIO
VTARG Level
BT_UART TX, RX, CTS, RTS QSPI F‐RAM
Monitoring Translator WL_UART TX, RX, KP_GPIO_0 Carrier VDDIO_0
Module
microSD Card
VDDIO_0 Slot
I2C EEPROM
3.3V, VTARG PSoC 6 MCU I/
KP_VBUS O Headers
2 x CapSense Buttons, (Arduino)
1 x 5‐segment PSoC 6 MCU I/
CapSense Slider O Headers
(Non Arduino)
USB Host & Device
The PSoC 62S2 Wi-Fi BT Pioneer Kit comes with the PSoC 62S2 Wi-Fi BT Pioneer Board.
Figure 2-3 and Figure 2-4 show the markup of the Pioneer Board.
Figure 2-3. PSoC 62S2 Wi-Fi BT Pioneer Board - Top View
35 34 16 29 29 33 16 32 31 28 30
1 29
28
2
27
26
3 25
24
4
23
5 22
21
6 20
19
18
9 10 9 11 12 13 14 15 16 17
Kit Operation
Figure 2-4. PSoC 62S2 Wi-Fi BT Pioneer Board - Bottom View
The PSoC 62S2 Wi-Fi BT Pioneer Board has the following peripherals:
1. Power LED (LED1): This Yellow LED indicates the status of power supplied to board.
2. KitProg3 USB connector (J6): The USB cable provided along with the PSoC 62S2 Wi-Fi BT
Pioneer Board connects between this USB connector and the PC to use the KitProg3 onboard
programmer and debugger and to provide power to the board.
3. PSoC 6 MCU VDD power selection jumper (J14): This jumper is used to select the PSoC 6
MCU VDD supply voltage between 1.8 V and 3.3 V.
4. KitProg3 programming mode selection button (SW3): This button can be used to switch
between various modes of operation of KitProg3 (CMSIS-DAP BULK, CMSIS-DAP HID or
DAPLink modes). For more details, see the KitProg3 User Guide.
5. PSoC 6 MCU VDD current measurement jumper (J15): An ammeter can be connected to this
jumper to measure the current consumed by the PSoC 6 MCU VDD power domain.
6. PSoC 6 MCU VDDIO2 and CYW43012 VDDIO power selection jumper (J16): This jumper is
used to select the PSoC 6 MCU VDDIO2 and CYW43012 VDDIO supply voltage between 1.8 V
and 3.3 V. This is not loaded by default.
7. PSoC 6 MCU VDDIO0 current measurement jumper (J19): An ammeter can be connected to
this jumper to measure the current consumed by the PSoC 6 MCU VDDIO0 power domain. This
is not loaded by default.
8. External power supply VIN connector (J5): This connector connects an external DC power
supply input to the onboard regulators.
9. PSoC 6 MCU user buttons (SW2 and SW4): These buttons can be used to provide an input to
PSoC 6 MCU. Note that by default these buttons connect the PSoC 6 MCU pin to ground when
pressed, so you need to configure the PSoC 6 MCU pin as a digital input with resistive pull-up for
detecting the button press. These buttons also provides a wake-up source from low-power
modes of the device. In addition, this button can be used to activate the regulator control output
from PSoC 6 MCU.
Kit Operation
10. Potentiometer connection jumper (J25): This jumper connects the PSoC 6 MCU VDDA to
potentiometer.
11. Potentiometer (R1): This is a 10k Ohm potentiometer connected to PSoC 6 MCU pin P10[6]. It
can be used to simulate a sensor output to PSoC 6 MCU.
12. Arduino-compatible power header (J1): This header powers the Arduino shields. It also has a
provision to power the kit though the VIN input.
13. PSoC 6 MCU reset button (SW1): This button is used to reset PSoC 6 MCU. It connects the
PSoC 6 MCU reset (XRES) pin to ground.
14. PSoC 6 MCU debug and trace header (J12): This header can be connected to an Embedded
Trace Macrocell (ETM)-compatible programmer/debugger. This is not loaded by default.
15. PSoC 6 MCU program and debug header (J11): This 10-pin header allows you to program and
debug the PSoC 6 MCU using an external programmer such as MiniProg4.
16. Arduino Uno R3-compatible I/O headers (J2, J3, and J4): These I/O headers bring out pins
from PSoC 6 MCU to interface with the Arduino shields. Some of these pins are multiplexed with
onboard peripherals and are not connected to PSoC 6 MCU by default. For a detailed informa-
tion on how to rework the kit to access these pins, see Table 1-1 on page 10.
17. CapSense slider (SLIDER) and buttons (BTN0 and BTN1): The CapSense touch-sensing
slider and two buttons, all of which are capable of both self-capacitance (CSD) and mutual-
capacitance (CSX) operation, allow you to evaluate Cypress’ fourth-generation CapSense tech-
nology. The slider and buttons have a 1-mm acrylic overlay for smooth touch sensing.
18. PSoC 6 MCU VDDIO2 current measurement jumper (J18): An ammeter can be connected to
this jumper to measure the current consumed by the PSoC 6 MCU VDDIO2 power domain. This
is not loaded by default.
19. CYW43012 VDDIO current measurement jumper(J17): An ammeter can be connected to this
jumper to measure the current consumed by the CYW43012 VDDIO power domain.
20. Cypress serial NOR flash memory (S25FL512S, U3): The S25HL512S NOR flash of 512-Mbit
capacity is connected to the Quad SPI interface of the PSoC 6 MCU. The NOR device can be
used for both data and code memory with execute-in-place (XIP) supports and encryption.
21. Cypress PSoC 6 (2M) with CYW43012 Carrier Module (CY8CMOD-062S2-43012, MOD1):
This kit is designed to highlight the features of the PSoC 6 MCU on the
CY8CMOD-062S2-43012. For details, see CY8CMOD-062S2-43012 (MOD1) on page 29.
22. CYW43012 based Murata Type 1LV module: The Type 1LV module is an ultra-small module
that includes 2.4 GHz and 5 GHz dual-band WLAN and Bluetooth functionality. Based on
Cypress CYW43012, the module provides high-efficiency RF front end circuits. To ease Wi-Fi
certification, the Type 1LV module complies with IEEE 802.11a/b/g/n and Bluetooth Version 5.0
plus EDR, Power Class 1 + BLE.
23. Wi-Fi/BT antenna: This is the onboard antenna connected to the Wi-Fi and Bluetooth module.
24. PSoC 6 MCU: This kit is designed to highlight the features of the PSoC 6 MCU. For details on
PSoC 6 MCU pin mapping, refer to Table 1-1 on page 10.
25. Cypress serial Ferroelectric RAM (CY15B104QSN, U4): The CY15B104QSN is a 4-Mbit non-
volatile memory employing an advanced ferroelectric process. F-RAM is nonvolatile and per-
forms reads and writes similar to a RAM. It provides reliable data retention for 151 years and is
connected to the Quad SPI interface of the PSoC 6 MCU.
26. CYW43012 VBAT current measurement jumper (J8): An ammeter can be connected to this
jumper to measure the current consumed by the CYW43012 VBAT power domain.
27. CYW43012 VBAT power selection jumper (J9): This jumper is used to select the CYW43012
VBAT supply voltage between 1.8 V, 3.3 V and 3.6 V.
Kit Operation
28. PSoC 6 MCU user LEDs (LED8 and LED9): These two user LEDs can operate at the entire
operating voltage range of PSoC 6 MCU. The LED is active LOW, so the pins must be driven to
ground to turn ON the LED.
29. PSoC 6 I/O header (J21, J22, J24): These headers provide connectivity to PSoC 6 MCU GPIOs
that are not connected to the Arduino compatible headers. Some of these I/Os are also
connected to on-board peripherals see Table 1-1 on page 10 for pin mapping.
30. RGB LED (LED5): This onboard RGB LED can be controlled by the PSoC 6 MCU. The LEDs
are active LOW, so the pins must be driven to ground to turn ON the LEDs.
31. Wi-Fi/BT GPIO header (J23): This header brings out few IOs of the CYW43012 for general
purpose applications.
32. PSoC 6 USB device connector (J7): The USB cable provided with the PSoC 62S2 Wi-Fi BT
Pioneer Kit can also be connected between this USB connector and the PC to use the PSoC 6
MCU USB device applications.
33. Optional USB Host power supply header (J10): This header provides an option to supply
external power to the PSoC 6 USB when used as a USB Host.
34. KitProg3 status LED (LED2): This Yellow LED indicates the status of KitProg3. For details on
the KitProg3 status, see the KitProg3 User Guide.
35. KitProg3 (PSoC 5LP) programmer and debugger (CY8C5868LTI-LP039, U2): The PSoC 5LP
device (CY8C5868LTI-LP039) serving as KitProg3, is a multi-functional system, which includes
a SWD programmer, debugger, USB-I2C bridge and USB-UART bridge. For more details, see
the KitProg3 User Guide.
36. microSD Card holder (J20): Provide SDHC interface with microSD cards with the option to
detect the presence of the card.
See Hardware Functional Description on page 29 for details on various hardware blocks.
Kit Operation
2.2 KitProg3: On-Board Programmer/Debugger

The PSoC 62S2 Wi-Fi BT Pioneer Board can be programmed and debugged using the onboard
KitProg3. KitProg3 is an onboard programmer/debugger with USB-UART and USB-I2C functionality.
A Cypress PSoC 5LP device is used to implement KitProg3 functionality. For more details on the
KitProg3 functionality, see the KitProg3 User Guide.
2.2.1 Programming and Debugging using ModusToolbox

This section presents a quick overview of programming and debugging using ModusToolbox. For
detailed instructions, see Help > ModusToolbox IDE Documentation > User Guide.
1. Connect the board to the PC using the USB cable, as shown in Figure 2-5. It enumerates as a
USB Composite Device if you are connecting it to your PC for the first time. KitProg3 can operate
either in CMSIS-DAP Bulk mode (default), CMSIS-DAP HID mode or DAPLink mode (DAPLink
mode is required for programing using Mbed CLI). KitProg3 also supports CMSIS-DAP Bulk with
two UARTs. Programming is faster with the Bulk mode. The status LED (Yellow) is always ON in
Bulk mode, ramping at 1 Hz rate in HID mode, and ramping at 2 Hz rate in DAPLink mode. Press
and release the Mode select button (SW3) to switch between these modes. If you do not see the
desired LED status, see the KitProg3 User Guide for details on the KitProg3 status and
troubleshooting instructions.
Figure 2-5. Connect USB Cable to USB Connector on the Board
2. In the ModusToolbox IDE, import the desired code example (application) into a new workspace.
a. Click on New Application from Quick Panel.
Figure 2-6. Create New Application
Kit Operation
b. Select the CY8CKIT-062S2-43012 in the Choose Hardware Target window and click Next,
as shown in Figure 2-7.
Figure 2-7. New Application Creation: Choose Target Hardware
c. Select the application in Starter Application window and click Next, as shown in Figure 2-8.
Figure 2-8. New Application Creation: Select Starter Application
d. Click Finish in Summary window, as shown in Figure 2-9.

Figure 2-9. New Application Creation: Summary
Kit Operation
3. To build and program a PSoC 6 MCU application, in the Project Explorer, select <App_Name>
project. In the Quick Panel, scroll to the Launches section and click the <App_Name> Program
(KitProg3) configuration as shown in Figure 2-10.
Figure 2-10. Programming in ModusToolbox
4. ModusToolbox has an integrated debugger. To debug a PSoC 6 MCU application, in the Project
Explorer, select <App_Name> project. In the Quick Panel, scroll to the Launches section and
click the <App_Name> Debug (KitProg3) configuration as shown in Figure 2-11. For a detailed
explanation on how to debug using ModusToolbox, see KBA224621.
Figure 2-11. Debugging in ModusToolbox
Kit Operation
2.2.1.1 Using the OOB Example – PSoC 6 MCU: Hello World

The PSoC 62S2 Wi-Fi BT Pioneer Board is by default programmed with the code example: PSoC 6
MCU: Hello World. The steps below describe on how to use the example. For a detailed description
of the project refer to the example’s readme file in the GitHub repository.
Note: At any point of time, if you overwrite the OOB example, you can restore it back by
programming the PSoC 6 MCU: Hello World. Refer Programming and Debugging using
ModusToolbox on page 23 for programming the board.
1. Connect the board to your PC using the provided USB cable through the KitProg3 USB
connector.
2. Open a terminal program and select the KitProg3 COM port. Set the serial port parameters to
8N1 and 115200 baud.
3. Press the reset button (SW1) on the board and confirm that terminal application displays code
example title and other text Figure 2-12.
Figure 2-12. Hello World in Terminal
4. Confirm that the kit LED blinks at 1 Hz.

5. Press the Enter key. Confirm that the kit LED stops blinking. The terminal displays the message
“LED blinking paused”.
6. Press the Enter key again. Confirm that the kit LED resumes blinking at 1 Hz. The message
displayed on the terminal is updated to “LED blinking resumed”.
You can repeat steps 5 and 6 indefinitely.
Kit Operation
2.2.2 USB-UART Bridge

The KitProg3 on the PSoC 62S2 Wi-Fi BT Pioneer Board can act as a USB-UART bridge.
The primary UART and flow-control lines between the PSoC 6 MCU and the KitProg3 are hard-wired
on the board, as Figure 2-13 shows.
Figure 2-13. UART Connection between KitProg3 and PSoC 6
.LW3URJ 36R&0&8
5;
<WͺhZdϭͺdy 3>@
7;
86% <WͺhZdϭͺZy 3>@
576
<WͺhZdϭͺd^ 3>@
&76
<WͺhZdϭͺZd^ 3>@
The secondary UART and flow-control lines between the CYW43012 and the KitProg3 are hard-
wired on the board, as Figure 2-14 shows.
Figure 2-14. UART Connection between KitProg3 and CYW43012
.LW3URJ &<:
5;
<WͺhZdϮͺdy dͺhZdͺZy
7;
86% <WͺhZdϮͺZy dͺhZdͺdy
576
<WͺhZdϮͺd^ dͺhZdͺZd^
&76
<WͺhZdϮͺZd^ dͺhZdͺd^
For more details on the KitProg3 USB-UART functionality, see the KitProg3 User Guide.
Kit Operation
2.2.3 USB-I2C Bridge

The KitProg3 can function as a USB-I2C bridge and can communicate with the Bridge Control Panel
(BCP) software which acts as an I2C master. The I2C lines on the PSoC 6 MCU are hard-wired on
the board to the I2C lines of the KitProg3, with onboard pull-up resistors as Figure 2-15 shows. The
USB-I2C supports I2C speeds of 50 kHz, 100 kHz, 400 kHz, and 1 MHz. For more details on the
KitProg3 USB-I2C functionality, see the KitProg3 User Guide.
Figure 2-15. I2C Connection between KitProg3 and PSoC 6 MCU
P6_VDD
KitProg3 PSoC 6 MCU
R133 R134
USB 4.7K 4.7K
KP_I2C_SDA P6[1]
KP_I2C_SCL P6[0]
3. Hardware
3.1 Schematics
Refer to the schematic files available in the kit webpage.
3.2 Hardware Functional Description

This section explains in detail the individual hardware blocks.
3.2.1 CY8CMOD-062S2-43012 (MOD1)

CY8CMOD-062S2-43012 PSoC 6 (2M) with CYW43012 Carrier Module is a castellated PCB
module which consists mainly of PSoC 6 MCU and CYW43012 devices. The module also houses a
2.45-GHz/5-GHz dual-band chip antenna, RF switch for antenna diversity, Low Power Oscillator
(LPO) for CYW43012, crystal oscillators for PSoC 6 MCU, modulation and integration capacitors to
support CapSense and other passive components required for the proper working of PSoC 6 MCU
and CYW43012. Pre-certified Type 1LV module with CYW43012 from Murata, LBEE59B1LV, is used
for the ease of development. The antenna used is 2450AD14A5500 Dual Band 2.45GHz/5GHz Mini
Chip Antenna from Johanson. The castellated PCB module has 137 castellated pads, which are
used for different voltage rails and I/O signals of PSoC 6 MCU and CYW43012.
For more information, see the PSoC 6 MCU webpage, Murata Type 1LV webpage and the
datasheet.
Figure 3-1. Schematics of CY8CMOD-062S2-43012
Supply for PSoC 6 MCU

VDDA
U1B VBUCK
A12 J2 L4 2.2uH
A13 VDDA VIND1
VDDIOA K1 C14
VDDD NC1 K2 4.7uF
VDDIO1 NC2 K3 6.3V
A1 NC3 VREF
K12 VDDD
VDDIO1
VDDIO0 B13
VREF
C4 C24
VDDIO0 1uF
VDDIO2 6.3V
VCCD
L4
VDDIO2 A2
VDD_NS VCCD
C39
J1 1uF
VDD_NS 6.3V
VDDUSB
B12
M1 VSS0 C3
VDDUSB VSS1 D4
VBACKUP VSS2 D10 VBUCK VCCD
VSS3 K4
D1 VSS4 K10
VBACKUP VSS5 R20 0 OHM
CY 8C624ABZI-S2D44
Hardware
PSoC 6 MCU Signals

U1A
E3 F1
P0_0 E2 P0.0 XRES XRES_L
P0_1 E1 P0.1 H13
P0_2 F3 P0.2 P8.0 H12 P8_0
VDDIO_1LV P8_1
P0_3 F2 P0.3 P8.1 H11
P0_4 G3 P0.4 P8.2 G13 P8_2
R16 47K P8_3
P0_5 P0.5 P8.3 G12
R13 47K P8_4
R10 47K G2 P8.4 G11
P1_0 G1 P1.0 P8.5 F13 P8_5
R18 47K P8_6
P1_1 H3 P1.1 P8.6 F12
R22 47K P8_7
P1_2 H2 P1.2 P8.7
R17 47K DNI
P1_3 H1 P1.3 E11
R8 47K DNI P9_0
P1_4 J3 P1.4 P9.0 E12
P1_5 P1.5 P9.1 E13 P9_1
M2 P9.2 F11 P9_2
R6 33 OHM P9_3
SDIO_DATA0 N2 P2_0 P9.3 D13
R2 33 OHM P9_4
SDIO_DATA1 L3 P2_1 P9.4 D12
R4 33 OHM P9_5
SDIO_DATA2 M3 P2_2 P9.5 D11
R3 33 OHM P9_6
SDIO_DATA3 N3 P2_3 P9.6 C13
R19 33 OHM P9_7
SDIO_CMD N1 P2_4 P9.7
SDIO_CLK R7 33 OHM
M4 P2_5 C12
WL_REG_ON N4 P2_6 P10.0 A11 P10_0
WL_DEV_WAKE P2_7 P10.1 B11 P10_1
L5 P10.2 C11 P10_2
VDDIO_1LV BT_UART_TXD R29 0 OHM P10_3
R28 0 OHM M5 P3_0 P10.3 A10
BT_UART_RXD N5 P3_1 P10.4 B10 P10_4
R5 47K BT_UART_CTS R26 0 OHM P10_5
DNI R27 0 OHM L6 P3_2 P10.5 C10
BT_UART_RTS M6 P3_3 P10.6 A9 P10_6
BT_REG_ON N6 P3_4 P10.7 P10_7
BT_DEV_WAKE P3_5 B9
L7 P11.0 C9 P11_0
BT_HOST_WAKE M7 P4_0 P11.1 A8 P11_1
WL_HOST_WAKE P4_1 P11.2 B8 P11_2
N7 P11.3 C8 P11_3
P5_0 L8 P5.0 P11.4 A7 P11_4
P5_1 M8 P5.1 P11.5 B7 P11_5
P5_2 N8 P5.2 P11.6 C7 P11_6
P5_3 L9 P5.3 P11.7 P11_7
P5_4 M9 P5.4 A6
P5_5 N9 P5.5 P12.0 B6 P12_0
P5_6 N10 P5.6 P12.1 C6 P12_1
P5_7 P5.7 P12.2 A5 P12_2
M10 P12.3 B5 P12_3
P6_0 L10 P6.0 P12.4 C5 P12_4
P6_1 L11 P6.1 P12.5 A4 P12_5
P6_2 M11 P6.2 P12.6 B4 P12_6
P6_3 N11 P6.3 P12.7 P12_7
P6_4 M12 P6.4 B1
P6_5 N12 P6.5 P13.0 A3 P13_0
P6_6 M13 P6.6 P13.1 B3 P13_1
P6_7 P6.7 P13.2 B2 P13_2
L13 P13.3 C2 P13_3
P7_0 L12 P7.0 P13.4 C1 P13_4
P7_1
K13 P7.1 P13.5 D3 P13_5
P7_2
N13 P7.2 P13.6 D2 P13_6
P7_3 K11 P7.3 P13.7 P13_7
P7_4 J13 P7.4 L2
P7_5 J12 P7.5 USBDP L1 USBDP
P7_6 J11 P7.6 USBDM USBDM
P7_7
P7.7
CY 8C624ABZI-S2D44
Decoupling Capacitors
VDDD VDDIO0 VDDIO1 VDDIO2 VBACKUP
C35 C13 C32 C33 C16 C36 C9 C8 C26 C29

10uF 0.1uF 1uF 0.1uF 1uF 0.1uF 0.1uF 1uF 0.1uF 1uF
25V 10V 6.3V 10V 6.3V 10V 10V 6.3V 10V 6.3V
VDDA VDDUSB VDD_NS
C27 C28 C30 C34 C6 C5 C18 C17

10uF 0.1uF 1uF 0.1uF 0.1uF 1uF 10uF 0.1uF
25V 10V 6.3V 10V 10V 6.3V 25V 10V
Hardware
Reset
VDDD
R33
4.7K WCO
C20 22pF P0_1
25V
XRES_L
Y1
C45 32.768KHz
0.1uF
10V C23 22pF P0_0
25V
ECO
CINT, CMOD & CSH P12_6
C10 0.47nF P7_1 Y2 C37
CINTA 25V 17.2032MHz 10pF
3
25V
C15 0.47nF P7_2 4 2
CINTB 25V Optional CSH
C38
1
C19 2.2nF P7_7 10pF

CMOD 25V 25V
P12_7
Supply for 1LV Module

VBAT
U2B
13 27
14 VBAT1 GND27 30
VBAT2 GND30 36
VDDIO_1LV GND36 47
GND47 48
35 GND48 50
VDDIO GND50 52
VDDIO_SFL GND52 53
GND53 57
4 GND57 59
VDDIO_SFL GND59 60
VDDOUT_VDDIO GND60 65
GND65 72
28 GND72 73
VDDOUT_VDDIO GND73 94
VOUT_3P3 GND94 95
GND95 96
12 GND96 97
VOUT_3P3 GND97 98
1 GND98 99
2 GND1 GND99 100
3 GND2 GND100 101
6 GND3 GND101 102
11 GND6 GND102 103
15 GND11 GND103 104
19 GND15 GND104 105
20 GND19 GND105 106
GND20 GND106
LBEE59B1LV
Hardware
1LV Module Signals
U2A
24 58 RF_OUT C51 8.2pF RF_SW_IN

SDIO_CLK 26 SDIO_CLK ANT0 50V
SDIO_CMD 23 SDIO_CMD
SDIO_DATA0 22 SDIO_DATA_0 51 BT_RF C12 C11
SDIO_DATA1 21 SDIO_DATA_1 BT_RF_IN TBD TBD
SDIO_DATA2 25 SDIO_DATA_2 49 50V 50V
SDIO_DATA3 SDIO_DATA_3 BT_RF_OUT DNI DNI
7 54
WL_HOST_WAKE 8 WL_HOST_WAKE RF_SW_CTRL_5 56
WL_DEV_WAKE 10 WL_DEV_WAKE RF_SW_CTRL_6 16 RF_SW_CTRL_8
WL_REG_ON WL_REG_ON RF_SW_CTRL_8 55
62 RF_SW_CTRL_10 18
WL_UART_TX 63 WL_UART_TX RF_SW_CTRL_11 17
WL_UART_RX 64 WL_UART_RX RF_SW_CTRL_12
WL_GPIO_14 61 WL_GPIO_14 45
WL_GPIO_15 WL_GPIO_15 P0 TP_SMD10
46
P1 TP_SMD9
31 40
BT_UART_TXD 32 BT_UART_TXD P5 41 P5
BT_UART_RXD 33 BT_UART_RXD P6 43 P6
BT_UART_RTS 34 BT_UART_RTS P7 42 P7
BT_UART_CTS BT_UART_CTS P8 37 TP_SMD12
5 P9 38 TP_SMD11
BT_HOST_WAKE 29 BT_HOST_WAKE P11 44
BT_DEV_WAKE 9 BT_DEV_WAKE P12 39
BT_REG_ON BT_REG_ON P13
89
BT_I2S_DO 88 BT_I2S_DO 81
BT_I2S_DI 87 BT_I2S_DI CLK_REQ
BT_I2S_CLK 86 BT_I2S_CLK 79 WL_GPIO_14
BT_I2S_WS BT_I2S_WS SFL_CS 77 WL_GPIO_14
WL_GPIO_15
84 SFL_CLK 74 WL_GPIO_15
82 BT_PCM_IN SFL_IO0 78
85 BT_PCM_OUT SFL_IO1 76
83 BT_PCM_CLK SFL_IO2 75
BT_PCM_SY NC SFL_IO3
90 66
BT_GPIO_2 93 BT_GPIO_2 JTAG_TDO 67 WL_JTAG_TDO
BT_GPIO_3 92 BT_GPIO_3 JTAG_TDI 68 WL_JTAG_TDI
BT_GPIO_4 91 BT_GPIO_4 JTAG_TMS_SWD 69 WL_JTAG_TMS
BT_GPIO_5 BT_GPIO_5 JTAG_TCK_SWD 70 WL_JTAG_TCK
80 JTAG_SEL 71 WL_JTAG_SEL
LPO_OUT R35 0 OHM
EXT_LPO JTAG_TRS WL_JTAG_TRST_L
R36 0 OHM
EXT_LPO
DNI
LBEE59B1LV
Decoupling Capacitors
VOUT_3P3 VDDIO_SFL VDDOUT_VDDIO VDDIO_1LV VBAT
C4 C2 C21 C31 C1 C3
0.1uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF
10V 10V 10V 10V 25V 10V
DNI DNI
OnBoard LPO LHL IOs

VDDIO_1LV
Y3 R31 0 OHM BT_DEV_WAKE
P O LPO_OUT P5
R23 0 OHM SDIO_CMD
VDD OUT P6
R30 0 OHM WL_DEV_WAKE
P7
C40
1uF G N Make sure NO stub for SDIO_CMD net
6.3V GND NC
SIT1533AI-H4-DCC-32.768E
32.768KHz
Antenna Diversity Switch

VOUT_3P3
G3
C46 0.1uF J2
10V U3 G1
6 1 C47 8.2pF ANT0 S
VDD OUT1 DNI 50V G2
RF_SW_IN 5 3 ANT1_ANT2
IN OUT2 A-1JB
RF_SW_CTRL_8 4 2 DNI
VCTL GND
C48 RTC7608
8.2pF SON6H_0.35mm
50V
DNI
Hardware
Antenna A1
3 2
NC1 NC2
ANT1_ANT2 C49 8.2pF ANT1 L5 1.8nH 4 1
GND
50V FEED
C50 2450AD14A5500T
8.2pF C44 L6 L7
50V 0.2pF 1.5nH 1.8nH
DNI 200V
G3
J1
G1
ANT2 S
G2
A-1JB
DNI
Carrier Module Footprint

MOD1B
136 124
P6_0 133 I2C_SCL CSX_TX P1_0
VREF
P6_1 I2C_SDA 33
VDDA MOD1A VBAT P8_1
53 CSB_0 31
55 28 ARD_AREF CSB_1 P8_2
VDDA_MCU VBAT_WL 29 52 36
VBAT_WL P10_0 60 ARD_A0 CSS_0 34 P8_3
VDDD P10_1 P8_4
VDDIO_1LV 59 ARD_A1 CSS_1 32
83 P10_2 58 ARD_A2 CSS_2 38 P8_5
VDDD_MCU 115 P10_3 62 ARD_A3 CSS_3 37 P8_6
VDDIO_WL P10_4 63 ARD_A4 CSS_4 P8_7
VDDIO0 P10_5
VCCD 61 ARD_A5 98
67 P10_6 64 ARD_A6 CSD_SHIELD P7_4
VDDIO0_MCU 82 P10_7 ARD_A7 71
VCCD_MCU 44 FRAM_SSEL 72 P11_0
VDDIO1 P11_2
P7_0 ETM_CLK FLASH_SSEL 66
47 46 QSPI_CLK 70 P11_7
VDDIO1_MCU P9_0 48 ARD_A8 QSPI_DATA0 74 P11_6
P9_1 49 ARD_A9 QSPI_DATA1 65 P11_5
VDDIO2 P9_2 P11_4
45 ARD_A10 QSPI_DATA2 73
94 P9_3 50 ARD_A11 QSPI_DATA3 P11_3
VDDIO2_MCU P9_4 56 ARD_A12 79
P9_5 57 ARD_A13 SD_CMD 80 P12_4
VDD_NS P9_6 P12_5
51 ARD_A14 SD_CLK 88
89 P9_7 ARD_A15 SD_DATA0 86 P13_0
VDD_NS_MCU 2 SD_DATA1 85 P13_1
1 P5_0 3 ARD_D0 SD_DATA2 87 P13_2
VBACKUP P13_3
GND_1 30 P5_1 4 ARD_D1 SD_DATA3 97
84 GND_2 54 P5_2 6 ARD_D2 SD_CD_L P13_7
VBACKUP_MCU GND_3 68 P5_3 5 ARD_D3 92
GND_4 81 P5_4 9 ARD_D4 MCU_USBDP 91 USBDP
VDDUSB USBDM
GND_5 90 P5_5 7 ARD_D5 MCU_USBDM
93 GND_6 137 P5_6 8 ARD_D6 134
VDDUSB_MCU GND_7 P5_7 ARD_D7 USB_VBUS_DET 135 P6_2
23 USB_INT 127 P6_3
P7_5 25 ARD_D8 USB_HOST_EN P1_2
P7_6 78 ARD_D9 123
P12_3 76 ARD_D10 RGB_R 132 P1_1
P12_0 75 ARD_D11 RGB_G 26 P0_5
P12_1 77 ARD_D12 RGB_B P7_3
P12_2 ARD_D13 126
130 LED_1 69 P1_5
P0_4 125 BUTTON_1 LED_2 P11_1
MOD1C
P1_4 BUTTON_2 129
100 108 MCU_IO_0 131 P0_2
SDIO_DATA0 101 WL_SDIO_DATA0 BT_UART_TXD 106 BT_UART_TXD 39 MCU_IO_1 128 P0_3
SDIO_DATA1 102 WL_SDIO_DATA1 BT_UART_RXD 107 BT_UART_RXD XRES_L 40 MCU_XRES_L MCU_IO_2 24 P1_3
SDIO_DATA2 104 WL_SDIO_DATA2 BT_UART_CTS 109 BT_UART_CTS P6_4 43 MCU_TDO MCU_IO_3 35 P13_6
SDIO_DATA3 103 WL_SDIO_DATA3 BT_UART_RTS BT_UART_RTS P6_5 41 MCU_TDI MCU_IO_4 95 P8_0
SDIO_CMD 99 WL_SDIO_CMD 122 P6_6 42 MCU_TMS_SWDIO MCU_IO_5 96 P13_4
SDIO_CLK WL_SDIO_CLK BT_HOST_WAKE 120 BT_HOST_WAKE P6_7 MCU_TCLK_SWCLK MCU_IO_6 P13_5
14 BT_DEV_WAKE 121 BT_DEV_WAKE
WL_HOST_WAKE 15 WL_HOST_WAKE BT_REG_ON BT_REG_ON
WL_DEV_WAKE Carrier Module Footprint
16 WL_DEV_WAKE 112
WL_REG_ON WL_REG_ON BT_I2S_CLK 111 BT_I2S_CLK
11 BT_I2S_WS 114 BT_I2S_WS
WL_UART_TX 12 WL_UART_TX BT_I2S_DO 113 BT_I2S_DO
WL_UART_RX 13 WL_UART_RX BT_I2S_DI BT_I2S_DI
WL_GPIO_14 10 WL_IO_1 116
WL_GPIO_15 WL_IO_2 BT_IO_2 117 BT_GPIO_2
20 BT_IO_3 119 BT_GPIO_3
WL_JTAG_TCK 19 WL_JTAG_TCK BT_IO_4 118 BT_GPIO_4
WL_JTAG_TMS 21 WL_JTAG_TMS BT_IO_5 BT_GPIO_5
WL_JTAG_TRST_L 18 WL_JTAG_TRST_L 27
WL_JTAG_TDI 17 WL_JTAG_TDI RFU_1 105
WL_JTAG_TDO 22 WL_JTAG_TDO RFU_2
WL_JTAG_SEL WL_JTAG_SEL 110
LPO_IN EXT_LPO
Hardware
3.2.2 PSoC 5LP-based KitProg3 (U2)

An onboard PSoC 5LP (CY8C5868LTI-LP039) device is used as KitProg3 to program and debug
PSoC 6 MCU. The PSoC 5LP device connects to the USB port of a PC through a USB connector
and to the SWD and other communication interfaces of PSoC 6 MCU.
The PSoC 5LP device is a true system-level solution providing MCU, memory, analog, and digital
peripheral functions in a single chip. For more information, visit the PSoC 5LP web page. Also, see
the CY8C58LPxx Family datasheet.
Figure 3-2. Schematics of PSoC 5LP based KitProg3
PSoC 5LP based KitProg3

PSoC 5LP Power
P5LP_VDD UART_1_CTS KP_VBUS P5LP_VDD
P5LP2_0 TP19
P5LP2_1 R2 0 OHM RED
P5LP2_2 P5LP_VCCD No Load
P5LP2_3
P5LP2_4
UART_2_RTS
C11 1uF
10V
SAR Bypass
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
Capacitor
H
U2
VDDIO
VDDIO2
EPAD
VDDD
VSSD
VCCD
P2[5]
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P15[5]
P15[4]
P0[7]
P0[6]
P0[5]
P0[4]
P5LP_VDD
1 51
2 P2[6] P0[3] 50 UART_2_TX
KP_PMIC_EN 3 P2[7] P0[2] 49 UART_2_CTS
RESET 4 P12[4] P0[1] 48 P5LP_SIO_VREF
5 P12[5] P0[0] 47
6 VSSB P12[3] 46 KP_SWCLK
7 IND P12[2] 45 KP_SWDIO
8 VBOOST VSSD 44
9 VBAT VDDA 43
VSSD CY8C5868LTI-LP039 VSSA
10 42 C13 1uF
TP1 11 XRES VCCA 41 10V
TP2 12 P1[0] P15[3] 40
TP3 P5LP1_2 13 P1[1] P15[2] 39
14 P1[2] P12[1] 38 KP_I2C_SDA
P5LP1_4 15 P1[3] P12[0] 37 KP_I2C_SCL
16 P1[4] P3[7] 36
P5LP_VDD 17 P1[5] P3[6] 35 KP_GPIO_1
P15[6] D+
P15[7] D-
VDDIO1 VDDIO3 P5LP_VDD

VDDD
VCCD
P12[6]
P12[7]
P15[0]
P15[1]
VSSD
P1[6]
P1[7]
P3[0]
P3[1]
P3[2]
P3[3]
P3[4]
P3[5]
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
P5LP_VDD P5LP_VCCD
KP_GPIO_0
UART_1_RTS USB_V_SENSE
UART_1_TX VTARG_MEAS
UART_1_RX
KP_USB_DP R11 22E C12 1uF
KP_USB_DM R12 22E 10V
Del-Sig Bypass Capacitor
UART_2_RX
Hardware
3.2.3 Serial Interconnection between PSoC 5LP and PSoC 6 MCU

In addition to the use as an onboard programmer, the PSoC 5LP device functions as an interface for
the USB-UART and USB-I2C bridges, as shown in Figure 3-3. The USB-Serial pins of the PSoC 5LP
device are hard-wired to the I2C/UART pins of the PSoC 6 MCU. These pins are also available on
the Arduino-compatible I/O headers.
Figure 3-3. Schematics of Programming and Serial Interface Connections
Target MCU SWD KitProg3 Interface

R37 0 OHM TMS_SWDIO
KP_SWDIO
R36 0 OHM TCLK_SWCLK
KP_SWCLK
RESET R35 0 OHM XRES_L_MCU
KitProg3 I2C Interface

P6_VDD
VTARG
I2C Pull-ups
R133 4.7K
No Load
R134 4.7K
No Load R13 R14
4.7K 4.7K
KP_I2C_SCL R58 0 OHM
P6_I2C_SCL
KP_I2C_SDA R59 0 OHM KP_I2C_SCL
P6_I2C_SDA
KP_I2C_SDA
Primary UART H/W Flow Control Level Translator

KitProg3 UART Interface P5LP_VDD P5LP_VDD P6_VDD_BUF
R61 0 OHM C25 0.1uF C26 0.1uF

UART_1_RX ARD_D1 16V 16V
R116 0 OHM IO1 U9
No Load R135 100K 1 6
No Load 3 VCCA VCCB 4
5 A B 2 B_UART_1_RTS
UART_1_TX R21 0 OHM ARD_D0
UART_1_RTS DIR GND
R115 0 OHM IO0 74LVC1T45DW-7
No Load C29 0.1uF C28 0.1uF
16V U10 16V
1 6
R19 0 OHM 3 VCCA VCCB 4
B_UART_1_CTS ARD_D2 UART_1_CTS 5 A B 2 B_UART_1_CTS
B_UART_1_RTS R18 0 OHM ARD_D3 DIR GND R5 100K
74LVC1T45DW-7
Hardware
3.2.4 Serial Interconnection Between PSoC 5LP and CYW43012

The PSoC 5LP device also has a secondary UART that is connected to the BT_UART of CYW43012
(Murata Type 1LV).
Figure 3-4. Serial Interconnection Between PSoC 5LP and CYW43012
KitProg3 Secondary UART Multiplexing

KitProg3 Level Translator for Secondary UART and GPIO
B_UART_2_TX R52 0 OHM BT_UART_RXD
P5LP_VDD VDDIO_WL R48 0 OHM WL_UART_RX
No Load
C31 1uF C30 1uF
16V 16V
B_UART_2_RX R53 0 OHM BT_UART_TXD
20
R49 0 OHM
1
U17 WL_UART_TX
No Load
VCCB
VCCA
19 2
UART_2_TX 18 B0 A0 3 B_UART_2_TX R54 0 OHM
UART_2_RX B1 A1 B_UART_2_RX B_UART_2_RTS BT_UART_CTS
17 4
UART_2_RTS 16 B2 A2 5 B_UART_2_RTS
UART_2_CTS 15 B3 A3 6 B_UART_2_CTS
KP_GPIO_0 14 B4 A4 7 B_KP_GPIO_0 B_UART_2_CTS R55 0 OHM BT_UART_RTS
KP_GPIO_1 13 B5 A5 8 TP21
12 B6 A6 9 VDDIO_WL 100K R137
B7 A7 No Load
H 11 R98 10K
GND
DAP OE No Load
FXMA108BQX R99
10
10K
P5LP_VDD
100K R136 UART_2_RTS

No Load
0 OHM R50
B_KP_GPIO_0 No Load USER_BTN_2
3.2.5 Power Supply System

The power supply system on this board is versatile, allowing the input supply to come from the
following sources:
■ 5V from the onboard USB Micro-B connectors (J6 and J7)
■ 7V–12V from external power supply through the VIN barrel jack (J5) or from an Arduino shield
Figure 3-5. Schematics of Power Supply Input and OR’ing
PSoC 6 MCU USB Host/Device
VIN Header Micro-B connector KitProg3 USB Micro-B KP_VBUS
VIN P6_VDD_BUF P6_VBUS connector
R175 100K J6
J7 10118194-0001LF 1
J5 VBUS
1 1 2
VBUS 2 TP24 DM 3 KP_USB_DM
3 C34 P6_USB_DM KP_USB_DP
DM 3 DP 4
2 1uF TVS1 P6_USB_DP
DP 4 ID 5
S6
S5
S4
S3
S2
S1
16V SD12CT1G ID 5 P6_USB_ID GND

S6
S5
S4
S3
S2
S1
POWER JACK P-5 30kV GND 10118194-0001LF

SH6
SH5
SH4
SH3
SH2
SH1
TP23
U5
SH6
SH5
SH4
SH3
SH2
SH1
U6 KP_VBUS
P6_VBUS 1 4
1 4 R17 100K 2 5
H
R27 100K 2 5 3 6
H
3 6 C1 10nF RCLAMP0854P.TCT C2
C23 10nF RCLAMP0854P.TCT C24 50V 0.1uF
50V 0.1uF 16V
Power Supply 'OR'ing 16V USB_Hold
VIN VCC_IN USB_Hold
JMP1
D3 PMEG3020BEP 1 2
1 2 JMP2
KP_VBUS
D1 PMEG3020BEP
P6_VBUS
D2 PMEG3020BEP
TP5
RED
No Load
Hardware
3.2.5.1 Voltage regulators

The power supply system is designed for the voltage configurations listed in Table 3-1. Some
configurations achievable on this kit are outside the operating range for the device. However, it is not
possible to achieve all applicable configurations by changing jumper positions but rather requires re-
work of respective 0-ohm resistors.
VDDIO_WL and VDDIO2_MCU must be at the same voltage since they power the SDIO interface
between PSoC 6 MCU and CYW43012. Hence both are supplied by the VCC_VDDIO2_IN domain.
Three buck regulators U15, U13 and U7 are used to achieve 1.8 V, 3.3 V and 3.6 V outputs
respectively. Figure 3-6 shows the schematics of the voltage regulator circuits.
Table 3-1. Operating voltage ranges of domains
Carrier Module (MOD1) Operating Voltage Voltage
Voltage Domain Power Pins powered by the Voltage Configuration Selection
domain Min (V) Max (V) applicable in kit Header
VCC_VBAT VBAT_WL 3.2 4.4 3.6V, 3.3V J9
VCC_VDDIO2_IN VDDIO2_MCU, VDDIO_WL 1.62 1.98 1.8V J16 (not loaded)
VTARG VDDD_MCU, VDDIO1_MCU, 1.7 3.6 1.8, 3.3V J14
VDDA_MCU, VDD_NS_MCU,
VBACKUP_MCU
VCC_VDDIO0 VDDIO0_MCU 1.7 3.6 1.8, 3.3V None
(uses 0 Ohms)
Figure 3-6. Voltage Regulators
VCC_IN
VBAT Voltage Regulator VCC_VBAT
U7 L1 4.7uH 3.6V 1A
5 6
IN LX C45
C42 C43 R71 10nF D5 C74 R69 C41 C79 C46
10uF 0.1uF 100K 1 50V PMEG3020BEP 47pF 40.2K 22uF 22uF 0.1uF
25V 16V BST 50V 1% 25V 25V 16V
4 3 R73
GND
EN FB 27.4K
1%
AOZ1280CI
2
B_KP_PMIC_EN
R70 13K R171 0 OHM
1% No Load
J9
Note: 1.8V is not a valid 1
operating voltage on this kit. 2
J9 Jumper Voltage (V) 3 R72 100K
1-2 1.8 1%
Not Present 3.3
2-3 3.6 R172 0 OHM
No Load
VCC_3V3
VCC_IN
3.3V Voltage Regulator
U13 L2 4.7uH 3.3V 600mA
5 6
IN LX C39
C36 C37 10nF D6 C75 R65 R75 C35 C80 C40
10uF 0.1uF 1 50V PMEG3020BEP 47pF 40.2K 88.7K 22uF 10uF 0.1uF
25V 16V BST 50V 1% 1% 25V 25V 16V
4 3
GND
EN FB
AOZ1280CI Note: If R74 is loaded

2
B_KP_PMIC_EN
R66 13K R74 0 OHM output will be 2.5V.
1% No Load
VCC_1V8
VCC_IN
1.8V Voltage Regulator
U15 L3 4.7uH 1.8V 600mA
5 6
IN LX C51
C48 C49 10nF D7 C76 R77 C47 C81 C52
10uF 0.1uF 1 50V PMEG3020BEP 47pF 40.2K 22uF 10uF 0.1uF
25V 16V BST 50V 1% 25V 25V 16V
4 3
GND
EN FB
AOZ1280CI
2
B_KP_PMIC_EN
R78 32.4K
1%
Hardware
3.2.5.2 Voltage Selection

VCC_VBAT has a dedicated regulator that changes voltage by varying the feedback voltage through
the resistor network at J9.
VTARG and VCC_VDDIO2_IN have dedicated 3-pin voltage selection headers J14 and J16
respectively that select between VCC_3V3 or VCC_1V8 voltages. Figure 3-7 shows the schematics
of the power selection circuits.
Note: In this kit, CYW43012 only works with VCC_VDDIO2_IN at VCC_1V8 configuration and
hence by default, R84 is loaded and J16 is not loaded.
Figure 3-7. Voltage Selection Headers
VTARG Voltage Selection Header VCC_VDDIO2_IN
VCC_1V8 VTARG VCC_3V3
Voltage Selection Header
VCC_1V8 VCC_VDDIO2_IN VCC_3V3
R82 0 OHM R83 0 OHM R84 0 OHM R85 0 OHM

No Load No Load No Load
1.8V 1.8V
1
2
3
1
2
3
3.3V J14 3.3V J16
No Load
VCC_VBAT
3.6V 1A
C74 R69
47pF 40.2K
50V 1%
R73
27.4K
1%
R171 0 OHM
No Load
J9
1
2
3 R72 100K
1%
R172 0 OHM
No Load
VCC_VDDIO0 voltage can be selected between VCC_3V3 and VCC_1V8 using zero-ohm resistors.
It is connected to VCC_3V3 by default as microSD card (powered by VCC_VDDIO0) works only at
3.3V. Figure 3-8 shows the schematics of the voltage selection circuits.
Figure 3-8. Voltage Selection
VDDIO0 Voltage Selection
VCC_3V3 VCC_VDDIO0 VCC_1V8
R44 0 OHM R45 0 OHM

No Load
Hardware
3.2.5.3 Current Measurement Headers

The current of the following domains have dedicated 2-pin headers to facilitate easy current mea-
surement using an ammeter across the pins.
Table 3-2. Current Measurement Headers
Domain Name Header Reference Designator Loaded by default
VBAT J8 Y
P6_VDD J15 Y
VDDIO_WL J17 Y
VDDIO2 J18 N
VDDIO0 J19 N
Figure 3-9. Current Measurement Headers

VDDIO0 Current Measurement
Current Measurement MCU Current Measurement
J19 HDR2
2
1
J8 HDR2 No Load J15 HDR2
2
1
VTARG P6_VDD
2
1
VCC_VBAT VBAT
VCC_VDDIO0 VDDIO0
R95 0 OHM R88 0 OHM

No Load R97 0 OHM No Load
VDDIO2 & VDDIO_WL Current Measurement

J17 HDR2 J18 HDR2
2
1
2
1
No Load
VCC_VDDIO2 VDDIO_WL VCC_VDDIO2 VDDIO2
R96 0 OHM R94 0 OHM

No Load
Note: When measuring P6_VDD current, make sure that the J25 jumper is removed. This will
disconnect the potentiometer from VDDA and removes the leakage caused by it.
3.2.6 I/O Headers

3.2.6.1 Arduino-compatible Headers (J1, J2, J3, J4)
The board has four Arduino-compatible headers: J1, J2, J3, and J4. You can connect 3.3 V Arduino-
compatible shields to develop applications based on the shield’s hardware.
Note: 5-V shields are not supported and connecting a 5-V shield may permanently damage the
board.
Note: All Arduino header pins are not connected to the same voltage reference. ARD_D[10:13] are
powered by VDDIO0 whereas rest are powered by domains connected to VTARG. Hence arduino
shields particularly that use ARD_D[10:13] must no be used when VTARG is 1.8V.
3.2.6.2 PSoC 6 MCU I/O Headers (J21, J22, and J24)

These headers provide connectivity to PSoC 6 MCU GPIOs that are not connected to the Arduino-
compatible headers. Majority of these pins are multiplexed with onboard peripherals and are not
connected to PSoC 6 MCU by default.
Hardware
3.2.6.3 WL/BT I/O Headers (J23)

These headers provide connectivity to a few of the CYW43012 GPIOs that are available at the cas-
tellated pads. All these I/O work at VDDIO_WL voltage (1.8 V by default).
Figure 3-10. I/O Headers
Arduino & Extended Headers VREF

J3 J21
10 10
P6_I2C_SCL 9 9 USER_BTN_2
P6_I2C_SDA 8 8 USER_BTN_1
IO15
J1 VTARG 7 7
IO14
8 J1_3V3 6 6
ARD_D13 IO13
7 5 5
ARD_D12 IO12
6 J1_5V0 4 4
XRES_L_MCU ARD_D11 IO11
5 3 3
ARD_D10 IO10
4 2 2
ARD_D9 IO9
3 VIN 1 1
ARD_D8 IO8
2
1 CON10 HEADER10
No Load
CON8 J4 J22
8 8
ARD_D7 IO7
J2 7 7
ARD_D6 IO6
1 2 6 6
ARD_A0 A8 ARD_D5 IO5
3 4 5 5
5 6 4 4
7 8 3 3
9 10 2 2
11 12 1 1
13 14
ARD_A6 15 16 A14
CON8 HEADER8
ARD_A7 A15
No Load
CON 8x2
J23
1 2
BT_I2S_CLK 3 4 BT_UART_RXD
J24 BT_I2S_WS BT_UART_TXD
2 1 5 6
O_LED_L 4 3 RGB_R_LED_L BT_I2S_DO 7 8 BT_UART_CTS
R_LED_L 6 5 RGB_G_LED_L BT_I2S_DI 9 10 BT_UART_RTS
IO16 RGB_B_LED_L BT_GPIO_2 WL_UART_RX
11 12
BT_GPIO_3 13 14 WL_UART_TX
CON 3x2 BT_GPIO_4 WL_GPIO_1
No Load 15 16
BT_GPIO_5 WL_GPIO_2
CON 8x2
No Load
3.2.7 CapSense Circuit

A CapSense slider and two buttons, all supporting both self-capacitance (CSD) and mutual-
capacitance (CSX) sensing are connected to PSoC 6 MCU as Figure 3-11 shows. Three external
capacitors - CMOD for CSD, CINTA and CINTB for CSX - are present on the CY8CMOD-062S2-
43012. Note that CINTA can be reused as CSH. For details on using CapSense including design
guidelines, see the Getting Started with CapSense Design Guide.
Figure 3-11. Schematics of CapSense Circuit
CAP_SH1
CapSense Buttons CapSense Shield
HATCH 1
CS_CAP_SH SH
CSB1
R56 0 OHM
2 1
Rx Tx CS_BTN_0
R173 0 OHM HATCH

No Load
CS_RX_TX CapSense Slider
CSB2
CSS1
2 1 0 CS_SLD_0
Rx Tx CS_BTN_1
1 CS_SLD_1
2 CS_SLD_2
3 CS_SLD_3
4 CS_SLD_4
5
Slider
CS_RX_TX
Hardware
Simultaneous GPIO switching with unrestricted drive strengths and frequency can affect CapSense
and ADC performance. For more details, see the Errata section of the corresponding device
datasheet.
3.2.8 LEDs
LED2 (Yellow) indicates the status of KitProg3 (See the KitProg3 User Guide for details). LED1
(Yellow) indicates indicate the status of the power supplied to the board.
The board also has two user-controllable LEDs (LED8 and LED9) and an RGB LED (LED5)
connected to PSoC 6 MCU pins for user applications.
Figure 3-12. LEDs
User LEDs
LED5
RGB_R_LED_L R15 750 OHM 1 4 R16 270 OHM RGB_B_LED_L

R B
2 3 R100 330 OHM RGB_G_LED_L
G
RGB LED
P6_VDD
R101 0 OHM LED8 ORANGE R22 1K O_LED_L
VDDIO0
LED9 RED R23 100 OHM R_LED_L
Power LED
VCC_3V3
R91 390 OHM LED1 Y ELLOW
D
NX3020NAKW,115
P6_VDD_BUF
Q3
R64 S
KitProg3 Status LED 100K
P5LP1_4 R10 750 OHM LED2 Y ELLOW
Hardware
3.2.9 Push Buttons

The board has a reset button, two user-controllable buttons and a KitProg3 Mode selection button.
The reset button (SW1) is connected to the XRES pin of the PSoC 6 MCU and is used to reset the
device. Two user buttons (SW2 and SW4) are connected to pin P0[4] and P1[4] of the PSoC 6 MCU
respectively. In addition, the Mode selection button (SW3) is connected to the PSoC 5LP device for
programming mode selection (Refer to the KitProg3 User Guide for details). All buttons are active
LOW configuration and short to GND when pressed. The CY8CMOD-062S2-43012 has a pull-up on
the PSoC 6 MCU XRES line.
Figure 3-13. Schematics of Push Buttons
User Button / Hibernate Wakeup
VDDD VBACKUP
Reset Button
R110 10K R20 10K XRES_L_MCU SW1

EVQ-PE105K
SW4 SW2
USER_BTN_2 EVQ-PNF04M USER_BTN_1 EVQ-PNF04M
Mode Switch
P5LP1_2 1 SW3 4
2 3
SKRPACE011
3.2.10 Cypress Quad SPI NOR Flash

The PSoC 62S2 Pioneer Board has a Cypress NOR flash memory (S25FL512SAGMFI010) of
512Mb capacity. The NOR flash is connected to the Quad SPI interface of the PSoC 6 MCU device.
The NOR flash device can be used for both data and code with execute-in-place (XIP) support and
encryption.
Figure 3-14. Schematics of QSPI Flash
VCC_FLASH
Quad SPI Flash Memory Section
U3 VCC_IO_FLASH
1 16
QSPI_IO3 2 HOLD /IO3 SCK 15 QSPI_SCK
FLASH_RST_L 3 VCC SI /IO0 14 QSPI_IO0
4 RESET /RFU DNU_7 13
5 DNU_1 DNU_6 12 FLASH_INT_L
6 DNU_2 DNU_5 11
7 DNU_3 DNU_4 10
FLASH_SS_L 8 CS VSS 9
QSPI_IO1 SO/IO1 WP /IO2 QSPI_IO2
S25FL512SAGMFI010
VCC_IO_FLASH VCC_IO_FLASH
R93
10K
R92 IO6 R107 0 OHM FLASH_RST_L
10K FLASH_SS_L No Load
No Load IO5 R138 0 OHM FLASH_INT_L
FLASH_INT_L No Load
VCC_VDDIO0 VCC_FLASH VCC_FLASH VCC_IO_FLASH
R90 0 OHM
TP9
C55 C32 C56 C54
VCC_IO_FLASH 1uF 0.1uF 1uF 0.1uF
10V 16V 10V 16V
R26 0 OHM
TP20
Hardware
3.2.11 Cypress Quad SPI F-RAM

The PSoC 62S2 Pioneer Board contains the CY15B104QSN Excelon™ F-RAM device, which can
be accessed through Quad SPI interface. The F-RAM is 4-Mbit (512K × 8) and is capable of Quad
SPI speed up to 108 MHz but PSoC 6 MCU is limited to 80 MHz.
Figure 3-15. Schematics of Quad SPI F-RAM
VCC_VDDIO0 FRAM_VDD
Quad SPI F-RAM
R109 0 OHM TP10
FRAM_VDD
R113 10K U4 FRAM_VDD
1 8
FRAM_SS_L 2 CS VDD 7
QSPI_IO1 3 SO/IO1 RESET/IO3 6 QSPI_IO3
QSPI_SCK C69
QSPI_IO2 4 WP/IO2 SCK 5 0.1uF
VSS SI/IO0 QSPI_IO0
16V
CY 15B104QSN
3.2.12 microSD card section

The PSoC 62S2 Pioneer Board contains a bottom-mounted microSD card holder with card detect
pin that is connected to PSoC 6 MCU. It is powered by VDD_VDDIO0 (connected to VCC_3V3 by
default). The PSoC 6 MCU is capable of UHS-I but is limited to High-Speed mode (50 MHz clock) in
this kit.
By default, the PSoC 6 MCU device is connected using an SDHC interface but optionally can be
connected using SPI by re-working a few zero-ohm resistors.
Figure 3-16. Schematics of microSD Card Section
VDDIO0 microSD Card Section
R43 49.9K J_SD_CMD
R42 49.9K J_SD_DAT0
R41 49.9K J_SD_DAT1 VCC_VDDIO0
R40 49.9K J_SD_DAT2
R39 49.9K J_SD_DAT3
J20 R46
4 4.7K
VDD
R168 0 OHM J_SD_CMD 10A
SD_CMD CD_COM1 10B
SD_DAT0 R169 0 OHM
No Load J_SD_CMD 3 CD_COM2
CMD 9A
J_SD_CLK 5 CD1 9B
7 CLK CD2 SD_CD_L
R166 0 OHM J_SD_CLK J_SD_DAT0
SD_CLK 8 DAT0
R167 0 OHM R163 0 OHM J_SD_DAT1
SD_DAT2 SD_DAT1 1 DAT1
No Load R162 0 OHM J_SD_DAT2 R34
SD_DAT2 2 DAT2 6
J_SD_DAT3 49.9K
SD_DAT3 DAT3 VSS
R164 0 OHM J_SD_DAT0 MICROSD CARD SOCKET
SD_DAT0
SD_DAT1 R165 0 OHM
No Load
Note: Load R165, R167 and R169 and

remove R162, R163, R164, R166 and R168
to change from SDHC to SPI interface to
microSD card
Hardware
3.2.13 PSoC 6 USB Section

The board contains a micro-B USB connector for PSoC 6 MCU. It is capable of both device and host
functionality. Although PSoC 6 MCU does not support USB-OTG, the hardware is compliant with it.
By default, the PSoC 6 MCU device will work as a USB device; when an OTG cable (all such cables
have ID pin connected to GND) is connected, it will work as USB Host.
As a USB Host, the board must provide power to a USB device that is connected to it. This power is
provided by VBUS_HOST which is controlled by PSoC 6 MCU using a load switch. By default,
VBUS_HOST is powered using KP_VBUS and optionally can be powered using external sources
through J10.
Figure 3-17. PSoC 6 USB
USB Host VBUS Enable
VCC_1V8 VBUS_HOST P6_VDD
C63 0.1uF
16V VBUS_HOST P6_VBUS
R103 R60
100K U18 10K
5
U11 5 1
IN OUT
VCC
2 4 4 3
GND
USB_HOST_EN A Y EN FLG USB_INT_L
1 C58 C59 C60
GND
NC 1uF 1uF AP2151WG-7 22uF
2
R102 16V 16V 25V
100K 74LVC1G07GW,125
3
J10 VBUS_HOST
KP_VBUS VBUS_HOST
1
R106 0 OHM 2
Note: P6_VBUS will be powered using KP_VBUS and
hence will be limited in current based on other loads on
the kit. Please remove R106 and connect and external HDR2
power supply that supplies 5V @ 500mA for full USB
host functionality No Load
PSoC 6 MCU USB Host/Device

Micro-B connector
P6_VDD_BUF P6_VBUS
R175 100K
J7 10118194-0001LF
1
VBUS 2 TP24
DM 3 P6_USB_DM
DP 4 P6_USB_DP
USB Device Port VBUS Detect ID 5 P6_USB_ID
S6
S5
S4
S3
S2
S1
VTARG GND
U19 TP23
5 4
SH6
SH5
SH4
SH3
SH2
SH1
P6_VBUS USB_VBUS_DET
VCC OUT U6
2 P6_VBUS
IN 1 4
R105 2 5
1 3 100K R27 100K
H
P6_USB_ID OE GND 3 6
74LVCE1G126W5-7 C23 10nF RCLAMP0854P.TCT C24
R104 C61 50V 0.1uF
100K 0.1uF 16V
16V USB_Hold
1 2 JMP2
3.2.14 Potentiometer Section

The board contains a 10K potentiometer connected to A6 (P10[6]) pin of Arduino-header (J2). The
fixed ends are connected to VDDA (VDD_POT through J25) and GND and hence may contribute to
leakage current on the P6_VDD. Remove jumper J25 to disconnect power from the potentiometer
when measuring P6_VDD current.
Figure 3-18. Schematics of Potentiometer
VDD_POT Potentiometer
J25 HDR2
2
1
VDDA VDD_POT R1
3386P-1-103TLF R51 0 OHM
ARD_A6
R170 0 OHM C70
No Load 0.1uF
16V
Hardware
3.3 PSoC 62S2 Wi-Fi BT Pioneer Kit Rework

3.3.1 CapSense Shield
The hatched pattern around the CapSense buttons and slider are connected to ground. In case
liquid tolerance is required, this pattern needs to be connected to a shield pin. This pattern can be
connected to P7[4] by populating R38 and removing R56. Pin P7[4] needs to be configured as a
shield pin in the firmware. CINTB (C15 on MOD1) connected to P7[2] must be configured as CSH in
firmware when using CapSense Shield.
Connecting the hatched pattern to shield instead of ground will also reduce the parasitic capacitance
of the sensors.
Figure 3-19. Schematics of CapSense Shield
p
CAP_SH1
CapSense Shield
HATCH 1
CS_CAP_SH SH
No Load
PAD_CAP_SH R38 0 OHM R56 0 OHM
CS_CAP_SH
R155 0 OHM
IO15
3.3.2 ETM Trace Header

The 20-pin ETM trace header J12 is not loaded by default and the lines to the header are used as I/
Os on header J2. To connect the PSoC 6 MCU to trace header, populate the resistors R126–R129
and remove resistors R117, R123–R125.
Figure 3-20. ETM Trace Header
TRACE Multiplexed Pins
PAD_A11 R117 0 OHM
A11
R129 0 OHM TRACEDATA_0
No Load
PAD_A10 R123 0 OHM

A10
No Load
PAD_A9 R124 0 OHM

A9
No Load
PAD_A8 R125 0 OHM

A8
No Load
3.3.3 microSD Card Detect Multiplexing

On the PSoC 6 MCU, the default card detect pin for the SHDC block is P12[1]. However, on this kit,
P13[7] is connected to the card detect pin on the microSD card slot. Therefore, the firmware must be
modified to use P13[7] as the card detect pin. In order to instead use the default PSoC 6 MCU card
detect pin, remove R161 and load R159. In this case, P13[7] can optionally be used as a GPIO by
loading R160 which connects it to an I/O header.
Figure 3-21. microSD Card Detect Multiplexing
Card Detect Multiplexing
R159 0 OHM
ARD_D12
No Load
PAD_SD_CD_L R161 0 OHM

SD_CD_L
R160 0 OHM
IO16
No Load
Hardware
3.3.4 microSD Card SPI Multiplexing

The microSD card is connected by a 6-pin SDHC interface by default i.e., CLK, CMD and DAT[0:3].
There is an optional provision to connect it over a 4-pin SPI interface i.e., CLK, MOSI, MISO and
SSEL . To do this, load R165, R167, and R169 and remove R162, R163, R164, R166, and R168.
Figure 3-22. microSD Card SPI Multiplexing
VDDIO0 microSD Card Section
R43 49.9K J_SD_CMD
R42 49.9K J_SD_DAT0
R41 49.9K J_SD_DAT1 VCC_VDDIO0
R40 49.9K J_SD_DAT2
R39 49.9K J_SD_DAT3
J20 R46
4 4.7K
VDD
R168 0 OHM J_SD_CMD 10A
SD_CMD CD_COM1 10B
SD_DAT0 R169 0 OHM
No Load J_SD_CMD 3 CD_COM2
CMD 9A
J_SD_CLK 5 CD1 9B
7 CLK CD2 SD_CD_L
R166 0 OHM J_SD_CLK J_SD_DAT0
SD_CLK 8 DAT0
R167 0 OHM R163 0 OHM J_SD_DAT1
SD_DAT2 SD_DAT1 1 DAT1
No Load R162 0 OHM J_SD_DAT2 R34
SD_DAT2 2 DAT2 6
J_SD_DAT3 49.9K
SD_DAT3 DAT3 VSS
R164 0 OHM J_SD_DAT0 MICROSD CARD SOCKET
SD_DAT0
SD_DAT1 R165 0 OHM
No Load
3.3.5 U.FL (UMCC) Connector for External Antenna

The RF output of CYW43012 is connected to the chip antenna by default. To disconnect the chip
antenna and connect an external antenna, remove C49 and populate C50, J1 on
CY8CMOD-062S2-43012.
Figure 3-23. U.FL (UMCC) Connector for External Antenna
Antenna A1
3 2
NC1 NC2
ANT1_ANT2 C49 8.2pF ANT1 L5 1.8nH 4 1
GND
50V FEED
C50 2450AD14A5500T
8.2pF C44 L6 L7
50V 0.2pF 1.5nH 1.8nH
DNI 200V
G3
J1
G1
ANT2 S
G2
A-1JB
DNI
3.3.6 U.FL (UMCC) Connector for Antenna Diversity

To evaluate antenna diversity, an external antenna can be connected to the output of antenna
diversity RF switch by populating C47 and J2 on CY8CMOD-062S2-43012.
Figure 3-24. U.FL (UMCC) Connector for Antenna Diversity
Antenna Diversity Switch

VOUT_3P3
G3
C46 0.1uF J2
10V U3 G1
6 1 C47 8.2pF ANT0 S
VDD OUT1 DNI 50V G2
RF_SW_IN 5 3 ANT1_ANT2
IN OUT2 A-1JB
RF_SW_CTRL_8 4 2 DNI
VCTL GND
C48 RTC7608
8.2pF SON6H_0.35mm
50V
DNI
Hardware
3.4 Bill of Materials

Refer to the BOM files in the kit webpage.
3.5 Frequently Asked Questions

1. How does CY8CKIT-062S2-43012 handle a voltage connection when multiple power sources are
plugged in?
There are three different options to power the baseboard; KitProg3 Micro-B USB connector (J6),
PSoC 6 Micro-B USB connector (J7), and External DC supply via VIN connector (J5). The
voltage from each of the sources in passed through ORing diodes that supply VCC_IN.
2. What are the input voltage tolerances? Is there any overvoltage protection on this kit?
Input voltage levels are as follows:
Table 3-3. Input voltage levels
Supply Typical I/P Voltage Absolute max
USB Micro-B connector (J6, J7) 4.5 V to 5.5 V 5.5 V
VIN connector (J5) 7 V to 12 V 18 V
There is no overvoltage protection on this kit.

3. Why is the voltage of the kit restricted to 3.3 V? Can’t it drive external 5-V interfaces?
PSoC 6 MCU is not meant to be operated at voltages greater than 3.6 V. Powering PSoC 6 to
more than 4 V will damage the chip. It is recommended to power PSoC 6 MCU at 3.3 V.
4. I am unable to program the target device.
a. Check J15 to ensure that jumper shunt is placed.
b. Make sure that no external devices are connected to the external programming header J11.
c. Update your KitProg3 version to the latest one using the steps mentioned in the KitProg3 User
Guide.
5. What additional overlays can be used with the CapSense?
Any kind of overlays (up to 5-mm thickness) like wood, acrylic, and glass can be used with
CapSense. Note that additional tuning may be required when the overlay is changed.
Hardware
6. Can I power the kit using external program/debug headers J11 and J12?
No, this is not possible by default in this board. The target MCU is powered by on-board
regulators only and hence one of the 3 main sources (J5, J6 and J7) must be present.
There is a protection circuit that prevents reverse voltage from VTARG_REF to VTARG. Hence
the board can't be powered through J11 and J12. However this can be by-passed by loading
R130.
Note: This modification is not recommended as the target MCU will have no protection and will
be permanently damaged if 5V is supplied.
Figure 3-25. VTARG Reverse Voltage Protection
VTARG Reverse Voltage Protection
VTARG VTARG_REF
R130 0 OHM
No Load
Q1 DMP2104LP-7
1
BCM857BV,115 2 5 BCM857BV,115
Q2A Q2B
6
R87 R47 R86

10K 137K 10K
1%
Note: VTARG_REF is only output voltage sense line

for external debuggers. PSoC 6 can't be powered
using external debugging headers J11 and J12
Note: If R130 is loaded and external power is used,
make sure to remove jumper shunt from J14 to
prevent reverse voltage to on-board regulator
Revision History
Document Revision History

Document Title: CY8CKIT-062S2-43012 PSoC 62S2 Wi-Fi BT Pioneer Kit Guide
Document Number: 002-28109
ECN
Revision Issue Date Description of Change
Number
** 6664175 09/19/2019 New kit guide.
*A 6703552 10/17/2019 Updated Introduction chapter on page 7:
Updated “Kit Contents” on page 8:
Updated Figure 1-1.
Updated “Board Details” on page 9:
Updated Table 1-1.
Updated Kit Operation chapter on page 18:
Updated “Theory of Operation” on page 18:
Updated description.
Updated “KitProg3: On-Board Programmer/Debugger” on page 23:
Updated “Programming and Debugging using ModusToolbox” on page 23:
Added “Using the OOB Example – PSoC 6 MCU: Hello World” on page 26.
Updated “USB-I2C Bridge” on page 28:
Updated Figure 2-15.
*B 6713283 10/25/2019 Updated Safety and Regulatory Compliance Information chapter on page 5:
Updated “General Safety Instructions” on page 6:
Updated “Handling Boards” on page 6:
Updated Introduction chapter on page 7:
Updated Table 1-1.
Updated “Using the OOB Example – PSoC 6 MCU: Hello World” on page 26:
Revision History
Document Revision History (continued)

Document Title: CY8CKIT-062S2-43012 PSoC 62S2 Wi-Fi BT Pioneer Kit Guide
Document Number: 002-28109
ECN
Revision Issue Date Description of Change
Number
*C 6754704 12/17/2019 Updated Introduction chapter on page 7:
Updated Figure 1-2.
Updated Figure 2-3.
Updated Figure 2-5.
Updated Hardware chapter on page 29:
Updated “Hardware Functional Description” on page 29:
Updated “Power Supply System” on page 36:
Updated “Voltage regulators” on page 37:
Updated Figure 3-6.
*D 6792835 01/30/2020 Updated Introduction chapter on page 7:
Updated Hardware chapter on page 29:
Updated “CY8CMOD-062S2-43012 (MOD1)” on page 29:
Updated Figure 3-1.
*E 6795725 02/11/2020 Updated Hardware chapter on page 29:
Updated “CY8CMOD-062S2-43012 (MOD1)” on page 29:
Updated hyperlinks.
Updated Figure 3-1.
*F 7062647 02/02/2021 Updated Safety and Regulatory Compliance Information chapter on page 5:
Removed description.
Updated “Regulatory Compliance Information” on page 5:
Removed “Regulatory Statements and Product Labeling”.
Updated to new template.
*G 7111681 03/26/2021 Updated Safety and Regulatory Compliance Information chapter on page 5:
Updated “Regulatory Compliance Information” on page 5:

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Safety and Regulatory Compliance Information 5

3.4 Bill of Materials ..........................................................................................................47

Regulatory Compliance Information

PSoC 62S2 Wi-Fi BT Pioneer Boards contain electrostatic discharge

1.1 Kit Contents

1.2 Getting Started

1.3 Board Details

Figure 1-2 shows the pinout of the Pioneer Board.

Table 1-1. Pioneer Board Pinout

Table 1-1. Pioneer Board Pinout (continued)

Table 1-1. Pioneer Board Pinout (continued)

Table 1-1. Pioneer Board Pinout (continued)

Table 1-1. Pioneer Board Pinout (continued)

Table 1-1. Pioneer Board Pinout (continued)

1.4 Additional Learning Resources

1.5 Technical Support

1.6 Documentation Conventions

Table 1-3. Acronyms Used in this Document (continued)

2.1 Theory of Operation

Serial Memory Interface (QSPI)

Figure 2-2. Block Diagram of Pioneer Board

KitProg3 Mode 10‐pin SWD/ 20‐Pin ETM Reset

1.8~3.3V SWD SWD

Figure 2-4. PSoC 62S2 Wi-Fi BT Pioneer Board - Bottom View

2.2 KitProg3: On-Board Programmer/Debugger

2.2.1 Programming and Debugging using ModusToolbox

d. Click Finish in Summary window, as shown in Figure 2-9.

2.2.1.1 Using the OOB Example – PSoC 6 MCU: Hello World

4. Confirm that the kit LED blinks at 1 Hz.

2.2.2 USB-UART Bridge

2.2.3 USB-I2C Bridge

3.2 Hardware Functional Description

3.2.1 CY8CMOD-062S2-43012 (MOD1)

Supply for PSoC 6 MCU

PSoC 6 MCU Signals

VDDD VDDIO0 VDDIO1 VDDIO2 VBACKUP

C35 C13 C32 C33 C16 C36 C9 C8 C26 C29

VDDA VDDUSB VDD_NS

C27 C28 C30 C34 C6 C5 C18 C17

C19 2.2nF P7_7 10pF

Supply for 1LV Module

1LV Module Signals

24 58 RF_OUT C51 8.2pF RF_SW_IN

VOUT_3P3 VDDIO_SFL VDDOUT_VDDIO VDDIO_1LV VBAT

OnBoard LPO LHL IOs

Antenna Diversity Switch

Carrier Module Footprint

Carrier Module Footprint

3.2.2 PSoC 5LP-based KitProg3 (U2)

PSoC 5LP based KitProg3

VDDIO1 VDDIO3 P5LP_VDD

3.2.3 Serial Interconnection between PSoC 5LP and PSoC 6 MCU

Target MCU SWD KitProg3 Interface

KitProg3 I2C Interface

Primary UART H/W Flow Control Level Translator

R61 0 OHM C25 0.1uF C26 0.1uF