04 선형회로망및테브난정리
04 선형회로망및테브난정리
04 선형회로망및테브난정리
선형회로망 및 테브닌 정리
Additivity property
i1 → v1 =
i1R
i2 → v2 =
i2 R
i1 + i2 → (i1 + i2 ) R = i1 R + i2 R = v1 + v2
Linear Circuit
• Superposition Principle
The voltage across (current through) an element in
a linear circuit is the algebraic sum of the
voltages across (currents through) that element due
to each independent source acting alone.
• Turn off, killed, inactive source:
– independent voltage source: 0 V (short circuit)
– independent current source: 0 A (open circuit)
• Dependent sources are left intact.
Example
i i
+ +
v v
- -
i
v = iR + vs
v v vs
vs i= −
-is R R
Thevenin’s Theorem
𝐼𝐼𝑠𝑠𝑠𝑠 𝑅𝑅𝑇𝑇𝑇𝑇
i
Linear +
two-terminal v Slope=1/Rth
circuit - v
Vth
Isc
Thevenin’s Voltage Calculation
Thevenin’s
Theorem
VTh
IL =
RTh + RL
RL
VL = RL I L = VTh (voltage division)
RTh + RL
회로를 테브닌의 정리로 단순화 한 뒤, 𝑉𝑉𝑇𝑇𝑇𝑇 및 𝑅𝑅𝑇𝑇𝑇𝑇 를 알 경우,
로드저항 𝑅𝑅𝐿𝐿 에 흐르는 전류 및 전압 크기를 쉽게 계산할 수 있음
Summary of Thevenin’s Theorem