Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd Logo
Upload

Welcome to Scribd!

  • 55 views

    Assignment 3

    Uploaded by

    Muhammad Umair
    The document summarizes key concepts from Chapter 4 and 7 of a textbook on computer organization and architecture. Chapter 4 discusses cache memory organization including direct mapping, set-associative mapping, and fields used to represent main memory addresses for different cache mapping techniques. Chapter 7 covers I/O systems including classifications of peripheral devices, techniques for performing I/O like programmed I/O and interrupt-driven I/O, and priorities of DMA transfers versus CPU memory access.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Assignment 3

    Uploaded by

    Muhammad Umair
    55 views9 pages
    The document summarizes key concepts from Chapter 4 and 7 of a textbook on computer organization and architecture. Chapter 4 discusses cache memory organization including direct mapping, set-associative mapping, and fields used to represent main memory addresses for different cache mapping techniques. Chapter 7 covers I/O systems including classifications of peripheral devices, techniques for performing I/O like programmed I/O and interrupt-driven I/O, and priorities of DMA transfers versus CPU memory access.

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document summarizes key concepts from Chapter 4 and 7 of a textbook on computer organization and architecture. Chapter 4 discusses cache memory organization including direct mapping, set-associative mapping, and fields used to represent main memory addresses for different cache mapping techniques. Chapter 7 covers I/O systems including classifications of peripheral devices, techniques for performing I/O like programmed I/O and interrupt-driven I/O, and priorities of DMA transfers versus CPU memory access.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    55 views9 pages

    Assignment 3

    Uploaded by

    Muhammad Umair
    The document summarizes key concepts from Chapter 4 and 7 of a textbook on computer organization and architecture. Chapter 4 discusses cache memory organization including direct mapping, set-associative mapping, and fields used to represent main memory addresses for different cache mapping techniques. Chapter 7 covers I/O systems including classifications of peripheral devices, techniques for performing I/O like programmed I/O and interrupt-driven I/O, and priorities of DMA transfers versus CPU memory access.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 9

    Assignment3

    Chapter 4:
    4.1 What are the differences among sequential access, direct access,
    and random access?
    Sequential access is accessing data in a specific linear sequence (example: tapes).

    Direct access has the data address based on a physical location.

    With random access, any location can be selected at random, and the addressable
    locations in memory have a unique, physically wired-in addressing mechanism.

    4.2 What is the general relationship among access time, memory cost,
    and capacity?
    As access time becomes faster, the cost per bit increases. As memory size increases,
    the cost per bit is smaller. Also, with greater capacity, the access time becomes
    slower.

    4.3 What are the differences among direct mapping, associative


    mapping, and set-associative mapping?
    Direct mapping maps each block of main memory into only one possible cache line.
    Associative mapping permits each main memory block to be loaded into any line of
    the cache.
    The set-associative mapping combines both methods while decreasing disadvantages.
    The cache consists of a number of sets, each of which consists of a number of line.

    4.4 For a direct-mapped cache, a main memory address is viewed as


    consisting of three fields. List and define the three fields.
    i is the cache line number
    j is the main memory block number
    m is the number of lines in the cache

    4.5 For an associative cache, a main memory address is viewed as


    consisting of two fields. List and define the two fields.
    Tag and Word fields.
    The Tag field uniquely identifies a block of main memory.
    The Word is what is to be placed in the block of memory.
    4.6 For a set-associative cache, a main memory address is viewed as
    consisting of three fields. List and define the three fields.
    The fields are Tag, Set and Word.
    The Tag identifies a block of main memory.
    The Set specifies one of the 2^s blocks of main memory.
    The word is what is to be placed in the main memory.

    4.7 A set-associative cache consists of 64 lines, or slots, divided into


    four-line sets. Main memory contains 4K blocks of 128 words each.
    Show the format of main memory addresses.
    Number of sets = 64/4 = 16
    => The cache is divided into 16( = 2⁴) sets
    Therefore, 4 bits are needed to identify the set number.
    Main memory consists of 4K = 2¹² blocks.
    Therefore, the set + tag lengths must be 12 bits
    tag length = 12 - 4 = 8
    Each block contains 128 words = 2⁷ words
    Therefore, 7 bits are needed to specify the word field
    So the main memory can be represented as
    TAG SET WORD
    8 4 7
    4.8 A two-way set-associative cache has lines of 16 bytes and a total size
    of 8 kB. The 64-MB main memory is byte addressable. Show the format
    of main memory addresses.
    There are a total of 8 kbytes/16 bytes = 512 lines in the cache. Thus the cache consists
    of 256 sets of 2 lines each. Therefore 8 bits are needed to identify the set number.
    For the 64-Mbyte main memory, a 26-bit address is needed. Main memory consists of
    64-Mbyte/16 bytes = 222 blocks. Therefore, the set plus tag lengths must be 22 bits,
    so the tag length is 14 bits and the word field length is 4 bits.
    4.9 For the hexadecimal main memory addresses 111111, 666666,
    BBBBBB, show the following information ,in hexadecimal format:

    a) Tag = 8 bits Line = 14 word =2

    1. BBBBBB = 1011 1011 1011 1011 1011 1011


    1. Tag = 1011 1011 = BB
    2. Line = 1011 1011 10 = 10 1110 1110 = 2EE
    3. Word = 11 = 3
    2. 666666 =0110 0110 0110 0110 0110 0110
    1. Tag = 0110 0110 = 66
    2. Line = 0110 0110 01 = 01 1001 1001 = 199
    3. Word = 10 = 2
    3. 111111 = 0001 0001 0001 0001 0001 0001
    1. Tag = 0001 0001 = 11
    2. Line = 0001 0001 00 = 00 0100 0100 = 44
    3. Word = 01 = 1

    b) Tag = 22 bits , word =2 bits

    1. BBBBBB = 1011 1011 1011 1011 1011 1011


    1. Tag = 1011 1011 1011 1011 1011 10 = 10 1110 1110 1110 1110 1110=
    2EEEE
    2. Word = 11 = 3
    2. 666666 =0110 0110 0110 0110 0110 0110
    1. Tag = 0110 0110 0110 0110 0110 01 = 01 1001 1001 1001 1001 1001
    = 299999
    2. Word = 10 = 2
    3. 111111 = 0001 0001 0001 0001 0001 0001
    1. Tag = 0001 0001 0001 0001 0001 00= 00 0100 0100 0100 0100 0100 =
    44444
    2. Word = 01 = 1

    c) Tag = 9 Set = 13 word =2

    1. BBBBBB = 1011 1011 1011 1011 1011 1011


    1. Tag = 1011 1011 1 = 1 0111 0111 = 177
    2. Set = 0111 0111 0111 0 = 0 1110 1110 1110 = EEE
    3. Word = 11 = 3
    2. 666666 =0110 0110 0110 0110 0110 0110
    1. Tag = 0110 0110 0= 0 1100 1100 = CC
    2. Set = 110 0110 0110 01 = 1 1001 1001 1001= 1999
    3. Word = 10 = 2
    3. 111111 = 0001 0001 0001 0001 0001 0001
    1. Tag = 0001 0001 0= 0 0010 0010 = 22
    2. Set = 0010 0010 0010 0= 0 0100 0100 0100= 444
    3. Word = 01 = 1
    4.10 List the following values:
    4.11 Consider a machine with a byte addressable main memory of 216
    bytes and block size of 8 bytes. Assume that a direct mapped cache
    consisting of 32 lines is used with this machine.

    a)
    Address length: 16 bits
    Word: 3 rightmost bits (as the block size if 8 bytes)
    Line: 5 middle bits (as there are 32 lines)
    Tag: 8 leftmost bits (as 16 – 3 – 5=8)

    b)
    0001 0001 0001 1011 ? line 3
    1100 0011 0011 0100 ? line 6
    1101 0000 0001 1101 ? line 3
    1010 1010 1010 1010 ? line 21

    c)
    bytes with addresses 0001 1010 0001 1000
    0001 1010 0001 1001
    0001 1010 0001 1010
    …
    0001 1010 0001 1111
    are stored in the cache.

    d)
    32 lines ? 8 bytes = 256 bytes

    e) It is because 2 items with two different memory addresses can be stored in


    the same place in the cache. The tag is used to distinguish between them.
    Chapter 7:
    7.1 List three broad classifications of external, or peripheral, devices.
    Human readable (suitable for communicating with computer user), machine
    readable(...equipment), communication(...remote devices).

    7.2 What are the major functions of an I/O module?


    control and timing, processor communication, device communication, data
    buffering, error detection

    7.3 List and briefly define three techniques for performing I/O.
    Programmed I/O: The processor issues an I/O command, on behalf of a process to
    an I/O module; that process then busy-waits for the operation to be completed
    before proceeding.
    Interrupt-driven I/O: The processor issues an I/O command on behalf of a process,
    continues to execute subsequent instructions, and is interrupted by the I/O module
    when latter has completed its work.
    Direct memory access: controls exchange of data between main memory and I/O
    module.

    7.4 What is the difference between memory mapped I/O and isolated
    I/O?
    with memory-mapped I/O, there is a single address space for memory locations and
    I.O devices.
    with isolated I/O, a command specifies whether the address refers to a memory
    location or an I/O device.

    7.5 When a device interrupt occurs, how does the processor determine
    which device issued the interrupt?
    multiple interrupt lines, software poll, daisy chain, bus arbitration.

    7.6 When a DMA module takes control of a bus, and while it retains
    control of the bus, what does the processor do?
    the processor pauses for each cycle stolen by the DMA module.
    7.7 For programmed I/O, Figure 7.5 indicates that the processor is stuck
    in a wait loop doing status checking of an I/O device. To increase
    efficiency, the I/O software could be written so that the processor
    periodically checks the status of the device. If the device is not ready,
    the processor can jump to other tasks. After some timed interval, the
    processor comes back to check status again.

    a)

    The printer outputs 20 characters per second. So it outputs 1000/20=50 msec to


    output one character. So if the status is checked every 50 msec then the printer will
    always have one character to be dealt with.

    b)

    On average character enter at a rate of 10 characters per second. So it takes 100


    msec to enter a character. Although interval between two consecutive key depression
    can be as short as 50 msec. Since it is single character buffer, to avoid data loss the
    keyboard buffer should be checked every 50 msec. Data loss would have occurred if
    one character is entered when the buffer is full. In worst case, characters were
    inserted after 50 msec. If the keyboard buffer is checked at a interval more than 50
    msec then data loss would happen. So time should be 50 msec.

    7.8 In virtually all systems that include DMA modules, DMA to main
    memory is given higher priority than CPU access to main memory. Why?
    The processor can wait a bit and not lose data. However, if the system does not
    handle data coming from an I/O device, such as the network, the data may be lost.
    Additionally, the DMA may be handling data that the CPU needs for a particular
    process to continue execution.

    7.9 A DMA module is transferring characters to memory using cycle


    stealing, from a device transmitting at 9600 bps. The processor is
    fetching instructions at the rate of 1 million instructions per second
    (1 MIPS). By how much will the processor be slowed down due to the
    DMA activity
    DMA module transferring characters at 9600 bps = 9600/8 Bps = 1200 Bps
    Processor is fetching instructions at the rate = 1 MIPS (million instruction per second)
    Slowdown = 1200/106 = 12*1000/104 ms
    = 1.2 ms

    You might also like