ECE667

Homework Assignment # 4 Due Monday April 26th by 12.00 noon in TAs mailbox in DL205

Spring 2010

In this assignment, you will design the necessary hardware components to implement a simple remote control module (Though for our purposes, the unit will be connected to the receiving unit through a pair of wires). In addition to the keypad scanner you have already designed, you will also add a design for an Asynchronous Serial Transmitter capable of transmitting data at one of four selectable bitrates. Transmission rate selection will be done through a Baud-Rate Generator, which is basically just a selectable version of the frequency divider designed in the previous homework. Finally, you will need to design a System Controller for the remote control module to coordinate the signals from the system components so that the keys pressed on the keypad are transmitted serially through the transmitter.

Baud Rate Generator:

Rate Select 0 (00) 1 (01) 2 (10) 3 (11)

Bit Rate 1200 bits/s 2400 bits/s 4800 bits/s 9600 bits/s

Clock Freq. 1200 Hz 2400 Hz 4800 Hz 9600 Hz

Basically, this circuit does the same exact thing as the 1 kHz clock generator from the previous homework assignment, with the added capability of a selectable frequency. The block diagram for this circuit should look as shown below:

From External Oscillator External Baud Rate Selection

4MHZ S1 S0

BAUD_CLK

To Async. Transmitter

Follow the same guidelines used in the design of the previous clock divider, and clearly show/explain the operation of the circuit.

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Homework Assignment # 4

Spring 2010

Asynchronous Serial Transmitter: The main function of the transmitter is to take parallel data from your circuit, and transmit this data bit by bit to a serial receiver. The baud-rate generation circuit you designed above will determine the rate at which this data will be sent. The transmitter should be designed to transmit in the standard RS-232 protocol. The format for data in this protocol is shown below.
LSB Start Bit 8 Data Bits MSB P Stop Bit

While the standard sets aside the eighth data bit as a parity bit (used in transmission/reception error detection), we will simplify our design by excluding parity calculation, and simply send eight bits of data. The block diagram for your transmitter design should look as shown below:

8 Parallel Data In Transmission Enable Baud Rate Clock P[7..0] TX CLK TX_RDY TX_DATA To System Controller Serial Data Transmission

Basically, eight bits of parallel data will be placed on lines P(7:0), and then the device will be enabled by setting TX high. Once enabled, output TX_DATA will serially transmit the data placed on the parallel inputs P(7:0) by first sending out bit P0 (the least significant bit) for one complete baud clock cycle. Each consecutive cycle after will place the next sequential bit on the data line until the most significant bit, P7, has been transmitted. However, in order to make our signal conform to the RS-232 protocol, the eight bits of data must be preceded by a start bit and followed by a stop bit. In order to understand the function of the start and stop bits, we must examine how we would like the TX_DATA output to behave when the device is not active. The following waveforms illustrate the desired circuit outputs based on the input signals:

ECE667

Homework Assignment # 4

Spring 2010

BAUD CLK

P(7:0)

Don't Care

TXMIT

TX_DATA

TX_RDY

The waveforms above show how the device should operate when it is not enabled (when TXMIT = 0). Since the device is not operating, we really don't care what is placed on the parallel inputs, as it shouldn't really make any difference. The output TX_DATA is to be maintained in a high state, also known as the stop condition. The receiver on the other end will recognize this condition, and understand that no data is being sent. The output TX_RDY is used to tell let any external devices know the state of the transmitter. In the waveform above, TX_RDY is maintained high, signaling that the transmitter is ready to accept a byte from the parallel inputs. To transmit our parallel data, we could just begin sending our bits after enabling the transmitter, but what if the first bit to be sent (P0) is a 1. How will the receiver know that the transfer has begun? Or what if the parallel data is all 1s (FF in hexadecimal). In this case the receiver wouldn't even know that a transfer was even attempted. To solve this problem, we will start all transmissions with a low signal for one clock cycle. This is known as the start bit. The receiver on the other end (in the RS-232 protocol) will interpret this to mean that the next 8 bits after the start bit will contain serial data in order from least to most significant bits. Following this data, the serial line will again enter the stop condition, signaling the end of the transmission. The waveforms on the next page illustrate the operation of the transmitter with the start and stop bits included.

ECE667

Homework Assignment # 4

Spring 2010

BAUD CLK

P(7:0)

9Dh

3Fh

TXMIT

TX_DATA

Start

Stop

TX_RDY

We begin by setting the parallel data on the P(7:0) inputs. For this example, we would like to send 9Dh (or 1001 1101 in binary). The transmitter is triggered on a positive edge of the baud clock while TXMIT is high. Once triggered, the start bit is placed on TX_DATA, and TX_RDY goes low signaling that the device is currently busy. Note that once the transmission has begun, it shouldn't matter if the parallel inputs change during the transfer. The transmitter should still transmit the byte it started (9Dh). The parallel data is then serialized and sent in the next eight baud-clock cycles in order from least to most significant bits. Once all of the data bits have been sent, TX_RDY goes high again (signaling that the device is ready to transmit the next byte), and TX_DATA returns to the stop condition. System Controller: Now that we have both a keypad scanner and a transmitter, we would like to combine these components so that when we press a key, the code for that key is sent serially through the transmitter. Design a system controller that will accomplish this. The block diagram for your controller should look as shown below.

Transmitter Status Keypad Scanner Status 4 MHz Clock Signal

TX_RDY KP_VALID 4M_CLK

TX_TXMIT

To Transmitter Enable

When the system begins operation, transmission will initially be disabled (TX_TXMIT = 0). When the controller detects that a valid key is currently pressed (KP_VALID = 1), the controller

ECE667

Homework Assignment # 4

Spring 2010

should then allow only one copy of the current key code to be transmitted by enabling the transmitter (TX_TXMIT = 1). (Hint: This can be done by monitoring the KP_VALID signal). Assume that the key outputs from the keypad scanner are connected directly to the low four bits of the transmitter. The high four bits , P(7:4), should be set to "0011" (or 3 in hexadecimal). This will set our transmitter to send the ASCII column of numbers to the receiver, and aid in verifying the operation of the unit once the design is programmed into the CPLD.

To Hand In:
Simulation of the Baud Rate Generator can take a good amount of time on a slow PC. However, it is necessary to show that the design is producing the proper clock signals. Turn in your graphical design for the Baud Rate generator along with the following results You will need to turn in a total of four simulation waveforms for this device, one for each of the frequencies generated (show the select signals on the baud rate generator waveforms). Select the end time of these simulations accordingly so that one full period of the clock waveform is shown for each case. You will not be able to divide the clock into the exact desired frequencies. Provide a detailed analysis of the error associated with each frequency (i.e find the % error from the ideal frequency) Clearly explain the operation of your circuits, and provide equations where they are relevant. Provide a schematic (either sketch or in Quartus II) for all circuits.(Asynchronous serial transmitter, System Controller) You may use any of the macrofunctions included in the Quartus II software package in your designs, but clearly explain how you are implementing these parts. If you decide not to use these parts, clearly show how you designed each of the components. You must include a state diagram for your system controller, as well as the supporting tables, equations, etc.