VLSI Record 2022-23

R.Y.M.E.
C, Ballari VLSI Lab, VII Sem/2022-23
APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC) DESIGN FLOW
The sequence of steps to design an ASIC is known as the design flow. The various steps involved
in ASIC design flow are given below.
1. Design entry: Design entry is a stage where the micro architecture is implemented in a
Hardware Description language like VHDL, Verilog, and System Verilog etc. In early days, a
schematic editor was used for design entry where designers instantiated gates. Increased
complexity in the current designs requires the use of HDLs to gain productivity. Another
advantage is that HDLs are independent of process technology and hence can be re-used over
time.
2. Logic synthesis: Use an HDL (VHDL or Verilog) and a logic synthesis tool to produce a net
list a description of the logic cells and their connections.
3. System partitioning: Divide a large system into ASIC-sized pieces.
4. Pre-layout simulation: Check to see if the design functions correctly.
5. Floor planning: Arrange the blocks of the net list on the chip.
6. Placement: Decide the locations of cells in a block.
7. Routing: Make the connections between cells and blocks.
8. Extraction: Determine the resistance and capacitance of the interconnect.
9. Post layout simulation. It is used to check to see whether the design still works with the added
loads of the interconnect or not
Fig shows ASIC design flow
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R.Y.M.E.C, Ballari VLSI Lab, VII Sem/2022-23
DIGITAL DESIGN
Dept. of ECE Page 2

Procedure for Digital Design Experiments:

1. Double click on ISE Design Suite 14.7
2. FileClose Project.
3. File New Project, Give Project Name & Project Location press next
4. Select the following project settings, select parameters & press next & finish
5. right click on xc9572-15pc84 New source select verilog module give file name next initialize
inputs & outputs press on nextfinish.
Dept. of ECE Page 3

6. Type the verilog Program & save it, select file expand implement design, double click on synthesize –
XST
7. Process "Synthesize - XST" completed successfully message should be displayed on console which
indicates no errors if errors click on errors tab & correct the error & rerun synthesize – XST.
8. right click on file_name.v & select new source & select verilog test fixture & give file_name_test.
9. in view select simulation select alu_test.v and expand ISim Simulator. Double click on Behavioral Check
Syntax.
Process "Behavioral Check Syntax" completed successfully should be displayed.
10. Double click on Simulate Behavioral Model.
11. Observe the output in ISim Simulator by selecting Default.wcfg.
12. click on Zoom to Full View to view all the output combinations in a single screen.
Dept. of ECE Page 4

Waveform of 4 bit adder
Dept. of ECE Page 5

1. Write a Verilog code for 4 bit adder with test bench for Verification.
a)Verilog Code:
module four_bit_adder(A,B,C0,S,C4);
input [3:0] A,B;
input C0;
output [3:0] S;
output C4;
wire C1,C2,C3;
full_adder fa0 (A[0],B[0],C0,S[0],C1);
endmodule
module full_adder( A,B,CIN,S,COUT);

input A,B,CIN;
output S,COUT;
assign S = A^B^CIN;
assign COUT = (A&B) |(B&CIN)| (CIN&A);

endmodule
b)Testbench Code:
// Initialize Inputs
initial
fork
A=4'b0011;A=#100 4'b1011;A=#200 4'b1111;
B=4'b0011;B=#100 4'b0111;B=#200 4'b1111;
C0 = 1'b0;C0 =#100 1'b1; C0 =#200 1'b1;
#300 $finish;
join
endmodule
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RESULT:
Waveform of D Flip-Flop
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2. a)Write a Verilog code for D Flip-Flop with test bench for Verification.
a)Verilog Code:
module df(d,clk,q,qb);
input d,clk;
output q,qb;
reg q,qb;
always @(posedge(clk))
begin
q=d;
qb=~q;
end
endmodule
b)Testbench Code:
initial
fork
clk=1'b1;
forever clk=#50 ~clk;

d=1'b0;d=#100 1'b1;d=#200 1'b0;d=#300 1'b1;
#400 $finish;
join
endmodule
RESULT:
Dept. of ECE Page 8

Waveform of SR Flip-Flop
Dept. of ECE Page 9

2. b)Write a Verilog code for SR Flip-Flop with test bench for Verification.
a)Verilog Code:
module sr_ff(sr,clk,q,qb);
input [1:0]sr;
input clk;
output q,qb;
reg q,qb;
begin
case(sr)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bz;
endcase
qb=~q;
end
endmodule
b)Testbench Code:
initial
fork
clk=1'b1;
sr=2'b01;sr=#100 2'b10;sr=#200 2'b00;sr=#300 2'b11;
#400 $finish;
join
endmodule
RESULT:
Dept. of ECE Page 10

Waveform of JK Flip-Flop

2. c)Write a Verilog code for JK Flip-Flop with test bench for Verification.
a)Verilog Code:
module jk(jk,clk,q,qb);
input [1:0]jk;
input clk;
output q,qb;
reg q,qb;
begin
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule
b)Testbench Code:
initial
fork
clk=1'b1;
jk=2'b01;jk=#100 2'b10;jk=#200 2'b11;jk=#300 2'b00;jk=#400 2'b01;
#500 $finish;
join
endmodule
RESULT:

Waveform of T Flip-Flop

2. d)Write a Verilog code for T Flip-Flop with test bench for Verification.
a)Verilog Code:
module tf(t,clk,q,qb);
input t,clk;
output q,qb;
reg q=1'b0,qb;
begin
if(t==1'b0)
q=q;
else
q=~q;
qb=~q;
end
endmodule
b)Testbench Code:
initial
fork
clk=1'b1;
t=1'b0;t=#100 1'b1;t=#200 1'b0;t=#300 1'b1;
#400 $finish;
join
endmodule
RESULT:

Waveform of D Latch

3. a) Write a Verilog code for D Latch with test bench for Verification.
a)Verilog Code:
module dlatch(d,en,q,qb);
input d,en;
output q,qb;
reg q,qb;
always @(en,d)
if(en==1'b1)
begin
q=d;
qb=~q;
end
endmodule
b)Testbench Code:
initial
fork
en=1'b1;d=1'b1;
d=#100 1'b0;
en=#200 1'b0;
d=#300 1'b1;
en=#400 1'b1;
#500 $finish;
join
endmodule
RESULT:

Waveform of SR Latch

3 b) Write a Verilog code for SR Latch with test bench for Verification.
a)Verilog Code:
module sr_latch(sr,en,q,qb);
input [1:0]sr;
input en;
output q,qb;
reg q,qb;
always @(en or sr)
if (en==1)
begin
case(sr)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bz;
endcase
qb=~q;
end
endmodule
b)Testbench Code:
initial
fork
en=1'b1;sr=2'b10;
sr=#100 2'b00;
en=#200 1'b0;
sr=#300 2'b01;
en=#400 1'b1;
sr=#500 2'b11;
#600 $finish;
join
endmodule
RESULT:

Waveform of JK Latch

3 c) Write a Verilog code for JK Latch with test bench for Verification.
a)Verilog Code:
module jk_latch(jk,en,q,qb);
input [1:0]jk;
input en;
output q,qb;
reg q,qb;
always @(en,jk)
begin
if(en==1'b1)
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule
b)Testbench Code:
initial
fork
en=1'b1;jk=2'b10;
jk=#100 2'b00;
en=#200 1'b0;
jk=#300 2'b01;
en=#400 1'b1;
jk=#500 2'b11;
#600 $finish;
join
endmodule
RESULT:

Waveform of T Latch

3 d) Write a Verilog code for T Latch with test bench for Verification.
a)Verilog Code:
module tlatch(t,en,q,qb);
input t,en;
output q,qb;
reg q=1'b0,qb;
always @(en,t)
begin
if(en==1'b1)
if(t==1'b0)
q=q;
else
q=~q;
qb=~q;
end
endmodule
b)Testbench Code:
initial
fork
en=1'b1;t=1'b1;
t=#100 1'b0;
en=#200 1'b0;
t=#300 1'b1;
en=#400 1'b1;
#500 $finish;
join
endmodule
RESULT:

Waveform of Asynchronous up counter

4. a) Write a Verilog code for Asynchronous up counter with test bench for Verification.
a)Verilog code
module async_up(clk,rst,q);
input clk,rst;
output [3:0] q;
reg q0,q1,q2,q3;
always@(posedge(clk)or posedge(rst))
begin
if(rst)
begin
q0=1'b0;
end
else
q0=~q0;
end
always@(negedge(q0)or posedge(rst))
begin
if(rst)
begin
q1=1'b0;
end
else
q1=~q1;
end
begin
if(rst)
begin
q2=1'b0;
end
else
q2=~q2;
end
begin
if(rst)
begin
q3=1'b0;
end
else
q3=~q3;
end
assign q={q3,q2,q1,q0};
endmodule


b)Testbench Code:
initial
fork
clk=1'b1;
rst=1'b1; rst=#100 1'b0; rst=#3600 1'bz;
#3700 $finish;
join
endmodule
RESULT:

Waveform of Asynchronous down counter

4 b) Write a Verilog code for Asynchronous down counter with test bench for Verification.
a)Verilog code
module async_down(clk,rst,q);
input clk,rst;
output [3:0] q;
reg q0,q1,q2,q3;
always@(posedge(clk)or posedge(rst))
begin
if(rst)
begin
q0=1'b0;
end
else
q0=~q0;
end
always@(posedge(q0)or posedge(rst))
begin
if(rst)
begin
q1=1'b0;
end
else
q1=~q1;
end
begin
if(rst)
begin
q2=1'b0;
end
else
q2=~q2;
end
begin
if(rst)
begin
q3=1'b0;
end
else
q3=~q3;
end
assign q={q3,q2,q1,q0};
endmodule


b)Testbench Code:
initial
fork
clk=1'b1;
rst=1'b1; rst=#100 1'b0; rst=#3600 1'bz;
#3700 $finish;
join
endmodule
RESULT:

Waveform of 32 bit ALU

5. a) Write a Verilog code for 32 bit ALU with test bench for Verification.
a)Verilog code
module alu_32bit_case(y,a,b,op);
input [31:0]a;
input [31:0]b;
input [2:0]op;
output reg [31:0]y;
always@(*)
begin
case(op)
3'b000:y=a&b;
3'b001:y=a|b;
3'b010:y=~(a&b);
3'b011:y=~(a|b);
3'b010:y=a+b;
3'b011:y=a-b;
3'b100:y=a*b;
default:y=32'bx;
endcase
end
endmodule
b)Testbench Code:
initial
fork
a=32'h00000011; b=32'hFFFFFFAF; op=3'b000;
op=#100 3'b001;
op=#200 3'b010;
op=#300 3'b100;
op=#400 3'b011;
#500 $finish;
join
endmodule
RESULT:


ANALOG DESIGN



Waveforms of CMOS inverter

1. Schematic of CMOS inverter


Layout of CMOS inverter
RESULT:

Waveforms of 2 input CMOS nand Gate

Schematic of 2 input CMOS nand Gate


Layout of 2 input CMOS nand Gate
RESULT:

Waveforms of Common source amplifier

Schematic of Common source amplifier


Layout of Common source amplifier
RESULT:

Waveforms of Operational Amplifier

Schematic of Operational Amplifier


Layout of Operational Amplifier
RESULT:

CONTENT BEYOND SYLLABUS
Waveforms of CMOS 3 input nand & and gate
CONTENT BEYOND SYLLABUS

Schematic of CMOS 3 input nand & and gate

Layout of CMOS 3 input nand & and gate

RESULT:
Waveforms of expression f= a+bc

Schematic of expression f= a+bc



Layout of expression f= a+bc
RESULT:
VIVA Questions

Part A:
1. Define HDL
HDL stand for Hardware description language, it is a computer aided design tool (CAD) for the
modern design and synthesis of digital system.
2. What is Verilog? Give IEEE std for Verilog.
Verilog is a general purpose hardware descriptor language. It is similar in syntax to the C
programming language. It can be used to model a digital system at many levels of abstraction
ranging from the algorithmic level to the switch level.
IEEE STD for Verilog 1364-1995
3. Give the different types of descriptions or styles in verilog with keywords.
1. Behavioral: Program is written with respect to functionality behavior of the output with
respect to input.
Keywords: always/initial
2. Dataflow: Output is written with respect to logical diagram or logical expression.
Keywords: wire, assign: these are used for intermediate outputs.
3. Structural: Structural modeling describes a digital logic networks in terms of the
components that make up the system.
Keywords: gates (and, or, xor, nor etc....)
4. Switch level: Digital circuits at the MOS-transistor level are described using the
MOSFET switches.
Keywords: nmos, cmos, pmos, tranifo, tran etc....
5. Mixed type: Combination of behavioral, dataflow, structural or switch level.
6. Mixed language: Combination of VHDL and Verilog.
4. Differentiate between combination circuit and sequential circuit.
Slno Combinational circuit Sequential circuit
1 Output depends only on the Output depends both on present state

inputs. inputs and previous state output
2 Memory less element It has memory
3 Example : MUX, De-mux, Example: Flip-flop, latches, counters

Encoder, decoder
Inputs Outputs
Combinational logic
Previous
Outputs
Memory
element
Fig: shows Block diagram of sequential circuit.

5. Differentiate between synchronous and asynchronous counter.

Slno Synchronous counter Asynchronous counter
1 Clock is common for all input stages Different clock input
2 It is also called as parallel sequential circuit It is also called as serial

sequential circuit.
3 Ex: ring counter, Johnson counter Ex: Binary ripple counter
6. Differentiate between flip flop and latch

Slno Flip flop Latch
1 Control signal is clock Control signal is enable
2 Flip flops are edge triggered( rising or Latches are level triggered
falling)
3 A flip-flop, on the other hand, is edge- In latch the outputs can change as
triggered and only changes state when soon as the inputs do (or at least
a control signal goes from high to low after a small propagation delay).
or low to high.
3
7. Which language supports multi-dimensional array

VHDL supports multi dimensional array.
Verilog supports 1-Dimensional array.
8. How to obtain T-ff from JK-ff.
Short the inputs of J and K and connect it to T.
T J Q
clk
K Q
Fig: Shows logic diagram of JK-ff

9. Expand D and T flip flop

D--- Delay or data, T --- Toggle
10. Give the expressions for all the flip flops
SR flip flop − − − Q+ = S + RQ
JK flip flop − − − Q+ = JQ + KQ
D flip flop − − −Q+ = Q
T flip flop − − − Q+ = Q
11. How to obtain D-ff from SR-ff?
Connect D to S & R to D
D
Q
clk
Fig: Shows the logic diagram of D-ff using SR-ff

12. Define Flip flop
Flip flop is a sequential circuit which can store 1-bit of data.
13. Differentiate between melay model and moore model
Slno Melay Moore
1 Output depends both upon present state Output depends only upon the present
and present input. state.
2 Q+ depends on Q and input combination Q+ depends only on Q.
14. Expand FPGA and CPLD

FPGA- Field programmable gate arrays
CPLD- complex Programmable logic devices
15. What are the specifications of FPGA
Device name XC9572
Family name XC9500CPLDs
Speed grade -15
16. Write the syntax of if, else if ,for, while and case statements in VHDL and Verilog
Verilog
If if(Boolean expression)
begin
---------; ---------;
end
else
begin

---------; ---------;
end
else-if if(Boolean expression1)

begin
---------; ---------;
end
else if(Boolean expression2)
begin
---------; ---------;
end
else
begin
---------; ---------; end
case case(control expression )

expr1 :Sequential statement 1;
expr2 :Sequential statement 2;
:
default: Sequential statement n;
endcase
for for (lower index; upper index; step)

begin
---------;---------;
end
While while (condition)

begin
---------;---------;
end
17. What are the value sets in Verilog?

Verilog supports four levels for the values needed to describe hardware referred to as value
sets.
Value levels Condition in hardware circuit
0 Logic zero, false condition

1 Logic one, true condition
X Unknown logic value ,Undefined state
Z High impedance, floating state
18. Name the types of ports in Verilog

Types of port Keyword
Input port Input
Output port Output
Bidirectional port inout
19. Give the different symbols for transmission gate.
20. Give the different types of ASIC.

 Full custom ASICs
 Semi-custom ASICs
 Programmable ASICs
 Programmable Logic Device (PLD)
 Field Programmable Gate Array (FPGA).
21. What is a FPGA?
 A field programmable gate array (FPGA) is a programmable logic device that supports
implementation of relatively large logic circuits.
 FPGAs can be used to implement a logic circuit with more than 20,000 gates whereas
a CPLD can implement circuits of up to about 20,000 equivalent gates.
Part B:
1. What is VLSI?
VLSI is ‘Very Large Scale Integration’. It is the process of designing, verifying, fabricating and
testing of a VLSI IC or CHIP.
2. Give the basic process for IC fabrication
 Silicon wafer Preparation
 Epitaxial Growth
 Oxidation
 Photolithography

 Diffusion
 Ion Implantation
 Isolation technique
 Metallization
 Assembly processing & Packaging
3. Different types of oxidation?
 Dry & Wet Oxidation
4. What is MOSFET?
The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistor is a semiconductor
device which is widely used for switching and amplifying electronic signals in the electronic
devices. The MOSFET is a core of integrated circuit and it can be designed and fabricated in a
single chip because of these very small sizes. The MOSFET is a four terminal device with
source(S), gate (G), drain (D) and body (B) terminals. The body of the MOSFET is frequently
connected to the source terminal so making it a three terminal device like field effect transistor.
5. What is Enhancement mode transistor?
 The device that is normally cut-off with zero gate bias.
6. What is Depletion mode Device?
 The Device that conduct with zero gate bias.
7. When the channel is said to be pinched –off?
 If a large Vds is applied this voltage with deplete the Inversion layer .This Voltage
effectively pinches off the channel near the drain.
8. Give the different types of CMOS process?
 p-well process
 n-well process
 Silicon-On-Insulator Process
 Twin- tub Process
9. What are the advantages of CMOS process?
 Low power Dissipation
 High Packing density
 Bi directional capability
10. Compare between CMOS and bipolar technologies.
CMOS Technology Bipolar technology
• Low static power dissipation • High power dissipation
• High input impedance (low drive • Low input impedance (high drive
current) current)
• Scalable threshold voltage • Low voltage swing logic
• High noise margin • Low packing density
• High packing density • Low delay sensitivity to load

• High delay sensitivity to load (fan-out • High output drive current
limitations) • High gm (gm α eVin)
• Low output drive current • High ft at low current
• Low gm (gm a Vin) • Essentially unidirectional
• Bidirectional capability
• A near ideal switching device
11. Why NMOS technology is preferred more than PMOS technology?

 n- Channel transistors have greater switching speed when compared to PMOS
transistors.
12. What are the different operating regions for MOS transistor?
 Cutoff region
 Non- Saturated Region(linear/active/triode)
 Saturated Region
13. What are the different MOS layers?
 n-diffusion
 p-diffusion
 Polysilicon
 Metal
14. What is Channel-length modulation?
The current between drain and source terminals is constant and independent of the applied
voltage over the terminals. This is not entirely correct. The effective length of the conductive
channel is actually modulated by the applied VDS, increasing VDS causes the depletion region
at the drain junction to grow, reducing the length of the effective channel.
15. What is Latch – up?
Latch up is a condition in which the parasitic components give rise to the establishment of
low resistance conducting paths between VDD and VSS with disastrous results. Careful control
during fabrication is necessary to avoid this problem.
16. Define Threshold voltage in CMOS?
The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between
the gate and the source of the MOS transistor below which the drain to source current, IDS
effectively drops to zero.
17. What is Body effect?
The body effect describes the changes in the threshold voltage by the change in the source-
bulk voltage.

The voltage difference between the source and the bulk, V BS changes the width of the
depletion layer and therefore also the voltage across the oxide due to the change of the charge
in the depletion region. This results in a difference in threshold voltage which equals the
difference in charge in the depletion region divided by the oxide capacitance.
17. Give the MOS symbols for Enhancement and Depletion mode FETs.
18. Explain regions of operation of MOSFET (nmos).

There are three regions of operation in the MOSFET
 When VGS < VT, no conductive channel is present and ID = 0, the cutoff region
 If VGS < VT and VDS < VDS, sat, the device is in the triode region of operation. Increasing
VDS increases the lateral field in the channel, and hence the current. Increasing V GS
increases the transverse field and hence the inversion layer density, which also increases
the current.
 If VGS < VT and VDS > VDS, sat, the device is in the saturation region of operation. Since
the drain end channel density has become small, the current is much less dependent on
VDS, but is still dependent on VGS, since increased VGS still increases the inversion layer
density.

Fig: Shows the output characteristics and transfer characteristics of nMOS FET.
For VGS < VT , ID = 0
 As VDS increases at a fixed VGS, ID increases in the triode region due to the increased
lateral field, but at a decreasing rate since the inversion layer density is decreasing
 Once pinch off is reached, further VDS increases only increase ID due to the formation of
the high field region
 The device starts in triode and ,moves into saturation at higher VDS
 As ID is increased at fixed VDS, no current flows until the inversion layer is established
 For VGS slightly above threshold, the device is in saturation since there is little inversion
layer density(the drain end is pinched off)
 As VGS increases, a point is reached where the drain end is no longer pinched off, and the
device is in the triode region
 A larger VDS value postpones the point of transition to triode.
19. Give the voltage and current equations of MOSFET(enhancement NMOS)
Sl.no Range of Region Current (ID)
operation
1 𝑉𝐺𝑆 − 𝑉𝑇 < 0 Cutoff 0
2
2 𝑉𝐺𝑆 − 𝑉𝑇 > 0 Triode 𝐾 2 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆 − 𝑉𝐷𝑆
𝑉𝐷𝑆 < 𝑉𝐺𝑆 − 𝑉𝑇
2
3 𝑉𝐺𝑆 − 𝑉𝑇 > 0 Saturation 𝐾 𝑉𝐺𝑆 − 𝑉𝑇
𝑉𝐷𝑆 > 𝑉𝐺𝑆 − 𝑉𝑇

Fig: MOSFET transfer characteristics
20. Explain CMOS Inverter.
Region VIN PMOS NMOS ID VOUT4
1 0≤VIN<VTN Linear Cutoff 0 VDD
2 VTN≤VIN<VDD/2 Linear Saturated VOUT> VDD/2
3 VIN =VDD/2 Saturated Saturated VOUT drops sharply
4 VDD/2<VIN≤VDD-|VTP| Saturated Linear K VOUT < VDD/2

5 VIN>VDD-|VTP| Cutoff Linear 0 0
Fig (a): CMOS inverter

Fig (b): DC analysis

Fig: CMOS INVERTER DC characteristics

21. Define signal degradation?
Signal degradation is defined as the short-term variations of a digital signal’s significant instants
from their ideal positions in time.
22. Which technology is used in microwind3.1 version?
90nm technology.
23. Define common source amplifier or voltage amplifier.
A common-source amplifier is one of three basic single-stage field-effect transistor (FET)
amplifier topologies, typically used as a voltage or transconductance amplifier. The easiest way to
tell if a FET is common source, common drain, or common gate is to examine where the signal
enters, and leaves. The remaining terminal is what is known as "common".
24. Write the characteristics equations for common source amplifier.
Characteristics:
 Voltage gain = Vout / Vin
 Voltage gain = - (gm. Rd) / (1 + gm. Rs)
 gm = MOSFET transconductance
 gm = 2*Id / Vgs - Vth
25. Define common drain amplifier.
A common-drain amplifier, also known as a source follower, is one of three basic single-stage
field effect transistor (FET) amplifier topologies, typically used as a voltage buffer. In this circuit
the gate terminal of the transistor serves as the input, the source is the output, and the drain is
common to both (input and output) therefore its name.
26. Write the characteristics equations for common source amplifier

Characteristics:
 Voltage gain = Vout / Vin
 Voltage gain = (gm. Rs) / (gm. Rs + 1) =~ 1
 gm = MOSFET transconductance
 gm = 2*Id / Vgs – Vth

27. What is differential amplifier?

The differential amplifier is the combination of inverting and non inverting amplifier. It
amplifies the difference between two input voltages but suppresses any voltage common to the
two inputs.
The output voltage is given by
VOUT = A (V+IN - V-IN)
Where A = gain of the amplifier.
V+IN = non inverting voltage.
V+IN = inverting voltage.
****** ALL THE BEST*****

COURSE OUTCOMES
Staff Name: Mr. Lokesh.K.S/ Mrs.Anitha A. Sem: 7 Sec: A/B
/ Mrs.Chinna V Gowdar/ Mr.Sharana Basavaraj B.
Course Name: VLSI -Lab Course Code:18ECL77
Academic year:2021-22
Course Outcomes
Use Xilinix Tool to write the Verilog Code and Test Bench for combinational
C407.1 circuits and verify the simulation results.
Use Xilinix Tool to write the Verilog Code and Test Bench for Sequential circuits
C407.2 and verify the simulation results.
Sketch the Schematic & layout for CMOS Inverter, CMOS 2 input NAND gate
C407.3 and Common Source using microwind Tool to verify DRC & LVS.
Sketch the Schematic for Differential Amplifier & Operational Amplifier &
C407.4 compute gain.
[Staff Signature]

PROGRAM OUTCOMES (POS)
Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions
in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive clear
instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.




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R.Y.M.E.

C, Ballari VLSI Lab, VII Sem/2022-23

APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC) DESIGN FLOW

Fig shows ASIC design flow

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Procedure for Digital Design Experiments:

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Process "Behavioral Check Syntax" completed successfully should be displayed.

10. Double click on Simulate Behavioral Model.

11. Observe the output in ISim Simulator by selecting Default.wcfg.

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Waveform of 4 bit adder

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module full_adder( A,B,CIN,S,COUT);

assign COUT = (A&B) |(B&CIN)| (CIN&A);

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forever clk=#50 ~clk;

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Waveform of Asynchronous up counter

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forever clk=#50 ~clk;

rst=1'b1; rst=#100 1'b0; rst=#3600 1'bz;

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Waveform of Asynchronous down counter

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forever clk=#50 ~clk;

rst=1'b1; rst=#100 1'b0; rst=#3600 1'bz;

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Waveform of 32 bit ALU

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Waveforms of CMOS inverter

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1. Schematic of CMOS inverter

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Layout of CMOS inverter

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Waveforms of 2 input CMOS nand Gate