Lecture #9: MIPS Instruction Format

2005-07-05
Big Idea: Stored-Program Concept

Computers built on 2 key principles:

1) Instructions are represented as data.
data
2) Therefore, entire programs can be
stored
t d in
i memory to t beb read
d or
written just like data.
 Consequence: Everything Addressed

• Everything
E thi has
h a memory address:
dd
instructions, data words

• One register keeps address of instruction

being executed: “Program Counter” (PC)
• Basically a pointer to memory: Intel calls it
Instruction Address Pointer, a better name
• Computer “brain”
brain executes the instruction at PC
• Jumps and branches modify PC
Instructions as Numbers (1/2)

• Currently all data we work with is in

words (32-bit blocks):
• Each register is a word.
•lw and sw both access memory one word
at a time.
• So how do we represent instructions?
• Remember: Computer only understands
1s and 0s, so “add $t0,$0,$0” is
meaningless. (Should be binary format)
• MIPS wants simplicity: since data is in
words make instructions be words too
words,
Instructions as Numbers (2/2)
• One word is 32 bits, so divide
instruction word into “fields”.
• Each field tells computer something
about instruction
instruction.
yp of instruction formats:
• 3 basic types
• R-format
• I-format
I format
• J-format
 Instruction Formats
• I (Immediate) -format: used for instructions
with immediates,, lw and sw ((since the
offset counts as an immediate), and the
branches (beq and bne),
• (but not the shift instructions; later)
• J-format:
J format: used for j and jal
(jump and link)

• R-format: used for all other instructions

 R-Format Instructions (1/5)
• Define
D fi “fi“fields”
ld ” off the
th following
f ll i number b
of bits each: 6 + 5 + 5 + 5 + 5 + 6 = 32
6 5 5 5 5 6
• For simplicity, each field has a name:
opcode rs rt rd shamt funct

• Important: On these slides and in book, each field

is viewed as a 5- or 6-bit unsigned integer, not as
part of a 32-bit
32 bit integer
integer.
5-bit fields  0-31, 6-bit fields  0-63.
 R-Format Instructions (2/5)
• What do these field integer values tell us?
opcode: partially specifies what instruction
•opcode:
it is
- Note: This number is equal to 0 for all R
R-Format
Format
instructions.
•funct: combined with opcode,
p , this number
exactly specifies the instruction for
R-Format instructions
R-Format Instructions (3/5)
• More fields:
•rs (Source Register): generally used to
specify register containing first operand
•rt (Target Register): generally used to
specify register containing second
operand (note that name is misleading)
•rd (Destination Register): generally used
to specify register which will receive
result of computation
 R-Format Instructions (4/5)
• Notes about register fields:
• Each register field is exactly 5 bits, which
means that it can specify any unsigned
integer in the range 0-31. Each of these
fields specifies one of the 32 registers by
number.
b
• The word “generally” was used because
there are exceptions that we’ll see later.
later
E.g.,
- mult and div have nothing important in the
rd field since the dest registers are hi and lo
- Mfhi (move form hi register) and mflo
(
(move form
f lo
l register)
i ) have
h nothing
thi
important in the rs and rt fields since the
source is determined by the instruction (p. 264
P&H)
R-Format Instructions (5/5)
• Final field:
shamt: This field contains the amount a
•shamt:
shift instruction will shift by. Shifting a
32-bit word by y more than 31 is useless,
so this field is only 5 bits (so it can
represent the numbers 0-31).
• This field is set to 0 in all but the shift
instructions.
• For a detailed description of field
usage for each instruction, see green
insert in COD 3/e
R-Format Example (1/2)

• MIPS Instruction:
add $8,$9,$10

opcode = 0 (look up in table in book)

funct = 32 (look up in table in book)
rs = 9 (first operand)
rt = 10 (second operand)
rd = 8 (destination)
shamt = 0 (not a shift)
R-Format Example (2/2)

• MIPS Instruction:
add $8,$9,$10
Decimal number per field representation:
0 9 10 8 0 32
Binary number per field representation:
000000 01001 01010 01000 00000 100000
hex
hex representation: 012A 4020hex
decimal representation: 19
19,546,144
546 144ten
• Called a Machine Language Instruction
I-Format Instructions (1/4)
• What about instructions with
immediates (e.g. addi and lw)?
• 5-bit field only represents numbers up to
the value 31: immediates may be much
larger than this
• Ideally,
y, MIPS would have onlyy one
instruction format (for simplicity):
unfortunately, we need to compromise
• Define new instruction format that is
partially consistent with R
R-format:
format:
• Notice that, if instruction has an immediate,
(if immediate > 31) then it uses at most 2
registers.
I-Format Instructions (2/4)
• Define “fields” of the following number
of bits each: 6 + 5 + 5 + 16 = 32 bits
6 5 5 16
• Again, each field has a name:
opcode rs rt immediate
• Key Concept: Only one field is
inconsistent with R-format. Most
importantly, opcode is still in same
location.
• Notice: No rd field
 I-Format Instructions (3/4)
• What do these fields mean?
•opcode: same as before except that, since
there’s
there s no funct field,
field opcode uniquely
specifies an instruction in I-format
• This also answers question of why
R-format has two 6-bit fields to identify
instruction instead of a single 12-bit field:
in order to be consistent with other
formats. (to be consistent with 6 bit I
Format opcode
p format))
•rs: specifies the only register operand (if
there is one)
•rt: specifies register which will receive
result of computation (this is why it’s
called the target register “rt”) (source for R format
before)
I-Format Instructions (4/4)
• The Immediate Field:
addi, slti, sltiu, the immediate is
•addi,
sign-extended to 32 bits. Thus, it’s
treated as a signed integer.
• 16 bits  can be used to represent
immediate up p to 216 different values
• This is large enough to handle the offset
in a typical
yp lw or sw,, plus
p a vast majority
j y
of values that will be used in the slti
instruction.
I-Format Example (1/2)
• MIPS Instruction:
addi
ddi $21
$21,$22,-50
$22 50

opcode = 8 (look up in table in book)

rs = 22 (register containing operand)
rt = 21 (target register)
immediate = -50 (by default, this is decimal)
I-Format Example (2/2)

• MIPS Instruction:
addi $21,$22,-50

Decimal/field representation:
8 22 21 -50
50
Binary/field representation:
001000 10110 10101 1111111111001110
hexadecimal representation: 22D5 FFCEhex
decimal representation: 584,449,998ten
 I-Format Problems (0/3)
• Problem 0: Unsigned # sign
sign-extended?
extended?
•addiu, sltiu, sign-extends immediates
to 32 bits
bits. Thus
Thus, # is a “signed”
signed integer.
integer
• Rationale
•addiu so that can add w/out overflow
(of immediate #) - See K&R pp. 230, 305
•sltiu suffers so that we can have ez HW
(
(easier
i hardware
h d but
b t problems
bl on sltiu)
lti )
- Does this mean we’ll get wrong answers?
- Nope,
Nope it means assembler has to handle any an
unsigned immediate 2 ≤ n < 2 (I.e., with a
15 16
1 in the 15th bit and 0s in the upper 2 bytes)
as it does for numbers that are too large
large.
Problem 1 rationale
I-Format Problems (1/3)

• Problem 1:
• Chances are that addi, lw, sw and slti
will use immediates small enough to fit in
the immediate field
field.
• …but what if it’s too big?
• We need a way to deal with a 32-bit
immediate in any I-format instruction.
I-Format Problems (2/3)
• Solution to Problem 1:
• Handle it in software + new instruction
• Don’t change the current instructions:
instead add a new instruction to help out
instead,
• New instruction: ((16b immediate solution))
lui register, immediate
• stands
t d forf Load
L d Upper
U I
Immediate
di t
• takes 16-bit immediate and puts these bits
i the
in th upper half
h lf (high
(hi h order
d half)
h lf) off the
th
specified register
• sets lower half to 0s
 I-Format Problems (3/3)
• Solution
S l ti tot Problem
P bl 1 ((continued):
ti d)
• So how does lui help
p us?
• Example:
addi $t0
$t0,$t0,
$t0 0xABABCDCD
becomes:
l i
lui $
$at,
t 0xABAB
0 ABAB
ori $at, $at, 0xCDCD
add $t0,$t0,$at
• Now each I-format instruction has only a 16-
bit immediate.
• Wouldn’t it be nice if the assembler would
tthis
s for
o us automatically?
auto at ca y ((later)
ate )
J-Format Instructions (0/5)

Jumps modify the PC:

“jj <label>
<label>”

means

“Set the next PC = the address of the

i t
instruction
ti pointed
i t d to
t by
b <label>”
<l b l>”
J-Format Instructions (1/5)

Jumps modify the PC:

• j and jal jump to labels
• but a label is jjust a name for an address!
• so, the ML (machine language) equivalents of j
and jjal use addresses
- Ideally, we could specify a 32-bit memory
address to jump to.
- Unfortunately, we can’t fit both a 6-bit
opcode and a 32-bit address into a single
32 bit word,
32-bit word so we compromise:
J-Format Instructions (2/5)
• Define fields of the following number
of bits each:
6 bits 26 bits
• As usual, each field has a name:
opcode target address
• Key Concepts
• Keep opcode field identical to R-format
and I-format
I format for consistency
consistency.
• Combine all other fields to make room
f llarge target
for t t address.
dd
J-Format Instructions (3/5)
• target has 26 bits of the 32-bit bit address.

• Optimization:
• jumps will only jump to word aligned
addresses,
addresses
- so last two bits of address are always 00 (in
binary).
binary)
- let’s just take this for granted and not even
specify them.
J-Format Instructions (4/5)
• Now : we have 28 bits of a 32-bit address
• Where
Wh d
do we gett the
th other
th 4 bits?
bit ?
• Byy definition,, take the 4 highest-order
g bits
from the PC.
• Technically, y, this means that we cannot jump
j p
to anywhere in memory, but it’s adequate
99.9999…% of the time, since programs
aren’t
’t that
th t long
l
- only if jump straddles a 256 MB (28bits)
boundary
- If we absolutely need to specify a 32-bit
address we can always put it in a register and
address,
use the jr instruction. (long jump)
J-Format Instructions (5/5)

• Summary:
• Next PC = { PC[31..28], target address, 00 }
• Understand where each part came from!
• Note: { , , } means concatenation
{ 4 bit
bits , 26 bits
bit , 2 bit
bits } = 32 bit address
dd
• { 1010,, 11111111111111111111111111,, 00 }
= 10101111111111111111111111111100
• Note: Book uses ||, Verilog uses { , , }
• We won’t actually be learning Verilog, but
it is useful to know a little of its notation
 Other Jumps and Branches

• We have j and jal

• What about jr?
• J-format won’t
won t work (no reg field)
• So, use R-format and ignore other regs:
opcode rs rt rd shamt funct
0 $ g
$reg 0 0 0 8

• What about beq and bne?

• Tight fit: 2 regs and an immediate (address)
Branches: PC-Relative Addressing (1/4)
• Use I-Format
opcode
d rs rt
t i
immediate
di t
• opcode
p specifies
p q v. bne
beq
• rs and rt specify registers to compare
• What can immediate specify?
•Immediate is only 16 bits
• Using word-align trick, we can get 18 bits
• Still not enough! (for target address)
- Would have to use jjr if straddling
g a 256KB.
Branches: PC-Relative Addressing (2/4)
• How do we usually use branches?
• Answer: if
if-else,
else, while, for
• Loops are generally small: typically up to
50 instructions
• Function calls and unconditional jumps are
done using jump instructions (j and jal),
jal)
not the branches.
• Conclusion: may want to branch to
anywhere in memory, but a branch often
changes PC by a small amount…
amount
Branches: PC-Relative Addressing (3/4)
• Solution to branches in a 32-bit
instruction: PC
PC-Relative
Relative Addressing
• Let the 16-bit immediate field be a
signed two’s complement integer to be
added to the PC if we take the branch.
• Now we can branch ± 215 words from
the PC, which should be enough to
cover almost
l t any loop.
l
• ((Notice : different from 4 bit concatenation before))
Branches: PC-Relative Addressing (4/4)
• Branch
B h Calculation:
C l l ti
• If we don’t take the branch:
next PC = PC + 4
PC+4 = byte address of next instruction
• If we do take the branch:
next PC = (PC + 4) + (immediate * 4)
• Observations
Obse at o s
- Immediate field specifies the number of
words to jump, which is simply the number of
instructions to jump.
- Immediate field can be positive or negative.
- Due to hardware, add immediate to (PC+4),
not to PC; will be clearer why later in course
Branch Example (1/3)
• MIPS Code:
Loop: beq $9
$9,$0,End
$0 End
add $8,$8,$10
addi $9,$9,-1
j Loop
End: sub $2
$2,$3,$4
$3 $4
q branch is I-Format:
• beq
opcode = 4 (look up in table)
rs = 9 (first operand)
rt = 0 (second operand)
immediate = ???
Branch Example (2/3)
• MIPS Code:
Loop: beq $9
$9,$0,End
$0 End
addi $8,$8,$10
addi $ ,$ ,
$9,$9,-1
j Loop
End: sub $2,$3,$4
• Immediate Field:
• Number of instructions to add to (or
subtract from) the PC, starting at the
i t
instruction
ti following
f ll i the
th branch
b h (“+4”).
(“ 4”)
• In beq case, immediate = 3
(not 4 from next PC)
Branch Example (3/3)
• MIPS Code:
Loop: beq $9
$9,$0,End
$0 End
addi $8,$8,$10
addi $ ,$ ,
$9,$9,-1
j Loop
End: sub $2,$3,$4

decimal representation:
4 9 0 3
binary representation:
000100 01001 00000 0000000000000011
Questions on PC-addressing

• Does the value in branch field change

if we move the code?

• What do we do if destination is > 215

instructions away
y from branch?
 MIPS So Far:
• MIPS Machine Language Instruction:
32 bits representing a single instruction
R opcode rs rt rd shamt funct
I opcode
d rs rt immediate
i di
J opcode target address

• Branches
B h use PC-relative
PC l ti addressing,
dd i
Jumps use PC-absolute addressing.
 Decoding Machine Language
• How do we convert 1s and 0s to C code?
Machine language  C?
• For each 32 bits:
• Look at opcode: 0 means R-Format, 2 or 3
mean J J-Format,
Format otherwise II-Format.
Format
• Use instruction type to determine which
fields exist.
exist
• Write out MIPS assembly code, converting
eachh field
fi ld to
t name, register
i t number/name,
b /
or decimal/hex number.
• Logically
i ll convert this
hi MIPS coded into
i valid
lid
C code. Always possible? Unique? (No)
Decoding Example (1/7)
• Here are six machine language
instructions in hexadecimal:
00001025hex
0005402Ahex
11000003hex
00441020hex
20A5FFFFhex
08100001hex
• Let the first instruction be at address
4 194 304ten (0x00400000hex).
4,194,304 )
p convert hex to binary
• Next step: y
Decoding Example (2/7)

• The six machine language instructions in

binary:
00000000000000000001000000100101
00000000000001010100000000101010
00010001000000000000000000000011
00000000010001000001000000100000
00100000101001011111111111111111
00001000000100000000000000000001
• Next step: identify opcode and format

R 0 rs rt rd shamt funct
I 1, 4-31 rs rt immediate
J 2 or 3 target address
 Decoding Example (3/7)
• Select the opcode (first 6 bits)
to determine the format:
Format:

R 00000000000000000001000000100101
R 00000000000001010100000000101010
I 00010001000000000000000000000011
R 00000000010001000001000000100000
I 00100000101001011111111111111111
J 00001000000100000000000000000001
• Look at opcode:
0 means R-Format,,
2 or 3 mean J-Format,
otherwise I-Format.
• Next step: separation of fields
 Decoding Example (4/7)

• Fields separated based on format/opcode:

Format:
R 0 0 0 2 0 37
R 0 0 5 8 0 42
I 4 8 0 +3
R 0 2 4 2 0 32
I 8 5 5 -1
J 2 1,048,577

• Next step: translate (“disassemble”) to

MIPS assembly y instructions
Decoding Example (5/7)

• MIPS Assembly (Part 1):

Address: Assembly instructions:
0x00400000 or $2
$2,$0,$0
$0 $0
0x00400004 slt $8,$0,$5
0x00400008 beq $8,$0,3
0 0040000
0x0040000c add
dd $2
$2,$2,$4
$2 $4
0x00400010 addi $5,$5,-1
0x00400014 j 0x100001
• Better solution: translate to more
meaningful MIPS instructions (fix the
branch/jump and add labels, registers)
Decoding Example (6/7)

• MIPS Assembly (Part 2):

or $v0,$0,$0
Loop: slt $t0,$0,$a1
beq $t0,$0,Exit
add
dd $
$v0,$v0,$a0
0 $ 0 $ 0
addi $a1,$a1,-1
j Loop
Exit:

• Next step: translate to C code

(be creative!)
 Decoding Example (7/7)
Before Hex: • After C code (Mapping below)
$v0: product
0000 0 5hex
00001025 $a0: multiplicand
0005402Ahex $a1: multiplier
11000003hex
00 1020hex
00441020 product = 0;
20A5FFFFhex while (multiplier > 0) {
product += multiplicand;
08100001hex multiplier
lti li -= 1;
1
}
or $v0,$0,$0
$ 0 $0 $0
Loop: slt $t0,$0,$a1 Instructions are just
beq $t0,$0,Exit numbers code is
numbers,
add $v0,$v0,$a0
treated like data
addi $a1,$a1,-1
j Loop
Exit:
Peer Instruction Question

(for A,B) When combining two C files into

one executable,
e ec table recall we e can compile them
independently & then merge them together.
A. Jump p insts don’t require
q any
y changes.
g
B. Branch insts don’t require any changes.
C. You now have all the tools to be able to
“decompile” a stream of 1s and 0s into C!