M. Penchala Prasad et al Int. Journal of Engineering Research and Applications www.ijera.

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ISSN : 2248-9622, Vol. 4, Issue 2( Version 3), February 2014, pp.33-42

RESEARCH ARTICLE OPEN ACCESS

Performance Enhancement of a Novel Interleaved Boost

Converter by Using a Soft-Switching Technique
M. Penchala Prasad1, Ch. Jayavardhana Rao M.Tech 2, Dr. Venu Gopal. N M.E Phd.3
P.G Scholar, Associate Professor, Professor
1, 2, 3
Kuppam Engineering College, Kuppam, Chittoor Dist, A.P, India

ABSTRACT
In this paper a novel Interleaved Boost Converter (IBC) with soft-switching techniques is proposed. Through the
zero-voltage switching (ZVS) and zero-current switching (ZCS) reduces the current stress of the main circuit
components, in addition to this it can also reduces the ripple of the input current and output voltage. In this
approach, it can be faster switching, reduce the size and cost with suitable impedance matching is achieved with
reduction in auxiliary circuit reactance that has contributed much increase in the overall performance. Coupled
inductor in the boosting stage helps higher current sharing between the switches. The overall ripple and Total
harmonics distortions are reduced in this technique without sacrificing the performance and efficiency of the
converter. The driving circuit can automatically detect operational conditions depending on the situation of the
duty cycle whether the driving signals of the main switches are more than 50% or not and get the driving signal
of the auxiliary switch. Auxiliary circuit acts as support circuit to both main switches(two conditions) and
reduce the total losses and improve efficiency& power factor for large loads. The operational principle,
theoretical analysis, and design method of the proposed converter are presented. The entire proposed system will
be tested using MATLAB/SIMULINK and the simulation results are also presented.
Keywords: Interleaved Boost Converter(IBC), Zero-Voltage Switching (ZVS) & Zero-Current Switching
(ZCS)

I. INTRODUCTION
A basic boost converter converts a DC same power condition. The single boost converter
voltage to a higher DC voltage. Interleaving adds can use the zero-voltage switching (ZVS) and/or
additional benefits such as reduced ripple currents in zero-current switching (ZCS) to reduce the switching
both the input and output circuits. Higher efficiency loss of the high-frequency switching. However, they
is realized by splitting the output current into two are considered for the single topology.
paths, substantially reducing losses and inductor AC The major challenge of designing a boost
losses converter for high power application is how to handle
In the field of power electronics, application the high current at the input and high voltage at the
of interleaving technique can be traced back to very output . An interleaved boost dc-dc converter is a
early days, especially in high power applications. In suitable candidate for current sharing and stepping up
high power applications, the voltage and current the voltage on high power application. In the
stress can easily go beyond the range that one power interleaved boost converter topology, one important
device can handle. Multiple power devices connected operating parameter is called the duty cycle D.For the
in parallel and/or series could be one solution. boost converter, the ideal duty cycle is the ratio of
However, voltage sharing and/or current sharing are voltage output and input difference with output
still the concerns. Instead of paralleling power voltage.
devices, paralleling power converters is another The PWM converters, the resonant
solution which could be more beneficial. Benefits converters are widely employed for high voltage
like harmonic cancellation, better efficiency, better applications because they can easily achieve ZVS or
thermal performance, and high power density. ZCS soft-switching operation during the whole
An interleaved boost converter usually switching transition. However, the series resonant
combines more than two conventional topologies, converter has the poor voltage regulation at very light
and the current in the element of the interleaved boost load conditions. The parallel resonant converter is
converter is half of the conventional topology in the hard to regulate the output voltage at short-circuit
conditions. The LCC (one resonant inductor, one

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parallel capacitor and one series capacitor) resonant transferring energy from an input source to output. In
converter and the LLC (one resonant inductor, one some of these converters or some members of
magnetizing inductor and one series capacitor) converter family, the auxiliary circuit can boost the
resonant converter have good voltage regulation at effective duty cycle, but the amount of energy that is
light-load and short-circuit conditions. Also, the transferred through the auxiliary circuit cannot be
output diode reverse-recovery problem is alleviated controlled once the converter is designed. In the ZVT
because of its natural commutation of the rectifier converter family introduced in, the output current can
current. However, the current through the series be shared between main and auxiliary switches even
capacitor is very large, which needs more bulky though the authors did not have the intention of
capacitors in parallel to reduce the equivalent series current sharing for these converters. In ZCT
resistance (ESR). Meanwhile, the conduction losses converters introduced in, the output current is shared
are greater than the pulse width modulated (PWM) between the switches; however, the switches do not
converters because of its resonant operation mode. turn off under soft-switching condition.
In high-power applications, interleaving of The main intension of the paper is to
two boost converters is very often employed to develop the zero voltage switching and zero current
improve performance and reduce size of the PFC switching actions in boost converter by using
front end. Namely, because interleaving effectively interleaved approach to mainly reduce the sudden
doubles the switching frequency and also partially voltage and current changes(on & off).Auxiliary
cancels the input and output ripples, the size of the circuits acts as support circuit to both main switches
energy storage inductors and differential-mode (two conditions) and reduce the total losses and
electromagnetic interference (EMI) filter in improve efficiency& power factor for large loads.
interleaved implementations can be reduced. The voltage stresses of the main switches and
A new active soft switching circuit based on auxiliary switch are equal to the output voltage and
interleaving two boost converters and adding two the duty cycle of the proposed topology can be
simple auxiliary commutation circuits is proposed in increased to more than 50%. The proposed converter
this paper. Compared to the conventional interleaved is the parallel of two boost converters and their
boost converters, the main switches are ZCS at turn- driving signals stagger 180◦ and this makes the
on transition and ZVS at turn-off transition. The operation assumed symmetrical. Moreover, by
added auxiliary switches do not cause extra voltages establishing the common soft-switching module, the
on the main switches and the auxiliary switches are soft-switching interleaved converter can further
zero-voltage transmission (ZVT) during the whole reduce the size and cost.
switching transition. Compared to the previous
published soft switching interleaved boost converters, II. ANALYSIS OF OPERATION
no extra inductor is needed in the auxiliary unit, so Fig: 1 shows the proposed circuit. It uses the
the auxiliary unit is simple. interleaved boost topology and applies the common
Several soft-switching techniques, gaining soft-switching circuit. The resonant circuit consists of
the features of zero-voltage switching (ZVS) or zero- the resonant inductor � , resonant capacitor ,
current switching (ZCS) for dc/dc converters, have parasitic capacitors and , and auxiliary switch
been proposed to substantially reduce switching to become a resonant way to reach ZVS and ZCS
losses, and hence, attain high efficiency at increased functions. Fig: 2 shows the two operating modes of
frequencies. The main problem with these kinds of this circuit, depending on whether the duty cycle of
converters is that the voltage stresses on the power the main switch is more than 50% or not.
switches are too high in the resonant converters,
especially for the high-input dc-voltage applications Operational Analysis of D <50% Mode
Converters with interleaved operation are The operating principle of the proposed
fascinating techniques nowadays. Interleaved boost topology is described in this section. There are 24
converters are applied as power-factor-correction operational modes in the complete cycle. Only the 12
front ends. An interleaved converter with a coupled modes related to the main switch Sa are analyzed,
winding is proposed to a provide a lossless clamp. because the interleaved topology is symmetrical. Fig:
Additional active switches are also appended to 3 shows the related waveforms when the duty cycle
provide soft-switching characteristics .These of the main switch is less than 50%. There are some
converters are able to provide higher output power assumptions to simplify the circuit analysis.
and lower output ripple 1) All switches and diodes are assumed ideal.
In ZVT and ZCT converters, an auxiliary 2) Idealizing the input and output reactance.
circuit containing resonant elements and an auxiliary 3) The two boost inductors are equal.
switch is used that provide soft switching at 4) The duty cycles (D1 = D2) for the main switches
switching instances and is usually incapable of and .

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Mode 1 [� − � ]: Fig: 4 (a) shows the equivalent the main switch voltages � and � decrease to
circuit. In this mode, the main switches S and S are zero, because the resonance occurs among ,
turned OFF, the auxiliary switch S and the rectifier and � . Then, the body diodes (S ) and (S )
diodes and are turned ON, and the clamped can be turned ON as shown in Fig: 4(b)
diode is turned OFF. The voltages across the
parasitic capacitors and of the main switches The resonant time 12 and resonant inductor current
and the resonant capacitor Cr are all equal to the � ( 2 ) are
output voltage; i.e. � = � = � = �0 in the
previous mode. π π
t12 = = . Lr . Csa + Csb + Cr ( )
The resonant inductor current � linearly 2ω0 0 2
ramps up until it reaches � at t = 1 . When the V0 V0
ILr = nIin + = Iin + (3)
resonant inductor current �� is equal to � , the mode Z0 Lr
1 will end. Then, the rectifier diodes are turned OFF. Csa + Csb + Cr
The interval time 01 is where
��
�0 = 1/ Lr . Csa + Csb +Cr
01 =� . (1)
�0
And 0 = � /( + + )
Mode 2 [� − � ]: In mode 2, the resonant inductor
current continues to increase to the peak value, and

Fig: 1 A novel interleaved boost converter with characteristics of zero-voltage switching and zero-current
switching

Fig: 2 Switching waveforms of the main switches S Fig:3 Related waveforms (D < 50%).
and S And auxiliary switch S .(a)D < 50% mode

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ISSN : 2248-9622, Vol. 4, Issue 2( Version 3), February 2014, pp.33-42

Mode 3 [� –� ]: Fig: 4(c) shows the equivalent auxiliary switch Sr needs to be more than t 01 +t12 to
circuit of this mode. At the end of mode 2, the main achieve the function of ZVS.
switch voltage � decreases to zero, so the body The interval time t 03 is
diode of S is turned ON at 2 . At this time, the
� �
main switch can achieve ZVS. The on-time t 03 of the 03 ≥ 01 + 12 =� . + . � .( + +
� 2
(4)

Fig:4 Equivalent circuits of different modes (D < 50%). (a) Mode 1 [ 0 – 1 ]. (b) Mode 2 [ 1 − 2 ]. (c) Mode 3
[ 2 − 3 ]. (d) Mode 4 [ 3 − 4 ]. (e) Mode 5 [ 4 − 5 ].(f) Mode 6 [ 5 – 6 ] (g) Mode 7 [ 6 – 7 ]. (h-a) Mode 8 [ 7
– ]. (h-b) Mode 8 [ – 8 ]. (h-c) Detailed waveform of the Mode 8.

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ISSN : 2248-9622, Vol. 4, Issue 2( Version 3), February 2014, pp.33-42

Fig. 4 (Continued.) Equivalent circuits of different modes (D <50%). (i) Mode 9 [ 8 – 9 ]. (j) Mode 10 [ 9 – 10 ].
(k) Mode 11 [ 10 – 11 ]. (l) Mode 12 [ 11 – 12 ].
The resonant time 45 is

Mode 4 [� − � ]: Fig: 4 (d) shows the equivalent

circuit of this mode. In this mode, the auxiliary
�
switch is turned OFF, and the clamped diode is 45 =� (7)
turned ON. During this interval, the energy stored in +
the resonant inductor � is transferred to the output Where, = +
load.
The resonant inductor current �� decreases Mode 6 [� − � ]: Fig : 4(f) shows the equivalent
to zero and the clamped diode is turned OFF at circuit. The parasitic capacitor CSr of the auxiliary
4 . The energy discharge time of the resonant switch is linearly charged by IL2 −Io toVo . Then, the
inductor is clamped diode Dr is turned ON at t 6 .
The interval time 56 is
� �
34 = � + . (5) .�
� � + + = . (8)
56
��2 − �

Mode 5 [� − � ]: In this mode, the clamped diode

Dr is turned OFF. The energy of the boost_L2 is Mode 7 [� − � ]: Fig: 4(g) shows the equivalent
transferred to Cr and Csb and the energy stored in the circuit. In this mode, the clamped diode Dr is turned
parasitic capacitor Csr of the auxiliary switch is ON. The energy stored in the resonant inductor Lr is
transferred to the inductor Lr and resonant capacitor transferred to the output load by the clamped diode
Cr at this time. The rectifier diode Db is turned ON Dr .At t 7 , the clamped diode Dr is turned OFF
when the voltage across the main switch Sb reaches because the auxiliary switch Sr is turned ON.
Vo at t =t 5 . The interval time t 67 and the resonant
The resonant inductor current iLr t is inductor current are

+ ��2 67 = 1 − + 36 (9)
� = −� +
� + � +
� 7 ≈ � 6 = ��2 − � . 10
+
× 1− (6)
�

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Mode 8 [� − � ]: In the interval [t 7 − t a ], the � �

resonant inductor current ILr increases linearly until it = � + (16)
� � +
reaches IL2 and the rectifier diode current IDb
decreases to zero at t = t a , so the rectifier diode Db is
� 10 =� 10 =� 10
turned OFF. Fig: 4(h-a) shows the equivalent circuit.
The interval time t 7a is
1
� = 10
� − � ( ) . (17)
( + + )
7 =� . . (11) 9
�

As for the interval time [ − 8 ].Fig: Mode 11 [� − � ]: The capacitors Csa , Csb , and
4[ − 8 ].The resonant inductor current continues to Cr are linearly charged by Iin to Vo , and the rectifier
increase to the peak value and the main switch diodes Da and Db are turned ON at t11 . as shown in
voltage V decreases to zero because of the Fig: 4(k).
resonance among , , and � . At t = 8 , the body
diode of is turned ON. This charged time t10−11 is
The interval time 8 is
( ). (� − �
+ 10 ) +
� � 10−11 = (18)
8 = = . � + (12) �
2� 1 2
Mode 12 [� − � ]: In this mode, the operation of
the interleaved boost topology is identical to that of
Then, 78 is
� � the conventional boost converter. The ending time t12
78 = � . + . �
� 2
+ . (13) is equal to the starting time t 0 of another cycle,
because the operation of the interleaved topology is
Mode 9 [� − � ]: In this mode, the resonant inductor symmetrical. As shown in Fig :4(l)
current ILr is equivalent to a constant current
source.Fig :4(i) shows the equivalent circuit. In order The interval time 11−12 is
to meet the demand that the main switch Sa is turned
OFF under the ZCS condition, iLr t 8 ≈ iLr t 9 must
11−12 = − 1 + 03 + 9−11 . 19
be greater than Iin . Then the main switch currents Isa 2
and Isb are less than or equal to zero, so the main
switch Sa is turned OFF under the ZCS condition. Voltage Ratio of D < 50% Mode Fig: 5 shows the
The interval time 89 is equivalent circuits about the operation for the boost
89 = 1 − 38. 14 inductor Boost_�1 . The inductor Boost_�2 has the
And, the zero-current switching conditions similar results. So, when the switch is turned ON, the
are boost inductor current can be derived to be
� ∆
8 ≈ �
�1
� 9 = � +
� + =
≥� 15 � × ∆ +∆ +∆ +∆ +∆
=
and the duty time of ZCS is longer than the �1
interval time 78 ( T > 78 ). � × +2 � 1 +
= (20)
�1
Mode 10 [� − � ]: When the main switch Sa and And when the switch is turned OFF, the boost
the auxiliary switch Sr are turned OFF, the energy inductor current is
stored in the resonant inductor Lr is transferred to the � −� × ∆ +∆ +∆
output load by the clamped diode Dr . When the ∆ �1 =
�1
resonant inductor current ILr decreases to zero at t10 , =
the clamped diode Dr is turned OFF. Then, the
capacitorsCsa , Csb , and Cr are charged by Iin as shown � −� × 1− 1 + +2 �
= . 21
in Fig: 4(j). �1
The interval time 9−10 and capacitor Then, the voltage conversion ratio can be
voltages of , , and are derived to be
� 1
� � = . 22
= + � 1− 1 + +2 �
9−10 �
� 1

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Fig.5 Equivalent circuits for the boost inductor (D < 50%) (a) Boost_L1 in the stage (b) Boost_L1 in the stage
with output capacitor

III. SIMULATION RESULTS

A .Simulation Circuit From Operational Analysis circuit. The proposed Interleaved Boost
Of D <50% Mode Converter with both ZVS and ZCS characteristics
was built.
Fig: 6 show the simulink model of proposed Fig: 8 show the simulink model of proposed
diagram from D<50% . Fig: 7 show the simulation diagram from D>50% .Fig:9 show the simulation
results. They verify the operation of the proposed results. They verify the operation of the proposed
circuit. The proposed Interleaved Boost Converter
with both ZVS and ZCS characteristics was built

Fig: 6 Simulink Model of Proposed diagram from D<50%

(a) (b)

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(b) (d)

(e) (f)
Fig:7 simulation waveforms of the main switches and (D<50% and load current 1.5A) (a)Mosfet1
Current & Voltage, (b)Mosfet2 Current & Voltage,(c)Diode1 & Mosfet1 Voltage,(d)Diode2 & Mosfet2
Voltage,(e) Output Current,(f) Output Voltage

B.Simulation Circuit From Operational Analysis Of D >50% Mode

Fig: 8 Simulink Model of Proposed diagram from D>50%

(a) (b)

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(c) (d)

(e) (f)
Fig:9 simulation waveforms of the main switches and (D>50% and load current 1.5A) (a) Mosfet1
Current & Voltage , (b) Mosfet2 Current & Voltage , (c) Diode1 & Mosfet1 Voltage, (d) Diode2 & Mosfet2
Voltage, (e) Output Current, (f) Output Voltage

IV. CONCLUSION
High efficiency of step-up DC/DC [2] C. M. Wang, “A new single-phase ZCS-
converters can be achieved by decreasing duty cycle PWM boost rectifier with high power factor
(lower conduction losses) and reducing voltage stress and low conduction losses,” IEEE Trans.
on switches (cheaper and lower RDS−on switches) Ind. Electron., vol. 53, no. 2, pp. 500–510,
applying soft switching technique (minimizing Apr. 2006.
switching losses). [3] H. M. Suryawanshi, M. R. Ramteke, K. L.
The main switches S and S can achieve Thakre, and V. B. Borghate, “Unity-power-
both ZVS and ZCS. The voltage stress of all switches factor operation of three-phase AC–DC soft
is equal to the output voltage. It has the smaller switched converter based on boost active
current stress of elements. It uses the resonant clamp topology in modular approach,” IEEE
inductor � , resonant capacitor , parasitic Trans. Power Electron., vol. 23, no. 1, pp.
capacitors and , and auxiliary switch S to 229–236, Jan. 2008.
become a common resonant way to reach ZVS and [4] C. J. Tseng andC. L.Chen, “A passive
ZCS of the main switches S and S .The driving lossless snubber cell for nonisolated PWM
circuit can automatically detect whether the driving DC/DC converters,” IEEE Trans. Ind.
signals of the main switches are more than 50% or Electron., vol. 45, no. 4, pp. 593–601, Aug.
not and get the driving signal of the auxiliary switch. 1998.
The users can only apply the ZVS or ZCS function [5] Y.-C. Hsieh, T.-C. Hsueh, and H.-C. Yen,
just by the adjustment of the driving circuit. The “An interleaved boost converter with zero-
efficiency is 94.6% with output power of 600W and voltage transition,” IEEE Trans. Power
input voltage of 150V and it is 95.5% with output Electron., vol. 24, no. 4, pp. 973–978, Apr.
power of 400W and input voltage of 250V 2009.
[6] C. M. de Oliveira Stein, J. R. Pinheiro, and
REFERENCES H. L. Hey, “A ZCT auxiliarycommutation
[1] G. C. Hua, W. A. Tabisz, C. S. Leu, N. Dai, circuit for interleaved boost converters
R. Watson, and F. C. Lee,“Development of a operating in critical conduction mode,”
DC distributed power system,” in Proc. IEEE Trans. Power Electron., vol. 17, no. 6,
IEEE 9th Annu. Appl. Power Electron. Conf. pp. 954–962, Nov. 2002.
Expo., Feb. 1994, vol. 2, pp. 763–769.

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M. Penchala Prasad M.Tech Student from

Kuppam Engineering College at Kuppam (JNTU A).
I was awarded B.Tech from P.B.R Visvodaya
Institute of Technology& Science (JNTU A) in 2011.

Dr.Venugopal ME, Ph.D., working as

Professor, he was awarded Ph.D(video processing)
from Dr. MGR University, Chennai, in 2011, he was
awarded M.E (Power electronics) from University
Visveshwaraya College of Engineering, Bangalore, in
1998, he was awarded B.E (EEE) from R.V. College
of Engineering, Bangalore, in 1995. He has 16 years
of teaching experience and he is currently working as
Director (Research & Development) in Kuppam
engineering college, kuppam. His research area
interested in power electronics, vedio processing,
power systems & renewable energy sources.

Ch. Jayavardhana Rao M.Tech working as

Associate Professor, he was awarded M.Tech from
University college of Engineering Kakinada (JNTU
K) in 2009, he was awarded B.Tech from JNTU
Hyderabad in 2002. He has 5 years of Industrial
experience at RINL and he has 5 years of teaching
experience. His area of interest is Power systems,
High Voltage Engineering & Power Electronic

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