AAST-CC312-Fall 21 - Lec 02

CC312 Computer Organization
Fall 2021
Lecture 2
Introduction
Register Transfer Language
Transfer Microoperation
introduction
 Digital systems are composed of modules
 Modules are registers, counters, arithmetic elements, etc connected via:

▪ Data paths routes on which information is moved
▪ Control paths routes on which control signals are moved
 Digital modules are best defined by the registers they contain
 The operations executed on data stored in registers are called microoperations
 A microoperation is an elementary operation performed on the information stored

in one or more registers
▪ Examples are shift, count, clear, and load

Introduction
Introduction
Register Transfer
Language
Transfer Microoperation
RTL
 Rather than specifying a digital system in words, a specific notation is used,
 RTL is a symbolic notation to describe the microoperation transfers among registers
 Example
If (P = 1) then (R1 R2) else If (Q = 1) then (R1R3)
P: RI R2
P’Q: R1R3
 Register transfer language
❑ A symbolic language
❑ A convenient tool for describing the internal organization of digital computers
❑ Can also be used to facilitate the design process of digital systems
 Three basic components:
❑ set of registers
❑ microopertions
❑ control of operations
RTL
 Registers are designated by capital letters, sometimes followed by numbers
(e.g., A, R13, IR)
 Often the names indicate function:
 MAR - memory address register
 PC - program counter
 IR - instruction register
 Registers and their contents can be viewed and represented in various ways
MAR 7 6 5 4 3 2 1 0
Single entity Showing individual bits
15 0 15 8 7 0
PC Upper byte PC(H) PC(L) Lower byte
Numbering of bits
Partitioned into two parts
RTL
8
RTL
 Often actions need to only occur if a certain condition is true
 This is similar to an “if” statement in a programming language
 In digital systems, this is often done via a control signal, called a control function
 If the signal is 1, the action takes place
 This is represented as:
P: R2  R1
Which means “if P = 1, then transfer the contents of register R1 into register R2”, i.e.,
if (P = 1) then (R2  R1)
 Example:
If (P = 1) then (R1 R2) else If (Q = 1) then (R1R3)

P: RI R2
P’Q: R1R3
RTL
Hardware implementation of a controlled transfer: P: R2 ← R1
Block diagram: Control P Load

R2 Clock
Circuit
R1
t t+1
Timing diagram
Clock
Synchronized
Load
with the clock
Transfer occurs here
Types of microoperations
❑ Transfer
❑ move data from one set of registers to another
❑ Arithmetic
❑ perform arithmetic on data in registers
❑ Example + - / …..etc
❑ Logic
❑ manipulate data or use bitwise logical operations
❑ Example AND OR
❑ Shift
❑ shift data in registers (left, right, circulate)
Introduction
Transfer
TransferMicrooperation
Microoperation
Registers transfer
 In a digital system with many registers, it is impractical to have data and control
lines to directly allow each register to be loaded with the contents of every
possible other registers
 To completely connect n registers → n(n-1) lines
 This is not a realistic approach to use in a large digital system
 Instead, take a different approach Like BUS
 Have one centralized set of circuits for data transfer
 Have control circuits to select which register is the source, and which is the destination
Registers transfer
 A bus: set of common lines, one for each bit of a register, through which binary information is
transferred one at a time
 The bus is connected to the inputs of all destination registers and will activate the
load control of the selected register when it is ready to transfer data. This can be
written as:
R2  BUS, BUS  R1 or R2  R1
 Ways of selecting a common bus system include multiplexers, decoders and tri state buffer
Bus Transfer
 Multiplexers can be used to construct a common bus
 Multiplexers select the source register whose binary information is then placed on the bus
 The select lines are connected to the selection inputs of the multiplexers and choose the bits of one
register
 In general, a bus system will multiplex k registers of n bits each to produce an n-line common bus
 This requires n multiplexers – one for each bit
 The size of each multiplexer must be k x 1
 To transfer information from the bus to a register, the bus lines are connected to the inputs of all
destination registers and the corresponding load control line must be activated
Bus Transfer
4-Line Common bus

Bus Transfer
 Instead of using multiplexers, three-state gates can be used to construct the bus system
 A three-state gate is a digital circuit that exhibits three states
 Two of the states are signals equivalent to logic 1 and 0
 The third state is a high-impedance state – this behaves like an open circuit, which means the output
is disconnected and does not have a logic significance
 The three-state buffer gate has a normal input and a control input which determines the output state
 With control 1, the output equals the normal input
 With control 0, the gate goes to a high-impedance state
 This enables a large number of three-state gate outputs to be connected with wires to form a common
bus line without endangering loading effects
Bus Transfer
 Decoders are used to ensure that no more than one control input is active at any given time
 This circuit can replace the multiplexer in Figure 4.3
 To construct a common bus for m registers of n bits each using three-state buffers,
 we need m x n buffers
 Only one decoder is necessary to select between the four registers
Bus Transfer
 Sofar we have designed the transfer from register to bus

 The design of the transfer from bus to registers as follows:
Bus Transfer
• Determine the control signals that implement the following RTL statements:
a) R0  R3 b) R1  R2 c) R3  R1 d) R2  R0
Then draw its logic diagram
Memory Transfer
 Memory (RAM) can be thought as a sequential circuits containing some number of registers
 These registers hold the words of memory
 Each of the r words is indicated by an address
 These addresses range from 0 to r-1
 Each word can hold n bits of data
 Assume the RAM size is 2k x 16. It needs the following
 n data input lines (16 bit or 2 byte)
data input lines
 n data output lines (16 bit or 2 byte)
n
 k address lines (11 bit)
 A Read control line address lines
A Write control line k
 RAM
Read
unit
Write
n
data output lines
Memory Transfer
 Designate a memory word by the letter M
 Since memory contains multiple locations, we must specify which address in memory will be used
 Memory is usually accessed in computer systems by putting the desired address in a special
register, the Memory Address Register (MAR, or AR)
 The read operation can be stated as: Read

Memory
AR
 DR ← M[AR] unit Write
 The contents of the AR get sent to the memory address lines

Data out Data in
 A Read =1 sent to the memory unit
 The contents of the specified address are put on the memory’s output data lines
 These data sent over the bus to be loaded into register DR

Memory Transfer
 To write a value from a register to a location in memory looks like this in
register transfer language:
M[MAR]  R1 AR
address Memory Read
unit Write
 This causes the following to occur

Data out Data in
 The contents of the MAR get sent to the memory address lines
 A Write =1sent to the memory unit
 The values in register R1 sent over the bus to the data input lines of the memory
 The values loaded into the specified address in the memory
Memory Transfer
AR
x0C 19
x12 x0E 34
R1 x10 45
100 x12 66
x14 0
x16 13
R1←M[AR] x18 22
RAM
R1 R1
100 66
Example
 Show the block diagram of the hardware that implements the following register
transfer statement:
P: M[AR]  R1, R2  R1
P’T: R1  R2
Thank you

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CC312 Computer Organization

Register Transfer Language

 Modules are registers, counters, arithmetic elements, etc connected via:

▪ Control paths routes on which control signals are moved

 Digital modules are best defined by the registers they contain

 The operations executed on data stored in registers are called microoperations

 A microoperation is an elementary operation performed on the information stored

▪ Examples are shift, count, clear, and load

Single entity Showing individual bits

If (P = 1) then (R1 R2) else If (Q = 1) then (R1R3)

Block diagram: Control P Load

Register Transfer Language

possible other registers

 To completely connect n registers → n(n-1) lines

 This is not a realistic approach to use in a large digital system

 Instead, take a different approach Like BUS

 Have one centralized set of circuits for data transfer

transferred one at a time

 This requires n multiplexers – one for each bit

 The size of each multiplexer must be k x 1

4-Line Common bus

 Sofar we have designed the transfer from register to bus

 The read operation can be stated as: Read

 The contents of the AR get sent to the memory address lines

 These data sent over the bus to be loaded into register DR

 This causes the following to occur

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