Register Transfer Language

and Microoperations
Unit-2
Contents:
1. Register Transfer Language 11. Instruction Cycle
2. Register Transfer 12. Memory-Reference Instructions
3. Bus and Memory Transfers 13. Input-Output and Interrupt
4. Arithmetic Microoperations 14. Stack Organization
5. Logic Microoperations 15. Instruction Formats
6. Shift Microoperations 16. Addressing Modes
7. Arithmetic Logic Shift Unit 17. Data Transfer and Manipulation
8. Instruction codes 18. Program Control
9. Computer Registers 19. Reduced Instruction Set
10. Computer Instructions Computer (RISC)
1. Register Transfer Language
SIMPLE DIGITAL SYSTEMS
 Combinational and sequential circuits can be used to create simple

digital systems.
 These are the low-level building blocks of a digital computer.

 Simple digital systems are frequently characterized in terms of

 the registers they contain, and

 the operations that they perform.

 Typically,
 Operations are performed on the data in the registers.

 Information is passed between registers.

Microoperations(1)
 The operations on the data in registers are called microoperations.

 The functions built into registers are examples of microoperations

 Shift

 Load

 Clear

 Increment

 …
Microoperations (2)
An elementary operation performed (during one clock pulse),
on the information stored in one or more registers.

Registers ALU 1 clock cycle

(R) (f)

R  f(R, R)
f: shift, load, clear, increment, add, subtract, complement, and, or, xor, …
 Organization of a Digital System
The internal organization of a computer is defined as
1. Set of registers and their functions.
2. Microoperations (Set of allowable microoperations provided by the
organization of the computer).
3. Control signals that initiate the sequence of microoperations (to
perform the functions).
Register Transfer Level
 Viewing a computer, or any digital system, in this way is called

the register transfer level.

 This is because we’re focusing on
 The system’s registers

 The data transformations in them, and

 The data transfers between them.

Register Transfer Language
 Rather than specifying a digital system in words, a specific notation is

used called register transfer language.

 For any function of the computer, the register transfer language can

be used to describe the (sequence of) microoperations.

 Register transfer language
 A symbolic language.

 A convenient tool for describing the internal organization of digital computers.

 Can also be used to facilitate the design process of digital systems.

2. Register Transfer
Registers are designated by capital letters, sometimes followed by numbers
(e.g., A, R13, IR)
 Often the names indicate function:
 MAR- memory address register

 PC - program counter
 IR - instruction register

 Registers and their contents can be viewed and represented in various ways.
 A register can be viewed as a single entity:

MAR

 Registers may also be represented showing the bits of data they contain
Register Transfer contd..
• Designation of a register
- a register
- portion of a register
- a bit of a register
• Common ways of drawing the block diagram of a register
Showing individual bits
Register
R1
7 6 5 4 3 2 1 0
15 0
15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields
Register Transfer contd..
 Copying the contents of one register to another is a register transfer.

 A register transfer is indicated as

R2  R1
 In this case the contents of register R1 are copied (loaded) into register R2.

 A simultaneous transfer of all bits from the source R1 to the destination

register R2, during one clock pulse.

 Note that this is a non-destructive; i.e. the contents of R1 are not altered

by copying (loading) them to R2.

Register Transfer contd..
 A register transfer such as

R3  R5

Implies that the digital system has

 The data lines from the source register (R5) to the destination register

(R3).
 Parallel load in the destination register (R3).

 Control lines to perform the action.

Register Transfer contd..
Often actions need to only occur if a certain condition is true
 This is similar to an “if” statement in a programming language.

 In digital systems, this is often done via a control signal, called a

control function.
 If the signal P is 1, the action takes place

 This is represented as:

P: R2  R1

Which means “if P = 1, then load the contents of register R1 into register R2”,
i.e., if (P = 1) then (R2  R1).
Hardware Implementation Of Controlled Transfers
Implementation of controlled transfer
P: R2 R1

Block diagram Control P Load

R2 Clock
Circuit
n
R1

Timing diagram t t+1

Clock

Load
Transfer occurs here

• The same clock controls the circuits that generate the control function and the destination
register.
• Registers are assumed to use positive-edge-triggered flip-flops.
Simultaneous Operations
 If two or more operations are to occur simultaneously, they are separated

with commas.
P: R3  R5,, MAR  IR
 Here, if the control function P = 1, load the contents of R5 into R3, and at

the same time (clock), load the contents of register IR into register MAR.
Basic Symbols For Register Transfers

Symbols Description Examples

Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)

Arrow  Denotes transfer of information R2  R1

Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A  B, B  A
Connecting Registers
 In a digital system with many registers, it is impractical to have data

and control lines to directly allow each register to be loaded with the
contents of every possible other registers.
 To completely connect n registers  n(n-1) lines.
 This is not a realistic approach to use in a large digital system

 Instead, take a different approach

 Have one centralized set of circuits for data transfer .bus

 Have control circuits to select which register is the source, and which is

the destination.
3. Bus and Bus Transfer
Bus is a path(of a group of wires) over which information is transferred,
from any of several sources to any of several destinations.
From a register to bus: BUS  R
Register A Register B Register C Register D

Bus lines

Register A Register B Register C Register D

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

B 1 C 1 D 1 B2 C 2 D 2 B 3 C 3 D 3 B4 C 4 D 4

0 0 0 0
4 x1 4 x1 4 x1 4 x1
MUX MUX MUX MUX

x
select
y

4-line bus
Bus and Memory Transfers
Register A Register B Register C Register D

Bus lines

. Register D Register C Register B Register A

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

D 3 D2 D1 D0 C3 C2 C1 C0 B3 B2 B1 B0 A3 A 2 A 1 A 0

D3 C3 B3 A3 D 2 C2 B 2 A 2 D1 C1 B1 A1 D0 C0 B0 A0

3 2 1 0 3 2 1 0 3 2 1 0
3 2 1 0 S0
S0 S0 S0
MUX3 MUX2 MUX1 MUX0 S1
S1 S1 S1

4-Line Common Bus

Bus and Memory Transfers: Three-State Bus Buffers
 A bus system can be constructed with three-state buffer gates instead

of multiplexers.
 A three-state buffer is a digital circuit that exhibits three states: logic-0,

logic-1, and high-impedance (Hi-Z)

Output Y=A if C=1

High-impedance if C=0

Control input C

Normal input A Output B

Three-State Buffer
Bus and Memory Transfers: Three-State Bus Buffers
cont.

C=1

Buffer
A B A B

C=0

Open Circuit
A B A B
Bus and Memory Transfers: Three-State Bus Buffers
cont.

S1 0
Select Bus line for bit 0
S0 1
2×4 A0
Decoder 2
Enable E
3

B0

C0

Bus line with three-state buffer

(replaces MUX0 in the previous D0

diagram)
Bus Transfer In RTL
 Depending on whether the bus is to be mentioned explicitly or not,

register transfer can be indicated as either

R2 R1
or

BUS R1, R2  BUS

 In the former case the bus is implicit, but in the latter, it is explicitly

indicated
Memory (RAM)
 Memory (RAM) can be thought as a sequential circuits containing some

number of registers
 These registers hold the words of memory

 Each of the r registers is indicated by an address

 These addresses range from 0 to r-1

 Each register (word) can hold n bits of data data input lines

 Assume the RAM contains r = 2k words. It needs the following n

 n data input lines address lines

k
 n data output lines RAM
Read
unit
 k address lines Write
 A Read control line n

 A Write control line data output lines

Bus and Memory Transfers: Memory Transfer
 Memory read : Transfer from memory

 Memory write : Transfer to memory

 Data being read or written is called a memory word (called M).

 It is necessary to specify the address of M when writing /reading

memory.
 This is done by enclosing the address in square brackets following the

letter M.
 Memory Read
 To read a value from a location in memory and load it into a register,

the register transfer language notation looks like this:

R1  M[MAR]]
 This causes the following to occur
 The contents of the MAR get sent to the memory address lines.

 A Read (= 1) gets sent to the memory unit.

 The contents of the specified address are put on the memory’s output data lines.

 These values are sent over the bus to be loaded into register R1.
Memory Write
 To write a value from a register to a location in memory looks like this in

register transfer language:

M[MAR]  R1

 This causes the following to occur

 The contents of the MAR get sent to the memory address lines.

 A Write (= 1) gets sent to the memory unit.

 The values in register R1 get sent over the bus to the data input lines of the memory.

 The values get loaded into the specified address in the memory.
Summary Of R. Transfer Microoperations
A B Transfer content of reg. B into reg. A
AR DR(AD) Transfer content of AD portion of reg. DR into reg. AR
A  constant Transfer a binary constant into reg. A
ABUS  R1, Transfer content of R1 into bus A and, at the same time,
R2 ABUS Transfer content of bus A into R2
AR Address register
DR Data register
M[R] Memory word specified by reg. R
M Equivalent to M[AR]
DR  M Memory read operation: transfers content of memory word
specified by AR into DR
M  DR Memory write operation: transfers content of DR into
memory
word specified by AR
4. Arithmetic Microoperations
 The microoperations most often encountered in digital computers are

classified into four categories:

 Register transfer microoperations

 Arithmetic microoperations (on numeric data stored in the

registers)
 Logic microoperations (bit manipulations on non-numeric data)

 Shift microoperations
Arithmetic Microoperations cont.
 The basic arithmetic microoperations are:

 addition

 subtraction

 increment

 decrement

 shift
 Addition Microoperation:

R3 R1+R2

 Subtraction Microoperation:
1’s complement
R3 R1-R2 (or)

R3 R1+ R2 +1
Arithmetic Microoperations cont
 One’s Complement Microoperation:

R2 R2
 Two’s Complement Microoperation:

R2 R2+1
 Increment Microoperation:

R2 R2+1
 Decrement Microoperation:

R2 R2-1
Summary of Typical Arithmetic Micro-Operations

Operations Description
R3  R1 + R2 Contents of R1 plus R2 transferred to R3
R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R2  R2 Complement the contents of R2
R2  R2+ 1 2's complement the contents of R2 (negate)
R3  R1 + R2+ 1 subtraction
R1  R1 + 1 Increment
R1  R1 - 1 Decrement
Arithmetic Microoperations: Binary Adder

B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1
FA FA FA FA C0

C4 S3 S2 S1 S0

4-bit binary adder (connection of FAs)

. Arithmetic Microoperations: Binary Adder-
Subtractor
B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0
FA FA FA FA

C4 S3 S2 S1 S0

4-bit adder-subtractor
Arithmetic Microoperations : Binary Adder-Subtractor
 For unsigned numbers, this gives A – B if A≥B or the 2’s complement of
(B – A) if A < B.
(example: 3 – 5 = -2= 1110)
 For signed numbers, the result is A – B provided that there is no
overflow. (example : -3 – 5= -8)
1101
1011 +
1000 C3 1, if overflow
=V
C4 0, if no overflow

Overflow detector for signed numbers

Arithmetic Microoperations Binary Incrementer
A3 A2 A1 A0 1

x y x y x y x y

HA HA HA HA

C S C S C S C S

C4 S3 S2 S1 S0

4-bit Binary Incrementer

 Binary Incrementer can also be implemented using a counter.

 A binary decrementer can be implemented by adding 1111 to the desired

register each time.

Arithmetic Microoperations Arithmetic Circuit

 This circuit performs seven distinct arithmetic operations and the basic

component of it is the parallel adder.

 The output of the binary adder is calculated from the following

arithmetic sum:
 D = A + Y + Cin
Arithmetic Microoperations : Arithmetic Circuit cont.
A3 A2 A1 A0
1 0 B 3 B 3 S1 S0 1 0 B 2 B 2 S1 S0 1 0 B 1 B 1 S1 S0 1 0 B 0 B 0 S1 S0

3 2 1 0 S 1 S0 3 2 1 0 S 1 S0 3 2 1 0 S 1 S0 3 2 1 0 S 1 S0

4×1 MUX 4×1 MUX 4×1 MUX

Figure A
4×1 MUX

Y3 X3 Y2 X2 Y1 X1 Y0 X0
C3 C2 C1
FA FA FA FA Cin

Cout D3 D2 D1 D0

4-bit Arithmetic Circuit

Arithmetic Circuit
Cin
S1
S0
A0 X0 C0

4x1
S1
S0
Y0 FAC1
D0
B0 0
MUX
1
2
3
A1 X1 C1

B1
4x1
S1
S0
Y1 FAC2
D1
0
MUX
1
2
3
A2 X2 C2
S1 D2
B2
4x1
S0
0 Y2 FAC3
1
MUX
2
3
A3 X3 C3
4x1
S1 D3
Y3 FAC4
S0
B3 0
MUX
1
2
3 Cout
0 1

S1 S0 Cin Y Output Microoperation

0 0 0 B D=A+B Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 B’ D = A + B’ Subtract with borrow
0 1 1 B’ D = A + B’+ 1 Subtract
1 0 0 0 D=A Transfer A
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A-1 Decrement A
1 1 1 1 D=A Transfer A
 5. Logic Microoperations
 Specify binary operations on the strings of bits in registers
 Logic microoperations are bit-wise operations, i.e., they work on the individual bits of
data.
 useful for bit manipulations on binary data .
 useful for making logical decisions based on the bit value.
 There are,16 different logic functions that can be defined over two binary input

variables

A B F0 F1 F2 … F13 F14 F15

0 0 0 0 0 … 1 1 1
0 1 0 0 0 … 1 1 1
1 0 0 0 1 … 0 1 1
1 1 0 1 0 … 1 0 1

 However, most systems only implement four of these

 AND (), OR (), XOR (), Complement/NOT

 The others can be created from combination of these.

 List of Logic Microoperations
- 16 different logic operations with 2 binary variables.

x 0011 Boolean Micro-

Name
y 0101 Function Operations
0000 F0 = 0 F0 Clear
0001 F1 = xy F  A  B AND
0010 F2 = xy' F  A  B’
0011 F3 = x FA Transfer A
0100 F4 = x'y F  A’ B
0101 F5 = y FB Transfer B
0110 F6 = x  y FAB Exclusive-
OR
0111 F7 = x + y FAB OR
1000 F8 = (x + y)' F  A  B)’ NOR
1001 F9 = (x  y)' F  (A  B)’ Exclusive-
NOR
1010 F10 = y' F  B’
Complement B
1011 F11 = x + y' FAB
1100 F12 = x' F  A’
Complement A
1101 F13 = x' + y F  A’ B
Truth tables for
1 116
1 0functions
F14of  (A
2 variables andFthe
= (xy)'  B)’
corresponding 16NAND
logic micro-operations
1111 F15 = 1 F  all 1's Set to all 1's
 Logic Microoperations

OR Microoperation
Symbol: , +
Gate:

Example: 1001102  10101102 = 11101102

OR
OR

P+Q: R1 R2+R3, R4 R5 R6

ADD
 Logic Microoperations
AND Microoperation
• Symbol: 

• Gate:

• Example: 1001102  10101102 = 00001102

 Logic Microoperations

Complement (NOT) Microoperation

• 
Symbol:

• Gate:

• Example: 10101102 = 01010012

 Logic Microoperations

XOR (Exclusive-OR) Microoperation

• Symbol: 

• Gate:

• Example: 1001102  10101102 = 11100002

Hardware Implementation Of Logic Microoperations
Ai
0
Bi

1
4X1 Fi
MUX
2

3 Select

S1
S0

Function table
S1 S0 Output -operation
0 0 F=AB AND
0 1 F = AB OR
1 0 F=AB XOR
1 1 F = A’ Complement
Applications Of Logic Microoperations
 Logic microoperations can be used to manipulate individual bits or a

portions of a word in a register

 Consider the data in a register A. In another register, B, is bit data that will

be used to modify the contents of A

 Selective-set AA+B
 Selective-complement AAB
 Selective-clear A  A • B’
 Mask (Delete) AA•B
 Clear AAB
 Insert A  (A • B) + C
 Compare AAB
 ...
 Selective Set
 In a selective set operation, the bit pattern in B is used to set certain

bits in A

1100 At

1010 B

1110 At+1 (A  A + B)

 If a bit in B is set to 1, that same position in A gets set to 1, otherwise

that bit in A keeps its previous value

Selective Complement
 In a selective complement operation, the bit pattern in B is used to

complement certain bits in A

1100 At

1010 B

0110 At+1 (A  A  B)

 If a bit in B is set to 1, that same position in A gets complemented

from its original value, otherwise it is unchanged

Selective Clear
 In a selective clear operation, the bit pattern in B is used to clear

certain bits in A.

1100 At

1010 B

0 1 0 0 At+1 (A  A  B’)

 If a bit in B is set to 1, that same position in A gets set to 0, otherwise

it is unchanged.
Mask Operation
 In a mask operation, the bit pattern in B is used to clear certain bits

in A.

1100 At

1010 B

1 0 0 0 At+1 (A  A  B)

 If a bit in B is set to 0, that same position in A gets set to 0,

otherwise it is unchanged.
 Clear Operation
 In a clear operation, if the bits in the same position in A and B are

the same, they are cleared in A, otherwise they are set in A

1100 At

1010 B

0110 At+1 (A  A  B)
Insert Operation
 Step1: mask the desired bits

 Step2: OR them with the desired value

Example: suppose R1 = 0110 1010, and we desire to replace the

leftmost 4 bits (0110) with 1001 then:

 Step1: 0110 1010 A before

0000 1111 B (mask)
0000 1010 A After

Step2: 0000 1010 A before

1001 0000 B (insert)
 R1 = 1001 1010
6. Shift Microoperations
 There are three types of shifts
 Logical shift

 Circular shift

 Arithmetic shift

 What differentiates them is the information that goes into the serial

input.
• A right shift operation

Serial
input

• A left shift operation

Serial
input
 Logical Shift
 In a logical shift the serial input to the shift is a 0.
 A right logical shift operation:

 A left logical shift operation:

 In a Register Transfer Language, the following notation is used

 shl for a logical shift left
 shr for a logical shift right
 Examples:

 R2  shr R2
 R3  shl R3
 Circular Shift
 In a circular shift the serial input is the bit that is shifted out of the other end of the

register.
 A right circular shift operation:

 A left circular shift operation:

 In a RTL, the following notation is used

 cil for a circular shift left
 cir for a circular shift right
 Examples:

 R2  cir R2
 R3  cil R3
 Arithmetic Shift
 An arithmetic shift is meant for signed binary numbers

(integer).
 An arithmetic left shift multiplies a signed number by two.

 An arithmetic right shift divides a signed number by two.

R n-1 R n-2 R1 R0

A right arithmetic shift operation:

sign
bit

A left arithmetic 0
sign shift operation:
bit
Arithmetic Shift
• In a RTL, the following notation is used
– ashl for an arithmetic shift left
– ashr for an arithmetic shift right
– Examples:

» R2  ashr R2

» R3  ashl R3
 Arithmetic Shifts
 Shifts a signed binary number to the left or right

 An arithmetic shift-left multiplies a signed binary number by 2:

ashl (00100): 01000

 An arithmetic shift-right divides the number by 2.

ashr (00100) : 00010

 An overflow may occur in arithmetic shift-left, and occurs when the

sign bit is changed (sign reversal).

Shift Microoperations
 Example: Assume R1=11001110, then:
• Arithmetic shift right once : R1 = 11100111
• Arithmetic shift right twice : R1 = 11110011
• Arithmetic shift left once : R1 = 10011100
• Arithmetic shift left twice : R1 = 00111000
• Logical shift right once : R1 = 01100111
• Logical shift left once : R1 = 10011100
• Circular shift right once : R1 = 01100111
• Circular shift left once : R1 = 10011101
Hardware Implementation Of Shift Microoperations
0 for shift right (down)
Serial Select
input (IR) 1 for shift left (up)

S
MUX H0
0
1
A0

A1 S
MUX H1
0
A2 1

A3
S
MUX H2
0
1

S
MUX H3
0
1

Serial
input (IL)
Arithmetic Logic Shift Unit
S3
S2 Ci
S1
S0

Arithmetic Di
Circuit
Select

C i+1
0 4x1 Fi
1 MUX
2
3
Ei
Logic
Bi
Ai
Circuit
A i-1 shr
A i+1 shl

S3 S2 S1 S0 Cin Operation Function

0 0 0 0 0 F=A Transfer A
0 0 0 0 1 F=A+1 Increment A
0 0 0 1 0 F=A+B Addition
0 0 0 1 1 F=A+B+1 Add with carry
0 0 1 0 0 F = A + B’ Subtract with
borrow
0 0 1 0 1 F = A + B’+ 1 Subtraction
0 0 1 1 0 F=A-1 Decrement A
0 0 1 1 1 F=A TransferA
0 1 0 0 X F=AB AND
0 1 0 1 X F = A B OR
0 1 1 0 X F=AB XOR
0 1 1 1 X F = A’ Complement A
1 0 X X X F = shr A Shift right A into F
1 1 X X X F = shl A Shift left A into F
Basic Computer Organization And Design

• Instruction Codes

• Computer Registers
• Computer Instructions
• Instruction Cycle
• Memory Reference Instructions
• Input-Output and Interrupt
8. Instruction Codes
Instruction Code:

It is a group of bits that instruct the computer to perform a specific

operation.
Opcode Address
Instruction Format
Operation code :

The operation code of an instruction is a group of bits that define such as

add

subtract

multiply

shift

complement.
 The Basic Computer
 The Basic Computer has two components, a processor and memory

 The memory has 4096 words in it

 4096 = 212, so it takes 12 bits to select a word in memory

 Each word is 16 bits long Memory

4096X16
15 12 11 0
Opcode Address Instructions
(program)
Instruction Format

15 0 Operands
Binary operand (data)

Processor register
Fig: Stored program organization (accumulator or AC)
Instruction Format
 A computer instruction is often divided into two parts
 An opcode (Operation Code) that specifies the operation for that instruction
 An address that specifies the registers and/or locations in memory to use for that operation

 In the Basic Computer, since the memory contains 4096 (= 2 12) words, we needs

12 bit to specify which memory address this instruction will use

15 14 12 11 0
Opcode Address
I

Addressing mode Instruction Format

 In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0:

direct addressing, 1: indirect addressing)

 Since the memory words, and hence the instructions, are 16 bits long, that leaves

3 bits for the instruction’s opcode.

10. Basic Computer Instructions
• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation
Basic Computer Instructions
Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
 Instruction Set Completeness
A computer should have a set of instructions so that the user can construct
machine language programs to evaluate any function that is known to be
computable.
Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT
 11. Instruction Cycle
 In Basic Computer, a machine instruction is executed in the

following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect
address
4. Execute the instruction
 After an instruction is executed, the cycle starts again at step 1, for the next

instruction.
 Note: Every different processor has its own (different) instruction cycle .
Fetch and Decode
• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2
T0 S1 Bus

S0
Memory
unit 7
Address
Read
AR 1
LD
PC 2
INR
IR 5
LD Clock
Common bus
Determine The Type Of Instruction
Start
SC  0

AR  PC T0
T1
IR M[AR],PCPC + 1
T2
Decode Opcode in IR(12-14),
AR IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I
T3 T3
T3 T3
Execute Execute AR M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
Register Reference Instructions
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3
r = D7 IT3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
 12. Memory Reference Instructions
Operation
Symbol Decoder Symbolic Description
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
Memory Reference Instructions
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory
Memory Reference Instructions
BSA:
D5T4: M[AR]  PC, AR  AR + 1

D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]

D6T5: DR  DR + 1

D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

Flowchart For Memory Reference Instructions
Memory-reference instruction

AND ADD LDA STA

D T4 D1 T 4 D2T 4 D 3T 4
0
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D0T 5 D1 T 5 D2T 5
AC  AC DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4T 4 D5T 4 D6T 4

PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5T 5 D6T 5

PC  AR DR  DR + 1
SC  0
D6T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
Basic Computer Instructions
Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
13. Input-Output And Interrupt
A Terminal with a keyboard and a Printer
• Input-Output Configuration
Input-output Serial Computer
terminal communication
interface registers and
Receiver flip-flops
Printer interface OUTR FGO

AC

Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

- The terminal sends and receives serial information

- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the computer
Input-Output Instructions

D7IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off
Program-Controlled Input/Output
Program-controlled I/O

- Continuous CPU involvement

I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware
 Interrupt Initiated Input/Output
-Open communication only when some data has to be passed --> interrupt.
-- The I/O interface, instead of the CPU, monitors the I/O device.
- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops momentarily the task
it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.

* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions.

- when cleared, the computer cannot be interrupted.
 Flowchart For Interrupt Cycle
R = Interrupt f/f
Instruction cycle Interrupt cycle
=0 =1
R

Fetch and decode Store return address

instructions in location 0
M[0]  PC

Execute =0
IEN
instructions
=1 Branch to location 1
=1
FGI
PC 1
=0
=1
IEN 0
FGO R0
=0
R 1

- The interrupt cycle is a HW implementation of a branch and save return address

operation.
- At the beginning of the next instruction cycle, the instruction that is read from memory
is in address 1.
- At memory address 1, the programmer must store a branch instruction that sends the
control to an interrupt service routine.
- The instruction that returns the control to the original program is "indirect BUN 0“.
Register Transfer Operations In Interrupt Cycle
Memory
Before interrupt After interrupt cycle
0 0 256
1 0 BUN 1120 PC = 1 0 BUN 1120
Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program

1 BUN 0 1 BUN 0
Register Transfer Statements for Interrupt Cycle
- R F/F  1 if IEN (FGI + FGO)T0T1T2

 T0T1T2 (IEN)(FGI + FGO): R  1

- The fetch and decode phases of the instruction cycle
must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :

RT0: AR  0, TR  PC

RT1: M[AR]  TR, PC  0

 14. A Stack Machine
A Stack machine has a stack as
Processor a part of the processor state
typical operations:
stack Main
push, pop, +, *, ...
Store
Instructions like + implicitly
:
specify the top 2 elements of
the stack as operands.

push c
push b  c pop
 b b  b
a a a a

07/18/2024
Register Stack Organization
Stack
- Very useful feature for nested subroutines, nested interrupt services
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
- Pointer: SP
- Only PUSH and POP operations are applicable stack Address
Register Stack Flags 63

FULL EMPTY

Stack pointer 4
SP C 3
6 bits B 2
A 1
Push, Pop operations 0
DR

PUSH POP
SP  SP + 1 DR  M[SP]
M[SP]  DR SP  SP  1
If (SP = 0) then (FULL  1) If (SP = 0) then (EMPTY  1)
EMPTY  0 FULL  0
Memory Stack Organization
1000
Program
PC (instructions)
Memory with Program, Data,
and Stack Segments Data
AR (operands)

SP 3000
stack
3997
3998
3999
- A portion of memory is used as a stack with a processor 4000
4001
register as a stack pointer. Stack grows
In this direction
- PUSH: SP  SP - 1
M[SP]  DR
- POP: DR  M[SP]
SP  SP + 1

- Most computers do not provide hardware to check stack overflow (full stack) or
underflow (empty stack)  must be done in software
Reverse Polish Notation
• Arithmetic Expressions: A + B
A+B Infix notation
+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation
- The reverse Polish notation is very suitable for stack
manipulation
• Evaluation of Arithmetic Expressions
Any arithmetic expression can be expressed in parenthesis-free
Polish notation, including reverse Polish notation

(3 * 4) + (5 * 6)  34*56*+

6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +
Processor Organization
 In general, most processors are organized in one of 3 ways

Single register (Accumulator) organization

 Basic Computer is a good example.
 Accumulator is the only general purpose register.

General register organization

 Used by most modern computer processors.
 Any of the registers can be used as the source or destination for computer
operations.

Stack organization
 All operations are done using the hardware stack.
 For example, an OR instruction will pop the two top elements from the stack, do a
logical OR on them, and push the result on the stack.
 15. Instruction Format
Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(es) or a processor register(s)
Mode field - determines how the address field is to be interpreted (to get effective
address or the operand)
• The number of address fields in the instruction format depends on the
internal organization of CPU.
• The three most common CPU organizations:
Single accumulator organization:
ADD X /* AC  AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */
Stack organization:
PUSH X /* TOS  M[X] */
ADD
Three, and Two-Address Instructions
• Three-Address Instructions

Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B] */
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */

- Results in short programs

- Instruction becomes long (many bits)

• Two-Address Instructions

Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1  M[A] */

ADD R1, B /* R1  R1 + M[A] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */
One and Zero-Address Instructions
• One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */
• Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS  A */
PUSH B /* TOS  B */
ADD /* TOS  (A + B) */
PUSH C /* TOS  C */
PUSH D /* TOS  D */
ADD /* TOS  (C + D) */
MUL /* TOS  (C + D) * (A + B) */
POP X /* M[X]  TOS */
The End