Unit-1

Register Transfer and Micro Operations:

Bus and Memory Transfer, Logic Micro Operations, Shift Micro Operations,
register transfer language, Register transfer, Arithmetic logic shift unit
Content
 Register

 Shift Register
Register

 Group of flip flop with each F/F capable of storing One bit of information
 ‘n’ bit register – ‘n’ F/F
 Can have additional combinational gates to perform specific tasks
 Transferring of new information into register – Loading
 All the bits of the register are loaded simultaneously with common clock pulse – Parallel
Loading
 4-bit Register with Parallel Load
 Load Input – Determines action to be taken with each
clock pulse
 The clock input receive clock pulses at all times
 The Buffer gate in the clock input will increase “Fan-out”

 Load – 0 (Previous State, No Change )

 Load – 1 (All four input Transfer Loading)

 When the load input is 1, the data in the four inputs are
transferred into the register with the next positive
transition of a clock pulse
 When the load input is 0, the data inputs are inhibited and
the D-output of flip flop are connected to their inputs.
 Shift Register
 Register capable of shifting its Binary information in one or both directions – Shift Register
 Logical Configuration of Shift Register consists of chain of Flip Flops in cascade, with the
output of one flip flop connected to the input of next F/F
 The Serial Input determines what goes into the leftmost position during the shift
 The Serial output is taken from the output of the rightmost flip flop
Bidirectional Shift Register with Parallel Load

 Register capable of shifting in One direction only – Unidirectional Shift Register

 Register that can shift in both direction – Bidirectional Shift Register
 The most general shift register has capabilities:
 An input clock pulse to synchronize all operations
 A shift right/left(Serial output/input)
 Parallel load ‘n’ parallel output lines
 Register unchanged even though clock pulses are applied continuously
 4-Bit bidirectional shift register with parallel load
 SISO
Bidirectional Shift Register with Parallel Load SIPO

… (Universal Shift Register) PISO

PIPO
 4-Bit bidirectional shift register with
parallel load
 4:1 MUX – 4
 D F/F – 4

Mode Operation
S1 S0
0 0 No Change
0 1 Shift Right (Down)
1 0 Shift Left (Up)
1 1 Parallel Load
Content
 Register Transfer Language

 Register Transfer

 Bus and Memory Transfer

 Logic Micro Operations

 Shift Micro Operations

 Arithmetic Logic Shift Unit

Register Transfer Language (RTL)

 Combinational and sequential circuits can be used to create simple digital systems.
 These are the low-level building blocks of a digital computer
 Simple digital systems are frequently characterized in terms of
 the registers they contain, and
 the operations that are performed on data stored in them
 The operations executed on the data in registers – micro-operations e.g. shift, count, clear
and load
Register Transfer Language (RTL) …

 Internal hardware organization of a digital computer:

 Set of registers and their functions

 Sequence of microoperations performed on binary information stored in registers

 Control signals that initiate the sequence of micro-operations (to perform the functions)
Register Transfer Language (RTL) …

 Rather than specifying a digital system in words, a specific notation is used – Register
Transfer Language
 Symbolic notation used to describe the micro-operation transfer among register –
Register Transfer Language
 For any function of the computer, the register transfer language can be used to describe the
(sequence of) micro-operations
 Register Transfer Language
 A symbolic language
 A convenient tool for describing the internal organization of digital computers in concise/precise
manner.
Register Transfer Language (RTL) …

 Registers are designated by capital letters, sometimes followed by numbers (e.g., A, R13,
IR)

 Often the names indicate function:

 MAR – Memory Address Register
 PC – Program Counter
 IR – Instruction Register

 Registers and their contents can be viewed and represented in various ways
 A register can be viewed as a single entity:

MAR
Register Transfer Language (RTL) …

 Individual F/F in ’n’ bit register are numbered in sequence [0(rightmost) to n-1]

 16 bit register – Program Counter

 Common ways of drawing the block diagram of a register

Register R Showing individual bits

R1 7 6 5 4 3 2 1

15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields
Register Transfer

 Information transfer from one register to another is designated in symbolic form by means
of a replacement operator

 In this case the contents of register R1 are copied (loaded) into register R2
 A simultaneous transfer of all bits from the source R1 to the destination register R2, during
one clock pulse
 Note that this is a non-destructive; i.e. the contents of R1 are not altered by copying
(loading) them to R2
Register Transfer …

 A register transfer such as

 Implies that the digital system has

 the data lines from the source register (R5) to the destination register (R3)
 Parallel load in the destination register (R3)
 Control lines to perform the action
Control Function
 Often actions need to only occur if a certain condition is true
 This is similar to an “if” statement in a programming language
 In digital systems, this is often done via a control signal – control function
 If the signal is 1, the action takes place

 This is represented as:

 Which means “if P = 1, then load the contents of register R1 into register R2”, i.e.,
 Hardware Implementation of Controlled
Transfer
Implementation of controlled transfer
P: R2 R1
‘n’ outputs of R1 are connected to ‘n’ inputs of R2

Block diagram Control P Load

R2 Clock
Circuit
n
R1

Timing diagram t t+1

Clock

Load
Transfer occurs here

 The same clock controls the circuits that generate the control function and the
destination register
 Registers are assumed to use positive-edge-triggered flip-flops
 Basic Symbols for Register Transfer

Symbol Description Examples

Letters (and Numerals) Denotes a Register MAR, R2
Parentheses () Denotes a part of a Register R2(0-7), R2(L)
Arrow Denotes transfer of Information R2 R1
Comma Separates two micro-operations R2 R1, R1 R2
Content
 Register Transfer Language

 Register Transfer

 Bus and Memory Transfer

 Logic Micro Operations

 Shift Micro Operations

 Arithmetic Logic Shift Unit

 Connecting Registers - Bus Transfer
 In a digital system with many registers, it is impractical to have data and control lines to directly allow
each register to be loaded with the contents of every possible other registers

 To completely connect ‘n’ registers ‘n(n-1)’ lines

 0(n2) cost
 This is not a realistic approach to use in a large digital system

 Instead, take a different approach

 Have one centralized set of circuits for data transfer – the bus

 BUS STRUCTURE CONSISTS OF SET OF COMMON LINES, ONE FOR EACH BIT OF A
REGISTER THROUGH WHICH BINARY INFORMATION IS TRANSFERRED ONE AT A TIME

 Have control circuits to select which register is the source, and which is the destination
 Common Bus System

 One way of constructing common bus system is with multiplexers

 Multiplexer selects the source register whose binary information is kept on the bus

 Construction of bus system for 4 register (Next Fig)

 4 bit register X 4
 Four 4X1 multiplexer
 Bus selection S0, S1
S1 S0 Register Selected

0 0 A
0 1 B
1 0 C
1 1 D
Common Bus System …

 For a bus system to multiplex ‘k’ registers of ‘n’ bits each

 No. of multiplexer = n = No. of bits
 Size of each multiplexer = k x 1, ‘k’ data lines in each MUX

 Construction of bus system for 8 register with 16 bits

 16 bit register X 8
 Sixteen 8X1 multiplexer
 Bus selection S0, S1, S2
Connecting Registers - Bus Transfer

 Transfer of information from a bus into one of many destination registers can be
accomplished by connecting the bus lines to the inputs of all the destination registers and
activating load control of the particular destination register selected.
Connecting Registers - Bus Transfer
Connecting Registers - Bus Transfer
 Memory – RAM

 Memory (RAM) can be thought as a sequential circuits containing some number of

registers
 Memory stores binary information in groups of bits called words
 These registers hold the words of memory
 Each of the ‘r’ registers is indicated by an address
 These addresses range from 0 to r-1
data input lines
 Each register (word) can hold ‘n’ bits of data
n
 Assume the RAM contains r = 2 words. It needs the following
k
address lines
 ‘n’ data input lines k
RAM
 Read
‘n’ data output lines unit
 Write
‘k’ address lines
n
 A Read control line
data output lines
 A Write control line
Memory Transfer

 Memory is usually accessed in computer systems by putting the desired address in a

special register, the Memory Address Register (MAR, or AR)

M
Memory Read
AR
unit Write

Data out Data in

Memory Transfer

 Memory read: Transfer from memory

 Memory write: Transfer to memory
 Data being read or wrote is called a memory word (called M)
 It is necessary to specify the address of ‘M ‘when writing /reading memory
 This is done by enclosing the address in square brackets following the letter M
 Example: M[0016] : the memory contents at address 0x0016
 Memory Transfer
 Assume that the address of a memory unit is stored in a register called the Address
Register AR
 Lets represent a Data Register with DR, then:
 Read: DR ← M[AR]
 Write: M[AR] ← DR
AR
x0C 19
x12 x0E 34
R1 x10 45
100 x12 66
x14 0
x16 13
R1←M[AR] x18 22

RAM
R1 R1
100 66
 Summary of Register Transfer Microoperations

Symbolic Description
Transfer content of reg. B into reg. A
Transfer a binary constant into reg. A
Transfer content of R1 into bus A and, at the same time,
transfer content of bus A into R2
Address register
Data register
Memory word specified by reg. R
Equivalent to M[AR]
Memory read operation: transfers content of memory word
specified by AR into DR
Memory write operation: transfers content of DR into
memory word specified by AR
Micro-operations

 Computer system microoperations are of four types:

 Register transfer microoperations

 Arithmetic microoperations
 Logic microoperations
 Shift microoperations
Content
 Register Transfer Language

 Register Transfer

 Bus and Memory Transfer

 Arithmetic Micro-operation

 Logic Micro Operations

 Shift Micro Operations

 Arithmetic Logic Shift Unit

 Arithmetic Microoperations
 The basic arithmetic
microoperations are
 Addition
Symbolic Description
 Subtraction
Contents of R1 plus R2 transferred to R3
 Increment
Contents of R1 minus R2 transferred to R3
 Decrement
Complement the contents of R2
2's complement the contents of R2 (negate)
 The additional arithmetic
Subtraction
microoperations are
 Increment
Add with carry
 Decrement
Subtract with borrow
 Transfer/Load
 etc. …
Binary Adder

 4-bit Binary Adder:

 Full adder = 2-bits sum + previous carry
 Binary Adder = arithmetic sum of two binary number of any length
 C0 (Input Carry), C4 (Output Carry)
 
Binary Adder Subtractor Mode input ‘M’ controls the operation
 M=0 (Adder)
 M=1 (Subtractor)
B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0
FA FA FA FA

C4 S3 S2 S1 S0
For unsigned numbers, this gives A – B if A≥B
or the 2’s complement of (B – A) if A < B (example: 3 – 5 = -2= 2’s complement of (110)

For signed numbers, the result is A – B provided that there is no overflow.

(example : -3 – 5= -8)
1011
+ 1101
11000
 Binary Incrementer
A3 A2 A1 A0 1

x y x y x y x y

HA HA HA HA

C S C S C S C S

C4 S3 S2 S1 S0
4-bit Binary Incrementer

Binary Incrementer can also be implemented using a counter

A binary decrementer can be implemented by adding 1111 to the desired register each time!
Arithmetic Circuit

 This circuit performs eight distinct arithmetic operations and the basic component of it is
the parallel adder

 Output of the binary adder is calculated from the following arithmetic sum:
 Arithmetic Circuits S1
S0

A0 X0 C0

S1 D0
S1 S0 Cin I /P O/P Operation S0 FA
(Y) B0 0
4x1
Y0 C1
1
0 0 0 B D=A+B Add 2 MUX
3

0 0 1 B D=A+B+1 Add with carry A1 X1 C1

D=A+B’ Subtract with S1 D1

0 1 0 B’ borrow S0 FA
B1 Y1 C2
0 1 1 B’ D=A+B’+1 Subtract
0
1
4x1
2 MUX
D=A Transfer A 3
1 0 0 0
A2 X2 C2
1 0 1 0 D=A+1 Increment A
S1 D2

1 1 0 1 D=A-1 Decrement A S0 FA
B2 Y2 C3
0
1 4x1
1 1 1 1 D=A Transfer A 2 MUX
3

A3 X3 C3

1011 S1 D3
S0 FA
+ 1111 Y3 C4
B3 0
4x1
1010 1
2 MUX
3 Co

0 1
Content
 Register Transfer Language

 Register Transfer

 Bus and Memory Transfer

 Arithmetic Micro-operation

 Logic Micro Operations

 Shift Micro Operations

 Arithmetic Logic Shift Unit

Logic Operation (OR Microoperation)

 Symbol: , +

 Gate:

 Example: (100110)2 (1010110)2 = (1110110)2

OR OR

Add
Logic Operation (AND Microoperation)

 Symbol:

 Gate:

 Example: (100110)2  (1010110)2 = (0000110)2

Logic Operation (NOT Microoperation)

 Symbol:

 Gate:

 Example:
Logic Operation (XOR Microoperation)

Exclusive – OR

 Symbol: 

 Gate:

 Example: (100110)2  (1010110)2 = (1110000)2

 Hardware Implementation (Logic Micro-
operations)
S1
 The hardware implementation of logic microoperations requires that 4×1
S0
logic gates be inserted for each bit or pair of bits in the registers to MUX
Ai
perform the required logic function
Bi
 Most computers use only four (AND, OR, XOR, and NOT) from 0
which all others can be derived.

1 Ei

S1 S0 Output Operation
2
0 0 E=A B AND
0 1 E=AvB OR
3
1 0 E=AB XOR
1 1 E = A’ Complement
Applications of Logic Microoperations

 Logic micro operations can be used to manipulate individual bits or a portions of a word
in a register. They can be used to change bit values, delete a group of bits, or insert new
bit values into a register.
 Consider the data in a register A. In another register, B, is bit data that will be used to
modify the contents of A

 Selective-set A Av B
 Selective-complement A A B
 Selective-clear A  A • B’
 Mask (Delete) A A• B
 Clear A A B
 Insert A  (A • B) v C
 Compare A A B
Selective-Set Operation (OR)

 In a selective set operation, the bit pattern in B is used to set certain bits in A
1010 At
1100 B (Logic
operand)
1110 A(t+1) (A  A v B)

 If a bit in B is set to 1, that same position in A gets set to 1, otherwise that bit in A keeps its
previous value
Selective-Complement Operation (XOR)

 In a selective-complement operation, the bit pattern in B is used to complement certain

bits in A

1010 At
1100 B (Logic
operand)
0110 A(t+1) (A  A  B)

 If a bit in B is set to 1, that same position in A gets complemented from its original value,
otherwise it is unchanged
Selective-Clear Operation (A.B’)

 In a selective-clear operation, the bit pattern in B is used to clear certain bits in A

1010 At
1100 B (Logic
operand)
0010 A(t+1) (A  A B’)

 If a bit in B is set to 1, that same position in A gets set to 0, otherwise it is unchanged

Mask Operation (A.B)

 In a mask operation, the bit pattern in B is used to clear certain bits in A. It is similar to
selective-clear operation except that the bits of A are cleared only where there are
corresponding 0’s in B

1010 At
1100 B (Logic
operand)
1000 A(t+1) (A  A B)

 If a bit in B is set to 0, that same position in A gets set to 0, otherwise it is unchanged

Clear Operation (A  B)
 In a clear operation, if the bits in the same position in A and B are the same, they are cleared
in A, otherwise they are set in A

1010 At
1100 B (Logic operand)
0110 A(t+1) (A  A  B)

 Insert – First masking then insert using OR

0000 1010 At
0110 1010 At
1001 0000 B (Logic
0000 1111 B (Logic operand)
operand)
0000 1010 A(t+1) (A  A B) 1001 1010 A(t+1) (A  A v B)
Example

 Suppose you wanted to introduce 1010 into the low order four bits of A:
1101 1000 1011 0001 A (Original)
1101 1000 1011 1010 A (Desired)

 Solution
1101 1000 1011 0001 A (Original)
1111 1111 1111 0000 Mask
1101 1000 1011 0000 A (Intermediate)
0000 0000 0000 1010 Added bits
1101 1000 1011 1010 A (Desired)
Content
 Register Transfer Language

 Register Transfer

 Bus and Memory Transfer

 Arithmetic Micro-operation

 Logic Micro Operations

 Shift Micro Operations

 Arithmetic Logic Shift Unit

 Shift Microoperations
 There are three types of shifts
 Logical shift
 Circular shift
 Arithmetic shift
 What differentiates them is the information that goes into the serial input.

Serial Input rn-1 r3 r2 r1 r0 Serial Output

Determines the Shift Right

“shift” type

Serial Output rn-1 r3 r2 r1 r0 Serial Input

Shift Left

**Note that the bit ri is the bit at position (i) of the register
 Logical Shift
 In a logical shift the serial input to the shift is a 0.
 A right logical shift operation:

Serial Input (0) Serial Output

rn-1 r3 r2 r1 r0

Shift Right
 A left logical shift operation:
Serial Output Serial Input (0)
rn-1 r3 r2 r1 r0

Shift Left
 In a Register Transfer Language, the following notation is used
 shl for a logical shift left
 shr for a logical shift right
 Examples:
 R1  shl R1
 R2  shr R2
Circular Shift (Rotate)
• In a circular shift the serial input is the bit that is shifted out of the other
end of the register.

• A right circular shift operation:

• A left circular shift operation:

• In a RTL, the following notation is used

– cil for a circular shift left
– cir for a circular shift right
– Examples:
• R2  cir R2
• R3  cil R3
Arithmetic Shift
 An arithmetic shift is meant for signed binary numbers (integer) left/right
 An arithmetic left shift multiplies a signed number by two
 An arithmetic right shift divides a signed number by two
 Sign bit : 0 for positive and 1 for negative
 The main distinction of an arithmetic shift is that it must keep the sign of the number the
same as it performs the multiplication or division

 A right arithmetic shift operation:

sign
bit

 A left arithmetic shift operation: 0

sign
bit
 Arithmetic Shift
• An left arithmetic shift operation must be checked for the overflow

0
sign
bit

Before the shift, if the leftmost two

V bits differ, the shift will result in an
overflow

• In a RTL, the following notation is used

– ashl for an arithmetic shift left
– ashr for an arithmetic shift right
– Examples:
» R2  ashr R2
» R3  ashl R3

CSE 211
Shift Micro-Operations

Symbolic Designations Description

Shift-left register R
Shift-right register R
Circular shift-left register R
Circular shift-right register R
Arithmetic shift-left register R
Arithmetic shift-right register R
 Hardware Implementation
Serial Input IR Serial Input IL
A0A1 A2 A3

Select
0 for shift right
S 1 0 S 1 0 S 1 0 S 1 0
1 for shift left
MUX MUX MUX MUX

H0 H1 H2 H3

Select Output
S H0 H1 H2 H3
0 IR A0 A1 A2
1 A1 A2 A3 IL
 Arithmetic Logic and Shift Unit
S3
S3 S2 S1 S0 Cin Operation
S2
S1 Ci 0 0 0 0 0 F=A
S0 0 0 0 0 1 F = A+1

0 0 0 1 0 F = A+B
One stage of Di 0 0 0 1 1 F = A+B+1
arithmetic circuit
(Fig.A) F=A+B’
0 0 1 0 0
One stage of Select
0 0 1 0 1 F=A+B’+1
ALU
Fi 0 0 1 1 0 F=A-1
Ci+1 0 4×1 F=A
0 0 1 1 1
1 MUX
0 1 0 0 X F=A
One stage of Ei 2
logic circuit 0 1 0 1 X F=AvB
Bi (Fig.B) 3
Ai
0 1 1 0 X F=AB

0 1 1 1 X F=A’
shr
Ai+1 F=shr A
shl 1 0 X X X
Ai-1
1 1 X X X F=shl A