FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

FAN3100C / FAN3100T
Single 2 A High-Speed, Low-Side Gate Driver

Features Description
 3 A Peak Sink/Source at V DD = 12 V The FAN3100 2 A gate driver is designed to drive an N-
channel enhancement-mode MOSFET in low -side
 4.5 to 18 V Operating Range
sw itching applications by providing high peak current
 2.5 A Sink / 1.8 A Source at V OUT = 6 V pulses during the short sw itching intervals. The driver is
available w ith either TTL (FAN3100T) or CMOS
 Dual-Logic Inputs Allow Configuration as
(FAN3100C) input thresholds. Internal circuitry provides
Non-Inverting or Inverting w ith Enable Function
an under-voltage lockout function by holding the output
 Internal Resistors Turn Driver Off If No Inputs LOW until the supply voltage is w ithin the operating range.
 13 ns Typical Rise Time and 9 ns Typical Fall-Time The FAN3100 delivers fast MOSFET sw itching
w ith 1 nF Load performance, w hich helps maximize efficiency in high-
frequency pow er converter designs.
 Choice of TTL or CMOS Input Thresholds
FAN3100 drivers incorporate MillerDrive™ architecture for
 MillerDrive™ Technology
the final output stage. This bipolar-MOSFET combination
 Typical Propagation Delay Time Under 20 ns w ith provides high peak current during the Miller plateau stage
Input Falling or Rising of the MOSFET turn-on / turn-off process to minimize
sw itching loss, w hile providing rail-to-rail voltage sw ing
 6-Lead, 2x2 mm MLP or 5-Pin, SOT23 Packages
and reverse current capability.
 Rated from –40°C to 125°C Ambient
The FAN3100 also offers dual inputs that can be
configured to operate in non-inverting or inverting mode
Applications and allow implementation of an enable function. If one or
both inputs are left unconnected, internal resistors bias
 Sw itched-Mode Pow er Supplies (SMPS) the inputs such that the output is pulled LOW to hold the
 High-Efficiency MOSFET Sw itching pow er MOSFET off.
 Synchronous Rectifier Circuits The FAN3100 is available in a lead-free finish, 2x2 mm, 6-
 DC-to-DC Converters lead, Molded Leadless Package (MLP) for the smallest
size w ith excellent thermal performance; or industry-
 Motor Control standard, 5-pin, SOT23.

Functional Pin Configurations

VDD 1 5 OUT
IN+ 1 6 IN-

AGND 2 5 PGND GND 2

VDD 3 4 OUT
IN+ 3 4 IN−

© 2007 Semiconductor Components Industries, LLC. Publication Order Number:

December-2017, Rev . 2 FAN3100T/D
 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Figure 1. 6-Lead MLP (Top View ) Figure 2. SOT23-5 (Top View )

Ordering Information

Input
Part Number Package Packing Method Quantity / Reel
Threshold

FAN3100CMPX CMOS 6-Lead, 2x2 mm MLP Tape & Reel 3000

FAN3100CSX CMOS 5-Pin, SOT23 Tape & Reel 3000

FAN3100TMPX TTL 6-Lead, 2x2 mm MLP Tape & Reel 3000

FAN3100TSX TTL 5-Pin, SOT23 Tape & Reel 3000

Package Outlines

VDD 1 5 OUT
IN+ 1 6 IN−

AGND 2 5 PGND GND 2

VDD 3 4 OUT
IN+ 3 4 IN−

Figure 3. 6-Lead MLP (Top View ) Figure 4. SOT23-5 (Top View )

Thermal Characteristics(1)

Package ΘJL(2) ΘJT(3) ΘJA(4) Ψ JB(5) Ψ JT(6) Units

6-Lead, 2x2 mm Molded Leadless Package (MLP) 2.7 133 58 2.8 42 °C/W
SOT23-5 56 99 157 51 5 °C/W
Notes:
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (ΘJL): Thermal resistance betw een the semiconductor junction and the bottom surface of all the leads
(including any thermal pad) that are typically soldered to a PCB.
3. Theta_JT (ΘJT ): Thermal resistance betw een the semiconductor junction and the top surface of the package,
assuming it is held at a uniform temperature by a top-side heatsink.
4. Theta_JA (ΘJA ): Thermal resistance betw een junction and ambient, dependent on the PCB design, heat sinking, and
airflow . The value given is for natural convection w ith no heatsink using a 2SP2 board, as specified in JEDEC
standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.
5. Psi_JB (ΨJB ): Thermal characterization parameter providing correlation betw een semiconductor junction temperature
and an application circuit board reference point for the thermal environment defined in Note 4. For the MLP-6
package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either
end of the package. For the SOT23-5 package, the board reference is defined as the PCB copper adjacent to pin 2.
6. Psi_JT (ΨJT ): Thermal characterization parameter providing correlation betw een the semiconductor junction
temperature and the center of the top of the package for the thermal environment defined in Note 4.

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Pin Definitions

SOT23 MLP
Name Pin Description
Pin # Pin #
1 3 VDD Supply Voltage. Provides pow er to the IC.

2 AGND Analog ground for input signals (MLP only). Connect to PGND underneath the IC.

2 GND Ground (SOT-23 only). Common ground reference for input and output circuits.

3 1 IN+ Non-Inverting Input. Connect to VDD to enable output.

4 6 IN- Inverting Input. Connect to AGND or PGND to enable output.

Gate Drive Output: Held LOW unless required inputs are present and V DD is above UVLO
5 4 OUT
threshold.

Therm al Pad (MLP only). Exposed metal on the bottom of the package, w hich is
Pad P1
electrically connected to pin 5.

Pow er Ground (MLP only). For output drive circuit; separates sw itching noise from
5 PGND
inputs.

Output Logic
IN+ IN− OUT
0(7) 0 0

0(7) 1(7) 0

1 0 1

1 1(7) 0
Note:
7. Default input signal if no external connection is made.

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Block Diagrams

1 VDD

UVLO

100kΩ VDD_OK

IN+ 3
5 OUT
100kΩ
100kΩ

IN- 4

2 GND

Figure 5. Sim plified Block Diagram (SOT23 Pin-out)

3 VDD

UVLO

100kΩ VDD_OK

IN+ 1
4 OUT
100kΩ

100kΩ
IN- 6

AGND 2
5 PGND

0.4Ω

Figure 6. Sim plified Block Diagram (MLP Pin-out)

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

V DD VDD to PGND -0.3 20.0 V

V IN Voltage on IN+ and IN- to GND, AGND, or PGND GND - 0.3 V DD + 0.3 V

V OUT Voltage on OUT to GND, AGND, or PGND GND - 0.3 V DD + 0.3 V

TL Lead Soldering Temperature (10 Seconds) +260 ºC

TJ Junction Temperature -55 +150 ºC

TST G Storage Temperature -65 +150 ºC

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor
does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Unit

V DD Supply Voltage Range 4.5 18.0 V

V IN Input Voltage IN+, IN- 0 V DD V

TA Operating Ambient Temperature -40 +125 ºC

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Electrical Characteristics
Unless otherw ise noted, V DD = 12 V, TJ = -40°C to +125°C. Currents are defined as positive into the device and negative
out of the device.

Symbol Parameter Conditions Min. Typ. Max. Unit

Supply

V DD Operating Range 4.5 18.0 V

(8)
Supply Current FAN3100C 0.20 0.35 mA
IDD
Inputs/EN Not Connected FAN3100T 0.50 0.80 mA

V ON Turn-On Voltage 3.5 3.9 4.3 V

V OFF Turn-Off Voltage 3.3 3.7 4.1 V

Inputs (FAN3100T)

V INL_T IN+, IN- Logic LOW Voltage, Maximum 0.8 V

V INH_T IN+, IN- Logic HIGH Voltage, Minimum 2.0 V

IIN+ Non-inverting Input IN from 0 to V DD -1 175 µA

IIN- Inverting Input IN from 0 to V DD -175 1 µA

V HYS IN+, IN- Logic Hysteresis Voltage 0.2 0.4 0.8 V

Inputs (FAN3100C)

V INL_C IN+, IN- Logic LOW Voltage 30 %V DD

V INH_C IN+, IN- Logic HIGH Voltage 70 %V DD

IINL IN Current, LOW IN from 0 to V DD -1 175 µA

IINH IN Current, HIGH IN from 0 to V DD -175 1 µA

V HYS_C IN+, IN- Logic Hysteresis Voltage 17 %V DD

Output

OUT at V DD/2,
ISINK OUT Current, Mid-Voltage, Sinking(9) 2.5 A
CLOAD = 0.1 µF, f = 1 kHz

OUT at V DD/2,
ISOURCE OUT Current, Mid-Voltage, Sourcing(9) -1.8 A
CLOAD = 0.1 µF, f = 1 kHz

IPK_SINK OUT Current, Peak, Sinking(9) CLOAD = 0.1 µF, f = 1 kHz 3 A

IPK_SOURCE OUT Current, Peak, Sourcing(9) CLOAD = 0.1 µF, f = 1 kHz -3 A

(10)
tRISE Output Rise Time CLOAD = 1000 pF 13 20 ns

tFALL Output Fall Time(10) CLOAD = 1000 pF 9 14 ns

tD1, tD2 Output Prop. Delay, CMOS Inputs (10) 0 – 12 V IN; 1 V/ns Slew Rate 7 15 28 ns
(10)
tD1, tD2 Output Prop. Delay, TTL Inputs 0 – 5 V IN; 1 V/ns Slew Rate 9 16 30 ns

IRVS Output Reverse Current Withstand(9) 500 mA

Notes:
8. Low er supply current due to inactive TTL circuitry.
9. Not tested in production.
10. See Timing Diagrams of Figure 7 and Figure 8.
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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Timing Diagrams

90% 90%
Output Output
10% 10%

VINH
VINH
Input
VINL Input
VINL
tD1 tD2 tD1 tD2

tRISE tFALL tFALL tRISE

Figure 7. Non-Inverting Figure 8. Inverting

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.

Figure 9. IDD (Static) vs. Supply Voltage Figure 10. IDD (Static) vs. Supply Voltage

Figure 11. IDD (No-Load) vs. Frequency Figure 12. IDD (No-Load) vs. Frequency

Figure 13. IDD (1 nF Load) vs. Frequency Figure 14. IDD (1 nF Load) vs. Frequency

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.

Figure 15. IDD (Static) vs. Tem perature Figure 16. IDD (Static) vs. Tem perature

Figure 17. Input Thresholds vs. Supply Voltage Figure 18. Input Thresholds vs. Supply Voltage

Figure 19. Input Thresholds % vs. Supply Voltage

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.

Figure 20. CMOS Input Thresholds vs. Tem perature Figure 21. TTL Input Thresholds vs. Tem perature

Figure 22. UVLO Thresholds vs. Tem perature Figure 23. UVLO Hysteresis vs. Tem perature

Figure 24. Propagation Delay vs. Supply Voltage Figure 25. Propagation Delay vs. Supply Voltage

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.

Figure 26. Propagation Delay vs. Supply Voltage Figure 27. Propagation Delay vs. Supply Voltage

Figure 28. Propagation Delay vs. Tem perature Figure 29. Propagation Delay vs. Tem perature

Figure 30. Propagation Delay vs. Tem perature Figure 31. Propagation Delay vs. Tem perature

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.

Figure 32. Fall Tim e vs. Supply Voltage Figure 33. Rise Tim e vs. Supply Voltage

Figure 34. Rise and Fall Tim e vs. Tem perature

Figure 35. Rise / Fall Waveform s w ith 1 nF Load Figure 36. Rise / Fall Waveform s w ith 10 nF Load

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.

Figure 37. Quasi-Static Source Current w ith V DD=12 V Figure 38. Quasi-Static Sink Current w ith V DD=12 V

Figure 39. Quasi-Static Source Current w ith V DD=8 V Figure 40. Quasi-Static Sink Current w ith V DD=8 V
VDD

4.7µF 470µF
ceramic Al. El.

Current Probe
LECROY AP015

IOUT
IN 1µF CLOAD
1kHz ceramic VOUT
0.1µF

Figure 41. Quasi-Static IOUT / V OUT Test Circuit

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Applications Information
the Miller plateau is not present. This situation often
Input Thresholds occurs in synchronous rectifier applications because the
The FAN3100 offers TTL or CMOS input thresholds. In the body diode is generally conducting before the MOSFET is
FAN3100T, the input thresholds meet industry-standard sw itched on.
TTL logic thresholds, independent of the V DD voltage, and The output pin slew rate is determined by V DD voltage and
there is a hysteresis voltage of approximately 0.4 V. the load on the output. It is not user adjustable, but if a
These levels permit the inputs to be driven from a range of slow er rise or fall time at the MOSFET gate is needed, a
input logic signal levels for w hich a voltage over 2 V is series resistor can be added.
considered logic HIGH. The driving signal for the TTL
VDD
inputs should have fast rising and falling edges w ith a
slew rate of 6 V/µs or faster, so the rise time from 0 to
3.3 V should be 550 ns or less. With reduced slew rate,
circuit noise could cause the driver input voltage to
exceed the hysteresis voltage and retrigger the driver
input, causing erratic operation. Input
stage VOUT
In the FAN3100C, the logic input thresholds are dependent
on the V DD level and, w ith V DD of 12 V, the logic rising
edge threshold is approximately 55% of V DD and the input
falling edge threshold is approximately 38% of V DD. The
CMOS input configuration offers a hysteresis voltage of
approximately 17% of V DD. The CMOS inputs can be used
w ith relatively slow edges (approaching DC) if good Figure 42. MillerDrive™ Output Architecture
decoupling and bypass techniques are incorporated in the Under-Voltage Lockout
system design to prevent noise from violating the input The FAN3100 start-up logic is optimized to drive ground
voltage hysteresis w indow . This allow s setting precise referenced N-channel MOSFETs w ith a under-voltage
timing intervals by fitting an R-C circuit betw een the lockout (UVLO) function to ensure that the IC starts up in
controlling signal and the IN pin of the driver. The slow an orderly fashion. When V DD is rising, yet below the
rising edge at the IN pin of the driver introduces a delay 3.9 V operational level, this circuit holds the output LOW,
betw een the controlling signal and the OUT pin of the regardless of the status of the input pins. After the part is
driver. active, the supply voltage must drop 0.2 V before the part
shuts dow n. This hysteresis helps prevent chatter w hen
Static Supply Current low V DD supply voltages have noise from the pow er
In the IDD (static) typical performance graphs (Figure 9 - sw itching. This configuration is not suitable for driving
Figure 10 and Figure 15 - Figure 16), the curve is high-side P-channel MOSFETs because the low output
produced w ith all inputs floating (OUT is LOW) and voltage of the driver w ould turn the P-channel MOSFET on
indicates the low est static IDD current for the tested w ith V DD below 3.9 V.
configuration. For other states, additional current flow s
through the 100 kΩ resistors on the inputs and outputs VDD Bypass Capacitor Guidelines
show n in the block diagrams (see Figure 5 - Figure 6). In To enable this IC to turn a pow er device on quickly, a
these cases, the actual static IDD current is the value local, high-frequency, bypass capacitor CBYP w ith low
obtained from the curves plus this additional current. ESR and ESL should be connected betw een the VDD and
GND pins w ith minimal trace length. This capacitor is in
MillerDrive™ Gate Drive Technology addition to bulk electrolytic capacitance of 10µF to 47µF
FAN3100 drivers incorporate the MillerDrive™ often found on driver and controller bias circuits.
architecture show n in Figure 42 for the output stage, a A typical criterion for choosing the value of CBYP is to
combination of bipolar and MOS devices capable of keep the ripple voltage on the V DD supply ≤5%. Often this
providing large currents over a w ide range of supply is achieved w ith a value ≥ 20 times the equivalent load
voltage and temperature variations. The bipolar devices capacitance CEQV , defined here as Qgate/V DD. Ceramic
carry the bulk of the current as OUT sw ings betw een 1/3 capacitors of 0.1µF to 1µF or larger are common choices,
to 2/3 V DD and the MOS devices pull the output to the high as are dielectrics, such as X5R and X7R, w hich have
or low rail. good temperature characteristics and high pulse current
The purpose of the MillerDrive™ architecture is to speed capability.
up sw itching by providing the highest current during the If circuit noise affects normal operation, the value of CBYP
Miller plateau region w hen the gate-drain capacitance of may be increased to 50-100 times the CEQV , or CBYP may
the MOSFET is being charged or discharged as part of the be split into tw o capacitors. One should be a larger value,
turn-on / turn-off process. based on equivalent load capacitance, and the other a
For applications that have zero voltage sw itching during smaller value, such as 1-10 nF, mounted closest to the
the MOSFET turn-on or turn-off interval, the driver VDD and GND pins to carry the higher-frequency
supplies high peak current for fast sw itching even though components of the current pulses.
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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Layout and Connection Guidelines Figure 44 show s the current path w hen the gate driver
turns the MOSFET off. Ideally, the driver shunts the
The FAN3100 incorporates fast-reacting input circuits, current directly to the source of the MOSFET in a small
short propagation delays, and pow erful output stages circuit loop. For fast turn-off times, the resistance and
capable of delivering current peaks over 2 A to facilitate inductance in this path should be minimized.
voltage transition times from under 10 ns to over 100 ns.
VDD VDS
The follow ing layout and connection guidelines are
strongly recommended:
CBYP
 Keep high-current output and pow er ground paths FAN3100
separate from logic input signals and signal ground
paths. This is especially critical w hen dealing w ith
TTL-level logic thresholds. PWM
 Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve high-speed Figure 44. Current Path for MOSFET Turn-Off
sw itching, w hile reducing the loop area that can Truth Table of Logic Operation
radiate EMI to the driver inputs and other surrounding The truth table indicates the operational states using the
circuitry. dual-input configuration. In a non-inverting driver
 The FAN3100 is available in tw o packages w ith configuration, the IN- pin should be a logic LOW signal. If
slightly different pinouts, offering similar the IN- pin is connected to logic HIGH, a disable function is
performance. In the 6-pin MLP package, Pin 2 is realized, and the driver output remains LOW regardless of
internally connected to the input analog ground and the state of the IN+ pin.
should be connected to pow er ground, Pin 5, through
a short direct path underneath the IC. In the 5-pin IN+ IN- OUT
SOT23, the internal analog and pow er ground 0 0 0
connections are made through separate, individual 0 1 0
bond w ires to Pin 2, w hich should be used as the
1 0 1
common ground point for pow er and control signals.
1 1 0
 Many high-speed pow er circuits can be susceptible
to noise injected from their ow n output or other In the non-inverting driver configuration in Figure 45, the
external sources, possibly causing output re- IN- pin is tied to ground and the input signal (PWM) is
triggering. These effects can be especially obvious if applied to IN+ pin. The IN- pin can be connected to logic
the circuit is tested in breadboard or non-optimal HIGH to disable the driver and the output remains LOW,
circuit layouts w ith long input, enable, or output regardless of the state of the IN+ pin.
leads. For best results, make connections to all pins VDD
as short and direct as possible.
 The turn-on and turn-off current paths should be IN+
minimized as discussed in the follow ing sections. PWM
OUT
FAN3100
IN-
Figure 43 show s the pulsed gate drive current path w hen
the gate driver is supplying gate charge to turn the GND
MOSFET on. The current is supplied from the local bypass
capacitor, CBYP , and flow s through the driver to the
MOSFET gate and to ground. To reach the high peak Figure 45. Dual-Input Driver Enabled,
currents possible, the resistance and inductance in the Non-Inverting Configuration
path should be minimized. The localized CBYP acts to In the inverting driver application show n in Figure 46, the
contain the high peak current pulses w ithin this driver- IN+ pin is tied HIGH. Pulling the IN+ pin to GND forces the
MOSFET circuit, preventing them from disturbing the output LOW, regardless of the state of the IN- pin.
sensitive analog circuitry in the PWM controller. VDD

VDD VDS

CBYP IN+ OUT

FAN3100
PWM
FAN3100 IN-
GND
PWM
Figure 46. Dual-Input Driver Enabled,
Inverting Configuration
Figure 43. Current Path for MOSFET Turn-On
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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Operational Waveforms source voltage, V GS , w ith gate charge, QG, at
At pow er up, the driver output remains LOW until the V DD sw itching frequency, f SW , is determined by:
voltage reaches the turn-on threshold. The magnitude of PGAT E = QG • V GS • f SW (2)
the OUT pulses rises w ith V DD until steady-state V DD is Dynamic Pre-drive / Shoot-through Current: A pow er
reached. The non-inverting operation illustrated in Figure loss resulting from internal current consumption
47 show s that the output remains LOW until the UVLO under dynamic operating conditions, including pin
threshold is reached, then the output is in-phase w ith the pull-up / pull-dow n resistors, can be obtained using
input. the IDD (no-Load) vs. Frequency graphs in Typical
VDD
Performance Characteristics to determine the current
Turn-on Threshold IDYNAMIC draw n from V DD under actual operating
conditions:
IN-
PDYNAMIC = IDYNAMIC • V DD (3)
Once the pow er dissipated in the driver is determined, the
driver junction rise w ith respect to circuit board can be
IN+
evaluated using the follow ing thermal equation, assuming
ψ JB w as determined for a similar thermal design (heat
sinking and air flow ):
TJ = PT OT AL • ψ JB + TB (4)
OUT
w here:
TJ = driver junction temperature
Figure 47. Non-Inverting Start-Up Waveform s ψ JB = (psi) thermal characterization parameter
For the inverting configuration of Figure 46, start-up relating temperature rise to total pow er
w aveforms are show n in Figure 48. With IN+ tied to VDD dissipation
and the input signal applied to IN–, the OUT pulses are TB = board temperature in location defined in the
inverted w ith respect to the input. At pow er up, the Thermal Characteristics table.
inverted output remains LOW until the V DD voltage
In a typical forw ard converter application w ith 48 V input,
reaches the turn-on threshold, then it follow s the input
as show n in Figure 49, the FDS2672 w ould be a potential
w ith inverted phase.
MOSFET selection. The typical gate charge w ould be
VDD
Turn-on Threshold
32 nC w ith V GS = V DD = 10 V. Using a TTL input driver at a
sw itching frequency of 500 kHz, the total pow er
dissipation can be calculated as:
IN- PGAT E = 32 nC • 10 V • 500 kHz = 0.160 W (5)
PDYNAMIC = 8 mA • 10 V = 0.080 W (6)
PT OT AL = 0.24 W (7)
IN+
(VDD)
The 5-pin SOT23 has a junction-to-lead thermal
characterization parameter ψ JB = 51°C/W.
In a system application, the localized temperature around
OUT the device is a function of the layout and construction of
the PCB along w ith airflow across the surfaces. To
Figure 48. Inverting Start-Up Waveform s ensure reliable operation, the maximum junction
temperature of the device must be prevented from
Thermal Guidelines exceeding the maximum rating of 150°C; w ith 80%
Gate drivers used to sw itch MOSFETs and IGBTs at high derating, TJ w ould be limited to 120°C. Rearranging
frequencies can dissipate significant amounts of pow er. It Equation 4 determines the board temperature required to
is important to determine the driver pow er dissipation and maintain the junction temperature below 120°C:
the resulting junction temperature in the application to
TB,MAX = TJ - PT OT AL • ψ JB (8)
ensure that the part is operating w ithin acceptable
TB,MAX = 120°C – 0.24W • 51°C/W = 108°C (9)
temperature limits.
For comparison purposes, replace the 5-pin SOT23 used
The total pow er dissipation in a gate driver is the sum of in the previous example w ith the 6-pin MLP package w ith
tw o components; PGAT E and PDYNAMIC: ψ JB = 2.8°C/W. The 6-pin MLP package can operate at a
PT OT AL = PGAT E + PDYNAMIC (1) PCB temperature of 119°C, w hile maintaining the junction
Gate Driving Loss: The most significant pow er loss temperature below 120°C. This illustrates that the
results from supplying gate current (charge per unit physically smaller MLP package w ith thermal pad offers a
time) to sw itch the load MOSFET on and off at the more conductive path to remove the heat from the driver.
sw itching frequency. The pow er dissipation that Consider the tradeoffs betw een reducing overall circuit
results from driving a MOSFET at a specified gate- size w ith junction temperature reduction for increased
reliability.
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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Application Diagrams
VIN
ENABLE
Active LOW
FAN3100
IN+ IN-
PWM 1 6
AGND PGND
2 5
OUT
VDD 3 4

Figure 49. Forw ard Converter, Prim ary-Side Gate Drive (MLP Package Show n)

VIN Q1
T2
T1

D1
VDD VSEC
D2
FAN3100
Q2
PWM CC

0.1µF

Figure 50. Driver for Tw o-Transistor Forw ard Converter Gate Transform er

VIN
Q1

T1 L VOUT

D1 VSEC Q5
PWM
Control/ D2
Isolation Q3

SR Q2

VDRV

ISOLATION

FAN3100

Figure 51. Secondary Synchronous Rectifier Driver

VDD
R FAN3100C

IN
C OUT

Delay
IN

OUT

Figure 52. Program m able Delay Using CMOS Input

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Table 1. Related Products

Gate
Part Input
Type Drive (11) Logic Package
Num ber Threshold
(Sink/Src)

Single
FAN3100C +2.5 A / -1.8A CMOS Single Channel of Tw o-Input/One-Output SOT23-5, MLP6
2A

Single
FAN3100T +2.5 A / -1.8A TTL Single Channel of Tw o-Input/One-Output SOT23-5, MLP6
2A

+2.4 A / -
FAN3226C Dual 2 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8
1.6 A

+2.4 A / -
FAN3226T Dual 2 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8
1.6 A

+2.4 A / -
FAN3227C Dual 2 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8
1.6 A

+2.4 A / -
FAN3227T Dual 2 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8
1.6 A

+2.4 A / -
FAN3228C Dual 2 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8
1.6 A

+2.4 A / -
FAN3228T Dual 2 A TTL Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8
1.6 A

+2.4 A / -
FAN3229C Dual 2 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8
1.6 A

+2.4 A / -
FAN3229T Dual 2 A TTL Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8
1.6 A

+4.3 A / -
FAN3223C Dual 4 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8
2.8 A

+4.3 A / -
FAN3223T Dual 4 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8
2.8 A

+4.3 A / -
FAN3224C Dual 4 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8
2.8 A

+4.3 A / -
FAN3224T Dual 4 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8
2.8 A

+4.3 A / -
FAN3225C Dual 4 A CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8
2.8 A

+4.3 A / -
FAN3225T Dual 4 A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8
2.8 A

Note:
11. Typical currents w ith OUT at 6 V and V DD = 12 V.

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Physical Dimensions

0.05 C 2.0 A 1.72

2X B 1.68
6 4
0.15

2.0 0.90 1.21

2.25
0.52(6X)
0.05 C 1 3
PIN#1 IDENT TOP VIEW 2X
0.65 0.42(6X)

RECOMMENDED
LAND PATTERN
0.75±0.05
0.10 C
0.20±0.05

0.08 C NOTES:
0.025±0.025 SIDE VIEW C A. PACKAGE DOES NOT FULLY CONFORM
SEATING TO JEDEC MO-229 REGISTRATION
PLANE
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
2.00±0.05 ASME Y14.5M, 2009.
1.40±0.05 D. LAND PATTERN RECOMMENDATION IS
(0.70) EXISTING INDUSTRY LAND PATTERN.
PIN #1 IDENT (0.20)4X
E. DRAWING FILENAME: MKT-MLP06Krev5.
1 3
0.32±0.05 (0.40)
(6X)

0.80±0.05

(0.60)
6 4
0.65 0.30±0.05 (6X)
0.10 C A B
1.30
0.05 C

BOTTOM VIEW

Figure 53. 2x2 m m , 6-Lead, Molded Leadless Package (MLP)

Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change
in any manner without notice. Please note the revision and/or date on the drawing and contact an ON Semiconductor
representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON
Semiconductor’s worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor
products.

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Physical Dimensions
SYMM
CL
3.00 A 0.95 0.95
2.80

5 4
B

3.00
2.60
1.70
1.50
2.60

1 2 3

(0.30)
0.50 1.00
0.95 0.30
0.20 C A B
1.90
0.70

TOP VIEW LAND PATTERN RECOMMENDATION

SEE DETAIL A

1.30
0.90 1.45 MAX

0.15
0.05 C 0.22
0.08
0.10 C

NOTES: UNLESS OTHEWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MO-178, ISSUE B, VARIATION AA,
GAGE PLANE B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) MA05Brev5
0.25

8°
0°

0.55
0.35
SEATING PLANE
0.60 REF

Figure 54. 5-Lead SOT-23

Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change
in any manner without notice. Please note the revision and/or date on the drawing and contact an ON Semiconductor
representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON
Semiconductor’s worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor
products.

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 FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
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