5 DTM

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
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(ISO/IEC - 27001 - 2013 Certified)
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WINTER – 19EXAMINATION
Subject Name: Digital Techniques and Microprocessor Model Answer Subject Code: 22323
Important Instructions to examiners:
1) The answers should be examined by key words and not as word-to-word as given in themodel answer
scheme.
2) The model answer and the answer written by candidate may vary but the examiner may tryto assess the
understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given moreImportance (Not applicable
for subject English and Communication Skills.
4) While assessing figures, examiner may give credit for principal components indicated in thefigure. The figures
drawn by candidate and model answer may vary. The examiner may give credit for anyequivalent figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the assumed constantvalues may vary
and there may be some difference in the candidate’s answers and model answer.
6) In case of some questions credit may be given by judgement on part of examiner of relevant answer based on
candidate’s understanding.
7) For programming language papers, credit may be given to any other program based on equivalent concept.
Q. Sub Answer Marking

No. Q. N. Scheme
10-Total
Q.1 Attempt any FIVE of the following:
Marks
a) List one application of each of following 2M
(i) Gray code
(ii) ASCII code
Ans: (i) Gray codes are used for error correction in digital communication system. 1M
(ii)ASCII codes are used for identifying characters and numerals in a keyboard. Each
b) State the principle of multiplexer and mention its two types. 2M
Ans: Principle of multiplexer 1M

Multiplexer is a circuit with many inputs and only one output. By applying control signals on
select lines we can direct any input to the output. 1M
Types 4:1,16:1 etc
c) Draw the circuit of one bit memory cell. 2M
Ans: Circuit : 2M
d) List features of 8086 microprpcessor.(Any four) 2M
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Ans: (Note: Consider any 4) 2M
Features of 8086 microprpcessor
1)It requires +5v power supply.
2)It has 20 bit address bus,can acceess 220 =1MB memory location.
3)16 bit data bus.
4)It is a 16 bit processor having 16 bit ALU,16 bit registers.
5)It has instruction queue which is capable of storing 6 instruction bytes from the memory
for faster processing.
6)It has pipelining,fetch and execute stagefor improving performance.
7)It has 256 vectored interrupts.
8)Clock range is 5-10 MHz.
e) Convert the following numbers into Hexadecimal number. 2M
(i) (10110111)2 = (?)16
(ii) (567)8 = (?)16
Ans: (i) (10110111)2 =(B7)16 2M
(ii) (567)8 =(177)16
f) State four characteristics of RISC processor. 2M
Ans: 1)Reduced instruction set. 2M
2)Simple addressing mode.
3)RISC processor consumes less power and has high performance.
4)Instruction is of uniform fixed length.
5)Large number of registers.
g) Give example of any two types of addressing mode of 8086 2M
Ans: 1)Direct addressing mode
Eg:MOV CL,[1234]
2)Immediate addressing mode
Eg:MOV AX,0005H Any two
3)Register addressing mode 1M each
Eg: MOV AX,BX
4)Base indexed addressing mode
Eg:MOV CL,[BX+SI]
Attempt any THREE of the following: 12-Total

Q.2
Marks
a) Perform the following subtaction using 1’s compliment and 2’s compliment (1010 0101)2
4M
– (1110 1110)2.
Ans: Subtaction using 1‟s compliment

(1010 0101)2 – (1110 1110)2.
Find 1‟s complement of the subtrahend 00010001
Add minuend 00010001 +
10100101
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10110110
Since carry is 0,the resullt is –ve and in 1‟s complement form.
The answer is -01001001
Subtaction using 2‟s compliment
Find 1‟s complement of the subtrahend 00010001+1=00010010+
Add minuend 10100101
10110111
Since there is no carry,answer is –ve and is in its 2‟s complement form.
The answer is -01001001
Simplify the given equation into standard SOP form Y = AB +A ̅ + BC and represent
b) 4M
the same equation in standard POS form.
Ans:
2M
2M
c) Differentiate between D FF and T FF. 4M
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Ans: 4M
Input is transferred after a delay When T=1, output toggles
Used in shift registers Used in counters, frequency dividers
D Qn+1 T Qn+1
0 0 0 Qn
1 1 1 ̅̅̅̅
d) Describe the characteristics of digital IC’s (Any four). 4M
Ans: Characteristics of digital IC‟s are 1M

1)Fan out:It is the number of loads that the output of the gate can drive. each
2)Power dissipation:Power consumed by the gate when fully driven by all its inputs.
3)Propagation delay:Time for the signal to propagate from input to output.\
4)Noise margin:The maximum noise voltage added to an input signal that does not cause
undesirable change in output.
Fan in:It is the number of inputs connected to the gate without any degradation in the voltage
level.
Operating Temperature:It is the range of temperature in which the performance of IC is
effective.
Figure of merit:It is the product of speed and power.
12-Total
Q.3 Attempt any THREE of the following:
Marks
Reduce the following Boolean expression using laws of Boolean algebra and realize
a) using logic gates. 4M
Y = (A + BC) (B + ̅ A)
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2M
Ans:
2M
Write an assembly language program to transfer block of 10 numbers from one memory
b) location to another. 4M
(Assume suitable data.)
Ans: .model small 4M
.data
src_arr dw 1,2,3,4,5,6,7,8,9,10
dst_arr dw 10(dup) ;empty array
.code
mov ax,@data ;initialize data
mov ds, ax
mov cx,10 ; initialize counter
mov si,offset src_arr ;initialize memory pointer for source
mov di,offset dst_arr ;initialize memory pointer for destination
up:
mov ax,[si] ;read number from source array
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mov [di] , ax ;write number to destination array
add si,2 ;increment source memory pointer
add di,2 ;increment destination memory pointer
loop up ;check word counter for zero ,if not zero then read up number from
array
ends
end
For the given circuit, identify the inputs and outputs. Name the circuit and draw its
truth table. Refer Fig .No. 1.
c) 4M
Ans: 4M
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Simplify the given K-map using standard form and realize the circuit using gates. Ƒ
Refer Fig. No. 2.
d) 4M
Ans: 2M
2M
Q.4 Attempt any THREE of the following : 12-Total

Marks
a) Write an assembly language program to find the sum of series of ten numbers 4M
stored in memory.(Assume suitable data.)
Ans: Sum Of Series: 4M
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b) Minimize the four variable logic function using K- map. 4M
Ƒ(A,B,C,D) Ʃm (0, 1, 2, 3, 5, 7, 8, 9, 11, 14)

Ans: 4M
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c) Differentiate between sequential and combinational logic circuits. (Any four points) 4M
Ans: 4M
d) Describe the use of flag register and segment registers in 8086. 4M
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Ans:  Use of Flag Register: Microprocessor 8086 has 16 bit flag register among which 9 bits 2M
are active. The purpose of flag register is to indicate the status of the processor
Depending upon the value of result after any arithmetic and logical operation the flag
bits become set (1) or reset (0).
1. Carry Flag (CF): Set 1 if there is carry out of MSB position.
2. Auxiliary Flag (AF): Set 1 if carry from lower nibble to upper nibble.
3. Parity Flag (PF): Set 1 if operation contains even number.
4. Zero Flag (ZF): Set 1 if result of arithmetic or logical operation is zero.
5. Sign Flag (SF): Set 1 if result of operation is negative.
6. Overflow Flag (OF): Set 1 if result is too large to fit in the numbers bits available to
accommodate it.
7. Control Flags:
(i) Trap Flag (TF): Set 1 if program can be run in single step.
(ii) Interrupt Flag (IF): Set 1 if INTR of 8086 is enabled.
(iii) Direction Flag (DF): Set 1 if string bytes are write or read from higher memory
address to lower memory address.
 Use of Segment Register: The 8086 has four segment register of 16 bit each. i.e. 2M
CS,DS,SS and ES. The code segment CS register used to address a memory location
in the code segment of memory. The data segment point to data segment of memory
where the data is stored the extra segment ES used to address the segment is
additional data segment. The Stack segment SS register is used to point location in
stack segment of the memory, used to store data temporarily on the stack.
e) Describe the construction of half adder using K – map. 4M
Ans: Half Adder using k-map: 2M
Half adder is a combinational logic circuit with two inputs and two output , circuit has two
outputs namely “carry” and “sum”, and two inputs A and B.
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2M
Q.5 Attempt any TWO of the following 12-Total

Marks
Write an assembly language program to find the factorial of a number using looping
(a) 6M
process.
Ans: DATA SEGMENT 6M

A DW0005H
FACT_LSBDW?
FACT_MSBDW?
DATA ENDS
CODE SEGMENT
ASSUME DS:DATA,CS:CODE
START:MOVAX,DATA
MOV DS,AX
CALL FACTORIAL
MOVAH,4CH
INT 21H
FACTORIAL PROC
MOV AX,A
MOV BX,AX
DEC BX
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UP: MUL BX ; MULTIPLY AX*BX
MOV FACT_LSB,AX ; ANS DX:AX PAIR
MOV FACT_MSB,DX
DEC BX
CMP BX,0
JNZ UP
RET
FACTORIAL ENDP
OR
DATA SEGMENT
NUM DB 05H
RES DW ?
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START:
MOVAX,DATA
MOV DS,AX
CALL FAC
MOV RES,AX
MOVAH,4CH
INT 21H
FAC PROC
MOVCL,NUM
DEC CL
MOV AL,NUM
MOVAH,00H
MOV BL,CL
MOV BH,00H
L1: MUL BX
DEC BX
DEC CL
JNZ L1
RET
FAC ENDP
CODE ENDS
END START
Correct Program with any other logic can be given marks.
Describe the principle of working of JK FF and draw its circuit diagram and truth
(b) 6M
table.
Ans: The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry
that prevents the illegal or invalid output condition that can occur when both inputs S and R
are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four
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possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a
JK flip flop is similar to that of an SR Bistable Latch as seen in the previous tutorial except
for the addition of a clock input.
The Basic JK Flip-flop
2M
Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs
called the J and K inputs. Then this equates to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and Q. This
cross coupling of the SR flip-flop allows the previously invalid condition of S = “1” and R =
“1” state to be used to produce a “toggle action” as the two inputs are now interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the
lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” status
of Q through the upper NAND gate. As Q and Q are always different we can use them to
control the input. When both inputs J and K are equal to logic “1”, the JK flip flop toggles as
shown in the following truth table.
The Truth Table for the JK Function
CLK J K Qn+1 Qn+1 Description
2M
1,0,↑ X X Qn Qn No Change
↓ 0 0 Qn Qn No Change
↓ 0 1 0 1 Reset Condition
↓ 1 0 1 0 set Condition
↓ 1 1 Q n Q n Toggle condition
Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of its
two input terminals, either SET or RESET to be active at any one time thereby eliminating
the invalid condition seen previously in the SR flip flop circuit.
2M
Also when both the J and the K inputs are at logic level “1” at the same time, and the clock
input is pulsed “HIGH”, the circuit will “toggle” from its SET state to a RESET state, or visa-
versa. These results in the JK flip flop acting more like a T-type toggle flip-flop when both
terminals are “HIGH”.
Although this circuit is an improvement on the clocked SR flip-flop it still suffers from timing
problems called “race” if the output Q changes state before the timing pulse of the clock input
has time to go “OFF”. To avoid this the timing pulse period ( T ) must be kept as short as
possible (high frequency). As this is sometimes not possible with modern TTL IC‟s the much
improved Master-Slave JK Flip-flop was developed.
(c) Differentiate between CISC and RISC and justify use of each of them in practice. 6M
Ans: The architecture of the Central Processing Unit (CPU) operates the capacity to function from 2M
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“Instruction Set Architecture” to where it was designed. The architectural design of the CPU
is Reduced instruction set computing (RISC) and Complex instruction set computing (CISC).
CISC has the capacity to perform multi-step operations or addressing modes within one
instruction set. It is the CPU design where one instruction works several low-level acts. For
instance, memory storage, loading from memory, and an arithmetic operation. Reduced
instruction set computing is a Central Processing Unit design strategy based on the vision that
basic instruction set gives a great performance when combined with a
microprocessor architecture which has the capacity to perform the instructions by using some
microprocessor cycles per instruction. The hardware part of the Intel is named as Complex
Instruction Set Computer (CISC), and Apple hardware is Reduced Instruction Set Computer
(RISC).
Sr.
CISC RISC
No.
A large number of instructions are present Very fewer instructions are present.
1 in the architecture. The number of instructions are
generally less than 100. 4M
Some instructions with long execution No instruction with a long execution
times. These include instructions that copy time due to very simple instruction set.
an entire block from one part of memory to Some early RISC machines did not
2 another and others that copy multiple even have an integer multiply
registers to and from memory. instruction, requiring compilers to
implement multiplication as a sequence
of additions.
Variable-length encodings of the Fixed-length encodings of the
3
instructions. instructions are used.
Example: IA32 instruction size can range Example: In IA32, generally all
4 instructions are encoded as 4 bytes.
from 1 to 15 bytes.
Multiple formats are supported for Simple addressing formats are
specifying operands. A memory operand supported. Only base and displacement
5 specifier can have many different addressing is allowed.
combinations of displacement, base and
index registers.
6 CISC supports array. RISC does not supports array.
Arithmetic and logical operations can be Arithmetic and logical operations only
applied to both memory and register use register operands. Memory
operands. referencing is only allowed by load and
7
store instructions, i.e. reading from
memory into a register and writing
from a register to memory respectively.
Implementation programs are hidden Implementation programs exposed to
from machine level programs. The ISA machine level programs. Few RISC
8
provides a clean abstraction between machines do not allow specific
programs and how they get executed. instruction sequences.
9 Condition codes are used. No condition codes are used.
Registers are being used for procedure
The stack is being used for procedure arguments and return addresses.
10
arguments and return addresses. Memory references can be avoided by
some procedures.
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Q.6 Attempt any TWO of the following: 12Total

Marks
Describe the concept of pipelining and process of physical address generation in 8086
(a) 6M
microprocessor.
Ans: CONCEPT OF PIPELINING

Fetching the next instruction while the current instruction executes is known as pipelining it
means When first instruction is getting executed, second one‟s is decoded and third
instruction code is fetched from memory. This process is known as pipelining. It improves
speed of operation to great extent.
To speed up program execution, the Bus Interface Unit(BIU) fetches as many as 6 instruction
bytes ahead of time from the memory and these are held for execution unit in the (FIFO) 3M
group of registers called QUEUE.
The BIU can fetch instruction bytes while EU is decoding or executing an instruction which
does not require the use of buses. When the EU is ready for the next instruction, it simply
reads the instruction from the QUEUE in the BIU. This is much faster than sending out
addresses to system memory and waiting for the memory to send back the next instruction
byte.
The Queue is refilled when at least two bytes are empty as 8086 has a 16-bit data bus.
In case of Branch instructions however, the instructions pre-fetched in the queue are of no
use. Hence the QUEUE has to be dumped and new instructions are fetched from the
destination addresses specified by the branch instructions.
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Physical Address Generation:
The 8086 addresses a segmented memory. The complete physical address which is 20-bits
long is generated using segment and offset registers each of the size 16-bit.The content of a
segment register also called as segment address, and content of an offset register also called
as offset address. To get total physical address, put the lower nibble 0H to segment address
and add offset address. The figure shows formation of 20-bit physical address.
3M
The physical address is calculated as follows:

XXXX0
+ 0YYYY
ZZZZZ
Where (X X X X)H 16 bit segment address

(Y Y Y Y )H 16 bit offset address
and (Z Z Z Z Z )H 20 bit offset address
 A segment is a 64 K block, hence, there could be 16 non overlapping segments in 1 MB

of memory.
 The size of any segment cannot be greater than 64KB.
 The size of any segment cannot be lesser than 16 Byte.
(b) State the names of universal logic gates and design basic gates using universal gates. 6M
Ans: Universal logic gates : 1M

NAND gate NAND:2.5
NOR gate M
NOR:2.5M
NAND GATE AS AN UNIVERSAL GATES:
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1. Implementing an Inverter Using only NAND Gate The figure shows two ways in which a
NAND gate can be used as an inverter (NOT gate).All NAND input pins connect to the input
signal A gives an output A‟.
2. Implementing AND Using only NAND Gates An AND gate can be replaced by NAND
gates as shown in the figure (The AND is replaced by a NAND gate with its output
complemented by a NAND gate inverter).
3. Implementing OR Using only NAND Gates An OR gate can be replaced by NAND gates
as shown in the figure (The OR gate is replaced by a NAND gate with all its inputs
complemented by NAND gate.
inverters)
NOR GATE AS AN UNIVERSAL GATES:

1. All NOR input pins connect to the input signal A gives an output A‟.
2. Implementing OR Using only NOR Gates An OR gate can be replaced by NOR gates as
shown in the figure (The OR is replaced by a NOR gate with its output complemented by a
NOR gate inverter).
3. An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is
replaced by a NOR gate with all its inputs complemented by NOR gate inverters)
(c) Describe the use of shift and rotate instructions as well as string instructions with the 6M
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help of one relevant examples of each.
Ans: SHIFT AND ROTATE INSTRUCTIONS

In the 8086 microprocessor, we have 16-bit registers to handle our data. Sometimes, the need
to perform some necessary shift and rotate operations on our data may occur according to the
given condition and requirement. So, for that purpose, we have various Shift and Rotate
instructions present in the 8086 microprocessor.
1) SHR : Shift Right
The SHR instruction is an abbreviation for „Shift Right‟. This instruction simply shifts the
mentioned bits in the register to the right side one by one by inserting the same number (bits
that are being shifted) of zeroes from the left end. The rightmost bit that is being shifted is
stored in the Carry Flag (CF).
Syntax: SHR Register, Bits to be shifted
Example: SHRAX, 2
Working:
2) SAR : Shift Arithmetic Right

The SAR instruction stands for „Shift Arithmetic Right‟. This instruction shifts the mentioned
bits in the register to the right side one by one, but instead of inserting the zeroes from the left
end, the MSB is restored. The rightmost bit that is being shifted is stored in the Carry Flag INSTRU
(CF). CTION:1
Syntax: SAR Register, Bits to be shifted M
Example: SAR BX, 5 ,EXAMPL
E:1M
Working:
EACH
2) SHL : Shift Left

The SHL instruction is an abbreviation for „Shift Left‟. This instruction simply shifts the
mentioned bits in the register to the left side one by one by inserting the same number (bits
that are being shifted) of zeroes from the right end. The leftmost bit that is being shifted is
stored in the Carry Flag (CF).
Syntax: SHL Register, Bits to be shifted
Example: SHLAX, 2
Working:
3) SAL : Shift Arithmetic Left

The SAL instruction is an abbreviation for „Shift Arithmetic Left‟. This instruction is the
same as SHL.
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Syntax: SAL Register, Bits to be shifted
Example: SAL CL, 2
Working:
5) ROL : Rotate Left

The ROL instruction is an abbreviation for „Rotate Left‟. This instruction rotates the
mentioned bits in the register to the left side one by one such that leftmost bit that is being
rotated is again stored as the rightmost bit in the register, and it is also stored in the Carry
Flag (CF).
Syntax: ROL Register, Bits to be shifted
Example: ROL AH, 4
Working:
6) ROR : Rotate Right

The ROR instruction stands for „Rotate Right‟. This instruction rotates the mentioned bits in
the register to the right side one by one such that rightmost bit that is being rotated is again
stored as the MSB in the register, and it is also stored in the Carry Flag (CF).
Syntax: ROR Register, Bits to be shifted
Example: ROR AH, 4
Working:
7) RCL : Rotate Carry Left

This instruction rotates the mentioned bits in the register to the left side one by one such that
leftmost bit that is being rotated it is stored in the Carry Flag (CF), and the bit in the CF
moved as the LSB in the register.
Syntax: RCL Register, Bits to be shifted
Example: RCL CH, 1
Working:
8) RCR : Rotate Carry Right

This instruction rotates the mentioned bits in the register to the right side such that rightmost
bit that is being rotated it is stored in the Carry Flag (CF), and the bit in the CF moved as the
MSB in the register.
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Syntax: RCR Register, Bits to be shifted
Example: RCRBH, 6
Working:
STRING INSTRUCTIONS
String is a group of bytes/words and their memory is always allocated in a sequential order.
1. MOVS/MOVSB/MOVSW Instruction :
This instruction copies a byte or word from a location in the data segment to a location in the
extra segment. The offset of the source byte or word in the data segment must be in the SI
register. The offset of the destination in the extra segment must be contained in the DI
register. For multiple byte or multiple word moves the number of elements to be moved is put
in the CX register so that it can function as a counter. After the byte or word is moved SI and
DI are automatically adjusted to point to the next source and the next destination. If the
direction flag is 0, then SI and DI will be incremented by 1 after a byte move and they will
incremented by 2 after a word move. If the DF is a 1, then SI and DI will be decremented by
1 after a byte move and they will be decremented by 2 after a word move. MOVS affects no
flags.
2. CMPS/CMPSB/CMPSW Instruction :
A 8086 String Instructions is a series of the same type of data items in sequential memory
locations. The CMPS instruction can be used to compare a byte in one string with a byte in
another string or to compare a word in one string with a word in another string. SI is used to
hold the offset of a byte or word in the source string and DI is used to hold the offset of a byte
or a word in the other string. The comparison is done by subtracting the byte or word pointed
to by DI from the byte or word pointed to by SI. The AF, CF, OF, PF, SF, and ZF flags are
affected by the comparison, but neither operand is affected.
After the comparison SI and DI will be automatically incremented or decremented according

to direction flag to point to the next element in the two strings (if DF = 0, SI and DI ↑) CX
functions as a counter which is decremented after each comparison. This will go on until CX
=0
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3. SCAS/SCASB/SCASW Instruction :
SCAS compares a string byte with a byte in AL or a string word with word in AX. The
instruction affects the flags, but it does not change either the operand in AL (AX) or the
operand in the 8086 String Instructions. The string to be „scanned must be in the extra
segment and DI must contain the offset of the byte or the word to be compared.
After the comparison DI will be automatically incremented or decremented according to
direction flag, to point to the next element in the two strings (if DF = 0, SI and DI ↑ ) CX
functions as a counter which is decremented after each comparison. This will go on until CX
= 0. SCAS affects the AF, CF, OF, PF, SF and ZF flags.
SCASB says compare 8086 String Instructions as bytes and SCASW says compare strings as
words.
4. LODS/LODSB/LODSW Instruction :
This instruction copies a byte from a string location pointed to by SI to AL, or a word from a
string location pointed to by SI to AX. LODS does not affect any flags. LODSB copies byte
and LODSW copies a word.
5. STOS/STOSB/STOSW Instruction :
The STOS instruction copies a byte from AL or a word from AX to a memory location in the
extra segment. DI is used to hold the offset of the memory location in the extra segment.
After the copy, DI is automatically incremented or decremented to point to the next string
element in memory. If the direction flag, DF, is cleared, then DI will automatically be
incremented by one for a byte string or incremented by two for a word 8086 String
Instructions. If the direction flag is set, DI will be automatically decremented by ono for a
byte string or decremented by two for a word string. STOS does not affect any flags. STOSB
copies byte and STOSW copies a word.
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SUMMER – 2019 EXAMINATION

MODEL ANSWER
Subject: Digital Techniques and Microprocessor Subject Code: 22323

1) The answers should be examined by key words and not as word-to-word as given in the model
answer scheme.
2) The model answer and the answer written by candidate may vary but the examiner may try to
assess the understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given more Importance
(Not applicable for subject English and Communication Skills).
4) While assessing figures, examiner may give credit for principal components indicated in the
figure. The figures drawn by candidate and model answer may vary. The examiner may give
credit for any equivalent figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the assumed constant
values may vary and there may be some difference in the candidate’s answers and model
answer.
6) In case of some questions credit may be given by judgement on part of examiner of relevant
answer based on candidate’s understanding.
7) For programming language papers, credit may be given to any other program based on
equivalent concept.

No Q.N. Scheme
.
1. Attempt any FIVE of the following: 10
a) State the function of linker and debugger. 2M
Ans. Function of linker and debugger:
Linker: There are certain programs which are large in size and
cannot be executed at one go simultaneously. Such programs are
divided into sub programs also known as modules. The linker is used Each
to link such small programs to form one large program. It also function
generates an executable file. 1M
Debugger: Debugger is used to test and debug programs. The

debugger allows a user to test a program step by step, so that the
problem points or steps can be identified and rectified. It allows the
user to inspect the registers and memory locations after a program has
been executed.
b) List any four addressing modes and give one example of each. 2M
Ans. Addressing Modes:
1. Immediate Addressing Mode:
Example: MOV CL, 03H
ADD AX, 1234H
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2. Register Addressing Mode:

Example: MOV AL, BL
ADD CL, DL
MOV DS, AX Any
3. Direct Addressing Mode: four
Example: MOV AL, [2000H] addressi
MOV [1020], 5050H ng
4. Register Indirect Addressing Mode modes
Example: MOV [DI], 1234H with
MOV AX, [BX] example
1/2
5. Based Addressing with displacement M
Example: MOV AX, [BX+300H] each
MOV AX, [BX-2H]
6. Indexed Addressing Mode
Example: MOV [DI + 2345H], 1234H
MOV AX, [SI + 45H]
7. Based Indexed Addressing Mode
Example: MOV [BX + DI], 1234H
MOV AX, [SI + BX]
8. Based Indexed Addressing with Displacement Mode
Example: MOV [DI + BX + 37H], AX
MOV AL, [BX + SI + 278H]
9. Fixed or Direct Port Addressing:
Example: OUT 06H, AL
IN AX, 85H
10. Variable or Indirect Port Addressing
Example: IN AL, DX
OUT DX, AX
11. Implied (Implicit) Addressing Modes
Example: CLC
DAA
c) State any two Boolean laws with expression. 2M
Ans. 1. A . 0 = 0
2. A . 1 = A And law
3. A . A = A Any 2
4. A . A = 0 Boolean
5. Commutative Law laws 1M
A. B. = B. A. each
6. Associative Law
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A. (B.C) = (A.B)C
7. Distributive Law
A.(B+C) = A.B + A.C.
8. A.(A+B) = A
9. A. (A + B) = AB
10. A = A
11. De-Morgan's theorem
A. B = A + B
12. A + 0 = A
13. A + 1 = 1 A + 1 =1 OR law
14. A + A = A
15. A + A = 1
16. A + B = B + A
17. A + (B + C) = (A + B) + C
18. A + (B. C) = (A + B) . (A + C)
19. A + AB = A
20. A + AB = A + B
21. A + AB = A+ B
22. A + AB= A + B
23. A + B = A . B
d) Define: 2M
i) Bit
ii) Nibble
Ans.
i) Bit: Bit is a Binary digit which is the smallest unit of data in
digital systems. A bit has a single binary value, either 0 or 1. Each
definitio
ii) Nibble: A group of 4 bits is referred as Nibble. Eg: 1011, 1001, n 1M
1100
e) Convert following number into its equivalent Binary Number 2M

(146.25)10
Ans.
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1M
1M
f) Define Minterm and Maxterm. 2M

Ans. Minterm:
Each individual term in the canonical SOP (Sum of Products) form is
called as Minterm.
Example:
Each
definitio
n 1M
Maxterm:
Each individual term in the canonical POS (Product of Sums) form is
called as Maxterm.
Example:
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g) Draw three variable K-map format. 2M

Ans.
Correct
diagram
OR 2M
OR
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2 Attempt any THREE of the following: 12

a) Draw symbol and truth table of D and T flip flop. State theie 4M
applications.
Ans. D flip flop:
D flip
flop
Symbol -
½M;
Truth
Symbol Truth Table table-
Applications of D flip flop: 1M;
1. used as a Latch One
2. Divide - by - 4 Ripple Counter applicati
3. Ring Counter on -½M
4. Johnson Counter
5. Used in registers
T flip flop:
T flip
flop
Symbol -
½M;
Truth
table-
Symbol Truth Table 1M;
One
Applications of T flip flop: applicati
1. As the basic building block of counter. on -½M
2. In frequency divider circuits.
3. Used in D to A converter (DAC)
b) Minimize the following function using K-map. 4M
F = Σm (0,1,2,3,11,12,14,15).
(Note: Any other equations shall be considered).
Ans.
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Four
variable
K-map
2M
Final
equation
2M
OR
Minimized Expression
F = 𝑨𝑩 + A B𝑫 + A C D
c) Perform binary subtraction using 2's complement of the 4M

following:
i) (63)10 - (20)10 = ?
ii) (34)10 - (48)10 = ?
Ans. i) (63)10 - (20)10 = ?
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2M
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MODEL ANSWER
ii) (34)10 - (48)10 = ?
2M
d) Simplify the following Boolean expression 4M

i) Y = AB + ABC + 𝐀B + 𝐀𝐁𝐂
ii) Y = (A + B) (A + 𝐁) (𝐀 + 𝐁)
Note: Any other method of simplifying using the Boolean laws
shall also be considered.
Ans. i) Y = AB + ABC + 𝐀B + 𝐀𝐁𝐂
= AB (1 + C) + A (B + BC)
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= AB + A(B + C) ∵ 1 + C = C, B + BC = B + C
= AB + AB + AC
= B (A + A) + AC ∵ A+A=1 2M
= B (1) + AC
= B + 𝐀C
ii) Y = (A + B) (A + 𝐁) (𝐀 + 𝐁)
=(A.A + A B + AB + B B) (A + B)
= (A + A B + AB + 0) (A+ B) (∵ A.A = A, B B =0)
= A (1 + B + B) (A + B)
2M
= A (1) (A + B) (∵ B+B=1, 1+A=1)
= A (A + B)
= A A + AB
= 0 + AB (∵ A A = 0)
= AB
3. Attempt any THREE of the following: 12
a) Draw 8086 architecture block diagram and state the functions of 4M
EV and B/V.
(Note: EV and B/V are considered as EU and BIU).
Ans.
Diagram
2M
Fig: Functional Block Diagram of Intel 8086 microprocessor
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BIU: It handles all transfers of data and addresses on the buses for the
execution unit.
 Sends out addresses
 Fetches instructions from memory. 1M for
 Read / write data from/to ports and memory i.e. handles all BIU
transfers of data and addresses on the busses
EU:
 Tells BIU where to fetch instructions or data from 1M for
 Decodes instructions EU
 Executes instructions
OR
The functions performed by the Bus interface unit are:
- The BIU is responsible for the external bus operations.
- It performs fetching, reading, writing for memory as well as I/O of
data for peripheral devices.
- The BIU also performs address generation and the population of the
instruction queue.
The Execution unit is responsible for the following work:

- The instructions are decoded and executed by it.
- The EU accepts instructions from the instruction queue and from the
general purpose registers it takes data.
- It has no relation with the system buses.
b) Design half adder using K-map and realize it using basic gate. 4M
Ans. Half Adder:
Half adder is a combinational circuit that performs simple addition of
two binary digits.
Half Adder Truth Table:

If we assume A and B as the two bits whose addition is to be 1M for
performed, a truth table for half adder with A, B as inputs and Sum, Truth
Carry as outputs can be tabulated as follows. Table
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1M each
for K
map of
sum and
carry
K map for sum
Sum= A B+ A B
K map for Carry
Carry=A.B
Logic Diagram for Half Adder:
1M for
Logic
Diagram
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c) Construct NOT, AND, OR, NOR gates using NAND gate. 4M

Ans. NAND as NOT gate:
1M for
each
conversi
AND using NAND: on
OR using NAND:
NOR using NAND:
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d) Interpret the given program and specify the output for the 4M
following situation.
MOV AX, 34F9H
MOV BX, 3A69H.
(i) Masking of lower nibble of AX.
(ii) Rotate right through carry contents of BX by 4 positions.
(iii) Shift left contents of BX by 6 positions..
(iv) XOR AX, BX
(Note: If the outputs are written correctly according to the sequence
also, marks shall be given. Weightage shall be given to the output
need not consider the steps).
(i) Masking of lower nibble of AX:
Ans. AND AL,0F0H
After the execution of this instruction the content of AX register will
be 34F0H.
AX= 34F0H
(ii) Rotate right through carry contents of BX by 4 positions: 1M for

The instruction will be the
MOV CL,04H output
RCR BL,CL of each
instructi
on
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After the Execution of the instruction the data will be 23A6H.

BX= 23A6H
(iii) Shift left contents of BX by 6 positions:

Register BX is 3A69H, after shifting it by 6 positions, using SHL BX,
CL instruction, where CL=06
After the execution the content of regBx will be 9A40H

BX= 9A40H
(iv) XOR AX, BX:
After the Execution of the instruction Register AX will contain data

0E90H
AX= 0E90H

a) Explain the concept of pipelining. 4M
Ans. In pipelined processor, fetch, decode and execute operation are Explain
performed simultaneously or in parallel. When first instruction is ation
being decoded, same time code of the next instruction is fetched. 2M
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• When first instruction is getting executed, second one’s is decoded

and third instruction code is fetched from memory. This process is
known as pipelining. It improves speed of operation to great extent.
Diagram
2M
b) Explain concept of physical address calculation with suitable 4M

diagram and examples.
Ans. The 8086 addresses a segmented memory. The complete physical
address which is 20-bits long is generated using segment and offset
registers each of the size 16-bit.The content of a segment register also
called as segment address, and content of an offset register also called 2M for
as offset address. To get total physical address, put the lower nibble explaina
0H to segment address and add offset address. The figure shows tion
formation of 20-bit physical address.
1M
diagram
Fig: Physical address formation

Calculate the physical address for the given CS=3420H,
IP=689AH.
CS=3420H
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IP=689AH
Zero is inserted 1M for
3 4 20 0 example
+ 6 8 9A
=3AA9A
c) State and prove De-Morgan's Theorems. 4M

Ans. Theorem no 1:
It states that the, complement of a sum is equal to product of their
complements
For
each
theorem
2M
Theorem no 2:
It states that, the complement of a product is equal to sum of the
complements.
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d) Describe race-around condition in JK flip flop and suggest ways 4M

to overcome it.
Ans. Race around condition in JK flip-flop:
In a J-K Flip-flop, when J=K=1, the output toggles.
If the clock pulse as shown below is applied at the clock input, for a
level triggered J-K flip-flop, after a time interval Δt equal to the
propagation delay through two NAND gates, the output again toggles. 2M for
After another time interval Δt, the output changes again. Hence descripti
during tp of the clock pulse, the output will oscillate back and forth on
between 0 and 1. At the end of the clock pulse, the value of Q is
uncertain. This situation is referred as race -around condition.
This can be avoided if tp < Δt < T. A practical method of overcoming
this difficulty is the use of the master-slave (MS) configuration. It can
also be achieved through edge triggering.
2M for
suggesti
on
e) Compare combinational and sequential circuits (four points). 4M

Ans. Sr. Combinational circuits Sequential circuits
No.
1 Output depends on Output depends on present
inputs present at that inputs and past inputs/ outputs Any
time four
2 Memory is not Memory is necessary points
necessary 1M each
3 Clock input is not Clock input is necessary
necessary
4 Design is simple Design is complex
5 For e.g. Adders, For e.g. Shift registers, Counters
Subtractors
5. Attempt any TWO of the following: 12
a) Write an assembly language program with algorithm for finding 6M
smallest number from the array of 10 numbers (Assume suitable
data).
(Note: Any other logic shall be considered).
Ans.
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Algorithm:
1. Start
2. Load the array offset in BX
3. Initialize the CX with count value. Algorith
m 2M
4. Initialize AL with FFh.
5. Compare the first number in BL with AL
6. Compare and transfer the smallest number in AL.
7. Decrement counter and if it is not zero then repeat the loop from
step 5.
8. Store the smallest number in the defined destination location.
9. Stop the process.
Program:
data segment
STRING1 DB 08h,14h,05h,0Fh,09h, 01h, 05h, 18h, 2Ah, 0ACh
res db ?
data ends Correct
code segment Program
4M
assume cs:code, ds:data
start: mov ax, data
mov ds, ax
mov al, 0ffh
mov cx, 0ah
mov bx, offset STRING1
again: cmp al, [bx]
jc skip
mov al, [bx]
skip: inc bx
loop again
mov res, al
int 3
code ends
end start
b) Draw minimum mode configuration of 8086 and explain the 6M
function of any four control signals.
Ans.
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Diagram
4M
1. 𝐈𝐍𝐓𝐀: This is related to the non-vectored interrupt. It indicates

that the processor has accepted INTR interrupt.
2. ALE: (Address Latch Enable): This signal is used to demultiplex
the multiplexed the address and data at the falling edge of the
ALE.
i. If ALE = 1 => AD0-AD15 will form A0-A15 Function
ii. If ALE =0 => AD0-AD15 will form D0-D15. of any 4
3. 𝐃𝐄𝐍 (Data Enable): It provides an output enable for the 8286 in a control
minimum mode which uses a transceiver. It is active LOW during signals
each memory and I/O access and for INTA cycle. 2M
4. 𝐃𝐓/𝐑 (Data Transmit / Receive): It is an output signal which
controls the direction of data flow through the transceivers. If it is
at logic 1 the buffers are enabled to transmit data from the 8086. If
it is at logic 0 the buffers are enabled to receive data.
5. 𝐌/𝐈𝐎: It is used to distinguish a memory transfer or I/O transfer.
For memory operation M/IO=1 and for I/O operation M/IO=0.
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6. 𝐖𝐑: It is used by the 8086 for outputting a low to indicate that the
processor is performing a write memory or write I/O operation
depending on the 𝑀/𝐼𝑂 signal.
7. HOLD:This is s request signal which is given by peripheral device
to the microprocessor to have control over address and data lines.
8. HLDA: If the microprocessor is ready to give the control of
address and data lines to external device then it provides Hold
Acknowledge.
c) List the addressing modes of 8086 and describe them with an 6M
example.
Ans. Addressing Modes:
1. Immediate Addressing Mode
2. Register Addressing Mode
3. Direct Addressing Mode
4. Indirect Addressing mode List (any
5. Register Indirect Addressing Mode 4) -2M
6. Based Addressing with displacement
7. Indexed Addressing Mode
8. Based Indexed Addressing Mode
9. Based Indexed Addressing with Displacement Mode
10. Fixed or Direct Port Addressing
11. Variable or Indirect Port Addressing
12. Implied (Implicit) Addressing Modes
1. Immediate Addressing Mode: In immediate addressing 8/16 bit

data is specified as a part of instruction or specified in the
instruction itself. The immediate operand can be only source Any 4
descriptio
operand.
n – 1M
Ex: MOV CL, 03H each
ADD AX, 1234H.
2. Register Addressing Mode: In this addressing mode the source and

destination operand are specified in a register. The operand can be
8/16 bit wide. The 8 bit operand can be any one of the register:
AL, AH, BH, BL, CH, CL, DH, DL and the 16-bit operand can be
AX, BX, CX, DX, SI, DI, SP. The 16-bit operand can be also be
either of the segment registers.
Ex: MOV AL, BL
ADD CL, DL
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MOV DS, AX
3. Memory Addressing Mode: The memory addressing mode is

classified under two categories:
 Direct Addressing Mode: In this 16-bit offset address is
provided in the instruction itself. Here [ ] refers the contents of
the offset address.
Ex: MOV AL, [2000H]; MOV [1020], 5050H
 Indirect Addressing mode: In this mode the Effective address is
calculated from the contents of one or two registers along with
the displacement value. The indirect addressing mode is
classified in five categories:
i. Register Indirect Addressing Mode: In this mode EA is
provided in an index register or base register. The index register
can be SI or DI and the base register can be BX.
EA= [BX, SI, DI]
Ex: MOV [DI], 1234H; MOV AX, [BX]
ii. Based Addressing with displacement: In this mode EA is sum

of an 8/16 bit displacement and the contents of base register
(BX or BP).
Ex: MOV AX, [BX+300H]; MOV AX, [BX-2H]
iii. Indexed Addressing Mode: In this EA is the sum of the 8/16 bit
displacement plus the contents of the index registers SI or DI.
Ex: MOV [DI + 2345H], 1234H; MOV AX, [SI + 45H]
iv. Based Indexed Addressing Mode: In this EA is the sum of base

registers (BX or BP) and the indexed register (SI or DI) both
which are specified in the instruction.
Ex: MOV [BX + DI], 1234H; MOV AX, [SI + BX]
v. Based Indexed Addressing with Displacement Mode: In this EA

is the sum of base registers (BX or BP) and the indexed register
(SI or DI) along with the 8/16 bit displacement.
Ex: MOV [DI + BX + 37H], AX; MOV AL, [BX + SI + 278H]
4. I/O Port addressing: There are two types of I/O port addressing:
i. Fixed or Direct Port Addressing: In this case a one byte port
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address will be provided in the instruction. This allows fixed

access to ports numbered 0 to 255 (00-FFH).
Ex: OUT 06H, AL; IN AX, 85H
ii. Variable or Indirect Port Addressing: In this case port address

will not be explicitly in the instruction. The address of port
number is taken from DX allowing 64K 8 bit ports or 32K 16
bit ports. This mode is known as variable or indirect port
address. The 8 and 16 bit I/O data transfers should take place
only through AL or AX.
Ex: IN AL, DX; OUT DX, AX.
5. Implied (Implicit) Addressing Modes: In this the instructions does

not have any operand.
Ex: CLC, DAA
6. Attempt any TWO of the following: 12
a) Define the following term with respect the digital IC's: 6M
(i) Propagation delay
(ii) Fan in
(iii) Fan out
(iv) Power Dissipation
(v) Noise Margin
(vi) Threshold Voltage.
Ans. (i) Propagation delay: Propagation delay is defined as the time taken
to obtain the O/P when the I/P is applied. It is given in nano seconds.
(1 ns=10-9 sec).
The I/P and O/P wave forms of a logic gate are as follows:
Each
definitio
n 1M
The delay times are measured between 50% voltage levels of I/P &
O/P wave forms. There are 2 delay times t PHL when O/P goes from
high to low & t PLH when it goes from low to high. The propagation
delay time of the logic gate is taken as the average of these 2 delay
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MODEL ANSWER
times.
(ii) Fan in: Fan-In is defined as the number of inputs the gate has. For
e.g. a two input gate will have fan-in equal to 2.
(iii) Fan out: Fan-out is the no. of similar gates which can be driven
by the gate. High fan out is better as it reduces need for additional
drivers to drive more gates
(iv) Power dissipation: Power dissipation is the power required in

mW in an IC. Low power requirement indicates low speed of
operation & vice versa. Hence, to select an IC, figure of merit is
considered. It is the product of propagation delay & power, i.e. ns x
mw = pJ. The gate of the lowest fig. of merit is selected.
(v) Noise margin: Some electric & magnetic fields can induce
unwanted voltages on the wires between logic circuits. They are
called ‘Noise Signals’. They may cause a change in VIH or VIL &
may produce undesired operation. The ability of circuit to tolerate
these noise signals is called as Noise immunity. These are indicated
by noise margins. If they are defined above, they are called DC noise
margins. If the noise pulse width is less & is approaching the
propagation delay of circuit, it is called AC noise margin.
(vi) Threshold voltage: For any logic family, there are a number of
threshold voltage levels to know:
1. VOH -- Minimum OUTPUT Voltage level a
TTL device will provide for a HIGH signal.
2. VIH -- Minimum INPUT Voltage level to be
considered a HIGH.
3. VOL -- Maximum OUTPUT Voltage level a
device will provide for a LOW signal.
4. VIL -- Maximum INPUT Voltage level to still
be considered a LOW.
b) Write an assembly language program to arrange any array of 10 6M

bytes in ascending order. Draw flowchart for the same.
(Note: Any other logic shall also be considered).
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Ans. Program:
DATA SEGMENT
ARRAY DB 15h,05h,08h,78h,56h, 60h, 54h, 35h, 24h, 67h
DATA ENDS
CODE SEGMENT
ASSUME CS: CODE, DS:DATA
START:MOV DX, DATA
MOV DS, DX
MOV BL,0AH
step1: MOV SI,OFFSET ARRAY Correct
MOV CL,09H Program
step: MOV AL,[SI] 4M
CMP AL,[SI+1]
JC Down
XCHG AL,[SI+1]
XCHG AL,[SI]
Down : ADD SI,1
LOOP step
DEC BL
JNZ step1
MOV AH,4CH
INT 21H
CODE ENDS
END START
Flowchart:
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MODEL ANSWER
Flowchar
t 2M
c) Refer given Fig. No.1 and write the outputs for each of the 6M
following input:
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MODEL ANSWER
(Note: Writing Boolean expression shall be considered as option.

Any four correct output shall be given 3M).
Ans.
F  ( AB ).( BC ).( A  C )
F  AB  BC  ( A  C )
F  A  B  BC  A  C
F  A  A  B  BC  C Correct
F  1 B  C outputs
F  1 C 6M
F 1
A B C F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
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WINTER – 2018 EXAMINATION

MODEL ANSWER
Subject: Digital Techniques & Microprocessor Subject Code: 22323

1) The answers should be examined by key words and not as word-to-word as given in the model
answer scheme.
2) The model answer and the answer written by candidate may vary but the examiner may try to
assess the understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given more Importance
(Not applicable for subject English and Communication Skills).
4) While assessing figures, examiner may give credit for principal components indicated in the
figure. The figures drawn by candidate and model answer may vary. The examiner may give
credit for any equivalent figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the assumed constant
values may vary and there may be some difference in the candidate’s answers and model
answer.
6) In case of some questions credit may be given by judgement on part of examiner of relevant
answer based on candidate’s understanding.
7) For programming language papers, credit may be given to any other program based on
equivalent concept.

No Q.N. Scheme
.
1. Attempt any FIVE of the following: 10
a) Draw symbol and write truth table of EX-OR gate. 2M
Ans. Symbol
Symbol
Truth Table 1M
Truth Table for two input EX-OR gate. A logical gate whose output
is one when odd number of inputs are one, for any other condition
output is low.
Inputs Output
A B Y Truth
0 0 0 Table
1 0 1 1M
0 1 1
1 1 0
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b) Define terms “Minterm” and “Maxterm” with proper example of 2M

each.
Ans. Minterm:
Each individual term in the canonical SOP form is called as Minterm. Each
Example: Definitio
n with
example
1M
Maxterm:
Each individual term in the canonical POS form is called as Maxterm. Each
Example: Definitio
n with
example
1M
c) Draw symbol of JK flip-flop and write its truth table. 2M

Ans. Symbol
Symbol
1M
Truth Table:
Inputs Output Truth
Jn Kn Qn+1 Table
0 0 Qn 1M
0 1 0
1 0 1
1 1 Qn
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d) State importance of pipelining in 8086 microprocessor 2M

Ans.  In pipelining, while the current instruction is executing, next
instruction is fetched using a queue. Any two
 Pipelining enables many instructions to be executed at the same points
time. 2M
 It allows execution to be done in fewer cycles.
 Speed up the execution speed of the processor.
 More efficient use of processor.
e) Give any four applications of digital circuits. 2M
Ans. Applications of digital circuits
i) Object Counter Any
ii) Dancing Lights relevant
iii) Scrolling Notice board four
iv) Multiplexer applicati
v) Digital Computers ons
vi) Washing machines, Television 2M
vii) Digital Calculators
viii) Military Systems
ix) Medical Equipments
x) Mobile Phones
xi) Radar navigation and guiding systems
xii) Microprocessors
f) Define the following terms – 2M
(i) Physical Address
(ii) Effective Address
Ans. (i) Physical Address

(Note: Diagram is Optional) Each
Physical: The address given by BIU is 20 bit called as physical definitio
address. It is the actual address of the memory location accessed by n
the microprocessor. It is calculated as 1M
Page 3 / 26
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MODEL ANSWER
(ii) Effective Address

Effective Address: Effective address or the offset address is the
offset for a memory operand. It is an unassigned 16 bit number that
gives the operand's distance in bytes from the beginning of the
segment.
g) Choose instruction for following situations: 2M
(i) Addition of 16 bit Hex. No with carry
(ii) Division of 8 bit No.
(iii) Rotate content of BL by 4 bit.
(iv) Perform logical AND operation of AX and BX
Ans (i) Addition of 16 bit Hex. No with carry

(Note any other relevant registers shall also be considered) Each
ADC Destination 16, Source 16 instructi
OR on
ADC AX, BX ½M
OR
ADC AX, 4500H
(ii) Division of 8 bit No.

(Note any other relevant registers shall also be considered)
DIV SOURCE
OR
DIV BL
Page 4 / 26
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MODEL ANSWER
(iii)Rotate content of BL by 4 bit.

MOV CL,04H
ROR BL, CL
OR
MOV CL, 04H
ROL BL, CL
(iv) Perform logical AND operation of AX and BX

AND AX,BX

a) Convert following decimal to octal and Hexadecimal 4M
i) (297)10 = ( )8
ii) (453)10 = ( )16
Each
Ans. (i) (297)10 = ( )8 conversi
on
2M
(ii) (453)10 = ( )16
Page 5 / 26
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MODEL ANSWER
b) Convert the given minterm into standard POS form. 4M

𝒀 𝑨, 𝑩, 𝑪𝑫 = 𝑨. 𝑩𝑪 + 𝑩. 𝑪 𝑫 + (𝑨 𝑩)
Ans. Note: Solution is given by considering 𝒀 𝑨, 𝑩, 𝑪𝑫 𝒂𝒔 𝒀(𝑨, 𝑩, 𝑪, 𝑫)
Standar
d SOP
form
2M
Conversi
on to
Standar
d POS
2M
c) Draw symbol and write truth table for the following flip flop and 4M
give one application of each.
i) Clocked R-S flip flop
ii) T- flip flop
Ans. (i) Clocked R-S flip flop
Symbol
Symbol
½M
Page 6 / 26
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MODEL ANSWER
Truth Table
Truth
table
1M
Application: Any one

i) Clocked RS flip-flop can be used in sequential circuits. Applicat
ii) It can be used to design counters. ion
iii) It can be used as a latch in digital circuits. ½M
(ii) T- flip flop

Symbol
Symbol
½M
Truth Table
Truth
table
1M
Page 7 / 26
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MODEL ANSWER
Application: Any one

i) Used to design counters in digital circuits. Applicat
ii) Can be used in frequency divider circuits. ion
½M
d) Prove 𝑨 𝑨 + 𝑪 𝑨 𝑩 + 𝑪 𝑨 𝑩𝑪 + 𝑪 = 𝟎 4M
Ans. Note: Any other relevant laws applied shall be considered while
obtaining the correct answer.
Correct
solution
4M
3 Attempt any THREE of the following: 12

a) Implement OR gate and NOT gate using “Universal NAND 4M
gate”. Write expressions for both.
Ans. 1. "OR" gate using "Universal NAND" gate:
Output
Expressi
on
1M
Circuit
Diagram
1M
Page 8 / 26
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MODEL ANSWER
2. "NOT" gate using "Universal NAND" gate:
Output
Expressi
on
1M
Circuit
Diagram
1M
b) Explain following instructions for 8 bit and 16 bit data. 4M
(i) PUSH
(ii) DAA
(iii) IDJV
(iv) XOR
Note: Any other relevant registers shall also be considered in the
Ans example/explanation.
Explain
(i) PUSH ation of
Format: PUSH source each
½M
This instruction decrements the SP (Stack Pointer) register (by 2) and
copies the word specified by source to the location at the top of the
stack. Example
Here, Source can be a 16-bit general purpose register, segment for each
register or memory location. case
½M
Example- PUSH AX
OR
PUSH AX
This instruction decrements the stack pointer by 2 and copies the 16
bit data from AX register to the stack segment where the stack pointer
then points.
Page 9 / 26
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MODEL ANSWER
(ii) DAA
DAA stands for Decimal Adjust Accumulator AL after BCD
Addition
Explanation:
This instruction is used to make sure the result of adding
two packed BCD numbers is adjusted to be a correct BCD number.
The result of the addition must be in AL for DAA instruction to work
correctly. If the lower nibble in AL after addition is > 9 or Auxiliary
Carry Flag is set, then add 6 to lower nibble of AL. If the upper
nibble in AL is > 9H or Carry Flag is set, and then add 6 to upper
nibble of AL.
Example: - (Any Same Type of Example)
if AL=99 BCD and BL=99 BCD

Then ADD AL, BL
1001 1001 = AL= 99 BCD

+ 1001 1001 = BL = 99 BCD
----------------------------------------
0011 0010 = AL =32 H and CF=1, AF=1
After the execution of DAA instruction, the result is CF = 1
0011 0010 =AL =32 H AH =1
+ 0110 0110
-------------------------
1001 1000 =AL =98 in BCD
same type example for 16 bit can be considered.
OR
DAA instruction is used to convert the sum of two packed BCD
numbers in the register AL into a correct BCD number.
Example :
MOV AL, 23H

MOV BL, 47H
ADD AL, BL
DAA
After the execution of the above instructions, the result in AL = 70H.
Page 10 / 26
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MODEL ANSWER
(iii) IDJV
(NOTE: CONSIDER THE GIVEN INSTRUCTION AS IDIV):
Syntax : IDIV source
It divides a signed word in AX by an signed byte in source during
16/8 division. Also it is used to divide a signed double word in
DX,AX by an signed word in source during 16/8 division.
operation:
a. if the source is byte then
AL AL/signed 8 bit source
AH AL MOD signed 8 bit source
b. if the source is word then

AX DX,AX/signed 16 bit source
DX DX,AX MOD signed 16 bit source
OR
IDIV BL
This instruction is used to divide signed word in AX register by
signed byte in BL register. The quotient after division will be stored
in AL register, whereas the remainder is stored in AH register.
IDIV BX
This instruction is used to divide signed double word in DX,AX
register by signed word in BX register. The signed 16 bit quotient
will be stored in AX register, whereas the signed 16 bit remainder is
stored in AH register.
(iv) XOR − Used to perform Exclusive-OR operation over each bit

in a byte/word with the corresponding bit in another byte/word.
Syntax: XOR Destination, Source
Example:
For 8bit data:
XOR AL, BL
This instruction performs Exclusive-OR bit by bit at AL with BL and
the result is stored in AL..
For 16bit data:
XOR AX, BX
This instruction performs Exclusive-OR bit by bit word at AX with
word in BX and the result is stored in AX.
Page 11 / 26
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MODEL ANSWER
c) Draw waves for positive and negative triggering with proper 4M

labeling. Identify two situations where these triggering can be
used?
Ans. Note: Any additional relevant point related to triggering situation
shall be considered
Diagram
2M
Any
relevant
situation
1. Edge triggering can be used in flipflops as clock input. where
2. It is used in counters circuits. triggerin
3. They can be used in shift registers g is used
4. They can be used to synchronous data. 2M
d) Simplify Y=F(A, B,CD) 4M

=Σm (1, 2, 8, 9, 10, 12, 13) + d(4,5)
Using K-map and write expression
Ans Note: Solution is given considering Y=F(A, B,CD) as Y= F(A,
B,C,D)
Page 12 / 26
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MODEL ANSWER
Correct
K-map
2M
Correct
equation
2M
4 Attempt any THREE of the following 12

a) Suggest “Two instruction” for each of the following addressing 4M
modes.
(i) Register Addressing Mode.
(ii) Direct Addressing Mode
(iii) Based Indexed Addressing Mode
(iv) Immediate Addressing Mode.
Page 13 / 26
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MODEL ANSWER
Ans i) Register Addressing Mode: Conside

a. MOV AX, CX r any
b. AND AL, BL two
c. ROR AL, CL instructi
on,
ii) Direct addressing mode: each
a.MOV AL, [3000H] instructi
b. AND AX,[8000H] on
c.INC [4712H] ½M
iii) Based indexed Addressing mode:

1.MOV AX, [BX][SI]
2.ADD AL, [BX][DI]
3.MOV AX, [BX+SI]
iv) Immediate addressing mode:

1.MOV AL, 46H
2. MOV BX, 1234H
3. MOV DX, 0040H
b) Minimize the expression and draw logic circuit using basic gates. 4M
F (A,B,CD) = πm {0, 2, 4, 6, 7, 10, 11, 14, 15}
Ans. Note: Solution is given considering Y=F(A, B,CD) as Y= F(A,
B,C,D)
Correct
K-Map
2M
Page 14 / 26
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MODEL ANSWER
Simplifi
cation
1M
Logic
diagram
1M
c) Compare combinational and sequential circuits. Draw block 4M

diagram of sequential circuit and describe the function of each
block
Ans. Any 2
differen
ces
2M
Page 15 / 26
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MODEL ANSWER
Block
diagram
1M
1. Sequential logic circuits are those, whose output depends not only
on the present value of the input but also on previous values of the Explana
input signal. tion
2. Sequential circuit can be considered as combinational circuit with 1M
feedback circuit.
3. Sequential circuit uses a memory element like flip – flops as
feedback circuit in order to store past values.
d) i) Differentiate between RISC and CISC processor (Three point) 4M
ii) Compare 8086 and 80586 (Pentium)(3 points)
Ans i) Differentiate between RISC and CISC processor (Three point)
Sr. RISC
PARAMETER CISC PROCESSOR
No PROCESSOPR Any
1. Instruction set Few instructions More instructions three
points
2. Data types Few data types More data types
2M
3. Addressing Few Addressing More Addressing
mode modes modes
4. Registers Large number of Small number of
general purpose general purpose
registers registers & special
purpose registers.
5. Architecture Load/store architecture No load/store
type architecture
6. Operation Single- cycle Multi-cycle
7. Design Hardwired control Micro-coded
8. Instruction Set Fixed length Variable length

format
Page 16 / 26
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MODEL ANSWER
ii) Compare 8086 and 80586 (Pentium)(3 points)

Any
SR. 80586 three
PARAMETER 8086
NO (Pentium) points
1. Data Bus 16 bit 64 bit 2M
2 Address Bus 20 bit 32 bit
3 Physical memory 1 MB 4 GB
4 Register size 16 bit 32 bit
5 Voltage required 5V 3.3 V
6 Clock type 1x 3x
7 Pipelining Yes Yes
e) Draw 16:1 multiplexer using 4:1 multiplexers “ONLY” with 4M

proper labels.
Ans.
Correct
Diagram
3M
Proper
Labeling
1M
Page 17 / 26
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MODEL ANSWER
5 Attempt any TWO of the following: 12

a) Write algorithm and 8086 assembly language program to find
average salary of five employees of “SILICON Systems”. Assume 6M
4 digit salary of each employee. Also write output.
Ans. Note: Any other correct logic shall be considered.
ALGORITHM Algorith
1. START m
2. DEFINE ARRAY SALARY OF 5 NUMBERS EACH 4 DIGIT IN 2M
DATA SEGMENT
3. DEFINE VARIABLE AVG TO STORE RESULT IN DATA
SEGMENT
4. MOVE DATA IN AX
5. MOVE DATA FROM AX TO DS
6. MOVE NUM1 TO CX TO SET COUNTER
7. LOAD ADDRESS OF ARRAY SALARY TO BX
8. MOVE 0000H TO AX
9. ADD CONTENTS OF MEMORY POINTED BY BX TO AX
10. IF NO CARRY, GOTO STEP 12
11. INCREMENT DX REGISTER
12. INCREMENT BX TWICE TO POINT TO NEXT NUMBER
13. DECREMENT COUNTER CX; IF NOT ZERO GOTO STEP 9
14. DIVIDE THE SUM BY NUM1
15. STORE THE RESULT AX INTO AVG
16. END
PROGRAM
DATA SEGMENT
SALARY DW 4000H,5000H,6000H,7000H,8000H
NUM1 DW 05H
AVG DW ? Program
DATA ENDS 3M
CODE SEGMENT
ASSUME DS:DATA, CS:CODE
START:
MOV AX,DATA
MOV DS,AX
MOV CX,NUM1
MOV BX, OFFSET SALARY
MOV AX,0000H
Page 18 / 26
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MODEL ANSWER
L1: ADD AX, [BX]

JNC NEXT
INC DX
NEXT: INC BX
INC BX
LOOP L1
DIV NUM1
MOV AVG,AX
MOV AH,4CH
INT 21H
CODE ENDS
END START
Output
Output 1M
AVG=6000H
b) Refer Fig No. 1 and write truth table and output “Y”, write 6M
expression at output of gates. Redraw the Fig. No. 1.”
Fig No.1
Page 19 / 26
(Autonomous)

MODEL ANSWER
Truth Table
Truth Table
Input Output
A B C D Y
0 0 0 0 0
0 0 0 1 0
Ans 0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0 Truth
0 1 1 0 0 Table
0 1 1 1 0 3M
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Expressi
on at
output
of gates
3M
Page 20 / 26
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MODEL ANSWER
c) Draw minimum mode configuration of 8086 and explain the 6M

function of each block.
Ans.
Diagram
3M
When MN/ 𝑀𝑋 = 1 or connected to +VCC as shown in the figure, the

8086 microprocessor operates in minimum mode system. Explana
tion
 In this mode, the microprocessor chip itself gives out all the 3M
control signals. This is a single processor mode.
 The 8284 clock generator in the system is used to generate the
CLK and to synchronize some external signals with the system
clock. It is also used to generate RESET and READY signal
through wait state generator.
 Three 8282 address latches are used for separating the valid
address from the multiplexed address/data signals and the
controlled by the ALE signal generated by 8086.
 Two 8286 Transceivers are the bi-directional buffers. They are
required to separate the valid data from the time multiplexed
address/data signal. This is controlled by two signals, DEN &
DT/𝑅 .
Page 21 / 26
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MODEL ANSWER
6 Attempt any TWO of the following: 12

a) Draw architectural block diagram of 8086 microprocessor and 6M
describe the function of each block.
Ans Note: Any other relevant diagram shall be considered.
Internal architecture of Intel 8086: Explana
Intel 8086 is a 16 bit integer processor. It has 16-bit data bus and 20- tion of
bit address bus. The internal architecture of Intel 8086 is divided into blocks
two units, 3M
1. Bus Interface Unit (BIU)
2. Execution Unit (EU).
Bus Interface Unit (BIU )
Memory Interface:
The Bus Interface Unit (BIU) generates the 20-bit physical memory
address and provides the interface with external memory
(ROM/RAM). 8086 has a single memory interface.
Instruction Byte queue:
To speed up the execution, 6-bytes of instruction are fetched in
advance and kept in a 6- byte Instruction Queue while other
instructions are being executed in the Execution Unit (EU).
Segment registers:
There are four 16-bit segment registers, viz., the code segment (CS),
the stack segment (SS), the extra segment (ES), and the data segment
(DS). The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register.
Adder:
8086's BIU produces the 20-bit physical memory address by
combining a 16-bit segment address with a 16-bit offset address using
the adder circuit.
2. Execution Unit:
Control unit: The instructions fetched by BIU in the instruction byte
queue are decoded under the control of timing and control signals.
Arithmetic and Logic Unit (ALU) : Execution unit has a 16 bit
ALU, which performs arithmetic & logic operations.
General purpose register unit: All general registers of the 8086
microprocessor can be used for arithmetic and logic operations. The
general registers are: Accumulator register AL (8 bit), AX (AL & AH
for 16 bit), Base register, Count register, Data register , Stack Pointer
(SP), Base Pointer (BP), Source Index (SI), Destination Index (DI).
Flags: is a 16-bit register containing 9 1-bit flags: Overflow Flag
Page 22 / 26
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MODEL ANSWER
(OF), Direction Flag (DF), Interrupt-enable Flag (IF), Single-step

Flag (TF), Sign Flag (SF), Zero Flag (ZF), Auxiliary carry Flag (AF),
Parity Flag (PF), Carry Flag (CF).
Block
Diagram
3M
b) Design full adder using K-MAP and draw logic circuit using 6M
basic gates and write truth table.
Ans. Note : In logic diagram, instead of basic gates, Exclusive –OR
(EXOR) gates shall be considered.
Full Adder is the adder which adds three inputs and produces two
outputs. The first two inputs are A and B and the third input is an
input carry as Cin. The output carry is designated as Cout and the
normal output is designated as S which is SUM.
A full adder logic is designed in such a manner that can take eight
inputs together to create a byte-wide adder and cascade the carry bit
from one adder to the another.
Page 23 / 26
(Autonomous)

MODEL ANSWER
Truth Table
Truth
Table
2M
Based on the truth table, the Boolean functions for Sum (S) and Carry
– out (Cout) can be derived using K – Map.
For Sum S :
Page 24 / 26
(Autonomous)

MODEL ANSWER
The simplified equation for sum is

S = 𝐴𝐵 𝐶𝑖𝑛 + 𝐴𝐵𝐶𝑖𝑛 + 𝐴𝐵 𝐶 + 𝐴𝐵𝐶𝑖𝑛
=
For Carry – out (Cout ) :
K map
design
2M
The simplified equation for Coutis
Cout = AB + ACin + BCin
Logic Circuit Diagram
Logic
diagram
2M
Page 25 / 26
(Autonomous)

MODEL ANSWER
c) Write an assembly language program to find the largest number 6M

from an array of a 10 numbers. Assume suitable data.
Ans Note: Either 8bit or 16bit data shall be considered.
DATA SEGMENT
ARR DB 1,4,2,3,9,8,6,7,5,10
LN DW 10
L DB ? Correct
DATA ENDS logic
CODE SEGMENT 3M
ASSUME DS:DATA, CS:CODE
START:
MOV AX,DATA
MOV DS,AX Correct
LEA SI,ARR Instructi
MOV AL,ARR[SI] ons
MOV L,AL 3M
MOV CX,LN
REPEAT: MOV AL,ARR[SI]
CMP L,AL
JG NOCHANGE (or JNC NOCHANGE)
MOV L,AL
NOCHANGE: INC SI
LOOP REPEAT
MOV AH,4CH
INT 21H
CODE ENDS
END START
Page 26 / 26

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MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION

Q. Sub Answer Marking

Ans: Principle of multiplexer 1M

d) List features of 8086 microprpcessor.(Any four) 2M

Attempt any THREE of the following: 12-Total

Ans: Subtaction using 1‟s compliment

c) Differentiate between D FF and T FF. 4M

Input is transferred after a delay When T=1, output toggles

Used in shift registers Used in counters, frequency dividers

d) Describe the characteristics of digital IC’s (Any four). 4M

Ans: Characteristics of digital IC‟s are 1M

dst_arr dw 10(dup) ;empty array

mov ax,@data ;initialize data

mov cx,10 ; initialize counter

mov si,offset src_arr ;initialize memory pointer for source

mov di,offset dst_arr ;initialize memory pointer for destination

mov ax,[si] ;read number from source array

add si,2 ;increment source memory pointer

add di,2 ;increment destination memory pointer

Q.4 Attempt any THREE of the following : 12-Total

b) Minimize the four variable logic function using K- map. 4M

Ƒ(A,B,C,D) Ʃm (0, 1, 2, 3, 5, 7, 8, 9, 11, 14)

d) Describe the use of flag register and segment registers in 8086. 4M

Q.5 Attempt any TWO of the following 12-Total

Ans: DATA SEGMENT 6M

Q.6 Attempt any TWO of the following: 12Total

Ans: CONCEPT OF PIPELINING

The physical address is calculated as follows:

Where (X X X X)H 16 bit segment address

 A segment is a 64 K block, hence, there could be 16 non overlapping segments in 1 MB

Ans: Universal logic gates : 1M

NOR GATE AS AN UNIVERSAL GATES:

Ans: SHIFT AND ROTATE INSTRUCTIONS

2) SAR : Shift Arithmetic Right

2) SHL : Shift Left

3) SAL : Shift Arithmetic Left

5) ROL : Rotate Left

6) ROR : Rotate Right

7) RCL : Rotate Carry Left

8) RCR : Rotate Carry Right

After the comparison SI and DI will be automatically incremented or decremented according

SUMMER – 2019 EXAMINATION

Important Instructions to examiners:

Q. Sub Answer Marking

Debugger: Debugger is used to test and debug programs. The

SUMMER – 2019 EXAMINATION

2. Register Addressing Mode:

SUMMER – 2019 EXAMINATION

e) Convert following number into its equivalent Binary Number 2M

SUMMER – 2019 EXAMINATION

f) Define Minterm and Maxterm. 2M

SUMMER – 2019 EXAMINATION

g) Draw three variable K-map format. 2M

SUMMER – 2019 EXAMINATION

2 Attempt any THREE of the following: 12

SUMMER – 2019 EXAMINATION

c) Perform binary subtraction using 2's complement of the 4M

SUMMER – 2019 EXAMINATION