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Single Conversion stage AMplifier - SICAM
Ljusev, Petar
Publication date:
2006
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Citation (APA):
Ljusev, P. (2006). Single Conversion stage AMplifier - SICAM. Technical University of Denmark.
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Petar Ljušev
SIngle Conversion stage AMplifier

- SICAM
PhD thesis, December 2005

To Elena and Emma,
for their endless love and devotion
Preface
The work presented in this thesis is part of the project ”SICAM - SIngle Conversion
stage AMplifier”, funded by the Danish Energy Authority under the EFP2002 program,
J.nr. 1273/02-0001. The project was carried out at the Ørsted·DTU Automation depart-
ment within its Power Electronics Group (PEG) during the period November 15th 2002
to December 31st 2005. On the industry side, the cooperation with Bang & Olufsen ICE-
power a/s in Kgs. Lyngby has given additional quality to the project, by emphasizing its
relevance and importance within the extremely ”crowded” consumer audio market.
Part of the work concerning the direct audio power amplifiers for portable applications
and their digital modulators was conducted during my 1,5 months long external research
stay in the Laboratory for Low Power Management and Integrated SMPS at the University
of Toronto in Canada, under the supervision of Professor Aleksandar Prodić.
First I would like to express deepest gratitude to my supervisor Professor Michael
A.E. Andersen for taking me as his Ph.D. student to work on this highly interesting
topic, providing unbounded support for my wide research interests, managing the practical
issues about the demanding project, as well as spending lots of hours on fruitful discussions
and sharing his vast knowledge. Together with the colleagues from the Power Electronics
Group and the Ørsted·DTU Department, they are most responsible for making me feel
so comfortable and secure.
The practical relevance and technical appeal of the project would be much less pro-
nounced, if it was not for the tremendous effort shown by my second supervisor Lars
Petersen, from the cooperating company Bang & Olufsen ICEpower. His curious remarks
and on-place questions have always provoked me to rejudge the conclusions and find a
way out of the large maze I was put into when undertaking this project. The enthusiastic
B&O ICEpower employees showing me around the labs and attending my presentations
helped me build a serious approach so needed when tackling such a relevant subject.
Another thanks goes to my external research supervisor Professor Aleksandar Prodić
from the University of Toronto, for allowing me to spend a challenging few weeks in his
”fully digital world” and sharing his ideas and opinions, making the time spent in Toronto
an unforgettable experience.
During these three stressful years of hard work, tight schedules and numerous obliga-
tions, I have always found a peaceful shelter and source of endless joy and fulfilment in my
closest family - my wife Elena and our little daughter Emma. I would like to thank you
for being always by my side and showing me that the most important things in life cannot
be represented by equations, expressed in numbers nor measured in physical units...
Kongens Lyngby Petar Ljušev

December 2005
Abstract
This Ph.D. thesis presents a thorough analysis of the so called SICAM - SIngle Converter
stage AMplifier approach to building direct energy conversion audio power amplifiers.
The mainstream approach for building isolated audio power amplifiers today consists
of isolated DC power supply and Class D amplifier, which essentially represents a two
stage solution, where each of the components can be viewed as separate and independent
part. The proposed SICAM solution strives for direct energy conversion from the mains
to the audio output, by dedicating the operation of the components one to another and
integrating their functions, so that the final audio power amplifier represents a single-stage
topology with higher efficiency, lower volume, less board space, lower component count
and subsequently lower cost.
The SICAM approach is both applicable to non-isolated and isolated audio power
amplifiers, but the problems encountered in these two cases are different. Non-isolated
SICAM solutions are intended for both AC mains-connected and battery-powered de-
vices. In non-isolated mains-connected SICAMs the main idea is to simplify the power
supply or even provide integrated power factor correction (PFC) functions, while still
maintaining low component stress and good audio performance by generally decreasing
the input voltage level to the Class D audio power amplifier. On the other hand, non-
isolated battery-powered SICAMs have to cope with the ever changing battery voltage and
provide output voltage levels which are both lower and higher than the battery voltage,
while still being simple and single-stage energy conversion solutions. In isolated SICAMs
the isolation transformer adjusts the voltage level on the secondary side to the desired
level, so the main challenges here are decreasing the size of the magnetic core and reducing
the number and size of bulky reactive components as much as possible.
The main focus of this thesis is directed towards the isolated SICAMs and especially the
so called isolated SICAM with non-modulated transformer voltages. The latter is found
to be the most interesting isolated SICAM solution for the modern multichannel audio
power amplification systems, since all of the output stages corresponding to the different
audio channels can reuse the same input stage and transformer core. While the proposed
approach tends to be very simple from topological perspective and allows for reduction of
reactive component count, the commutation of the load current in the output bridge and
the bridge itself are much more complicated than their Class D predecessors.
The main contribution of the thesis can be found in the thorough analysis of the
present topologies for isolated SICAMs, as well as the numerous structural improvements
and several newly proposed control methods for alleviating the problem of load current
commutation and high-performance control of the whole SICAM. Another significant
contribution is the presentation of several interesting topologies and associated control
principles in the field of non-isolated SICAMs for mains-connected and portable audio
amplifiers.
Resumè (Abstract in Danish)
Denne Ph.D. afhandling giver en grundig analyse af den så kaldte SICAM - SIngle Con-
verter stage AMplifier fremgangsmåde til opbygning af audio effektforstærkere til direkt
energiomforming. Den aktuelle fremgangsmåde til opbygning af isolerede audio effekt-
forstærkere i dag består af en isoleret DC elforsyning efterfulgt af en Klasse D audio
effektforstærker, som faktisk repræsenterer to-trins løsning, hvor hver halvdel kan ses som
seperat og uafhengig del. Den foreslåede SICAM-løsning stræber efter så direkte energiom-
forming fra lysnetindgangen til audioudgangen som overhovedet muligt, ved at dedikere
virkningsmåden af delene til hinanden og integrere deres funktioner således, at den en-
delige audio effektforstærker repræsentere en en-trins topologi med højere effektivitet,
mindre volumen, mindre printareal, færre komponenter og dermed lavere omkostninger.
SICAM fremgangsmåden kan bruges til både uisolerede og isolerede audio effekt-
forstærkere, men problemstillingerne som i de to tilfælde er i grunden meget forskellige.
Uisolerede SICAMs anvendes til både lysnettilsluttede og batteridrevne apparater. Hov-
edideen i de uisolerede lysnettilsluttede SICAMs er at forenkle spændingsforsyningen og
lave PFC-funktion, mens det lav komponentstress og den god audioperformance bevares
ved at reducere indgangsspændingen til Klasse D forstærkeren. Uisolerede batteridrevne
SICAMs skal klare den varierende batterispænding og skabe en udgangsspænding, som er
både lavere og højere end batterispænding, men de skal stadigvæk være simple og en en-
trins energiomformer. I transformatoren i isolerede SICAMs designes spændingsniveauet
på sekundæren til det ønskede niveau og derfor er de vigtigste udfordringer her at reducere
volumen af den magnetiske kerne og reducere antallet af reaktive komponenter så meget
som muligt.
Hovedfokus i denne afhandling ligger på isolerede SICAMs og især de såkaldte isol-
erede SICAM med umodulerede transformatorspændinger. Den ovennævnte omformer er
den mest interessante SICAM-løsning til multikanalens audio effektforstærkersystemer,
fordi alle udgangstrinnene kan bruge det samme indgangstrin og den samme transforma-
torkerne. Den foreslåede løsning er meget enkelt fra en topologiside og tillader reduktion
af antalet of reaktive komponenter på sekundærsiden, men kommuteringen af belast-
ningsstrømmen i udgangstrinnet og udgangstrinnets ombygning selv er mere indviklet
end i Klasse D forstærkeren.
Afhandlingens hovedbidrag findes i den grundige analyse af nuværende topologier for
isolerede SICAMs, såvel som flere strukturele forbedringer og nogle foreslåede kontrol
metoder til at forbedre kommuteringen af belastningsstrømmen i udgangstrinnet og re-
alisere højperformance styring af hele SICAM-trinnet. Det anden væsentlige bidrag er
fremvisningen af adskillige interessanter topologier og deres styrestrategier til uisolerede
SICAMs til lysnettilslutning og brbare audio effektforstærkere.
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1 Linear audio power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2 Switching-mode audio power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3 SICAM project and problem definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.4 Need for energy storage on a single-phase AC-mains . . . . . . . . . . . . . . . . . . . . 22
1.5 Thesis outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Part I Non-isolated SICAMs
2 Matrix SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.1 Matrix converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2 Single-phase AC to single-phase AC matrix converter . . . . . . . . . . . . . . . . . . . 29
2.3 Two-phase AC to single-phase AC matrix converter . . . . . . . . . . . . . . . . . . . . 31
2.3.1 2ph-AC to 1ph-AC matrix converter without a central tap . . . . . . . . . . 33
2.3.2 2ph-AC to 1ph-AC matrix converter with fixed central tap . . . . . . . . . 34
2.3.3 2ph-AC to 1ph-AC matrix converter with switched central tap . . . . . . 35
2.3.4 Switching strategies for 2ph-AC to 1ph-AC matrix converter with
switched central tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.5 Obtaining another phase- lagging/leading voltage from AC-mains . . . 42
2.4 Matrix SICAM with LC-network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.4.1 Analysis of matrix SICAM switching between LkR and CkR . . . . . . . 47
2.4.2 Time domain analysis of the two load combinations . . . . . . . . . . . . . . . 51
2.4.3 HF switching of matrix SICAM for constructing the audio waveform . 52
2.4.4 Design of matrix SICAM with resonant LC-network . . . . . . . . . . . . . . . 53
2.4.5 Design example of matrix SICAM with resonant LC-network . . . . . . . 56
2.4.6 Influence of the output low-pass filter Lf , Cf . . . . . . . . . . . . . . . . . . . . . 57
2.4.7 Open-loop control principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.4.8 Simulations of matrix SICAM with LC-network . . . . . . . . . . . . . . . . . . . 63
2.5 Conclusion about matrix SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3 AC-mains connected Class D audio power amplifiers as SICAMs . . . . . 71

3.1 Non-isolated DC power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.2 Class D audio power amplifier with non-isolated DC power supply . . . . . . . . 73
3.3 Class D audio power amplifier with step-down PFC front-end . . . . . . . . . . . . 75
3.4 Combined Class D audio power amplifier and PFC . . . . . . . . . . . . . . . . . . . . . 76
3.4.1 Combined Class D audio power amplifier and boost PFC . . . . . . . . . . . 78
3.4.2 Combined Class D audio power amplifier and buck-boost PFC . . . . . . 83
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
XIV Contents
4 SICAM for portable devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.1 Single-stage step-up audio power amplifier topology for portable applications 89
4.2 Digital audio modulator for the double-boost SICAM . . . . . . . . . . . . . . . . . . . 91
4.2.1 Implementation of the digital modulator . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.2.2 Precompensator noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2.3 Simplified control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.3 Simulation of the double-boost SICAM with digital modulator . . . . . . . . . . . 100
4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Part II Isolated SICAMs
5 Introduction to isolated SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.1 Conventional solution with isolated SMPS and Class D audio power amplifier109
5.2 Isolated audio power amplification through HF-link conversion . . . . . . . . . . . 110
5.3 Frequency domain analysis of different PWM SICAM solutions . . . . . . . . . . . 111
5.3.1 Time domain and frequency domain operations of power electronics . 111
5.3.2 Audio amplification with only a primary side switching stage . . . . . . . 113
5.3.3 Coding and decoding of the audio signals for isolated amplifiers . . . . . 113
5.3.4 SICAM with modulated transformer voltages . . . . . . . . . . . . . . . . . . . . . 115
5.3.5 SICAM with non-modulated transformer voltages . . . . . . . . . . . . . . . . . 115
5.4 Developing SICAMs from SMPSs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.5 Bidirectional switches and gate drives for isolated SICAMs . . . . . . . . . . . . . . 118
5.5.1 Bidirectional switch arrangements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.5.2 Gate drives for bidirectional switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.6 Other possible approaches for isolated SICAMs . . . . . . . . . . . . . . . . . . . . . . . . 124
5.7 Patent investigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6 Topologies for isolated SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

6.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.1.2 Topologies for the input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.1.3 Resonant converter as input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.1.4 Soft-switched ZVS PWM inverter as input stage . . . . . . . . . . . . . . . . . . 138
6.1.5 Hard-switched DC-AC inverter as input stage . . . . . . . . . . . . . . . . . . . . . 147
6.1.6 Integration of the inverter input stage within the SICAM . . . . . . . . . . 147
6.1.7 Overdimensioning of the input stage in SICAMs . . . . . . . . . . . . . . . . . . 148
6.2 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.2.1 Commutation of the load current in the output stage through
safe-commutation switching sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.2.2 Commutation of the load current in the output stage with load clamps160
6.2.3 SICAM with active capacitive voltage clamp . . . . . . . . . . . . . . . . . . . . . . 162
6.3 Output impedance of isolated SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.4 Power losses and efficiency calculation in SICAMs . . . . . . . . . . . . . . . . . . . . . . 170
6.4.1 Current and voltage levels in SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.4.2 Power losses in SICAM components and stages . . . . . . . . . . . . . . . . . . . 174
6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Contents XV
7 Control methods for isolated SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

7.1 Unsynchronized control of both stages in isolated SICAMs . . . . . . . . . . . . . . . 195
7.1.1 Simple PWM modulator for unsynchronized operation . . . . . . . . . . . . . 195
7.1.2 Master/Slave operation of the input/output stage to accomplish
output stage safe commutation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.2 Synchronized control of both stages in isolated SICAMs . . . . . . . . . . . . . . . . . 199
7.2.1 Simple synchronized PWM method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
7.2.2 Optimized PWM method with synchronization and lower output
stage switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
7.2.3 Frequency spectrum of the new optimized PWM method in general
case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.3 Self-oscillating modulators for isolated SICAMs - SOHF . . . . . . . . . . . . . . . . . 206
7.3.1 Application and limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7.3.2 Operation fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
∗
7.3.3 Normal operation with M < Mlim ............................... 209
∗
7.3.4 Locked operation with M ≥ Mlim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.3.5 Output stage switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.3.6 Audio distortion of self-oscillating SICAM . . . . . . . . . . . . . . . . . . . . . . . . 212
7.4 Closed-loop control schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
8 Prototypes of isolated SICAMs with non-modulated transformer

voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
8.1 Isolated SICAM with master/slave operation for achieving safe commutation217
8.2 Isolated SICAM with simple PWM modulator and active capacitive load
voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.3 Isolated SICAM with optimized PWM modulator and safe-commutation
switching sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.4 Isolated self-oscillating SICAM with GLIM modulator . . . . . . . . . . . . . . . . . . 222
8.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
9 4Q flyback SICAM with modulated transformer voltages . . . . . . . . . . . . 229

9.1 Operation and design of 4Q flyback SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
9.2 Control of 4Q flyback SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
9.2.1 Peak current-mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
9.2.2 Average current-mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
9.3 Measurements on a 4Q flyback SICAM prototype with average
current-mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
9.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
10 Integrated magnetics for isolated SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

10.1 Analysis of the integrated magnetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
10.2 Application to HF-link converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
10.2.1Practical investigation of the proposed integrated magnetics . . . . . . . . 242
10.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
11 General conclusion about SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

XVI Contents
A Analysis of matrix SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

A.1 Time domain analysis of the two load combinations . . . . . . . . . . . . . . . . . . . . . 247
A.1.1 Time domain analysis of CkR combination . . . . . . . . . . . . . . . . . . . . . . . 247
A.1.2 Time domain analysis of LkR combination . . . . . . . . . . . . . . . . . . . . . . . 250
A.2 State-space model of matrix SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
B Analysis of combined mains-connected Class D audio power amplifier

and PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
B.1 Analysis of combined Class D audio power amplifier and boost PFC . . . . . . 257
B.2 Analysis of the synchronous operation of the combined Class D audio
power amplifier and buck-boost PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
B.3 Analysis of the asynchronous operation of the combined Class D audio
power amplifier and buck-boost PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
C Analysis of double-boost SICAM for portable applications . . . . . . . . . . . 295
D Analysis of flyback auxiliary converter for SICAM with active

capacitive voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
D.1 Analysis of CCM flyback auxiliary converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
D.2 Analysis of DCM flyback auxiliary converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
E Analysis of control methods for SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

E.1 Frequency spectrum of different PWM waveforms in isolated SICAMs . . . . . 309
E.1.1 Double Fourier Series of FN ADS,1h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
E.1.2 Double Fourier Series of FN ADS,2h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
E.1.3 Double Fourier Series of FN ADD,1h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
E.1.4 Double Fourier Series of FN ADD,2h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
E.2 Switching frequency of GLIM self-oscillating modulator . . . . . . . . . . . . . . . . . 313
F Prototype schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

F.1 Schematics of isolated SICAM with master/slave operation . . . . . . . . . . . . . . 315
F.2 Schematics of isolated SICAM with active capacitive load voltage clamp . . . 315
F.3 Schematics of isolated SICAM with optimized PWM modulator and
safe-commutation switching sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
F.4 Schematics of isolated self-oscillating SICAM with GLIM modulator . . . . . . 315
F.5 Schematics of 4Q flyback SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Contents of inclosed CDROM
• PhD thesis
– single file
– multiple files
• Orcad
– PSpice simulation files
– PCB files
• MATLAB
– My functions
– SICAM design
• VHDL Verilog
– Safe-commutation algorithm
– Double-boost SICAM control
• References
• My articles
List of Figures
1.1 I-V characteristics of MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.2 Linear audio power amplifier with MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3 Power supply voltage and load voltage with linear audio power amplifier . . 16
1.4 Switching-mode audio power amplifier with MOSFETs . . . . . . . . . . . . . . . . . 18
1.5 PWM bridge voltage and load voltage with switching-mode audio power
amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.6 Equivalent scheme of MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.7 Block diagram of completely switching-mode audio power amplifier . . . . . . . 19
1.8 Simple block diagram of SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.9 Dedication of the SMPS to the audio power amplifier in SICAM . . . . . . . . . 21
1.10 Comparison of linear amplifiers, switching-mode amplifiers and SICAMs . . 22
2.1 M-phase to N-phase matrix converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.2 M-phase to N-phase matrix converter with central tap in the M-th line . . . 28
2.3 Single-phase to single-phase matrix converter . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.4 Bounding region for the output voltage of a single-phase to single-phase
matrix converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5 Upper and lower bounds of the input voltages of a two-phase to
single-phase matrix converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6 Upper and lower bounds of the input voltages of a two-phase to
single-phase matrix converter in the optimal case φ = π/2 . . . . . . . . . . . . . . . 33
2.7 2ph-AC to 1ph-AC matrix converter without a central tap . . . . . . . . . . . . . . 33
2.8 Bounding region for the output voltage of a 2ph-AC to 1ph-AC matrix
converter without a central tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.9 2ph-AC to 1ph-AC matrix converter with fixed central tap . . . . . . . . . . . . . . 35
converter with fixed central tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.11 2ph-AC to 1ph-AC matrix converter with switched central tap . . . . . . . . . . . 36
converter with switched central tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.13 Diagonal switching: a) type A and b) type B . . . . . . . . . . . . . . . . . . . . . . . . . . 38
converter with switched central tap in case of diagonal switching strategy
- type A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.15 Time diagram for the diagonal switching strategy - type A . . . . . . . . . . . . . . 40
2.16 Phasor diagram for input voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.17 Phasor diagram for input voltages and output voltage . . . . . . . . . . . . . . . . . . 41
2 List of Figures
2.18 Distribution of switching patterns’ time intervals through one switching

interval Ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.19 L − R series circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.20 C − R series circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.21 L − C − R series circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.22 L − C − R parallel circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.23 Parallel-loaded resonant converter used for obtaining another voltage phase 45
2.24 MC-based SICAM with an LC-network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.25 General topologies: a) vin kR, b) LkR and c) CkR . . . . . . . . . . . . . . . . . . . . . . 46
2.26 Loading the LC-network with an additional resistor Ra . . . . . . . . . . . . . . . . . 48
2.27 Steady-state voltages in MC-based SICAM with resonant LC-network
and R/ωL=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.28 Approximate transient voltages in MC-based SICAM with resonant
LC-network and R/ωL=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.29 Possible topologies for the MC-based SICAM with loaded LC-network . . . . 53
2.30 Matrix SICAM with LC-network and output low-pass filter . . . . . . . . . . . . . 57
2.31 Frequency characteristic of the input impedance Zin (f ) of the output filter 58
2.32 Open-loop control principles: a) AM of the triangular carrier and b) ∆
modulation technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.33 AM of triangular carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.34 ∆ modulation control principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.35 Matrix SICAM with LC-network and purely resistive load (m=0,8,
f=10 kHz) - Top: Output voltage vout , Middle: FFT up to 1 MHz, Bottom:
FFT up to 30 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.36 Matrix SICAM with LC-network and purely resistive load (m=0,8,
f=10 kHz) - Top: Input voltage vin , capacitor voltage vC and inductor
voltage vL , Middle: Input current iin , capacitor current iC and inductor
current iL , Bottom: AM of triangular carrier . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.37 MC-based SICAM using an LC-network (m=0,8, f=10 kHz) - Top: Output
voltage vout , Middle: FFT up to 1 MHz, Bottom: FFT up to 30 kHz . . . . . . 68
2.38 MC-based SICAM using an LC-network (m=0,8, f=10 kHz) - Top: Input
voltage vin , capacitor voltage vC and inductor voltage vL , Middle: Input
current iin , capacitor current iC and inductor current iL , Bottom: AM of
triangular carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.1 Non-isolated DC power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.2 Voltage and current of the input storage capacitor . . . . . . . . . . . . . . . . . . . . . 72
3.3 Class D audio power amplifier with non-isolated DC power supply . . . . . . . 73
3.4 Class D audio power amplifier with step-down PFC front-end . . . . . . . . . . . . 75
3.5 SEPIC PFC preregulator [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.6 Full-bridge Class D audio power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.7 Variations in the output voltage and duty cycles . . . . . . . . . . . . . . . . . . . . . . . 78
3.8 Combined Class D audio power amplifier and boost PFC . . . . . . . . . . . . . . . 78
3.9 Possible connections in the combined Class D audio power amplifier and
boost PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.10 Combined Class D audio power amplifier and boost PFC with two boost
inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.11 Control diagram of a combined Class D audio power amplifier and boost
PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
List of Figures 3
3.12 Simulated waveforms of combined Class D audio power amplifier and

boost PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.13 Combined Class D audio power amplifier and buck-boost PFC: a) with 4
switches and a freewheeling diode, b) with 2 switches and a freewheeling
diode, c) with 2 switches, and d) one possible realization of the switch . . . . 83
3.14 Possible connections in the synchronously-operated combined Class D
audio power amplifier and buck-boost PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.15 Possible connections in the asynchronously-operated combined Class D
4.1 Double boost SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.2 Possible connections in the double-boost SICAM . . . . . . . . . . . . . . . . . . . . . . . 91
4.3 Digital modulator for the double-boost SICAM . . . . . . . . . . . . . . . . . . . . . . . . 92
4.4 Digitized sinewave with corresponding duty cycles for double-boost SICAM 94
4.5 Static transfer functions of the buck converter and double-boost SICAM . . 95
4.6 Static transfer functions of the buck converter and precompensated
double-boost SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.7 Precompensator RMS noise levels epr,rms with b2 = 5 . . . . . . . . . . . . . . . . . . . 99
4.8 Simplified control block diagram of digitally controlled double-boost SICAM 99
4.9 CRFB Σ − ∆ noise-shaper structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.10 Normalized output voltage vo /vb of the fully-digital double-boost SICAM
without feedback from the precompensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
with feedback from the precompensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
without feedback from the precompensator as a function of the modulation
index M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
without feedback from the precompensator as a function of the selected
linearizing coefficients k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
with feedback from the precompensator as a function of the modulation
index M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
with feedback from the precompensator as a function of the selected
linearizing coefficients k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
with feedback from the precompensator as a function of the number of
bits b4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.1 Conventional Class D audio power amplifier with isolated SMPS . . . . . . . . . 110
5.2 Direct conversion audio power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.3 Half-bridge schematic with the associated voltages and switching functions 112
5.4 Full-bridge schematic with the associated voltages and switching functions 112
5.5 Time and frequency domain analysis of full-bridge switching stage . . . . . . . . 112
5.6 Isolated audio power amplifier with only a primary-side switching stage . . . 113
5.7 2-level double-sided PWM signal FN ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.8 Frequency spectrum of FN ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.9 Rectangular pulse train Fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.10 Frequency spectrum of Fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4 List of Figures
5.11 Resultant PWM signal FN ADD · Fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.12 Frequency spectrum of FN ADD · Fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.13 SICAM with modulated transformer voltages . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.14 SICAM with non-modulated transformer voltages . . . . . . . . . . . . . . . . . . . . . . 117
5.15 SICAM development steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.16 Reworking a half-bridge SMPS for SICAM operation . . . . . . . . . . . . . . . . . . . 119
5.17 a) Voltage 2QSW, b) Current 2QSW, c) Antiparallel connection of two
voltage 2QSW, d) Antiseries connection of two current 2QSW . . . . . . . . . . . 119
5.18 Different arrangements of bidirectional switches (4QSW) . . . . . . . . . . . . . . . . 121
5.19 Test bench for bidirectional switches (4QSW) . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.20 THD+N as function of power at 1 kHz for 4QSW with one MOSFET and
four diodes in Fig. 5.18a measured before (bottom) and after (top) the
4QSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.21 THD+N as function of power at 1 kHz for 4QSW with two MOSFETs
and two diodes in Fig. 5.18b measured before (bottom) and after (top)
the 4QSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.22 THD+N as function of power at 1 kHz for 4QSW with two common-source
connected MOSFETs in Fig. 5.18c measured before (bottom) and after
(top) the 4QSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.23 THD+N as function of power at 1 kHz for 4QSW with just a single
Junction FET shown in Fig. 5.18d measured before (bottom) and after
(top) the 4QSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.24 a) Conventional grounding scheme for HF-link converters and b) Newly
proposed grounding scheme for easy level shifting . . . . . . . . . . . . . . . . . . . . . . 124
5.25 Negative voltage-tolerant level shifter and gate driver . . . . . . . . . . . . . . . . . . . 125
5.26 Circuit diagram from [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.34 Circuit diagram from [10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.1 Class D resonant converter types: a) series LC, b) parallel LC and

c) series-parallel LCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.2 Series-parallel LCC resonant converter loaded with bidirectional full-bridge
amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3 Output impedance of an SPRC for L = 11, 6µH and Cs = Cp = 5, 88nF . . 137
6.4 ZVS PWM inverter: a) power delivered to the load, b) capacitance of
T3 gets discharged, c) freewheeling cycle and d) capacitance of T2 gets
discharged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.5 ZVS PWM inverter output voltage v1 and switching waveforms:
a) phase-shift ZVS PWM inverter and b) simultaneous ZVS PWM inverter 140
List of Figures 5
6.6 ZVS PWM inverter with reflected load current in opposite direction from
the magnetizing current: a) power regenerated from the load through D1
and D3 , b) T4 is turned off with ZVS, c) capacitance of T4 gets charged
and T3 gets discharged and d) capacitance of T1 gets charged and T2 gets
discharged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.7 Soft-switched PWM inverter switching losses dependance on reflected load
′
current Iload for two different magnetizing currents Im1 = 2Im2 . . . . . . . . . . . 142
6.8 Determining the resonant capacitance Cr when switching: a) single leg
and b) both legs at the same time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.9 Input and output stage output voltage waveforms: a) PDM and b) PWM,
with the dashed line showing the desired output stage output voltage . . . . . 148
6.10 Electrical scheme: a) Conventional SMPS + Class D audio power amplifier
and b) SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.11 Class D audio power amplifier average MOSFET currents and average
secondary-side SMPS and SICAM currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.12 Full-bridge bidirectional SICAM output stage . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.13 Scheme of SICAM with single-ended output stage . . . . . . . . . . . . . . . . . . . . . . 154
6.14 Commutation diagrams with positive and negative HF-link voltages and
load currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.15 State diagram of the safe-commutation switching sequence . . . . . . . . . . . . . . 156
6.16 Average voltage error with ∆tnc,max < ∆td (above) and ∆tnc,max > ∆td
(below) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.17 THD of a safe-commutated SICAM with different secondary-side leakage
inductances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6.18 Isolated SICAM with output filter and load clamp . . . . . . . . . . . . . . . . . . . . . 161
6.19 Isolated SICAM with an active capacitive voltage clamp . . . . . . . . . . . . . . . . 162
6.20 Time waveforms of the active clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.21 Buck-boost auxiliary converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.22 Averaged switch model of the DCM flyback auxiliary converter . . . . . . . . . . 166
6.23 Small-signal AC model of DCM flyback auxiliary converter . . . . . . . . . . . . . . 167
6.24 Current-mode control of the auxiliary converter . . . . . . . . . . . . . . . . . . . . . . . . 168
6.25 Average voltage error ve of the SICAM with active capacitive voltage clamp 168
6.26 THD of SICAM with active capacitive voltage clamp . . . . . . . . . . . . . . . . . . . 169
6.27 Simplified schematic of SICAM for determining output impedance . . . . . . . 170
6.28 Relationship between the duty cycle and the normalized peak filter ripple
current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.29 Relationship between the modulation index and the normalized average
and RMS filter ripple current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.30 Switching transitions of the upper MOSFET in a switching leg driven
with 0, VG : a) schematic and b) waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.31 Switching transitions of the upper MOSFET in a switching leg driven
with ±VG : a) schematic and b) waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.32 Core losses Pf e , copper losses Pcu and total losses PT R as a function of the
primary number of turns N1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.33 a) Bidirectional switch and b) Voltage drop across the reverse conducting
MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.34 Energy stored in the parasitic output capacitance ECds and energy stored
in the transformer secondary leakage inductance ELsl . . . . . . . . . . . . . . . . . . . 188
6.35 Output filter: a) half circuit and b) full circuit . . . . . . . . . . . . . . . . . . . . . . . . . 189
6 List of Figures
7.1 Modified PWM modulator for SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

7.2 FFT (top) and THD+N (bottom) of two unsynchronized SICAMs with
and without tight control of switching frequencies . . . . . . . . . . . . . . . . . . . . . . 197
7.3 Master/slave control of isolated SICAM with safe commutation switching
strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
7.4 PWM method with 3 switchings during one carrier period Tc2 . . . . . . . . . . . 200
7.5 Proposed PWM method with 2 switchings during one carrier period Tc2 . . . 201
7.6 Optimized PWM modulator for SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.7 The new PWM pulse train (top) and its two constitutive parts (below) . . . 203
7.8 Frequency spectrum of the conventional PWM method FN ADD with
M = 0.1, fm = 10 kHz, fs1 = 150 kHz, fc2 = 300 kHz . . . . . . . . 204
7.9 Frequency spectrum of the new PWM method FN P W M with M = 0.1,
fm = 10 kHz, fs1 = 150 kHz, fc2 = 300 kHz . . . . . . . . . . . . . . . . . 205
7.10 Magnitudes of the switching harmonics in FN P W M with varying
modulation index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7.11 GLIM SOHF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7.12 Practical implementation of GLIM modulator for: a) Class D audio power
amplifier and b) SOHF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
7.13 Schematic of GLIM for Class D audio power amplifier . . . . . . . . . . . . . . . . . . 208
∗
7.14 Normal operation with M < Mlim .................................... 210
∗
7.15 Locked operation with M ≥ Mlim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.16 Asymptotic stability of the locked operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
7.17 Output stage switching frequency, transferred charge and clamp power (in
SICAMs with load voltage clamp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.18 THD of SICAM with active capacitive voltage clamp . . . . . . . . . . . . . . . . . . 213
7.19 Block diagram of simple output voltage control . . . . . . . . . . . . . . . . . . . . . . . . 214
7.20 Control block diagram of cascade control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
8.1 Photograph of the prototype master/slave-operated SICAM . . . . . . . . . . . . . 218

8.2 Detailed master/slave SICAM operation: 1) Input stage M/S line driver
base voltage, 2) output stage M/S line driver base voltage, 3) M/S line
voltage, and 4) input stage voltage polarity (T1 /T4 driving signal) (all
probes 10x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
8.3 Safe-commutation switching sequence: 1) MOSFETs 1&6 driving signal,
2) MOSFETs 2&5 driving signal, 3) MOSFETs 3&8 driving signal, and
4) MOSFETs 4&7 driving signal for negative rail voltage (all probes 10x) . 219
8.4 Open-loop operation with 10 kHz reference: 1) load voltage, 2) bridge
voltage, and 3) reference signal (probes 1 and 2 - 50x, 3 - 10x) . . . . . . . . . . . 219
8.5 Closed loop operation at Pout =0 W with 10 kHz reference: 1) load voltage,
2) reference signal, and M1) FFT (probe 1 - 50x, probe 2 - 10x) . . . . . . . . . 219
8.6 Closed loop operation at Pout =1 W with 10 kHz reference: 1) load voltage,
2) reference signal, and M1) FFT (probe 1 - 50x, probe 2 - 10x) . . . . . . . . . 219
8.7 Closed loop operation at Pout =10 W with 10 kHz reference: 1) load
voltage, 2) reference signal, and M1) FFT (probe 1 - 50x, probe 2 - 10x) . . 219
8.8 Photograph of the prototype SICAM with active capacitive voltage clamp . 220
8.9 Detailed SICAM operation: 1) HF-link voltage (100V/div), 2) bridge
voltage (100V/div), 3) voltage reference (2V/div), 4) output voltage
(5V/div) with 10 kHz reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
List of Figures 7
8.10 SICAM operation: 1) HF-link voltage (100V/div), 2) bridge voltage

(100V/div), 3) voltage reference (2V/div), 4) output voltage (5V/div)
with 10 kHz reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.11 THD+N versus frequency (BW=22kHz and AES17 filter): top - 10 W,
bottom - 50 W, middle - 75 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.12 THD+N versus power (BW=22kHz and AES17 filter): bottom - 100 Hz,
middle - 1 kHz, top - 6.67 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.13 Intermodulation distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.14 FFT at 50 W with a signal of 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.15 Distribution of power losses in prototype SICAM with active clamp . . . . . . 224
8.16 Theoretical efficiency of the prototype SICAM with active clamp
(”T”-shaped markings represent the targeted minimum efficiency) . . . . . . . . 224
8.17 Measure efficiency of the SICAM prototype with active clamp (”T”-shaped
markings represent the targeted minimum efficiency) . . . . . . . . . . . . . . . . . . . 224
8.18 Photo of the prototype SICAM with safe-commutation switching sequence 224
8.19 SICAM safe-commutation switching sequence with vHF > 0: 1) SW21,
2) SW22, 3) SW23, 4) SW24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.20 SICAM safe-commutation switching sequence with vHF > 0: 1) SW21,
2) SW22, 3) SW23, 4) SW24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.21 Optimized PWM method for SICAMs: 1) PWM with positive signal,
2) PWM with negative signal, 3) resultant PWM, 4) HF-link voltage . . . . . 225
8.22 SICAM safe-commutation switching sequence with vHF > 0: 1) reference
voltage, 2) triangular carrier, 3) bridge voltage, 4) HF-link voltage . . . . . . . 225
8.23 SICAM waveforms at Po =25 W: 1) reference voltage, 2) output voltage
3) bridge voltage, 4) HF-link voltage(50x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.24 SICAM waveforms at Po =25 W: 1) ref. voltage, 2) out. voltage 3) bridge
voltage, 4) HF-link voltage(50x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.25 THD+N vs. frequency at Po =10 W (top) and Po =40 W (bottom) . . . . . . . . 226
8.26 THD+N vs. output power at fo =100 Hz (bottom), fo =1 kHz (middle)
and fo =6.67 kHz (top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.27 Intermodulation distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.28 FFT of the output voltage at Po =25 W (100 W reference) . . . . . . . . . . . . . . 226
8.29 Distribution of power losses in prototype SICAM with safe-commutation
switching sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.30 Theoretical efficiency of the prototype SICAM with safe-commutation
switching sequence (”T”-shaped markings represent the targeted minimum
efficiency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.31 Measured efficiency of the SICAM prototype with safe-commutation
switching sequence (”T”-shaped markings represent the targeted minimum
efficiency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8.32 Photo of the prototype self-oscillating SICAM with GLIM modulator . . . . . 227
8.33 Self-oscillating SICAM waveforms with zero reference: 1) carrier, 2) out.
voltage 3) bridge voltage, 4) HF-link voltage(50x) . . . . . . . . . . . . . . . . . . . . . . 227
8.34 Self-oscillating SICAM waveforms at Vo = 10 V: 1) carrier, 2) out. voltage
3) bridge voltage, 4) HF-link voltage(50x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8.35 Self-oscillating SICAM waveforms with zero reference: 1) ref. voltage,
2) out. voltage 3) bridge voltage, 4) HF-link voltage(50x) . . . . . . . . . . . . . . . 228
8.36 Self-oscillating SICAM waveforms at Po = 6 W with 1 kHz reference:
1) ref. voltage, 2) out. voltage 3) bridge voltage, 4) HF-link voltage(50x) . . 228
8 List of Figures
8.37 Self-oscillating SICAM waveforms at Po = 6 W with 10 kHz reference:

1) ref. voltage, 2) out. voltage 3) bridge voltage, 4) HF-link voltage(50x) . . 228
8.38 THD+N vs. frequency at Po =6 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
9.1 Two-switch 4Q flyback SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

9.2 Waveforms of the 4Q flyback SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
9.3 Peak current-mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
9.4 Slope matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
9.5 Peak current-mode control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
9.6 Average current-mode control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 236
9.7 Average current-mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
9.8 4Q flyback SICAM prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
9.9 Waveforms with zero reference: 1) ref. voltage vref , 2) output voltage vo ,
3) comparator Q output, 4) primary gate drive . . . . . . . . . . . . . . . . . . . . . . . . 237
9.10 Waveforms with DC-reference: 1) ref. voltage vref , 2) output voltage vo ,
3) comparator Q output, 4) primary gate drive . . . . . . . . . . . . . . . . . . . . . . . . 237
9.11 Waveforms at Po =50 W with 200 Hz reference: 1) ref. voltage vref ,
2) output voltage vo , 3) comparator Q output, 4) primary gate drive . . . . . . 238
9.12 Efficiency of the 4Q flyback SICAM prototype (”T”-shaped markings
represent the targeted minimum efficiency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
10.1 Three-winding transformer and its equivalent electrical circuit . . . . . . . . . . . 240

10.2 Special design of the three-winding transformer . . . . . . . . . . . . . . . . . . . . . . . . 240
10.3 MMFs and induced voltages under symmetrical conditions ∆R = 0% . . . . . 241
10.4 MMFs and induced voltages under asymmetrical conditions ∆R = 10% . . . 241
10.5 2-switch 4Q flyback SICAM with integrated magnetics for auxiliary power
supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
10.6 SICAM with active capacitive voltage clamp using integrated magnetics . . 243
10.7 SICAM with safe commutation and synchronization through integrated
magnetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
10.8 SICAM with output filter inductor integrated on the main transformer . . . 244
10.9 Voltage waveforms across: 1) auxiliary power supply secondary-side
winding (5 V/div), and 2) main secondary-side winding (1 V/div) . . . . . . . . 244
10.10Voltage waveforms across: 1) auxiliary power supply secondary-side
winding (5 V/div), and 2) main secondary-side winding (20 V/div) . . . . . . . 244
A.1 General topologies: a) vin kR, b) LkR and c) CkR (same as Fig. 2.25) . . . . . 247
B.1 Possible connections in the combined Class D audio power amplifier and
boost PFC (same as Fig. 3.9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
B.2 Possible connections in the synchronously-operated combined Class D
audio power amplifier and buck-boost PFC (same as Fig. 3.14) . . . . . . . . . . 264
B.3 Possible connections in the asynchronously-operated combined Class D
audio power amplifier and buck-boost PFC (same as Fig. 3.15) . . . . . . . . . . 273
C.1 Possible connections in the double-boost SICAM (same as Fig. 4.2) . . . . . . 295
D.1 Buck-boost auxiliary converter (same as Fig. 6.21) . . . . . . . . . . . . . . . . . . . . . 303

D.2 Averaged switch model of the DCM flyback auxiliary converter (same as
Fig. 6.22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
D.3 Small-signal AC model of DCM flyback auxiliary converter (same as
Fig. 6.23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
List of Figures 9
E.1 Diagram of FN ADS,1h for developing its DFS . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

E.2 GLIM carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
F.1 Power circuit schematic of the isolated SICAM with master/slave operation 316
F.2 Open-loop control circuit schematic of the isolated SICAM with
master/slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
F.3 Closed-loop control circuit schematic of the isolated SICAM with
master/slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
F.4 Power circuit schematic of the isolated SICAM with active capacitive load
voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
F.5 Control circuit schematic of the isolated SICAM with active capacitive
load voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
F.6 Power circuit schematic of the isolated SICAM with optimized PWM
modulator and safe-commutation switching sequence . . . . . . . . . . . . . . . . . . . 321
F.7 Control circuit schematic of the isolated SICAM with optimized PWM
modulator and safe-commutation switching sequence . . . . . . . . . . . . . . . . . . . 322
F.8 Power circuit schematic of the isolated self-oscillating SICAM with GLIM
modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
F.9 Control circuit schematic of the isolated self-oscillating SICAM with
GLIM modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
F.10 Power circuit schematic of the 4Q flyback SICAM . . . . . . . . . . . . . . . . . . . . . . 325
F.11 Control circuit schematic of the 4Q flyback SICAM . . . . . . . . . . . . . . . . . . . . 326
List of Tables
2.1 Switching states of a single-phase AC to single-phase AC matrix converter 30

2.2 Switching states of a two-phase AC to single-phase AC matrix converter
without a central tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
with fixed central tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
with switched central tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.5 Sectors and corresponding output voltage polarities and angles ωtk . . . . . . . 41
2.6 Sectors and corresponding sector’s right and left vectors . . . . . . . . . . . . . . . . 41
2.7 Switching states of an MC-based SICAM with LC-network . . . . . . . . . . . . . . 47
2.8 Design specifications for matrix SICAM with LC-network . . . . . . . . . . . . . . . 56
4.1 Switching states of the double-boost SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.2 Precompensator Look-Up Table (LUT) for k = 3 . . . . . . . . . . . . . . . . . . . . . . . 96
4.3 Optimal and rounded CRFB noise-shaper coefficients . . . . . . . . . . . . . . . . . . . 101
6.1 Current controlled commutation sequence of the bidirectional bridge in

Fig. 6.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.2 Voltage controlled commutation sequence of the bidirectional bridge in
Fig. 6.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3 Voltage controlled commutation sequence - natural commutation (◦) and
forced commutation (•) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.4 One possible switching sequence of the output stage in SICAM with load
clamp with vHF = +V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.1 Explanation of the parameters in Fig. 7.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
B.1 Switching sequences of the asynchronously-operated combined Class D

List of Abbreviations
AC - Alternating Current
AM - Amplitude Modulation
CCM - Continuous Conduction Mode
DC - Direct Current
DCM - Discontinuous Conduction Mode
DFS - Double Fourier Series
EMC - ElectroMagnetic Compatibility
EMI - ElectroMagnetic Interference
ESR - Equivalent Series Resistance
ESL - Equivalent Series Inductance
GLIM - Global Loop Integrating Modulator
HF - High Frequency
HV - High Voltage
IC - Integrated Circuit
LF - Low Frequency
LV - Low Voltage
M/S - Master/Slave
ODF - Overdimensioning Factor
PAE - Pulse Amplitude Error
PDM - Pulse Density Modulation
PLD - Programmable Logic Device
PSRR - Power Supply Rejection Ratio
PTE - Pulse Timing Error
PWM - Pulse Width Modulation
RCD - Resistor-Capacitor-Diode
RHPZ - Right Half-Plane Zero
RMS - Root Mean Square
SICAM - SIngle Conversion stage AMplifier
SOHF - Self-Oscilating High Frequency-link converters
SPRC - Series-Parallel Resonant Converter
SRC - Series Resonant Converter
SMPS - Switching-Mode Power Supply
THD+N - Total Harmonic Distortion + Noise
UPS - Uninterruptible Power Supply
ZCS - Zero Current Switching
ZVS - Zero Voltage Switching
1
Introduction
”Even the longest journey starts with the first step.”
- Confucius
By definition, sound represents an acoustical or mechanical longitudinal pressure wave

motion in an elastic medium, like gas, liquid or a solid. The audible frequency range is
starting from around 20 Hz and ending around 20 kHz, but it is quite dependant on the
persons age and other personal dispositions. There are many different sound sources, like
a vibrating body (ex. vocal cords), throttled air stream (ex. whistle), thermal (ex. gas
heating), explosion (ex. firecracker), arc (ex. thunder), aeolian or vortex. It is interesting
to notice that most of the aforementioned natural sound sources have their counterparts in
the man-made musical instruments and other artificial objects from our everyday life. On
the other hand, the ultimate sound receiver, neglecting any intermediate sound storage,
is the human ear consisting of the external ear, ear drum, middle ear bones, membrane
and cochlea. Its complex structure leads to many interesting phenomena studied entirely
by the science of psychoacoustics and finding many useful technical applications, like for
example the advent of advanced human-hearing models for developing highly efficient
audio compression algorithms.
The need for audio sound amplification stems from the fact that most of the natural or
artificial sound sources today create just modest sound pressure levels, which are usually
not sufficient to effectively address the public and cover larger ambient. On the other
hand, audio power amplification is unavoidable when reproducing prerecorded materials,
no matter whether the storage has an analog or a digital format. Despite of the first me-
chanical audio power amplifiers using a wooden horn for amplifying the grooves embossed
on a cylinder or disk played back through a phonograph or gramophone, modern audio
power amplifiers are entirely electrical devices using some kind of electrodynamic (moving
coil or ribbon), electrostatic or piezoelectric loudspeaker as their output. The very low
power conversion efficiency of the most common electrodynamic loudspeakers emphasizes
even more the need for electrical audio power amplification.
The aim of this chapter is to make a short review of the common audio power ampli-
fication techniques, starting with the linear amplification as the oldest one and moving
to the switching-mode power amplification as the latest and most promising one. At the
end, the SICAM project will be presented as the newest and most radical contribution
to the switching-mode audio power amplification, developed for simplicity and effective-
ness by making the energy conversion from AC mains to audio output straightforward
and achieving the additional benefits of reduced volume and board space, less complexity,
lower component count and subsequently lower cost.
1.1 Linear audio power amplifiers

The linear audio power amplifier is characterized by having its output power devices,
being vacuum tubes, bipolar junction transistors (BJTs), field effect transistors (FETs)
16 1 Introduction
iD VGS-VGS(th)=vDS
Ohmic Active
VGS2>VGS1
VGS1
BVDSS vDS
Fig. 1.1. I-V characteristics of MOSFET
or some other semiconductor technology, operated in the linear part of their corresponding
current-voltage (I-V) characteristic, shown for the MOSFET in Fig. 1.1. In this case, the
MOSFET is operated with low gate-source voltages and is said to be in its active region
[13]:
vGS − VGS(th) < vDS (1.1)
where vGS is the gate-source voltage, VGS(th) is the gate-source threshold voltage and vDS
is the drain-source voltage. As shown in Fig. 1.1, in the active region of the MOSFET the
drain current iD is function only of the applied gate-source voltage vGS . At the same time,
the drain-source voltage vDS can be in a very large span of voltages up to the breakdown
voltage BVDSS , creating quite large conduction losses in the device:
PF ET,con = vDS · iD ≫ 0 (1.2)
A scheme of a MOSFET output stage of a single-ended linear audio power amplifier

is depicted in Fig. 1.2, while the power supply voltages and load voltage are shown in
Fig. 1.3. The scheme also includes the connection points of the control feedforward and
control feedback signals.
When looking in Fig. 1.3, it can be concluded that the output power devices in linear
audio power amplifiers act as voltage- or current-controlled variable resistors, dropping
across them the part of the voltage ∆vM 1 , ∆vM 2 being the difference between the fixed
V+ V+
1
∆v
Q11 M1
vB11
M1 0.5
vZ
RE11 L1
RG1
vn
0
feedforward
v
main feedback Z
RE12 R1 R −0.5
RG2 2 ∆ vM2
Z
−1
M2 C2 V−
vB12 0 1 2 3 4 5 6 7
Q12 anti-resonant ωt [rad/s]
. V- network
Fig. 1.3. Power supply voltage and load voltage
Fig. 1.2. Linear audio power amplifier with MOSFETs with linear audio power amplifier
1.2 Switching-mode audio power amplifiers 17
or variable split power supply voltages V+ , V− and the desired load voltage vZ across the
impedance Z, while conducting the whole load current. As mentioned earlier, this leads to
huge power dissipation in the active devices, which is comparable and often even higher
than the useful output power in the load.
There exist different classes of linear audio power amplifiers [14]:
• Class A: Large pre-bias voltage/current is applied in the output stage, resulting in
continuous conduction of both the low-side and high-side active devices throughout
the cycle of the signal waveform. High linearity and performance are combined with
huge power losses.
• Class B: Each of the active devices conducts only through the corresponding half of
the cycle of the signal waveform. Due to the non-ideality of the active devices, crossover
distortion is created when the signal waveform passes through zero.
• Class AB: Sufficient pre-bias voltage/current is applied to the Class B power amplifier,
so that any crossover distortion is avoided. Combines good audio performance with
satisfactory efficiency.
• Class C: Active devices are conducting less than half of the cycle of the signal wave-
form. Due to the higher level of signal distortion it is used only in Radio Frequency
(RF) power amplifiers / transmitters.
• Class B2, B3 ... BN: Multiple active devices operate on multiple power supply rails
to improve the efficiency of the Class B audio power amplifier depending on the signal
waveform amplitude. Complex solution with improved efficiency compared with the
conventional Class B.
• Class G: Linear audio power amplifier is operated with a variable power supply volt-
age. Highly efficient solution, but the complexity is transferred from the audio power
amplifier to the power supply.
Although a thorough treatment of the different linear audio power amplifier classes is
beyond the scope of this thesis, it can be mentioned that the large power losses accompa-
nying the operation of the linear audio power amplifier are major obstacle to the trend of
product integration. Latter is especially pronounced in the higher power range, where the
output devices of the linear power amplifiers must be mounted on bulky heat sinks quite
away from the temperature sensitive electronics. On the other end of the power range,
the low power linear audio power amplifiers not only yield shorter battery operation time
due to the inherent inefficiency of the output power stage, but also cause electronics over-
heating problems in the tightly crowded space of the modern portable devices. Therefore,
linear audio power amplifiers on the consumer market today are being more and more
replaced with the switching-mode audio power amplifiers, which tend to outperform the
former amplifiers in terms of power efficiency and prospects for high-level integration.
1.2 Switching-mode audio power amplifiers

In the switching-mode audio power amplifier, the active devices are operated as switching
elements by driving them deep into saturation or in off-state, rather than being linear
elements with controlled variable resistance. As shown below, this has tremendous effects
on the efficiency of the output power stage.
In the case of a MOSFET, switching-mode operation refers to operating the MOSFET
alternatively in blocking state and in its ohmic region [13], where for the latter the gate-
source voltage vGS obeys:
vGS − VGS(th) > vDS > 0 (1.3)

18 1 Introduction
V+
1
V+
main feedback
0.5
High-side M1
driver
vn
RG1 0
L1
PWM
modulator Z
−0.5
RG2
Low-side C2
driver −1
M2 V−
low-pass 0 1 2 3 4 5 6 7
V- filter ωt [rad/s]
Fig. 1.4. Switching-mode audio power amplifier with Fig. 1.5. PWM bridge voltage and load voltage
MOSFETs with switching-mode audio power amplifier
When looking on the MOSFET I − V characteristic shown in Fig. 1.1, this translates
to either driving the MOSFET with large gate-source voltage vGS to conduct large drain
currents iD with just a minor drain-source voltage vDS or completely removing the gate
drive to turn-off the device and collapse the drain current iD , while blocking the entire
power supply voltage across its drain-source. As a result of the switching-mode operation
where either the drain-source voltage vDS is negligible during the MOSFET on-state or
the drain current iD equals the very small drain-source leakage current IDSS during the
off-state, the conduction losses of the MOSFET approach zero:
PF ET,con = vDS · iD ≈ 0 (1.4)
A scheme of a MOSFET output stage of a single-ended switching-mode audio power

amplifier, usually referred as half-bridge Class D amplifier is depicted in Fig. 1.4, while
the bridge voltage and load voltage are shown in Fig. 1.5.
Coding of the desired signal waveform with just two power supply levels V+ and V−
necessitates some kind of modulation, either being Pulse Width Modulation (PWM),
Pulse Frequency Modulation (PFM), Pulse Density Modulation (PDM) or some other
hybrid type. Turning to the most common and popular type of modulation for Class
D amplifiers, that is PWM, according to the number of levels this modulation principle
can be further subdivided in two (AD) and three (BD) level, while according to the
carrier shape there is further subdivision into single-sided (S) and double-sided (D) [14].
In particular, Fig. 1.5 shows double-sided two level (NADD) PWM coding of the signal
waveform, the frequency of which is for the purpose of clarity comparable to the switching
frequency of the output stage.
As a result of the fact that the bridge voltage, being the output voltage at the midpoint
of the MOSFET totem pole, has only two or three voltage levels equal to the power
supply rails and/or ground respectively, there is significant amount of off-band switching
harmonics which are usually filtered out with second order low-pass LC filter placed in
front of the loudspeaker, as depicted in Fig. 1.4. This is the price one needs to pay for
reducing the energy of the high frequency (HF) switching harmonics and its sidebands, in
order to avoid subsequent excessive losses in the conventional loudspeaker [15] or comply
with the Electro-Magnetic Compatibility (EMC) standars. The problem with the possible
Electro-Magnetic Interference (EMI) from the rapidly changing currents flowing through
the Class D amplifier input lines is an issue, too.
Equation (1.4) predicts almost zero conduction losses of the ideal MOSFET operated in
switching-mode, but unfortunately the real-life power MOSFETs, as shown in Fig. 1.6 are
non-ideal switching elements which have a finite on-resistance of the conducting channel
RDS , leading to some conduction losses. On top of that, they have parasitic capacitances
1.2 Switching-mode audio power amplifiers 19
D
D
CGD
G G CDS BD
CGS RDS
S
S
Fig. 1.6. Equivalent scheme of MOSFET
AC-DC DC-AC AC-DC DC-AC

Rectifier HF Inverter Rectifier Inverter
AC mains
Control 1 Control 2
+ +
- -
SMPS Class D
Fig. 1.7. Block diagram of completely switching-mode audio power amplifier
between the different electrodes, limiting their switching speed, which results in switching
losses at each MOSFET state transitions. Both the conduction and switching losses of
the power MOSFETs lead to power losses, which together with the losses in other compo-
nents of the Class D audio power amplifier decrease its efficiency to a level which is still
significantly higher than the one of a Class AB linear audio power amplifier.
One of the usually overseen components when discussing Class D audio power amplifiers
is the power supply. No matter whether the application is AC mains-powered or battery-
powered, some kind of AC-DC or DC-DC power supply is needed to create DC-bus link
with sufficient voltage and low impedance, so that the audio performance of the amplifier
throughout the whole power and frequency range is up to the expectations. Similar to
the audio power amplifier, the power supply can be either linear or switching-mode, with
the latter being the best choice in applications where the efficiency, weight, size and
power density matter. The power supply itself is usually much more complex than the
Class D amplifier itself, especially when it is to provide safety isolation from the AC mains
with a minimum size magnetics and high efficiency, involving several energy conversion
steps. A simple block diagram of a completely switching-mode audio power amplifier
with a Switching-Mode Power Supply (SMPS) and a Class D audio power amplifier is
shown in Fig. 1.7. The latter clearly presents the numerous energy conversions needed
to transform the electrical energy from the input AC mains to the audio output. It also
shows that in the common switching-mode audio power amplifier, SMPS and Class D
audio power amplifier are connected through a DC-bus, i.e. a DC-link which separates
this two units and enables greater flexibility by allowing SMPSs and Class D amplifiers
from different manufacturers to get perfectly along, as long as the DC-bus has the right
voltage level, sufficient power rating and low enough output impedance. Most usually,
there is no communication between the SMPS and Class D amplifier and they both run
their own feedback loops for rejecting any disturbances on the input power lines or power
stage errors (except for the Class D audio power amplifiers with digital inputs, which are
usually run in open loop and feedback is replaced by error precompensation).
20 1 Introduction
If ηi represents the efficiency of the i-th energy conversion step in the audio power
amplification chain, the total efficiency of the audio power amplifier is product of the
corresponding efficiencies:
N
Y
ηtot = ηi (1.5)
i=1
Since the efficiency of each of the conversion steps is smaller than one due to the un-
avoidable losses associated with each energy transformation, the total efficiency is much
smaller than the efficiency of each of the constitutive parts. Equation (1.5) clearly empha-
sizes the improvement in efficiency resulting from possible reduction of number of energy
conversion steps.
1.3 SICAM project and problem definition

Recalling the lessons learned in the previous section, significant improvements can be ex-
pected from the possible reductions in the complexity of the present completely switching-
mode audio power amplifiers, by seamlessly integrating the SMPS and Class D audio power
amplifier into one or two closely dedicated stages. The resulting highly integrated audio
power amplifier is referred to as SIngle Conversion stage AMplifier - SICAM and
is the subject of thorough examination in this thesis.
The technological possibility allowing for this total integration is the similar principle
of operation of both the SMPS and Class D audio power amplifier, i.e. energy processing
by alternately switching their active elements. This allows for dedication of the SMPS
to the Class D audio power amplifier and vice versa, which excludes operation of the
same SMPS with some other conventional Class D amplifier of the type described in
Section 1.2. Even more, the roles of the two aforementioned units in creating the audio
output become so intertwined, that there is no way of drawing firm borders between the
power supply and the audio power amplifier anymore. Along with this integration of the
corresponding power stages comes an integration of the control functions into a single
unit, which further simplifies the resulting audio power amplifier. A simple block diagram
of a SICAM, without any implications on its structure, is given in Fig. 1.8.
The aforementioned dedication of the SMPS to the audio power amplifier in SICAMs
is being shown in a rather arbitrary way in Fig. 1.9. For example, the energy sent from
the front-end SMPS to the audio amplification stage can be in a form of:
AC-AC
AC-AC, DC-AC, AC-DC ...
Rectifier, Inverter, w/o isolation
AC mains
Control
+
-
SICAM
Fig. 1.8. Simple block diagram of SICAM
1.3 SICAM project and problem definition 21
• 2-phase phase-shifted AC voltage which can provide continuous power flow to a matrix
converter-type audio power amplifier,
• HF AC voltage from a resonant type SMPS is being delivered to a cycloconverting
audio power amplifier,
• 2-phase DC voltage is being used by DC-DC audio power amplifiers connecting the
load in differential mode,
• DC voltage is interfacing Class D audio power amplifier with a simple SMPS, etc.
The aforementioned approaches are by no means the only possible ones, and they are
merely presented to show the myriad of feasible solutions, although not all of them with
the same performance/cost ratios. The number of approaches increases even more with
the fact that SICAM is supposed to address both the isolated and non-isolated direct
energy conversion, since in certain instances where the audio power amplifier is entirely
enclosed within a nonconductive box together with the loudspeaker, there is no need for
providing isolation. Therefore, a proper definition of SICAM which is both general and
applicable is:
”SICAM presents any power converter topology which strives for as direct en-
ergy conversions as possible from the power source to the audio output, within
the given constraints.”
The main driving force behind the proposed higher level of integration and dedication
between units is the wish for much more efficient switching-mode audio power amplifiers
with even smaller form factors, higher power densities, lower component count and even-
tually the lower production cost that follows. It is also quite appealing for the Active
Transducer (AT) [16] approach for direct conversion of the mains power into acoustic
output in one simplified topological stage, like in the active loudspeaker systems and
dedicated subwoofer units. Graphical comparison of the linear amplifier, switching-mode
Class D amplifier and SICAM on the Level of integration / Cost scale is depicted in
Fig. 1.10.
The targeted efficiency and Total Harmonic Distortion + Noise (THD+N) of SICAMs
can be summarized in the following few points:
• <0.6% idle losses relative to full output power,
• >54% efficiency at 1% of full output power,
• >80% efficiency at full output power, and
• decent audio performance and low distortion (ex. THD+N<0.1%).
Although high energy conversion efficiency and low THD+N levels are very important
for the acceptance of the SICAM audio power amplifier on the market, it is believed that
there are some other factors like product simplicity, reliability, volume, power density,
component count and eventually cost which will be the prime movers for the companies
Audio
Power supply 2ph. AC HF AC amplification
AC mains Audio
stage
Switches Energy Power
storage switches
2ph. DC DC
Fig. 1.9. Dedication of the SMPS to the audio power amplifier in SICAM
22 1 Introduction
to push SICAM into technology development and later as products on the market. This
is especially true if comparable power efficiency and THD+N like the present Class D
solutions can be achieved, or they are such that at least some specific segments of the
audio market can be targeted.
The addressed power range is 50 W to 500 W, which means that the power source for
SICAM is intended to be single-phase AC-mains. For higher power range, some power
factor correction (PFC) i.e. input current shaping according to the input voltage should
be considered.
high
Linear amp
Cost
Class D
SICAM
low
low high
Level of integration
Fig. 1.10. Comparison of linear amplifiers, switching-mode amplifiers and SICAMs
This Ph.D. thesis should be looked upon in the light of the Confucius’ proverb from
the beginning of the chapter: it is just the first step to wider recognition, acceptance
and continuing research of the possibilities for direct energy conversion with different
SICAM-type converters not only for audio amplification, but also for Uninterruptible
Power Supplies (UPSs), converters for renewable energy sources like Photo-Voltaics (PVs)
and Fuel Cells (FCs), as well as general power conversion.
1.4 Need for energy storage on a single-phase AC-mains

One of the general issues that sheds some light on the limitations of the SICAM approach
is the essential need for some energy storage during the intervals with low or zero input
voltage of the single-phase AC-mains.
Rate at which electrical energy is supplied to the load is called electrical power, and
its instantaneous value p(t) can be found as a product of the voltage instantaneous value
u(t) and current instantaneous value i(t):
p(t) = u(t)i(t) (1.6)
AC-mains voltage has the form of a sinusoidal function:
u(t) = Um sin(ωt) (1.7)
where ω = 2πf [rad/s] is the AC mains voltage angular frequency, f [Hz] is the frequency
and t [s] represents the time.
From equations (1.6) and (1.7) it turns out that, at instants where mains voltage equals
zero (nπ where n is an integer), i.e. at zero crossings there is no energy transferred to
the load (unless the input current is infinite i(t) → ∞, which is certainly not a viable
assumption). Moreover, rate at which electrical grid supplies energy to the load is greatly
reduced and performance is compromised in some vicinity of the zero crossing points.
1.4 Need for energy storage on a single-phase AC-mains 23
In some appliances zero crossings of the main voltage does not disturb the operation
of the device, especially √ if they represent slow processes which respond to the voltage
effective value Uef = Um / 2 (ex. electroheating process, where the heater’s power equals
2
Uef /R). In the audio appliances, where the audio effect and content are created on a
time scale which is comparable or much shorter than the incidents of AC-mains zero
voltage, on a continuous basis, any minor failure to provide the necessary power causes a
major disturbance of the audio signal and adversely affects the high fidelity of the sound.
In order to overcome this problem, some energy storage elements are introduced in the
power supply, thus providing the energy needed for the audio amplification stage when
AC mains voltage lacks the ability to do that.
This is a basic limitation of the mains-connected SICAM, since it cannot be constructed
without some kind of a power supply, that will provide uninterrupted energy supply for
audio conversion. Therefore, SICAM is intended to be a dedicated and closely intercon-
nected two stage system, like the one depicted in Fig. 1.9, which has an input stage for
power conditioning and storage (i.e. a power supply), and output switching audio stage.
Going back to the principles, power supply should convert and store the electrical
energy into some other type of energy during the positive and negative half-cycles of the
input AC mains voltage. Then it should retrieve it back around the zero crossing points, or
deliver it to the load at a constant rate throughout the whole operating period. Electrical
energy can be converted into:
• Magnetic energy - magnetic field (inductor),
• Electrostatic energy - charge (capacitor),
• Mechanical kinetic energy (ex. a flywheel),
• Mechanical potential energy (ex. a mass m elevated on higher ground in gravitational
field),
• Chemical energy (battery), etc.
Except for the first two choices - the magnetic and electrostatic energy, all other types
of energy have a low rate of conversion from and to electrical energy because of the high
inertia they possess. Although the inductor and capacitor also possess some amount of
inertia, described by their inductance L and capacitance C, they are exclusively used in
the power supplies for the purpose of storing electrical energy.
SICAM doesn’t impose any limitations on the form of the power supply output. It
may seem that there is a huge array of different possible combinations of power supplies
and subsequent power converter topologies, but their number is substantially reduced if
one reconsiders the necessary conditions, that emerge from the SICAM and audio sound
definitions, as well as viable regulations:
• Power supply must be capable of delivering/receiving electrical energy to/from the
audio amplification stage at any time moment with the desired rate offering full dy-
namics,
• Power supply should incorporate a minimal number of switches (preferably unidi-
rectional), possibly having a topology or providing some algorithm for lowering the
switching and conduction losses, introduce low-level control (ex. for PFC) or make use
of uncontrollable switches (ex. diodes), which will reduce the number of switch drivers,
• Switching audio stage should incorporate a minimal number of switches (preferably
unidirectional), tending to minimize the losses without compromising the audio quality
and providing high-level control to deal with plant uncertainties and perturbations,
• Both the power supply and audio amplification stage should incorporate fewer energy
storage reactive components,
• Number of energy conversions should be kept as low as possible, and
24 1 Introduction
• Power supply or audio amplification stage must provide galvanic isolation from the
electrical grid if the voltage levels on the parts of the electric circuit that can be
externally accessed are greater than the regulatory limits.
It seems adequate at this point to mention some of the trade-offs that are likely to
be encountered in the quest for the ultimate direct single-stage audio power amplifier.
As already mentioned, one of the main drivers behind the research in SICAMs are the
savings that are expected to result from the tighter integration between the switching-
mode power supply and the Class D audio power amplifier. These savings are sometimes
too optimistically expected to arise from the reduced component count or the replacement
of reactive components with semiconductor switches, without thorough analysis of the
switch stress. Unfortunately, what the examples in other power electronics fields, like for
example Power Factor Correction (PFC), show is that along with the transition from
multi-stage to single-stage topologies with reduced component count the stress of this
few switches tends to increase significantly, leading unexpectedly to lower reliability and
higher component cost. The main intention of this discussion is to point out that moving
to single-stage audio power amplifiers does not necessarily imply achieving a competitive
edge with regard to the present state of the art two-stage approaches, and the advantages
must be carefully analyzed by close comparison of units with similar specifications.
1.5 Thesis outline

The Ph.D. thesis is divided into two major parts: Part I is dealing with non-isolated
SICAM topologies for both single-phase AC-mains and battery connected devices and
Part II is dealing entirely with the isolated SICAM topologies.
Part I starts with the study of the applicability of the general matrix converter topolo-
gies to non-isolated SICAMs. Afterwards, focus is shifted to non-isolated SICAM topolo-
gies which are using rectification of the AC-mains voltage combined with DC storage
capacitors to provide continuous power flow for the subsequent audio power amplification
stage. At the end, some interesting SICAM topologies for battery powered devices, capa-
ble of stepping-up the input voltage are presented, along with appropriate digital control
algorithms.
Part II begins with an introduction to the very complex topic of direct audio power
amplification in a presence of isolation transformer. The subsequent chapters propose
different topologies and several control approaches, capable of properly addressing most
of the design challenges and achieving satisfactory performance while still being reliable
and simple. Some combinations of SICAM topologies and control methods have been
built as prototypes and the results are summarized in separate chapters. Although the
main focus in the second part of the thesis is given to the group of isolated SICAMs
with so called non-modulated transformer voltages, which are especially appealing for
multichannel audio applications, one of the chapters will present very simple isolated
SICAM with modulated transformer voltages based on common flyback converter. The
final chapter in this part describes an especially interesting design of integrated magnetics,
which can be used in all SICAMs to reduce the number of magnetic cores and thus save
precious board space.
The thesis is finished with some concluding remarks and several appendices, dealing in
detail with mathematical and other matters referenced throughout the thesis.
Part I
Non-isolated SICAMs
2
Matrix SICAM
”You know that I write slowly. This is chiefly because I
am never satisfied until I have said as much as possible
in a few words, and writing briefly takes far more time
than writing at length. ”
- Carl Friedrich Gauss
2.1 Matrix converters

Direct AC-AC energy conversion using matrix converters is considered to be the most gen-
eral one [17],[18]. Matrix converter is capable of direct transformation of sinusoidal voltage
level and frequency without any energy storage components, but some limitations apply
[19]. In fact, maximum output voltage level is dependent on the input voltage amplitude
and use of some reactive components is compulsory, in order to provide input current
and output voltage filtering. However, these filtering reactive components have very low
energy storage capability and therefore it can be assumed that in matrix converters at
each point of time there is a balance between the energy taken from the utility grid and
the energy transferred to the load.
Important advantages of the matrix converter are:
• Sinusoidal input and output waveforms, less higher order harmonics and no subhar-
monics,
• Bidirectional flow of energy,
• Minimal size reactive components (for filtering purposes), and
• Adjustable power factor [20].
A matrix converter with M input lines, N output lines and switches at their intersec-
tions is presented in Fig. 2.1, where sources are of a voltage type and loads of a current
type.
State of each switch Sij can be represented by its switching function Hij , where:
(
0, if switch Sij is OFF
Hij = , i = 1, 2, ..., M and j = 1, 2, ..., N (2.1)
1, if switch Sij is ON
In each horizontal (output) line there can be only one switch turned on, otherwise
there will be a parallel connection of two ideal voltage sources on the input side, which
in general have different instantaneous voltages. Therefore, a voltage condition can be
defined as following:
M
X
H1j + H2j + ... + HM j = 1 , i.e. Hij = 1 (2.2)
i=1
At the same time, there must be a path for the output current from the ideal current
sources to flow, resulting in the next current condition for the input lines:
N
X
Hi1 + Hi2 + ... + HiN > 1 , i.e. Hij > 1 (2.3)
j=1
28 2 Matrix SICAM
i1
S11 S21 SM1 i2
j=1,...,N
S12 S22 SM2
:
iN
S1N S2N SMN
+ + +
..
v1 v2 vM
i=1,...,M
Fig. 2.1. M-phase to N-phase matrix converter
Matrix converter structure can be simplified by introducing a central tap in the M th

input line, by moving the voltage source VM to each of the M − 1 input lines to leave
the M th input line empty, or even connecting it directly to the N th output line, thus
eliminating the need for switches in that output line, according to the voltage condition
(2.2). Latter situation is shown in Fig. 2.2.
Input voltages and output currents can be regarded as independent quantities, since
their trajectory or time change is dictated by the electrical grid or the source requirements.
Switching strategies of matrix converters largely depend upon the desired output voltages,
i1
S11 S21 SM1 i2
j=1,...,N
S12 S22 SM2
:
iN
SMN
+ +
..
v1 v2
+ +
vM vM
i=1,...,M
Fig. 2.2. M-phase to N-phase matrix converter with central tap in the M-th line
2.2 Single-phase AC to single-phase AC matrix converter 29
which are controlled to satisfy specific load demands. Input currents can be also an object
of control to mitigate some power quality concerns, like low THD and providing PFC.
The subject of the following sections will be the problem of constructing single-phase
output i.e. an AC audio signal, from a single-phase input AC voltage. Since this proves to
be impossible, number of input phases will be increased, until the output characteristics
fulfill the demands.
2.2 Single-phase AC to single-phase AC matrix converter

Single-phase AC to single-phase AC matrix converter is shown in Fig. 2.3. It has two
input and two output lines, so it requires four switches.
v1, o
io
+
S11 S21 vo
S12 S22 v2, o
vin
Fig. 2.3. Single-phase to single-phase matrix converter
Voltage condition (2.2) and current condition (2.3) in the case of the matrix converter
shown in Fig. 2.3 transform to:
H11 + H21 = 1 , H12 + H22 = 1 (2.4)
Input voltage has the following sinusoidal waveform:
vin = Vin,max sin(ωin t) (2.5)
Output voltage vo across the load can be found as a difference between the voltages of
the output lines:
vo = v1,o − v2,o = H11 vin − H12 vin = (H11 − H12 )vin (2.6)
Input current is sum of the currents flowing through the output lines:
iin = (H11 − H12 )io (2.7)
Before proceeding to further analysis, it is useful to determine the nature and charac-
teristics of the switches Sij . This can be done by looking at the direction of the blocking
voltages vij when switched off and conducting currents iij when switched on.
Blocking voltages across the switches are:
S11 : v11 = vin − v1,o = vin − H11 vin = (1 − H11 )vin
S21 : v21 = 0 − v1,o = −H11 vin
(2.8)
S11 : v12 = vin − v2,o = vin − H12 vin = (1 − H12 )vin
S22 : v22 = 0 − v2,o = −H22 vin
30 2 Matrix SICAM
Conducted currents through the switches are:

S11 : i11 = H11 io
S21 : i21 = H21 io
(2.9)
S11 : i12 = −H12 io
S22 : i22 = −H22 io
Since input voltage vin and output current io are AC by nature, it is clear that the
blocking voltage (2.8) and the conducted current (2.9) for each switch will have both
polarities/directions. Therefore, matrix converter must consist of bidirectional switches
capable of blocking either voltage polarity and conducting current in either direction. This
conclusion is general and it applies to all of the AC-AC matrix converters throughout this
chapter.
All the switching states and the corresponding instantaneous values of the output
voltage for the single-phase AC to single-phase AC matrix converter are given in Table 2.1.
Time intervals t0 , t1 and t2 satisfy t0 + t1 + t2 = Ts , where Ts = 1/fs is the switching
interval.
Switches ON vo time interval

S11 , S22 vin t1
S11 , S12 0 t0
S21 , S12 −vin t2
S21 , S22 0 t0
Table 2.1. Switching states of a single-phase AC to single-phase AC matrix converter
Average value of the output voltage vo,av during one switching interval Ts , can be found
in a following way:
1 t1 − t2
vo,av = (t1 vin − t2 vin ) = vin (2.10)
Ts Ts
When input voltage vin (2.5) equals zero, equation (2.10) reveals near zero average
output voltage, and its value depends on the duration of the switching interval Ts . The
bounding region for the output voltage in the case of a single-phase AC to single-phase AC
matrix converter is shown in Fig. 2.4, with the input voltage normalized −1 ≤ vin,n ≤ 1.
The undertaken analysis, as well as the bounding region shown in Fig. 2.4 prove that
single-phase AC to single-phase AC matrix converter is not capable of constructing the
desired output voltage waveform. In other words, its structure imposes certain limitations,
of which the frequency of the output voltage being integer multiple of the input voltage
frequency is the most serious one.
Authors in [21] and [22] have come to similar conclusion, emphasizing the frequency
step-up and output voltage step-down capabilities, beside the restriction of output fun-
damental voltage being phase-locked to the input voltage.
Employing the conservative approach in [19], one can obtain even more stringent re-
strictions upon the output voltage waveform, generated from a single-phase AC mains
voltage. In the most general case, single-phase output voltage vo is synthesized from a set
of input voltages vin,h , h = 1, ..., n. During each switching interval Ts , output voltage vo is
constructed by connecting the output to different input lines. Therefore, this fundamental
inequality holds in each interval:
min vin,h (t) ≤ vo (t) ≤ max vin,h (t) (2.11)

h=1,...,n h=1,...,n
2.3 Two-phase AC to single-phase AC matrix converter 31
0.5
vin,n
0
−0.5
−1
0 2 4 6 8 10
ωt
Fig. 2.4. Bounding region for the output voltage of a single-phase to single-phase matrix converter
Establishing the upper bound (U Bi ) and the lower bound (LBi ) of the input voltages:
U Bi (t) = max vin,h (t) , LBi (t) = min vin,h (t) (2.12)
h=1,...,n h=1,...,n
and the upper bound (U Bo ) and the lower bound (LBo ) of the output voltage:
U Bo (t) = max vo (t) , LBi (t) = min vo (t) (2.13)
then the inequality (2.11) can be rewritten in the following form:
LBi (t) ≤ vo (t) ≤ U Bi (t) (2.14)
When striving for equal performance of the matrix converter throughout the operating
time, output voltage can be restricted to obey the following inequality:
min U Bi (t) ≥ max U Bo (t) (2.15)

t t
According to the entries in Table 2.1, single-phase AC to single-phase AC matrix

converter can apply both positive and negative input voltage across the load. Therefore,
the set of input voltages actually consists of:
vi,1 = vin = Vin,max sin(ωin t)
(2.16)
vi,2 = −vin = Vin,max sin(ωin t − π)
From Fig. 2.4 it follows that both upper and lower bounds of the set of input voltages
are zero:
min U Bi (t) = max LBi (t) = 0 (2.17)

t t
leading to zero output voltage vo = 0, which is certainly a very conservative conclusion,

but clearly shows the fundamental limitations imposed upon the single-phase AC to single-
phase AC matrix converter with sinusoidal input voltage.
2.3 Two-phase AC to single-phase AC matrix converter

From the points learned in the previous section it becomes clear that single-phase AC-
input matrix converter is not capable of creating the power flow dynamics, which is
32 2 Matrix SICAM
necessary for driving a high fidelity audio system. The fundamental limitation are the
regular zero-crossings of the input AC voltage, which asks for either some kind of energy
storage or an alternative voltage source used during the periods of low input voltage. In
order to preserve the ultimate advantage of the matrix converter with regard to avoiding
any energy storage on the input side, it is interesting to reconsider designing a matrix
converter with two input phases and their voltages having the same amplitudes and fre-
quencies, but being out of phase for φ radians. It should be noted, however, that in the
case where the second-phase voltage is derived from the first-phase voltage with some kind
of power processing, this can be referred to as introducing some kind of energy storage
for the periods of time with low input voltage on the first phase.
In Fig. 2.5 the phase lag of the input voltages is φ < π/2. At the same figure both
positive and negative polarities of input voltages are presented, since matrix converter
should be capable of applying them to the load, for the sake of increased functionality.
Maximums and minimums of the lower and upper bounds correspondingly are situated at
the intersections of the different sinewaves. When φ ≤ π/2, minimum of the upper bound
(mint U Bi (t)) and maximum of the lower bound (maxt LBi (t)) are established at the
intersections of positive and negative sinewaves of input voltages (bold horizontal lines).
When φ ≥ π/2, minimum of the upper bound (mint U Bi (t)) and maximum of the lower
bound (maxt LBi (t)) are established at the intersections of positive sinewaves of input
voltages and at the intersections of negative sinewaves of input voltages, correspondingly
(dash-dotted horizontal lines). According to the phase angles marked in Fig. 2.5, the
following applies when both voltages have the same amplitude:
(
mint U Bi (t) = sin φ2 , for 0 ≤ φ ≤ π2
φ
sin ( 2 + π) , for π2 ≤ φ ≤ π
( (2.18)
− sin φ2 , for 0 ≤ φ ≤ π2
maxt LBi (t) =
− sin ( φ2 + π) , for π2 ≤ φ ≤ π
0.5 min UB (t)

i
φ
2,in,n
0
,v
1,in,n
−0.5 max LB (t)

i
v
−1
φ/2 v
1,in
v
2,in
−v
1,in
−v
2,in
φ/2+π/2
−1.5
−2
0 2 4 6 8 10
ωt
Fig. 2.5. Upper and lower bounds of the input voltages of a two-phase to single-phase matrix converter
It is rather straightforward to show that maximal available mint U Bi (t) and minimal
available maxt LBi (t) will be reached as soon as the previously mentioned different bounds
for φ ≤ π/2 and φ ≥ π/2 merge. This will happen for phase lag in excess of π/2 radians,
that leads to symmetrical two-phase system. This case is shown in Fig. 2.6, and bounds
are equal to:
√
mint U Bi (t) = sin π4 = 22 =√0, 707
(2.19)
maxt LBi (t) = − sin π4 = − 22 = −0, 707
1
min UBi(t)
0.5
2,in,n
0
,v
1,in,n
−0.5
max LB (t)
v
i
−1
π/4 −v
2,in
v
1,in
v
2,in
−v
1,in
π/2
−1.5
−2
0 2 4 6 8 10
ωt
Fig. 2.6. Upper and lower bounds of the input voltages of a two-phase to single-phase matrix converter in the
optimal case φ = π/2
Therefore the optimal set of two AC input voltages should have the following form:
v1,in = Vin,max sin (ωin t)

(2.20)
v2,in = Vin,max sin (ωin t − π2 )
Two-phase AC to single-phase AC matrix converter can be built in several ways, like:

• 2ph-AC to 1ph-AC matrix converter without a central tap,
• 2ph-AC to 1ph-AC matrix converter with fixed central tap, and
• 2ph-AC to 1ph-AC matrix converter with switched central tap
These will be subject of investigation in the next three sections.
2.3.1 2ph-AC to 1ph-AC matrix converter without a central tap
2ph-AC to 1ph-AC matrix converter without a central tap is shown in Fig. 2.7. As men-
tioned previously, all switches Sij are bidirectional.
v1, o
io
+
S11 S21 vo
S12 S22 v2, o
v1, in v2, in
Fig. 2.7. 2ph-AC to 1ph-AC matrix converter without a central tap
34 2 Matrix SICAM
2ph-AC to 1ph-AC matrix converter without a central tap is similar to the 1ph-AC
to 1ph-AC matrix converter, where the two input lines are now subject to input voltage
difference equal to:
vin = v1,in − v2,in (2.21)
and this difference is a sinewave with the same frequency and bigger amplitude than both
the input voltages. So, there is still a voltage zero crossing problem.
Due to the aforementioned problem, it can be concluded that 2ph-AC to 1ph-AC
matrix converter without a central tap can not offer any advantages over the 1ph-AC to
1ph-AC matrix converter, as it is clear from the switching states shown in Table 2.2 and
the bounding region in Fig. 2.8.

S11 , S22 v1,in − v2,in t1
S11 , S12 0 t0
S21 , S12 v2,in − v1,in t2
S21 , S22 0 t0
Table 2.2. Switching states of a two-phase AC to single-phase AC matrix converter without a central tap
1.5
v2,in−v1,in
v1,in v2,in
1
v1,in, v2,in, +/−(v1,in− v2,in)
0.5
−0.5
−1
v1,in−v2,in
−1.5
0 2 4 6 8 10
ωt
Fig. 2.8. Bounding region for the output voltage of a 2ph-AC to 1ph-AC matrix converter without a central tap
2.3.2 2ph-AC to 1ph-AC matrix converter with fixed central tap

2ph-AC to 1ph-AC matrix converter with fixed central tap is shown in Fig. 2.9. All
switches Sij are bidirectional.
2ph-AC to 1ph-AC matrix converter with fixed central tap offers less switching combi-
nations, and their number is equal to the number of available switches in the first output
line. The list of switching states is provided in Table 2.3.
Average output voltage can be found using the following equation:

1 1 v1,in
vo,av = (t1 v1,in + t2 v2,in ) = t1 t2 (2.22)
Ts Ts v2,in
Using equation (2.22) one can conclude that when both input voltages are positive
(for π/2 < ωt < π) or negative (for 3π/2 < ωt < 2π), only positive or negative output
v1, o
io
+
S11 S21 S31 vo
v2, o
v1, in v2, in
Fig. 2.9. 2ph-AC to 1ph-AC matrix converter with fixed central tap

S11 v1,in t1
S21 v2,in t2
S31 0 t0
Table 2.3. Switching states of a two-phase AC to single-phase AC matrix converter with fixed central tap
voltages can be reconstructed by the matrix converter, correspondingly. Reason for this
is the incapability of the matrix converter to provide negative polarities of the input
voltages, because of the lack of controllable switches in the second output line of the
matrix converter. Bounding region for the output voltage is shown in Fig. 2.10.
1
v1,in v2,in
0.5
v1,in,n, v2,in,n
−0.5
−1
0 2 4 6 8 10
ωt
Fig. 2.10. Bounding region for the output voltage of a 2ph-AC to 1ph-AC matrix converter with fixed central
tap
2.3.3 2ph-AC to 1ph-AC matrix converter with switched central tap
2ph-AC to 1ph-AC matrix converter with switched central tap is shown in Fig. 2.11. All
switches Sij are bidirectional.
2ph-AC to 1ph-AC matrix converter with switched central tap offers more switching
combinations, on behalf of increased number of switches. The list of switching states is
provided in Table 2.4.
Average output voltage vo,av can be found using the following equation:
36 2 Matrix SICAM
v1, o
io
+
S11 S21 S31 vo
S12 S22 S32 v2, o
v1, in v2, in
Fig. 2.11. 2ph-AC to 1ph-AC matrix converter with switched central tap
Switches ON vout time interval

S11 , S12 0 t0
S11 , S22 v1,in − v2,in t1−2
S11 , S32 v1,in t1
S21 , S12 v2,in − v1,in t2−1
S21 , S22 0 t0
S21 , S32 v2,in t2
S31 , S12 −v1,in t−1
S31 , S22 −v2,in t−2
S31 , S32 0 t0
Table 2.4. Switching states of a two-phase AC to single-phase AC matrix converter with switched central tap
1
vo,av = [v1,in (t1 − t−1 + t1−2 − t2−1 ) + v2,in (t2 − t−2 + t2−1 − t1−2 )] =
Ts
1

v1,in
(2.23)
= t1 − t−1 + t1−2 − t2−1 t2 − t−2 + t2−1 − t1−2
Ts v2,in
All time intervals shown above form one switching interval Ts :
Ts = t0 + t1 + t2 + t−1 + t−2 + t1−2 + t2−1 (2.24)
When applying the switching strategy for the 2ph-AC to 1ph-AC matrix converter
with switched central tap, seven different time intervals should be determined according
to the desired output voltage. Two time intervals can be found using the equations (2.23)
and (2.24), so there are five degrees of freedom left to the switching strategy. Therefore,
a suitable strategy for determining single values for the time intervals in (2.23) should be
established.
Complexity of the switching strategies can be reduced if some switching patterns and
correspondingly some time intervals are avoided, like t1−2 and t2−1 . In this case the bound-
ing region for the output voltage is shown in Fig. 2.12, providing enough margin for syn-
thesizing high quality audio sound. The average value of the output voltage is given by
the following equation:

1 1 v1,in
vo,av = [v1,in (t1 − t−1 ) + v2,in (t2 − t−2 )] = t1 − t−1 t2 − t−2 (2.25)
Ts Ts v2,in
and for the switching interval Ts :
Ts = t0 + t1 + t2 + t−1 + t−2 (2.26)

0.5
v1,in,n, v2,in,n
0
−0.5
−1 −v2,in v1,in v2,in −v1,in

0 2 4 6 8 10
ωt
Fig. 2.12. Bounding region for the output voltage of a 2ph-AC to 1ph-AC matrix converter with switched central
tap
As a conclusion, the simplest matrix converter which can be appropriately designed to

provide uninterrupted power flow to single-phase load at audio frequencies has two input
voltages and a switched central tap. This topology of a matrix converter and especially
the corresponding control methods will be investigated in detail in the next few sections.
2.3.4 Switching strategies for 2ph-AC to 1ph-AC matrix converter with

switched central tap
Strategy with reduced number of switchings
This switching strategy tries to reduce the number of switchings and therefore switching
losses, by using the trial-and-error method to solve the equation (2.25). This method is
employed by using two switching states, one of them being zero output voltage switching
state for reconstructing the desired output voltage.
The procedure can be stated for the k-th switching interval as follows:
Try to solve one of the four equations:
k
tkj k
vout = v where: j = 1, 2, −1, −2 (2.27)
Ts j,in
with tkj satisfying the condition 0 < tkj ≤ Ts .

Then, the time interval tk0 of the zero output voltage is:
tk0 = Ts − tkj (2.28)
Changing from the switching state that corresponds to the time interval tkj to the
switching state for zero output voltage takes only one switching, since in each group of
switching states in Table 2.4 there is one zero voltage switching pattern. This will cause
only one switch to change state in the interior of the switching interval Ts , or two or three
switchings during the whole interval Ts , depending on the switching state used in the
previous interval and the one to be used in the following switching interval.
38 2 Matrix SICAM
Changing between the time intervals tkj and tk0 , which means connecting the load only
to one of the positive or negative polarities of the input phase voltages is enough, since
the envelope of the boundary region for this strategy corresponds to the one depicted in
Fig. 2.12. Any other combination of three or more switching states does not offer any
advantage, since the maximal value for the output voltage can not leave the bounding
region.
Looking from the point of reduced switching losses, having only one switch change its
state during the switching interval Ts looks certainly favorable. However, due to symmetry
concerns and in order to reduce the input current and the output voltage ripple along with
the associated HF harmonic content, it may be necessary to divide the zero voltage time
interval tk0 in two separated subintervals with same duration tk0 /2 and apply the nonzero
voltage time interval tkj in the middle.
This strategy with reduced number of switchings can be altered to include those switch-
ing states which produce the output voltages v1,in −v2,in and v2,in −v1,in , and will be referred
to as modified strategy with reduced number of switchings.
Diagonal switching strategy

There are two different approaches to diagonal switching: type A and type B, as shown
in Fig. 2.13.
S11 S21 S31 S11 S21 S31

tx ty tz tz tx ty
S12 S22 S32 S12 S22 S32
a) b)
Fig. 2.13. Diagonal switching: a) type A and b) type B
In both cases only three different switching states are used, without any zero output
voltage state. For simplicity, each of the three time intervals are indexed with x, y and z
consecutively tx , ty and tz , and their meaning is like the following:
• type A: tx → t1−2 , ty → t2 and tz → t−1
• type B: tx → t2−1 , ty → t−2 and tz → t1
The bounding region for the diagonal switching - type A is shown in Fig. 2.14 and it
proves to be slightly bigger than the bounding region for the previous unmodified switching
strategy with reduced number of switchings. However, number of switches changing state
is increased to four in the interior of the switching interval Ts , or six in the whole Ts . This
results in greater switching losses.
The average output voltage in the diagonal switching - type A, is calculated using the
following equation:
1
vo,av = [v1,in (tx − tz ) + v2,in (ty − tx )] (2.29)
Ts
and the switching interval is:
Ts = tx + ty + tz (2.30)
1.5
v1,in −v2,in
−v1,in,n, v2,in,n, v1,in,n−v2,in,n

0.5
−0.5
−1
−v1,in v2,in
−1.5
0 2 4 6 8 10
ωt
Fig. 2.14. Bounding region for the output voltage of a 2ph-AC to 1ph-AC matrix converter with switched central
tap in case of diagonal switching strategy - type A
In the diagonal strategy there is only one degree of freedom, since two time intervals
can be found from the equations (2.29) and (2.30).
By eliminating, for example, the time interval tz = Ts − tx − ty , the average output
voltage equation (2.29) becomes:
1
vo,av = [v1,in (2tx + ty − Ts ) + v2,in (ty − tx )] (2.31)
Ts
The procedure can be stated for the k-th switching interval as follows:
Start increasing the time interval tkx from 0 to Ts until time interval
tky is found that satisfies both the equation (2.31) and inequality
0 ≤ tky ≤ Ts − tkx , i.e.:
k
Ts vout,av + (Ts − 2tkx )v1,in
k
+ tkx v2,in
k
tky = k k
∈ [0, Ts − tx ] (2.32)
v1,in + v2,in
Then, time interval tkz is simply determined from:
tk3 = Ts − tk1 − tk2 (2.33)
The aforementioned procedure is also shown on the time diagram in Fig. 2.15, where
(s) marks the point at which the solution (2.32) was found.
Phasor-based switching strategy
Space-vector modulator for 3ph-AC to 3ph-AC matrix converter is presented in [23], based
on the indirect-transfer-function approach undertaken in [24]. Space-vector modulation
principle in 3ph-to-3ph AC to AC matrix converters [25] offers higher voltage gain and
less harmonic distortion in the input current and output voltage than other modulation
techniques. However, implementation of these techniques to the 2ph-AC to 1ph-AC matrix
converter with switched central tap is by no means straightforward. Similar approach can
40 2 Matrix SICAM
tx k
(s) tx
k+1
(s) tx
k k k k+1 k+1 k+1

tx ty tz tx ty tz
Ts Ts
Fig. 2.15. Time diagram for the diagonal switching strategy - type A
be designed using input voltage complex phasors, which is here referred as to phasor-based
switching strategy.
The set of input sinusoidal voltages with 90◦ phase shift and having the same angular
frequency ω = ωin given with the equation (2.20), can be represented by using complex
phasors v 1,in , v 2,in rotating clockwise in the complex plain, as shown in Fig. 2.16.
v1, in
-v2, in
v2, in
w
-v1, in
Fig. 2.16. Phasor diagram for input voltages
At the same time, the output voltage can have an arbitrary value due to the arbitrary
shape of the time waveform and it is irrational to connect any frequency or phase an-
gle to the latter. Assuming that this single value of the output voltage represents some
distance from the center of the complex coordinate system, it can be located on a top
of a radius vector named v out . As this vector is not moving, the same relation with the
phasor quantities of the input voltages will be kept if this radius vector is moving in the
counterclockwise direction with angular frequency ω and the phasors of the input voltages
standing still. The situation is depicted in Fig. 2.17.
According to the polarity of the output voltage and the value of the angle ωt, one can
put the output radius vector into corresponding sector, as shown in Table 2.5.
After the sector is found, from Table 2.6 the exact right (a) and the left (b) input
phasors can be determined, being either ±v 1,in or ±v 2,in . Combining this phasors during
k
one switching interval Ts will reconstruct the desired average of the output voltage vo,av :
k tka k tkb k
vo,av = va,in + vb,in (2.34)
Ts Ts
where the time intervals tka and tkb are found from the orthogonal projections va,out k
and
k
vb,out of the output phasor v out onto the right and left input voltage vector correspondingly:
II v1, in w I
vo
vb, o
-v2, in
wt
va, o
v2, in
III -v1, in IV
Fig. 2.17. Phasor diagram for input voltages and output voltage
Sector vok > 0 vok < 0

k
I 0 ≤ ωt ≤ π/2 π ≤ ωtk ≤ 3π/2
II π/2 ≤ ωtk ≤ π 3π/2 ≤ ωtk ≤ 2π
III π ≤ ωtk ≤ 3π/2 0 ≤ ωtk ≤ π/2
IV 3π/2 ≤ ωtk ≤ 2π π/2 ≤ ωtk ≤ π
Table 2.5. Sectors and corresponding output voltage polarities and angles ωtk
k
va,out
tka = Ts
|va,in |
k
k
vb,out
tb = Ts (2.35)
|vb,in |
k
k
va,out = |vout cos (ωtk )|
k
k
vb,out = |vout sin (ωtk )|
It should be stressed that the angular frequency ω is continuously corrected by checking

the moments when input voltages are passing through zero, i.e. determining the phase
through Phase-Locked Loops (PLLs).
Sector a b
I -2 1
II 1 2
III 2 -1
IV -1 -2
Table 2.6. Sectors and corresponding sector’s right and left vectors
When tka and tkb are determined, zero voltage vector time interval is calculated by the
following simple equation:
tk0 = Ts − tka − tkb (2.36)
For the purpose of pulse symmetry, switching patterns for the right and the left vector
should be appropriately divided on the either side of the central zero voltage vector, like
shown in Fig. 2.18.
42 2 Matrix SICAM
vout
.... ....
k k k k
ta /2 tb /2 t0 tb /2 ta /2
Ts
Fig. 2.18. Distribution of switching patterns’ time intervals through one switching interval Ts
2.3.5 Obtaining another phase- lagging/leading voltage from AC-mains
In one of the previous sections it was concluded that matrix converter with a single AC
output needs at least two phase-shifted voltages. Principles for obtaining another phase-
shifted voltage, which lags or leads the mains voltage can be divided mainly in two groups:
• Passive methods: using only reactive elements - inductors and capacitors, and
• Active methods: using dedicated switching-mode converter topologies.
Passive methods for obtaining another phase-shifted voltage
Each of these methods is characterized by including some reactive elements in the circuit,
which will cause some phase lag/lead in the circuit current. When this current is passed,
for example, through a serial or parallel resistor, corresponding voltage drop lags/leads
the input voltage from the AC mains.
However, adding some reactive elements between the AC mains voltage and the load
can cause the output voltage to have slightly smaller amplitude than the input one,
creating imbalances in the supply of the 2ph-AC to 1ph-AC matrix converter. The added
reactive components tend to be bulky because of the required phase-shifts close to 90◦
at the frequency of the AC-mains voltage. Even more, this can make the phase-shifted
voltage appear as a rather high impedance voltage source at higher frequencies, which
results in the output voltage from the passive phase-shifter being especially sensitive to
load variations.
In the following analysis a complex representation of the sinusoidal voltages and cur-
rents in steady-state will be used, in order to simplify the calculations. Let the input
voltage vs have the following time domain and complex notation representations:
√
vs (t) = 2Vs sin (ωt)
(2.37)
Vs = Vs 6 0◦
The following analysis of simple circuit combinations comprising of capacitor C, induc-

tor L and resistive load R is provided just to illustrate some possibilities, although their
feasibility is limited by the aforementioned problems of requiring large reactive compo-
nents to achieve the needed phase-shift. As already mentioned, the load being in this case
one of the input phases of a matrix converter is modelled as load resistance R to simplify
the analysis, although some other representation like constant power sink might be more
appropriate when dealing with switching-mode power converters.
• L − R series circuit:
R
VR = RIL = Vs (2.38)
R + jωL
and the corresponding amplitude and phase of the load voltage are:
R
|VR | = p Vs
R2 + (ωL)2 (2.39)
ωL
6 VR = − arctan
R
When ωL ≫ R, the load voltage amplitude and phase become:
R
|VR | ≈ Vs
ωL (2.40)
6 VR ≈ −90◦
iL L iC C
vs R vR vs R vR
Fig. 2.19. L − R series circuit Fig. 2.20. C − R series circuit
• C − R series circuit:
R
VR = RIC = 1 Vs (2.41)
R − j ωC
R
|VR | = q Vs
1
R2 + (ωC)2 (2.42)
1
6 VR = arctan
ωRC
When 1/ωC ≫ R, the load voltage amplitude and phase become:
|VR | ≈ ωRCVs
(2.43)
6 VR ≈ 90◦
• L − C − R series circuit:
R
VR = RIL = 1 Vs (2.44)
R + j(ωL − ωC
)
R
|VR | = q Vs
1 2
R2 + (ωL − ωC ) (2.45)
1
ωL − ωC
6 VR = − arctan
R
In case of resonance ωL = 1/ωC, the load voltage amplitude and phase become:
44 2 Matrix SICAM
iL L C iL L iR
vs R vR vs C R vR
Fig. 2.21. L − C − R series circuit Fig. 2.22. L − C − R parallel circuit
|VR | ≈ Vs
(2.46)
6 VR ≈ 0◦
When L → 0 or C → ∞ one obtains the C − R or L − R series circuit, which were

explained in the previous two paragraphs.
• L − C − R parallel circuit:
R
VR = RIR = Vs (2.47)
(R − ω 2 RLC) + j(ωL)
R
|VR | = p Vs
R2 (1 − ω 2 LC)2 + (ωL)2 (2.48)
ωL
6 VR = − arctan
R(1 − ω 2 LC)
In case of resonance ωL = 1/ωC, the load voltage amplitude and phase become:
R
|VR | ≈ Vs
ωL (2.49)
6 VR ≈ −90◦
It is clear that from all of the circuits presented, only the L − C − R parallel circuit
can offer −90◦ phase shift of the output voltage without requiring any huge values for
the inductance L or the capacitance C. The only condition, which should be fulfilled is
ωL = 1/ωC. However, in order to keep with some safety precautions, like not allowing the
output voltage to raise significantly above the levels of the input voltage, one must insure
that the resonant circuit will be appropriately loaded (small resistance R comparable to
the impedance of the series inductor ωL). If this can not be guaranteed, or the resonant
circuit is loaded in pulses, adding a fixed minimal resistance Rmin in parallel to the load
or even adding some silicon switches and passive nets in between can mitigate the voltage
conditions on the load side.
The load in all of these examples was taken to be a constant value linear resistance R.
Matrix converter connected at the power supply output can not be regarded as linear load,
since it is by its switching nature hardly nonlinear. These conditions can be mitigated by
employing some low-pass filtering on the matrix converter input, as well as employing
advanced control methods for power factor correction. On the other hand, some silicon
switching components can be added to the passive power supply used for obtaining another
phase, which will, when suitably controlled, diminish the effects of the varying load. This
represents an active method and it is subject of discussion in the following section.
Active methods for obtaining another phase-shifted voltage
Active methods refer to constructing another phase-shifted voltage by using some power
converter topology. This actually corresponds to building a dedicated power supply, where
the output voltage has the same form and frequency as the input AC-mains voltage, but
the phase is shifted to around 90◦ .
The most obvious choice for building the aforementioned power supply is certainly the
resonant converter. It is characterized with near sinusoidal output voltages (depending
on the operation mode), low electromagnetic interference (EMI), less switching losses
allowing for greater operating frequencies [26]. There are plenty of different approaches,
and the parallel-loaded resonant converter is probably the most favorite, due to its unique
features [27], [28]. Unlike the series loaded resonant converter (SLRC), parallel-loaded
resonant converter (PLRC) [26]:
• appears as a voltage source and hence is better suited for multiple outlets,
• does not possess inherent short-circuit protection capability, which is a drawback, and
• can step up (boost) as well as step down (buck) the voltage, unlike the SLRC which
can operate only as a step-down converter.
However, it seems very difficult to construct an AC-AC resonant converter that is
capable of synthesizing a 90◦ phase-shifted sinusoidal voltage with frequency of 50 Hz,
which is powered directly from the same AC-mains (although a 100 Hz voltage with
lower amplitude can be easily reconstructed). Therefore, a DC power supply must be
present in front of the resonant converter, in order to allow for some energy storage in
its reactive components, as shown √ in Fig. 2.23. Parallel resonant LC circuit is tuned to
angular frequency ω = 2πf = 1/ LC, where f = 50 Hz is the frequency of the AC mains
voltage, which clearly leads to rather bulky reactive components for the resonant tank. A
dedicated control unit should be used to drive the switches in the resonant converter, in
order to construct an output voltage that lags/leads the AC mains input-voltage for 90◦ .
Since the switching frequency should be fs = f = 50 Hz for getting output voltage with
the same frequency, some control over the output voltage magnitude can be provided by
using, for example, different duty ratios of the gate pulses [29].
Parallel-loaded resonant converter

Parallel resonant
DC power supply circuit
AC mains DC
il Lr Load
S1 S3
Rectifier Energy +
+
storage vd Cr vo R
S2 S4
Control unit
+ drivers
Fig. 2.23. Parallel-loaded resonant converter used for obtaining another voltage phase
Another active method as an alternative to the aforementioned PLRC comprises of

Voltage Source Inverter (VSI) with the same DC input voltage like in the case of the
PLRC, except for the fact that it is operated with much higher switching frequency in
PWM mode to reconstruct another phase-shifted AC-voltage with AC-mains frequency.
However, the reviewed power converters for creating another phase-shifted voltage rep-
resent additional burden for the already complex matrix converter based SICAM and are
46 2 Matrix SICAM
definitely not reconsidered as very appealing solution from either perspective. Therefore,
the following sections will analyze thoroughly the passive parallel LC approach to creating
another phase-shifted voltage for use in 2ph-AC to 1ph-AC matrix SICAM.
2.4 Matrix SICAM with LC-network

For further analysis, a two-phase switched-central-tap matrix converter (2ph SCT MC)
with an LC passive network is chosen. For larger output voltage margin, an LC-network
being resonant at the input voltage frequency ωin is required, but other designs are possible
too. Its scheme is shown in Fig. 2.24 and it will be referred to in the following paper as
MC-based SICAM or matrix SICAM with an LC-network.
+
S11 S21 S31 vo R
S12 S22 S32
L
vin C
Fig. 2.24. MC-based SICAM with an LC-network
It was already shown in Section 2.3.3 that a matrix converter with switched central tap
offers the greatest number of possible switching states and the output voltage margin is the
largest, on behalf of more complex switching strategy and greater number of bidirectional
switches. There are exactly three general equivalent topologies of the input voltage source
vin and the LC-network with respect to the load resistance R position: load resistance
can be either in parallel with the input voltage source vin i.e. unloading the LC-network -
Fig. 2.25a or it can be in parallel with the capacitor C or the inductor L, and thus loading
the LC-network - Fig. 2.25b,c.
R
L L L
vin C R vin C vin C
R
a) b) c)
Fig. 2.25. General topologies: a) vin kR, b) LkR and c) CkR
It is interesting to make a short analysis of the capacitor and inductor voltages in the
case of unloaded LC-network using complex domain analysis and phasors at frequency
ω = ωin .
1 Vin Vin Vin
VC = ZC · IC = 6 180◦
1 = − 2 = 2 (2.50)
jωC jωL + jωC ω LC − 1 ω LC − 1
2.4 Matrix SICAM with LC-network 47
Vin ω 2 LCVin ◦
VL = ZL · IL = jωL 1 = 6 0 (2.51)
jωL + jωC ω 2 LC − 1
Equations (2.50) and (2.51) show that both voltages are either in phase or with phase
difference of π radians with the input voltage. During this state the load is connected
across the input voltage source, and this connection can be used as long as the output
voltage is high enough. However, when choosing the LC-network to be resonant at the
input voltage frequency ω 2 = 1/LC, which is surely desirable for providing better output
voltage margin when switching as shown in Section 2.3.3, the amplitudes of the capacitor
and the inductor voltages become theoretically infinite:
Vin
VC = 2
→∞ (2.52)
ω LC − 1
ω 2 LCVin
VL = →∞ (2.53)
ω 2 LC − 1
Following the latter analysis, it is concluded that switching states which lead to un-
loaded LC-network should be avoided, especially if the LC-network is made to be resonant
or nearly resonant at the input voltage frequency. The revised list of switching states in
the case of MC-based SICAM with an LC-network is given in Table 2.7.
Switches ON vout time interval status

S11 , S12 0 t0 unloaded LC - not allowed
S11 , S22 v1,in − v2,in t1−2 LkR
S11 , S32 v1,in t1 unloaded LC - not allowed
S21 , S12 v2,in − v1,in t2−1 LkR
S21 , S32 v2,in t2 CkR
S31 , S12 −v1,in t−1 unloaded LC - not allowed
S31 , S22 −v2,in t−2 CkR
Table 2.7. Switching states of an MC-based SICAM with LC-network
Except for restricting the MC-based SICAM in applying certain switching states, an-
other approach can be employed. By applying an external permanent constant-valued
resistor Ra in parallel with the capacitor C, like shown in Fig. 2.26, the resonant LC-
network can be permanently loaded and reliable operation guarantied. However, this also
leads to additional power losses in excess of:
2
VC,rms
PRa = (2.54)
Ra
which can be very high, provided the resonant LC-network is properly loaded. Therefore,
it is advantageous to use only the load impedance for loading the LC-network.
In the following sections it will be assumed that the load is completely represented by
its resistance R. The influence of the output filter will be analyzed in Section 2.4.6.
2.4.1 Analysis of matrix SICAM switching between LkR and CkR
After taking a closer look at Table 2.7, it appears that each of the allowed switching states
either connects the load R in parallel with the inductor L, or in parallel with the capacitor
C.
48 2 Matrix SICAM
+
S11 S21 S31 vo R
S12 S22 S32
L
vin C Ra
Fig. 2.26. Loading the LC-network with an additional resistor Ra
For the sake of simplicity, the capacitor C voltage will be determined for each of the two
cases in steady-state, using complex domain phasors at input voltage frequency ω = ωin .
Then the inductor L voltage can be simply determined by subtracting the capacitor C
voltage from the input voltage vin .
• CkR: Output voltage vo is equal to the voltage across the capacitor C:
Vo = VC (2.55)
Capacitor C voltage phasor is:

1
R jωC
CkR 1
R+ jωC R
VC = Vin = 1 Vin = 2
Vin (2.56)
jωL + CkR R
jωL + R+jωC1 R(1 − ω LC) + jωL
jωC
Capacitor voltage magnitude and phase are:

R ωL
|VC | = p Vin 6 VC = − arctan (2.57)
R2 (1 − ω 2 LC)2 + (ωL)2 R(1 − ω 2 LC)
When a resonant LC-network is used, yielding ω 2 = 1/LC, capacitor voltage magnitude

and phase become:
R
|VC | = Vin 6 VC = −90◦ (2.58)
ωL
• LkR: Output voltage vo is equal to the voltage across the inductor L:
Vo = VL = Vin − VC (2.59)
Capacitor C voltage phasor is:

1 1
jωC jωC R + jωL
VC = 1 Vin = RjωL 1
Vin = Vin (2.60)
LkR + jωC R+jωL
+ jωC R(1 − ω 2 LC) + jωL
Capacitor voltage magnitude and phase are:

s
R2 + (ωL)2

ωL ωL
|VC | = · Vin 6 VC = arctan −
R2 (1 − ω 2 LC)2 + (ωL)2 R R(1 − ω 2 LC)
(2.61)
When a resonant LC-network is used, leading to ω 2 = 1/LC, capacitor voltage mag-

nitude and phase become:
s 2
R R
|VC | = 1 + · Vin 6 VC = − arctan (2.62)
ωL ωL
Voltages of both general topologies for the case R/ωL = 1 and a resonant LC-network
are shown in Fig. 2.27. Output voltages are marked with a bold line, and voltages for
the topologies CkR and LkR are clearly marked with subscript indexes C and L. Input
voltage is represented with v1,in and the capacitor voltage is the second phase voltage
v2,in .
L || R and C || R , R/ωL=1
1.5
v v −v
2,in,L 2,in,C 1,in
v −v
1 2,in,L 1,in
v
2,in,C
0.5
n
0
v
−0.5
−v
2,in,C
−1 v −v
1,in 2,in,L
−v v −v
2,in,L 1,in 2,in,C
−1.5
0 1 2 3 4 5 6 7 8 9 10
ωt
Fig. 2.27. Steady-state voltages in MC-based SICAM with resonant LC-network and R/ωL=1
From Fig. 2.27 it is apparent that both steady-state output voltages for the cases CkR
and LkR are the same. This leads to a conclusion that when the analysis is based only on
the steady-state sinusoidal components of the output voltages without any intermediate
switching between the two load arrangements CkR and LkR, the performance of the
MC-based SICAM using an LC-network is poor, with zero output voltage margin. This is
result of the output voltages being in phase (or a phase difference being π) for both CkR
and LkR general topologies.
This conclusion can be extended to non-resonant LC-networks, by observing the phase
of the steady-state sinusoidal output voltages. When MC-based SICAM operates in LkR
topology, the output voltage is:
Rω 2 LC

R + jωL
Vout = VL = VC − Vin = − 1 Vin = Vin
R(1 − ω 2 LC) + jωL R(1 − ω 2 LC) + jωL
(2.63)
Output voltage phase in this case is:

50 2 Matrix SICAM
ωL
6 VL = − arctan (2.64)
R(1 − ω 2 LC)
which is equal to the output voltage phase in (2.57) when CkR.
For the purpose of audio band output voltage construction, it is required that the
MC-based SICAM using an LC-network must switch between the two general topologies
CkR and LkR. At the switching instant, both the capacitor voltage vC and the inductor
current iL cannot have a leap, so there is only a change in the waveform slope. In order
to satisfy the initial conditions in terms of capacitor voltage and inductor current, ex-
ponential i.e. DC transient components are induced. These transient components in the
capacitor voltage and inductor current fade out with a time constant which depends upon
the capacitance C, inductance L and load resistance R, and they change the shape of
the steady-state output voltage waveforms. Switching between CkR and LkR and back
each half period of the input voltage in smartly determined instants, an envelope of the
output voltage possible waveforms i.e. an output voltage margin can be created which
never approaches zero. Fig. 2.28 presents only the approximate waveforms of the MC-
based SICAM, when switching from CkR to LkR and back. Again the input voltage is
represented with v1,in and the capacitor voltage is the second phase voltage v2,in .
L || R and C || R , R/ωL=1
1.5
v2,in,L v −v
2,in,C 1,in
v −v
1 2,in,L 1,in
v
2,in,C
0.5
desired
output
n
0
v
voltage
margin
−0.5
−v
2,in,C
−1 v1,in−v2,in,L
−v v1,in−v2,in,C
2,in,L
−1.5
0 1 2 3 4 5 6 7 8 9 ωt 10
C||R L||R C||R
Fig. 2.28. Approximate transient voltages in MC-based SICAM with resonant LC-network and R/ωL=1
Like shown in Fig. 2.28, switching from CkR topology to LkR topology occurs at
the instant when the output voltage, which in case of CkR is equal to the capacitor
voltage vo = v2,in,C , reaches the desired output voltage margin from outside. Then it
is changed to LkR topology, and the output voltage equals the difference between the
input voltage and the capacitor voltage vo = v2,in,L − v1,in (i.e. the inductor voltage).
However, when switching it is clear that capacitor voltage v2,in,C at that instant will
remain unchanged, so the output voltage will depart the sinusoid v2,in,L − v1,in and follow
the waveform v2,in,C − v1,in , like in the case of CkR. As DC transient components start
to fade out the output voltage tends to reach the steady-state inductor voltage waveform
vo → v2,in,L − v1,in , again approaching the desired output voltage margin from outside. As
soon as the output voltage reaches the margin, load is switched i.e. displaced from topology
LkR to CkR and the output voltage again becomes equal to the capacitor voltage instant
value vo = vC , which is slightly bigger than the steady state one v2,in,C for the case CkR
because of the DC transient components. This way the envelope of the output voltage can
stay out of the desired output voltage margin, provided:
• Switching from CkR to LkR and back occurs at correct instants, when maximal output
voltage is out of the desired output voltage margins, and
• Time constants of the LCR circuit, dominated by the capacitor value C, are long
enough to support a DC transient component of the capacitor voltage during the
whole of the time being in one of the general topologies.
It should be stressed, however, that the time diagram shown in Fig. 2.28 is only ap-
proximate one, since the induced DC transient components of the capacitor voltage will
change the appearance of the capacitor voltage waveform, which will more or less differ
from a sinusoidal one (depending on the time spent in each of the general topologies CkR
and LkR).
In the following subsections an exact time domain analysis of the two general topologies
CkR and LkR will be undertaken.
2.4.2 Time domain analysis of the two load combinations
As mentioned before, operation of the matrix SICAM with LC-network is restricted to

two load combinations - CkR and LkR. The differential equations describing the capacitor
voltage vc in this two cases are solved in the Appendix A.1 and the results are given below:
• CkR:
vC (t) = AC et/τ1 + BC et/τ2 + DC sin ωin t + EC cos ωin t (2.65)
where the constants in the solution are given with the following expressions:
− dvdtC0 + vC0 s2 − EC s1 + ωin DC

AC =
s2 − s1
dvC0
− vC0 s1 + EC s2 − ωin DC
BC = dt
s2 − s1
ωL2 (ωL2 − ωin
2
)
DC = 2 2 2
Vin (2.66)
(ωL − ωin ) + (ωR ωin )2
ωR ωL2 ωin
EC = − 2 2 2
Vin
1
ωR = RC
ωL = √1
LC
and the time constants are:

2
τ1,2 = p (2.67)
−ωR ± ωR2 − 4ωL2
• LkR:
vC (t) = AL et/τ1 + BL et/τ2 + DL sin ωin t + EL cos ωin t (2.68)
where the constants in the solution are given with the following expressions:
52 2 Matrix SICAM
− dvdtC0 + vC0 s2 − EL s1 + ωin DL

AL =
s2 − s1
dvC0
− vC0 s1 + EL s2 − ωin DL
BL = dt
s2 − s1
ω (ω − ω ) + (ωR ωin )2
2 2 2
DL = L 2 L 2 in2 Vin (2.69)
3
ωR ωin
EL = − 2 2 2
Vin
1
ωR = RC
ωL = √1
LC
and the time constants are:

2
τ1,2 = p (2.70)
−ωR ± ωR2 − 4ωL2
From the solutions for the capacitor voltage in the two aforementioned load combina-
tions it becomes clear that they include not only sinusoidal components created by the
input voltage but also transient components, which depend on the initial conditions and
decay with a time constant being a function of the values of the LC-network. It is due to
the latter transient components that the waveforms of the supply voltages start to depart
one from another and create enough output voltage margin.
2.4.3 HF switching of matrix SICAM for constructing the audio waveform

The analysis presented in the previous few sections handled about establishing the desired
output voltage margin by using the appropriately timed switching between CkR and
LkR topologies. The envelopes of the maximal and minimal output voltage coincide with
the capacitor voltage ±vC , when load is connected across the capacitor C (CkR) and
±(vin − vC ), when load is connected across the inductor L (LkR). The exact desired
output voltage value is situated somewhere within the output voltage margin, so it can be
reconstructed only by HF switching of the load between the positive and negative polarity
of the capacitor C or inductor L voltage in a predetermined way.
All the possible topologies for the MC-based SICAM with loaded LC-network are
shown in Fig. 2.29. When MC-based SICAM is in CkR topology, it resides in configuration
2 for time period t2 and in configuration -2 for time period t−2 . The output voltage
average equals:
1
vo,av = (t2 vc − t−2 vc ) = (d2 − d−2 )vc (2.71)
Ts
where Ts = t2 +t−2 represents the switching interval for CkR, d2 = t2 /Ts and d−2 = t−2 /Ts
represent the duty cycles for configurations 2 and -2 , correspondingly.
When MC-based SICAM is in LkR topology, it resides in configuration 1-2 for time
period t1−2 and in configuration 2-1 for time period t2−1 . The output voltage average
equals:
1
vo,av = [t1−2 (vin − vc ) + t2−1 (vc − vin )] = (d1−2 − d2−1 )(vin − vc ) (2.72)
Ts
where Ts = t1−2 + t2−1 represents the switching interval for LkR, d1−2 = t1−2 /Ts and
d2−1 = t2−1 /Ts represent the duty cycles for configurations 1-2 and 2-1 , correspondingly.
S21,S32 S31,S22
2 -2
iL L io iL L io
+ + +
vin vC C vo R vin vC C vo R
+
S11,S22 S21,S12
1-2 2-1
R io R io
+ vo vo +
iL L iL L
+ +
vin vC C vin vC C
Fig. 2.29. Possible topologies for the MC-based SICAM with loaded LC-network
While equations (2.71) and (2.72) describe the dependence of the output voltage on
the absolute values of the various duty cycles and the input and capacitor voltage, the
small-signal behavior of the output voltage when perturbations are present in the cir-
cuit quantities can be found by using the state-space averaging approach described in
Appendix A.2.
2.4.4 Design of matrix SICAM with resonant LC-network
Design of each matrix SICAM with LC-network starts with a list of audio perfor-
mance specifications: maximum output power Po , target audio bandwidth faudio and load
impedance Zo = R. While the target audio bandwidth primarily affects the values of the
output filter components and the switching frequency, the maximum output power and
the load impedance affect the selection of the LC-network values.
The output power is defined as:
2
Vo,rms
Po = (2.73)
R
which leads to the following expression for the maximal rms value of the output voltage:
p
Vo,rms = RPo (2.74)
and assuming sinusoidal output voltage the following expression for its maximal peak
value is obtained:
√ p
Vo,pk = 2Vo,rms = 2RPo (2.75)
Maximal peak value of the output voltage (2.74) is important, since it determines
how big is the desired output voltage margin. Failing to preserve this margin will lead to
reduced output power, while increasing the margin will lead to conservative approach with
bulky components, like for example bulky capacitor C resulting in large time constants
for the DC transient components, leading to inefficient and expensive design.
54 2 Matrix SICAM
After an insight in the specifications and the way they affect the output voltage margins
has been obtained, it can be proceeded to defining some important design parameters.
The first one is the resonance coefficient a, which states how much the resonant frequency
of the LC-network ωL differs from the input voltage angular frequency ωin = ω:
ωL 1
a= = √ (2.76)
ωin ω LC
The second one is the impedance ratio b, which determines how large is the inductor
impedance ωL in comparison with the load impedance Zo :
Zo R
b= = (2.77)
ωin L ωL
Design parameters a and b can be brought into close connection with the circuit voltages
and currents for different topologies and are therefore equivalent to using the capacitance
C and inductance L. After design parameters are found which satisfy the specifications,
they are used to determine the capacitance C and inductance L by the following relation-
ships:
R
L=
ωb
1 ω b b (2.78)
C= 2
= 2
=
LωL R ωL Ra2 ω
In the Appendix A.1 where the time domain analysis of the two general topologies CkR
and LkR is undertaken, it is shown that the DC transient components of the capacitor
voltage have the same exponential elements es1,2 t , defined by:
p s r
−ωR ± ωR2 − 4ωL2 ωL2 b2

ωR ωR
s1,2 = =− 1± 1−4 2 =− 1± 1−4 2 (2.79)
2 2 ωR 2 a
since:
ωL2 R2 C 2 R2 2 b2
= = ω LC = (2.80)
ωR2 LC (ωL)2 a2
In all of the cases where a2 < 4b2 , exponents s1,2 become two complex conjugates, which
means that DC component is actually consisting of a product of exponentially decaying
waveform and a sine/cosine components:
r r
b2 b2
ωR 1 − 4 t ωR − 1 − 4 t
Ai es1 t + Bi es2 t = Ai e− 2 t e a2 + Bi e− 2 t e a2 (2.81)
The real part of the exponents s1,2 is:
ωR 1
s0 = = (2.82)
2 2RC
and the associated time constant τ0 is:
1
τ0 = = 2RC (2.83)
s0
One of the conditions for proper operation of an MC-based SICAM with an LC-network
mentioned in Section 2.4.1 was having enough long LCR circuit time constants, which
will support the DC transient components of capacitor voltage for a longer time. Now
one can state it even more explicitly: the time constant τ0 should be comparable to the
time interval tC spent in CkR and to the time interval tL spent in LkR. Approximately
it should amount around a quarter of the input voltage period 20ms/4 = 5ms, since the
topology is switched four times during one period of input voltage. This can also limit
the minimum allowed value of the capacitance C.
The other important design issue is the value of the reactive current. When using
bulky inductors and capacitors in a SICAM for the higher power range, this may be an
important limitation too. Averaging principle on the two general topologies can be used
to determine the reactive component of the input current.
• CkR: 2 , -2
Input current in time domain is given with the equation:
vC dvC
iin,C = iL = iR + iC = +C (2.84)
R dt
or when taking (A.21) into consideration:
1 1
+ Cs1 es1 t + BC + Cs2 es2 t +

iin,C = AC
R R (2.85)
DC EC
+ − Cωin EC sin ωin t + + Cωin DC cos ωin t
R R
where AC , BC , DC and EC are given by the relations (A.20) and (A.24). If the transient
components and the sine component, which is in phase with the input voltage, are
neglected, the following relation for the maximum value of the input current reactive
component in CkR topology is obtained:
EC
Iin,C,react,max = + Cωin DC (2.86)
R
• LkR: 1-2 , 2-1

Input current in time domain is given with the equation:
dvC
iin,L = iC = C (2.87)
dt
or when taking (A.45) into consideration:
iin,L = Cs1 AL es1 t + Cs2 BL es2 t − Cωin EL sin ωin t + Cωin DL cos ωin t (2.88)
where AL , BL , DL and EL are given by the relations (A.44) and (A.48). If the transient
components and the sine component, which is in phase with the input voltage, are
neglected, the following relation for the maximum value of the input current reactive
component in LkR topology is obtained:
Iin,L,react,max = Cωin DL (2.89)
Now, an averaging on a time scale comparable to the input voltage period

Tin = 1/fin = 20ms can be undertaken, leading to the following averaged maximum
value of the input current reactive component:
56 2 Matrix SICAM
EC
Iin,react,max = dC Iin,C,react,max +dL Iin,L,react,max = dC +Cωin DC +dL Cωin DL (2.90)
R
where dC = 2tC /Tin and dL = 2tL /Tin represent the duty cycles in CkR and LkR topology,
correspondingly.
It is interesting to determine the input current reactive component when the
LC-network is designed to be resonant at input frequency. In that case DC , EC and
DL , EL are determined by (A.25) and (A.49), correspondingly , which leads to:
1 ωin
Iin,react,max = − dC + dL Cωin Vin,max = (dL − dC )Cωin Vin,max (2.91)
R ωR
The result is rather surprising, since it shows that whenever the duty cycles dC and
dL are chosen to satisfy dC = dL , there will be no input current reactive component. This
conclusion does not suggest anything about when the switching should occur, but it is
desired that one tries to commute the input current into another direction as soon as the
input voltage changes the polarity, just to stay in phase with it.
2.4.5 Design example of matrix SICAM with resonant LC-network

This section will briefly show the approach to select the most important components of
the matrix SICAM, based on given specifications.
The specifications in terms of target power range Po , target audio bandwidth faudio
and load impedance Zo = R are given in Table 2.8.
Pout 500 W
faudio 20 Hz - 20 kHz
R 8Ω
Table 2.8. Design specifications for matrix SICAM with LC-network
From the target power range, the peak output voltage Vo,pk can be easily calculated
using (2.75):
p √
Vo,pk = 2RPo = 2 · 8 · 500 ≈ 90V (2.92)
This peak output voltage will determine the desired output voltage margins (±90 V).
Since the target audio bandwidth is 20 Hz - 20 kHz, the corner frequency of the output
filter can be set to, for example, fcf = 25 kHz. Satisfactory output voltage ripple should
be expected if the switching frequency is, for example, at least ten times higher than the
output filter corner frequency fs = 10fcf = 250 kHz and thus the switching interval is
Ts = 1/fs = 4 µs.
The goal in this section is to design matrix SICAM with a resonant LC-network, which
will provide best performance in terms of output voltage margin. At the same time, the
impedance of the inductor at the input frequency ωin is chosen to be equal to the load
impedance Zo = R. Therefore both design parameters a and b in (2.76) and (2.77) are
equal to 1, a = b = 1.
Choosing a = b = 1 leads to the following values for the inductance L and capacitance
C, according to equations (2.78):
R 8
L= = = 25.5mH
ωb 2π50 · 1 (2.93)
b 1
C= = = 398µF
Ra2 ω 8 · 1 · 2π50
Selection of capacitor C value in (2.93) leads to the following time constant τ0 , as

defined in (2.83):
τ0 = 2RC = 2 · 8 · 398 · 10−6 = 6.4ms (2.94)
The time constant τ0 = 6.4 ms is very close to a quarter of the input voltage pe-
riod 20 ms/4=5 ms. Therefore, it is expected that there will be enough time for the DC
transient components in the capacitor voltage to support the output voltage when switch-
ing between the two switching general topology and maintain the desired output voltage
margin.
To avoid any reactive component in the input current one could choose dC = dL = 0.5,
as stated in Section 2.4.4.
2.4.6 Influence of the output low-pass filter Lf , Cf

The scheme of the matrix SICAM with LC-network and output low-pass filter added
between the converter and the load is shown in Fig. 2.30. Again, purely resistive load R
is assumed.
Lf
+
S11 S21 S31 Lf Cf vo R
S12 S22 S32
Zin
L
vin C
Fig. 2.30. Matrix SICAM with LC-network and output low-pass filter
Adding some inductance to the load on the output side of the matrix converter leads
to commutation problems of the bidirectional switches. Actually, a basic problem of the
matrix converter is the absence of a freewheeling path to the load. This is alleviated by
using different switch commutation techniques based on input voltage polarity or load
current direction measurement [30], as thoroughly explained in Section 6.2.1.
The biggest problem with introducing the output filter is its frequency dependent input
impedance characteristic Zin (ω):
R + sLf + s2 RLf Cf
Zin (s) = (2.95)
1 + sRCf
As it was mentioned earlier, the LC-network on the input side is made bulky and
resonant at the input voltage frequency ω in order to store enough energy in it during
the periods with low input voltage and maintain satisfactory output voltage margin.
Unfortunately, such a big input filter must be properly loaded on the output side in
order to avoid excessive voltage surge in the capacitor and inductor voltage and therefore
excess reactive currents. Since the matrix converter has switching frequency which is
significantly higher than the mains frequency, the output filter cannot be reconsidered
as purely resistive anymore but is likely to be dominated by the reactance of the output
filter inductor, as shown on the diagram in Fig. 2.31. This diagram is showed for low-pass
58 2 Matrix SICAM
Output filter input impedance Z (f)

in
45
40
Magnitude [dBΩ]
35
30
25
20
15
1 2 3 4 5 6
10 10 10 10 10 10
f [Hz]
100
Phase [deg] 80
60
40
20
0
1 2 3 4 5 6
10 10 10 10 10 10
f [Hz]
Fig. 2.31. Frequency characteristic of the input impedance Zin (f ) of the output filter
output filter designed the same way like in [31] and the components of a second-order
Butterworth filter with a load of R = 8 Ω are Lf = 36 µH and Cf = 560 nF.
All these aforementioned drawbacks of the matrix SICAM with LC-network when
output filter Lf , Cf is added for filtering the switching harmonics across the load are
seriously hampering the application prospects of this non-isolated SICAM topology.
2.4.7 Open-loop control principles
Open-loop control techniques should provide means for varying the output voltage of
the matrix SICAM with LC-network according to the audio reference signal in a simple
and satisfactory way without closing the feedback loop. Switching strategies presented
in Section 2.3.4 are computationally intensive and are better suited for digital imple-
mentation on a Digital Signal Processor (DSP) with lower switching frequencies of the
matrix SICAM. For the high switching frequencies required by the audio applications the
analogue implementation of the PWM modulator seems mush better suited.
The main challenge of the open-loop control techniques for matrix converters is the
need to cope with the slowly varying input voltage, i.e. to provide high enough power sup-
ply rejection ratio (PSRR). This is usually accomplished by implementing input voltage
feedforward to change correspondingly the conduction times of the bidirectional switches.
Without feedforward of the input voltage, the only possibility for improving perfor-
mance is through closed-loop control and feedback of the output voltage, which will cor-
rect for the variations in the input voltage once their effects appear in the output voltage.
From the closed-loop control principles, it is supposed that one-cycle nonlinear control
techniques, like the one presented in [32] should provide best performance for the matrix
SICAM. In the center of the one-cycle control principle is the integrator element, which
integrates the applied voltage across the load and determines the switching instants based
on the equality of that integral to the desired, reference value. Thus, these controllers can
easily cope with the varying input voltage by providing equal Volt-seconds on a cycle-by-
cycle basis despite of any disturbances. Their suitability for matrix SICAM is therefore
result of the very good power supply rejection ratio (PSRR) and the fast response. How-
ever, these methods were not investigated herein.
In this section, two different PWM open-loop control principles will be investigated,
which are appropriate for implementation in analog domain: amplitude modulation (AM)
of the triangular carrier and ∆ modulation technique.
clock +/-
(mains synchronized)
10ms
vo, ref +
|vin-vc| _Comp drivers Sij
|vc| }/Vo, pk
x
Carrier 5ms
1 clock
-1 C||R or L||R
a)
clock +/-
1/2 10ms
vo, ref .. D
+ +
_Comp drivers Sij
2|vin-vc|
2|vc| Carrier 5ms
1 clock
0 C||R or L||R
b)
Fig. 2.32. Open-loop control principles: a) AM of the triangular carrier and b) ∆ modulation technique
AM of the triangular carrier
Open-loop control technique called AM of the triangular carrier is shown in Fig. 2.32a.
The idea behind it is to make an amplitude modulation (AM) of the fixed-frequency
triangular carrier according to the available output voltage margin. Unfortunately, this
necessitates use of multiplying element.
This technique can be developed in analytical way by noting that the average output
voltage of the matrix SICAM is:
vo = d+ V+ + d− V− = (d+ − d− )V+ = ∆dV+ (2.96)
where d+ is the duty cycle of the load being connected to the positive output voltage V+
and d− is the duty cycle of the load being connected to the negative output voltage V− ,
with d+ + d− = 1 and V− = V+ being result of the specific way the matrix SICAM with
LC-network is operated.
The difference of the positive and negative duty cycle is simply expressed as:
vo vo
∆d = = (2.97)
V+ kVom
where Vom = Vo,pk represents the desired minimum output voltage margin, being in general
equal to the peak output voltage Vo,pk . When the design of the matrix SICAM with LC-
network has been done in a proper way which guarantees that the voltage of the rails is
always bigger than the output voltage margin V+ ≥ Vom , then the coefficient k ≥ 1. In
60 2 Matrix SICAM
simple words equation (2.97) says that whenever there are variations in the input voltage
of the matrix SICAM, the difference of the duty cycles d+ and d− must be inversely
proportional to the coefficient k expressing the amount of that variation in respect to the
output voltage margin Vom .
The duty cycles d+ and d− are determined by the intersections of the output voltage
reference vo,ref and the triangular carrier with peak value xVcrm in the PWM modulator,
as shown in Fig. 2.33, where x is the scaling factor which relationship to the coefficient k
is to be determined.
g(t) 4t/TS
xVcrm
Vcrm
vo, ref
2
1
t 1 t0 t
TS/4
d-TS
PWM
Fig. 2.33. AM of triangular carrier
The duty cycle with negative voltage d− is:

Ts vo,ref
d− = − (2.98)
2 2xVcrm
which gives the following difference of the duty cycles:
vo,ref
∆d = d+ − d− = 1 − 2d− = (2.99)
xVcrm
By comparing (2.97) and (2.99), x can be expressed as:
Vom vo,ref
x= k (2.100)
Vcrm vo
The gain of the matrix SICAM with PWM modulator and externally created triangular
carrier is:
vo Vom
ka = = (2.101)
vo,ref Vcrm
which replaced in (2.100) leads to the following final value for the scaling factor x:
x=k (2.102)
Equation (2.102) verifies the applicability of AM of the triangular carrier to cope with
the variations of the input voltage, but also states that the peak value of the triangular
carrier xVcrm must be scaled exactly with the coefficient k in order to reject completely
the variations of the input voltage.
In Fig. 2.32a, output voltage margin is following the capacitor voltage ±vC when the
matrix SICAM is in CkR topology, or the inductor voltage ±vL = ±(vin − vC ) in LkR
topology. The output voltage margin is normalized in respect to the peak output voltage
needed Vo,pk and this limit corresponds to the peak of the triangular carrier. Output
voltage reference is restricted to −1 < vo,ref < 1, or the input modulating signal is
defined as sine wave consisting of a modulation index 0 < m < 1 at input frequency fm
in the audio band. PWM pulses are obtained on the output of the comparator unit with
the output voltage reference vo,ref and the AM triangular carrier xvcr as inputs.
Driver block with its two clocks should be also considered as an important part of
the modulation technique, since it redirects the driving pulses to the correct bidirectional
switches. The CkR,LkR clock with time base tC = tL =5 ms guides the switching between
different general topologies CkR and LkR, according to which topology offers a greater
possible output voltage. The +/− clock with time base 10 ms tells the driver circuitry
whether the voltage of the upper output rail compared to lower output rail is positive or
negative, and this clock is synchronized with the changes in the CkR,LkR clock output.
From a modulation standpoint, the multiplication of the triangular carrier with a factor
k = vC /Vo,pk or k = (vin − vC )/Vo,pk which pulsates with the input voltage frequency
ω leads to different frequency spectrum of the PWM output signal in the AM of the
triangular carrier technique. The most common method for analysis of PWM problems
is the Double Fourier Series (DFS) presented in [33]. Indeed, when the frequency of the
modulation wave ωm and the frequency of the carrier ωc are incommensurable, the only
way to complete the analysis is to use a Fourier series from two independent parameters
- DFS. However, the problem of the AM of the triangular carrier seems to be a multi-
dimensional problem, since the amplitude of the triangular carrier is multiplied with a
signal γ(t) which contains harmonics of the input frequency ωin . This signal is periodic
and can be represented by Fourier series in a following way:
∞
α0 X
γ(t) = + αm sin (nωin t) + βm cos (nωin t) (2.103)
2 n=1
where αn , βn are Fourier coefficients:

R 2π
αn = π1 0 γ(t) cos (nωin t)d(ωin t)
R 2π (2.104)
βn = π1 0 γ(t) sin (nωin t)d(ωin t)
Although it seems logical to extend DFS to Multiple Fourier Series (MFS), the following
simple analysis will show the introduction of harmonics at the input voltage frequency ωin
in the driving PWM signal by the AM of the triangular carrier technique. The analysis is
based on the common triangular carrier waveforms and AM triangular carrier waveforms
depicted in Fig. 2.33.
When common triangular carrier waveform 1 is used, switching occurs at instant t0
when the output voltage reference vout,ref = m sin ωm t and triangular carrier waveform 1
4t/Ts are equal:
4to
− m sin ωm t0 = 0 (2.105)
Ts
where Ts = 1/fs = 2π/ωs is the switching interval.
62 2 Matrix SICAM
By using DFS presented in [33], it can be concluded that in this case the PWM signal
consists of the fundamental harmonic at the modulation frequency m · ωm , switching
harmonics k · ωs and intermodulation harmonics ±n · ωm + k · ωs .
On the other hand, in the case of the AM of triangular carrier technique, condition for
switching is fulfilled at instant t1 where the output voltage reference vo,ref = m sin ωm t
equals the AM triangular carrier waveform 2 4t/Ts · γ(t):
4t1
γ(t1 ) − m sin ωm t1 = 0 (2.106)
Ts
Dividing the equation (2.106) with γ(t1 ) the following expression is obtained:
4t1 m sin ωm t1
− =0 (2.107)
Ts γ(t1 )
Comparing equation (2.107) with equation (2.105) it is concluded that a simple si-
nusoidal output voltage reference vo,ref = m sin ωm t in the case of constant trian-
gular carrier has been replaced with a complex equivalent output voltage reference
eq
vo,ref = m sin ωm t/γ(t) in the case of AM. Therefore, harmonics and interharmonics as-
sociated with the input voltage frequency ωin and its multiples should be expected in the
PWM signal too.
The aforementioned PWM driving signal from the comparator section is subsequently
used to drive the power stage with bidirectional switches, which applies the varying in-
put voltage across the load. Due to the positive effect of the input voltage feedforward
to amplitude modulate the triangular carrier, the fundamental of the input modulating
signal will be precisely amplified despite of the variations in the input voltage, but the
output voltage will also incorporate some of the harmonics and interharmonics of the
feedforwarded input voltage found in the PWM driving signal, which are very unlikely to
be completely cancelled by the varying input voltage.
∆ modulation technique
Open-loop control technique called ∆ modulation is shown in Fig. 2.32b.
Assuming that during one switching interval Ts the input voltage does not change
V+ , V− = const, then by choosing both duty cycles to be equal d+0 = d−0 = 0.5 the
average of the output voltage will equal zero. d+0 , d−0 are called zero output voltage duty
cycles. Duty cycles d+ , d− can be expressed using the zero output voltage duty cycles
d+0 , d−0 and the ∆ duty cycle in the following way:
d+ = d+0 + ∆ = 0.5 + ∆
(2.108)
d− = d−0 − ∆ = 0.5 − ∆
Using the ∆ duty cycle, the average output voltage (2.96) becomes:
vo = [(d+0 + ∆) − (d−0 − ∆)]V+ = 2∆V+ (2.109)
Equation (2.109) can be used to calculate the ∆ duty cycle:

vo ka vo,ref ka vo,ref
∆= = = · (2.110)
2V+ 2kVom 2Vom k
As shown in (2.109), instead of modifying the triangular carrier this modulation technique
modulates the reference output voltage vo,ref in synchronism with the variations in the
1
vo, ref
D
0,5 d+0
d- d+ d- t
Fig. 2.34. ∆ modulation control principle
input voltage, expressed through the coefficient k. This unfortunately necessitates use of
division element. The waveforms of the proposed ∆ modulation principle are shown in
Fig. 2.34.
The role of the clocks in Fig. 2.32b is the same as in the previous AM of the triangular
carrier.
2.4.8 Simulations of matrix SICAM with LC-network
In this section, the results from Orcad PSpice simulations of 500 W / 8 Ω matrix SICAM
with resonant LC-network designed in Section 2.4.5 will be presented. All simulations
were made with AM of the triangular carrier open-loop control technique.
First simulation was performed with purely resistive load R. Simulation was made
with output voltage reference having a form of sine wave with modulation index m=0.8
at frequency 10 kHz. Time diagrams of the output voltage vo , its Fast Fourier Transform
(FFT) up to 1 MHz and up to 30 kHz are presented in Fig. 2.35, while the input voltage
vin , capacitor voltage vC , inductor voltage vL , input current iin , capacitor current iC ,
inductor current iL and AM of triangular carrier are shown in Fig. 2.36.
Since in this case the matrix SICAM is driving purely resistive load, the envelope of
the output voltage actually represents the output voltage margin. From the top diagram
in Fig. 2.35 it can be concluded that this output voltage margin is sufficient for this power
range, and maybe a slight readjustment of the time instants when configuration LkR is
changed to CkR can even lead to its improvement. The switching harmonics present in
the output voltage of the purely resistive load do not allow seeing the 10 kHz modulating
wave, but it is apparent in the FFT of the output voltage at the bottom diagram in
Fig. 2.35. On the middle FFT diagram of the output voltage in Fig. 2.35 the switching
harmonics n · fs and intermodulation sidebands n · fs ± k · fref are clearly visible.
The same simulations with output filter instead of a resistive load R were also per-
formed, giving quite different results. Again, the simulation was made with output refer-
ence in a form of a sine wave with modulation index m=0,8 at frequency 10 kHz. Time
diagrams of the output voltage vout , its FFT up to 1 MHz and up to 30 kHz are presented
in figure 2.37, while the input voltage vin , capacitor voltage vC , inductor voltage vL , input
current iin , capacitor current iC , inductor current iL and AM of triangular carrier are
shown in figure 2.38.
From the FFT of the output voltage in Fig. 2.37 it can be seen that, like in the pure
resistive load case, there are some DC and low frequency components in the output voltage,
which are certainly not desired. These are regarded to the open loop modulation principles
and the pitfalls of the AM of triangular carrier modulation technique. However, now the
presence of a low-pass filter on the load side which has a significant input impedance
at the switching frequency leads to relative unloading of the resonant LC-network and
64 2 Matrix SICAM
thus to creation of immense capacitor voltage and inductor current shown in Fig. 2.38.
This represents a huge stress for the reactive and switching components of the matrix
SICAM, which totally disqualifies it from further practical examination. At the FFT of
the output voltage at the middle diagram in Fig. 2.35 the switching harmonics n · fs and
intermodulation sidebands n · fs ± k · fref are clearly visible too.
2.5 Conclusion about matrix SICAMs

Matrix converter capability for direct energy conversion without any reactive components
(except for EMC filtering purposes) of the fixed input set of AC voltages to the output
set of AC voltages with arbitrary amplitudes and frequencies looks highly appealing for
use in SICAM. However, it was shown in previous sections that this conversion from a
single-phase AC mains is neither straightforward, nor simple. The fundamental problem
of unavoidable zero voltage crossings of the single sinusoidal input voltage asks for some
kind of energy storage, which again promotes use of reactive components in the, otherwise,
almost totally silicon-based matrix converter. It was found that the desired implementa-
tion of a matrix SICAM is the 2ph-AC to 1ph-AC matrix converter with switched central
tap.
For implementing the proposed matrix SICAM another voltage must be provided that
leads/lags the single-phase input voltage for certain phase angle, optimally 90◦ . It is
suggested that this can be done by using a single-phase AC-mains and an LC-network
being resonant or nearly resonant at the mains frequency to derive the other phase-
shifted input voltage. In real implementations poorer performance should be expected,
since the voltage in other phase will rarely be shifted for exactly 90◦ nor will have the same
amplitude as the input one. This will cause lowering of the bound margin |maxt LBi (t)| −
|mint U Bi (t)| as defined in (2.12) and (2.18), and subsequently will decrease the allowed
range for the output voltage reference.
Some other drawbacks are:
• Increased complexity of the power supply, which now must provide another phase-
shifted voltage with certain strict requirements upon its phase lag and amplitude,
• Six bidirectional switches must be used in the proposed matrix converter topology,
which increases the product cost, emphasizes the problem of the load current commu-
tation [34] and adds significantly to the complexity of the converter and the gate drive
circuitry, when compared to the other isolated and non-isolated solutions presented in
the later chapters,
• Huge voltage and current stress on all reactive and switching components due to un-
loading of the resonant LC-network makes the matrix SICAM totally incompatible for
use with output low-pass filter, and
• Matrix converters cannot provide galvanic isolation, which is a safety concern and
requires galvanic isolation somewhere in the energy conversion chain if there is a chance
for the user to physically access and touch the amplifier board or the loudspeaker.
Although the three phase matrix converter is very well investigated and is highly
competitive to the common three phase rectifier-inverter schemes with DC-bus, the single-
phase matrix converter is hampered by the bulky phase-shifting LC-network and does not
seem to offer any distinct advantages when compared to the AC-mains connected, non-
isolated SICAMs with Class D audio power amplifiers presented in the next chapter.
However, the proposed single-phase matrix SICAM with LC-network is a very interesting
AC-AC converter topology from a scientific point of view. Much of its limitations and
2.5 Conclusion about matrix SICAMs 65
problems with the LC-network for providing another phase-shifted voltage were revealed
in the previous chapters, together with a fairly simple analysis, as well as simple design
approach and lots of design considerations. It was concluded that bulky high voltage rating
capacitor C and bulky high current rating inductor L are needed to achieve a resonant LC
circuit with satisfactory long DC transient components which will guarantee large enough
output voltage margin. Open loop control issues were also addressed, by proposing simple
PWM methods appropriate for analog implementation with externally created triangular
carrier. Some simulation results have been shown to give a better insight into operation
of the matrix SICAM with phase-shifting LC-network.
66 2 Matrix SICAM
Fig. 2.35. Matrix SICAM with LC-network and purely resistive load (m=0,8, f=10 kHz) - Top: Output voltage
vout , Middle: FFT up to 1 MHz, Bottom: FFT up to 30 kHz
Fig. 2.36. Matrix SICAM with LC-network and purely resistive load (m=0,8, f=10 kHz) - Top: Input voltage
vin , capacitor voltage vC and inductor voltage vL , Middle: Input current iin , capacitor current iC and inductor
current iL , Bottom: AM of triangular carrier
68 2 Matrix SICAM
Fig. 2.37. MC-based SICAM using an LC-network (m=0,8, f=10 kHz) - Top: Output voltage vout , Middle: FFT
up to 1 MHz, Bottom: FFT up to 30 kHz
Fig. 2.38. MC-based SICAM using an LC-network (m=0,8, f=10 kHz) - Top: Input voltage vin , capacitor voltage
vC and inductor voltage vL , Middle: Input current iin , capacitor current iC and inductor current iL , Bottom: AM
of triangular carrier
3
AC-mains connected Class D audio power amplifiers
as SICAMs
”If the only tool you have is a hammer, you will see
every problem as a nail.”
- Abraham Maslow
This chapter deals with non-isolated, directly AC-mains connected Class D audio power
amplifiers. The main advantage of this approach, when compared to the previously pre-
sented matrix SICAMs, is that the necessary energy storage to cope with the regular zero
crossings of the input AC-mains voltage can be very effectively provided with a DC-bus
and unipolar electrolytic capacitors across it, combining very large charge capacity with a
small case size. Since the energy conversion from the input AC-mains to the loudspeaker
is performed as straightforward as possible, all these approaches can be referred to as
non-isolated SICAMs.
3.1 Non-isolated DC power supply

Schematic of the non-isolated DC power supply with some of the voltage and current
waveforms, as well as a block diagram of the rectifier are given in Fig. 3.1.
VAC VDC
D1 D3 + DBR
~ ~
AC mains Cin AC
Cin
IAC IDC mains -
D2 D4
Fig. 3.1. Non-isolated DC power supply
Taking a closer look at the voltage and current waveforms in Fig. 3.1 it becomes
apparent that the power flow from the AC-mains has a pulsative nature, in accordance
to the charging of the energy storage capacitor around the peak of the mains voltage. On
the other hand, power flow at the output is assumed nearly constant, which means that
the mains rectifier is averaging the power drawn from the utility grid by the help of the
storage capacitor following the rectifiers.
The development of design equations for the mains rectifier and input energy storage
capacitor will follow the lines given in [35].
Mains rectifier and storage capacitor are supplying both the output power Po and all
the losses in the downstream electronics Ploss , giving a total input power Pin equal to:
Po
Pin = Po + Ploss = (3.1)
η
where η is the efficiency of the electrical energy conversion in SICAM.
72 3 AC-mains connected Class D audio power amplifiers as SICAMs
The energy supplied from the AC mains during a full wave of the AC input voltage
with duration Tac = 1/fac is:
Pin
Win = Pin Tac = (3.2)
fac
Energy from the mains Win is delivered to the input energy storage capacitor Cin only
during the time when the rectified AC mains voltage is higher that the energy storage
capacitor voltage VCin . In the case of a full bridge rectifier, a half of the whole input energy
Win /2 is delivered each half-cycle of the AC mains voltage and in steady-state this leads
to the following balance of energies:
Win 1 2 2
= Cin (VCin,pk − VCin,min ) (3.3)
2 2
where VCin,pk and VCin,min are the peak and minimum voltage of the input energy storage
capacitor Cin , depicted in Fig. 3.2.
vCin
VCin, pk
VCin, min
t
tc Tac
iCin
ichg
Fig. 3.2. Voltage and current of the input storage capacitor
Minimum value of the input energy storage capacitor Cin,min to get the minimum
voltage of VCin,min is thus given with the following equation:
Win
Cin,min = 2 2
(3.4)
VCin,pk − VCin,min
The minimum voltage of the input energy storage capacitor is very important quantity
for the SICAM design, since all downstream switching electronics must be flexible enough
to cope with the large variation of the input voltage, which usually comes down to having
enough available duty cycle variation range to provide the desired output voltage. This
problem is even more pronounced in isolated SICAMs, where the minimum input voltage
determines the necessary transformer turns ratio n to achieve the desired peak output
voltage with maximum duty cycle. When the AC mains voltage is at its maximum, the
fixed turns ratio of the transformer will cause unnecessary high voltage stress on the
output stage switches, if it is allowed for the minimum input voltage to be significantly
lower than the peak input voltage.
The recharging time tc is found by noting that:
VCin,min
arccos( VCin,pk
)
VCin,min = VCin,pk cos(2πfac tc ) ⇒ tc = (3.5)
2πfac
By assuming constant charging current ichg during the recharging period tc , its mag-
nitude is found to be:
3.2 Class D audio power amplifier with non-isolated DC power supply 73
∆Q Cin (VCin,pk − VCin,min )

ichg = = (3.6)
tc tc
The RMS charging current flowing through the input energy storage capacitor is found
by subtracting the DC component of the charging current from the total charging current:
s 2
q
2 2 2 2 2 2
Ichg,rms = Ichg − Idc = ichg tc − ichg tc (3.7)
Tac Tac
The total RMS input capacitor current is calculated by adding the discharging com-
ponent of the capacitor current to the charging component from (3.7):
q
2 2
ICin,rms = Ichg,rms + Idis,rms (3.8)
Equations presented in this section are equally applicable to non-isolated and isolated
SICAMs.
3.2 Class D audio power amplifier with non-isolated DC power

supply
The simplest possibility for creating a non-isolated SICAM is to connect a Class D au-
dio power amplifier to the non-isolated and unregulated DC power supply presented in
Section 3.1. The resulting audio amplification topology with a full-bridge Class D audio
power amplifier is depicted in Fig. 3.3.
+
T1 T3
~ ~ Lf Lf
AC
Cin
mains -
T2 Cf T4
Fig. 3.3. Class D audio power amplifier with non-isolated DC power supply
The main features of the Class D audio power amplifier with non-isolated DC power
supply are the compact structure of the resulting amplifier unit and the very efficient
energy storage in the input capacitor Cin , being a result of the higher voltage on the
DC-bus. This eventually increases the hold-up time in case of temporary input voltage
dropout and leads also to much smaller form factors.
However, using higher input voltages to the Class D audio power amplifier includes
some necessary compromises, like for example the need for high blocking voltage active
devices (MOSFETs in Fig. 3.3), able to withstand the maximum rectified AC-mains volt-
age. The maximum blocking voltage VBR,DSS of the active device determines the minimum
width of the lightly doped epitaxial layer (in the case of an N-type MOSFET it is usually
referred to as N− ), increasing the on-resistance Rds,on of the device and the corresponding
voltage drop during conduction. The exact relation of the on-resistance RDS,on to the
maximum blocking voltage VBR,DSS depends primarily on the internal structure of the
active device. For example, for the most of the conventional Power MOSFET structures
with predominantly planar gate structure and die surface area Adie , the relation for RDS,on
is:
(VBR,DSS )2.5
RDS,on ∼ (3.9)
Adie
while the same relation for 3-dimensional complimentary p/n column structure with
trenches, like in the CoolMOS technology, shows significant improvement and is mov-
ing toward:
(VBR,DSS )2
RDS,on ∼ (3.10)
Adie
This clearly shows the reduction of conduction losses, which can be achieved by moving
to lower blocking voltage devices by decreasing the input voltage to the Class D audio
power amplifier.
As a conclusion, the switching devices with higher blocking voltage in the directly
mains-connected Class D audio power amplifier exhibit higher conduction losses due to
the higher on-resistance RDS,on , when compared to the low voltage devices used in the
conventional Class D audio power amplifiers, which are selected only on the basis of the
desired output power and the load impedance. As an example, a common load impedance
of 8 Ω asks for peak voltage of Vo,pk = 40 V to produce output power of Po = 100 W, while
the voltage of the DC-bus on a European AC-mains 230 V/50 Hz is Vdc = 325 V nominal.
In other words, the desired output voltage is produced with a very narrow variation of the
duty cycle of the corresponding switching legs, which is maybe only an order of magnitude
bigger than the dead (blanking) time inserted between the switching of the active devices
in a single switching leg and therefore leads to excessive THD. The distortion of the
Class D audio power amplifier with neglected effect of the output filter ripple current is
given by the following equation [14]:
v
uNmax
uX
t b2i
i=2
T HD = (3.11)
4tbl Vps
M Vps −
πTs
where M is the modulation index, Vps is the power supply voltage, tbl is the blanking (dead)
time, Ts = 1/fs is the switching period, Nmax is the number of distortion harmonics taken
into account and the Fourier coefficients an , bn of the resulting distortion waveform are
given by:
a0 = 0
an = 0
(3.12)
tbl sin(n π2 ) tbl (−1) n
bn = −2 Vps =2 Vps
Ts n π2 Ts (2n − 1) π2
The above THD equations assume ideal power stage, where the audio distortion is created
only during the short blanking time intervals. However, in a real power stage additional
audio distortion is created as a result of the nonlinear characteristics of the antiparallel
freewheeling diodes, when the load current diverts from the MOSFET channel with on-
resistance RDS,on to its body diode because of the higher voltage drop in the channel.
3.3 Class D audio power amplifier with step-down PFC front-end 75
This effect is likely to be even more pronounced in directly mains-connected Class D

audio power amplifiers, where MOSFETs are required to have blocking voltage somewhat
higher than the rectified mains voltage and thus higher on-resistance.
It can be seen from equations (3.11) and (3.12) that THD of the Class D audio power
amplifier increases with the increasing power supply voltage Vps which proves the fact that
the directly mains-interfaced Class D audio power amplifier will be worse performer. This
setback is even more pronounced because of the need to increase the blanking time tbl ,
because at such a high input voltages any shoot-through can lead to large and dangerous
short-circuit currents and it certainly takes more time for the drain-source voltage VDS to
completely slew to the final value.
Since the Class D audio amplification technology has been thoroughly explained else-
where [14], the discussion about non-isolated SICAMs in this chapter will focus on other
aspects, like alleviating the problems with the high voltage on the DC-bus in the straight-
forward implementation or integrating an extra PFC capability in the conventional Class
D audio power amplifier.
3.3 Class D audio power amplifier with step-down PFC

front-end
One of the ways to alleviate the aforementioned problems with the directly mains-
connected Class D audio power amplifiers is to decrease the input voltage to the Class D
audio power amplifier by introducing a step-down PFC front-end, as shown in Fig. 3.4.
+
T1 T3
~ ~ Step-down Lf Lf
AC PFC
Cin
mains - front-end
T2 Cf T4
Fig. 3.4. Class D audio power amplifier with step-down PFC front-end
The most common way of providing PFC capability to the switching-mode power
supplies is by implementing a boost stage front-end, which beside of acting as power factor
corrector with stepped-up output voltage has an inductor on the input side, featuring
continuous or discontinuous current and alleviating the Electro-Magnetic Compatibility
(EMC) requirements. As noted before, high output voltage of the PFC can have adverse
effects on the Class D audio power amplifier performance and therefore the boost PFC
front-end is not an interesting approach to follow.
One possible choice of a PFC front-end is the SEPIC [1] shown in Fig. 3.5, which
is capable of producing lower output voltages than the peak mains voltage. It has the
advantages of being a single switch topology with an inductor on the input side, alleviating
the EMC problems. Additionally, by coupling the two inductors in the topology and
introducing some intentional leakage inductance in series with the input inductor, the
inductor ripple current can be completely diverted from the input side to the internal
coupled inductor and therefore reduce the need for input EMC filtering.
Unfortunately, the SEPIC PFC preregulator is characterized with much higher voltage
and current stress on the main switch when compared to the common boost PFC prereg-
ulator, which becomes even more pronounced with much lower output voltages than the
input voltage. This becomes clear from the buck-boost static transfer characteristics of
the output voltage and the input current in the SEPIC case:
D
Vo = Vin
1−D (3.13)
D
Iin = Io
1−D
where Vin , Iin and Vo , Io are the input and output voltage and current of the SEPIC PFC
front-end, correspondingly.
Fig. 3.5. SEPIC PFC preregulator [1]
Another possible choice is selection of boost-buck derived PFC topologies like the
Sheppard-Taylor topology [36] and alike or more complex PFC schemes, like for example
the non-isolated and isolated EWIRAC [37]. No matter what is the actual step-down
PFC topology, a very interesting optimization problem can be set to find the optimal DC-
bus voltage at the output of the PFC which leads to minimal overall losses of the PFC
and Class D audio power amplifier, with as low as possible cost and acceptable audio
perfromance.
3.4 Combined Class D audio power amplifier and PFC

The group of combined Class D audio power amplifiers and PFCs comprises of topologies
where the whole or part of the Class D audio power amplifier plays some role in the
shaping of the input current i.e. it is part of the PFC circuit. Unfortunately, the functions
and the operation of an audio power amplifier and a PFC are not very similar, so that
two degrees of control freedom in the Class D audio power amplifier are by all means
necessary. These two degrees of control freedom are found only in the full-bridge amplifier
topologies, like the one shown in Fig. 3.6.
The duty cycles of the two totem poles i.e. switching legs 1 and 2 can be represented
as sums of an idling duty cycle 0 ≤ D0 ≤ 1 and variable duty cycles 0 ≤ ∆d1 , ∆d2 ≤ 0.5:
d1 = D0 + ∆d1
(3.14)
d2 = D0 + ∆d2
It is worth noting that during the duty cycle duration d1 · Ts and d2 · Ts both lower
switches (T2 , T4 ) in the switching legs are on and the upper switches (T1 , T3 ) are off. Both
the idling duty cycle D0 and the variable duty cycles ∆d1 , ∆d2 can be independently set,
but their corresponding sums must always represent a realizable duty cycle 0 ≤ d1 , d2 ≤ 1.
3.4 Combined Class D audio power amplifier and PFC 77
1 2
+ vo
+
T1 T3
vo1 vo2
Cin Lf Lf
Vps
Cin T2 Cf Cf T4
Fig. 3.6. Full-bridge Class D audio power amplifier
In conventional Class D audio power amplifier with appropriate input voltage, the value
of the idling duty cycle is selected in the middle D0 = 0.5.
The output voltages at both ends of the loudspeaker vo1 and vo2 referenced to ground
are given by the following equations:
1 − 2d1
vo1 = Vps
2 (3.15)
1 − 2d2
vo2 = Vps
2
The two degrees of freedom can be expressed as separate control of the differential mode
voltage vd being the load voltage and the common mode voltage vc being the average load
voltage to ground:
vd = vo1 − vo2 = (d2 − d1 )Vps = (∆d2 − ∆d1 )Vps

vo1 + vo2 (3.16)
vc = = [1 − (d1 + d2 )]Vps = [1 − (2D0 + ∆d1 + ∆d2 )]Vps
2
It can be concluded that by selecting the two variable duty cycles to have the same
magnitudes, but opposite signs ∆d = −∆d1 = ∆d2 , the differential mode and the common
mode load voltages become decoupled one from another and can be separately controlled
with the variable duty cycle ∆d and the idling duty cycle D0 correspondingly:
vd = vo1 − vo2 = 2∆dVps

vo1 + vo2 (3.17)
vc = = (1 − 2D0 )Vps
2
The calculation of the variable duty cycle ∆d starts by recognizing that the differential
mode voltage across the loudspeaker is in fact the desired load voltage vo = vd and
therefore:
vo
∆d = (3.18)
2Vps
and the idling duty cycle D0 is free to select as long as the resulting duty cycles of the
switching legs d1 , d2 are realizable i.e. 0 ≤ d1 , d2 ≤ 1 even at maximum output voltage.
As a result of this limitation, all changes in the duty cycle difference are limited to
0 ≤ ∆d ≤ 0.5, which corresponds well with the expression (3.18) and the fact that at
maximum duty cycle the output voltage of the full-bridge amplifier is vo = ±Vps . This
is graphically represented in Fig. 3.7, where the power supply voltage is Vps = 100 V
and the maximum output voltage is Vo,max = 40 V. With the given voltage levels, the
maximum difference duty cycle ∆dmax = 0.2 and the idling duty cycle can vary in the
range D0 = [0.2, 0.8].
100 1
Vps
2∆d
80 0.8
vo, Vps [V] vo
60 0.6
D0 var.
D0
range
40 0.4
vo
20 0.2
0 0
0 0.5 1 1.5 2
time [s] x 10
−3
Fig. 3.7. Variations in the output voltage and duty cycles
These conclusions will be used in the following few sections to simplify the construction
of combined Class D audio power amplifier and PFC stage, by reusing one or two of the
switching legs.
3.4.1 Combined Class D audio power amplifier and boost PFC
Combined Class D audio power amplifier with a boost PFC front-end is depicted in
Fig. 3.8. As it is shown, one switching leg of the Class D audio power amplifier is used as
a boost active switch with synchronous rectifier. The two degrees of freedom when selecting
the differential mode and common mode load voltage mean that the load voltage vo can be
set independently of the operation of the boost converter, which shapes the input current
iin while trying to keep constant voltage on the DC-link energy storage capacitor Cin ,
vCin .
T1 T3
Lb Lf Lf
+ Cin
~ ~
AC T2 Cf Cf T4
mains -
Fig. 3.8. Combined Class D audio power amplifier and boost PFC
The main disadvantage of the combined Class D audio power amplifier with boost
PFC is the high voltage across the energy storage capacitor Cin which is always higher
than the peak input voltage vCin > vin,pk . As discussed in the previous section, high input
voltage to the Class D audio power amplifier necessitates using higher blocking voltage
active devices and leads to increased conduction losses and lower audio performance with
increased THD. However, the topology looks very interesting from a theoretical point of
view, since it looks very compact and strongly reminds of the single-stage PFCs [38], [39].
The analysis of operation of the combined Class D audio power amplifier with boost
PFC front-end in Continuous Conduction Mode (CCM) through state-space averaging is
presented in Appendix B.1. The four different connections in the operation of the combined
Class D audio power amplifier and boost PFC are shown in Fig. 3.9. Stepping through the
different possible connections is performed according to the sign of the output voltage,
and is shown in Fig. 3.9 with the plus and minus sign.
iCin iCin
d0-Dd 1-d0-Dd
Lb 2Lf io R Lb 2Lf io R
+ iLb iLf Cin + iLb iLf Cin

vin iCf vin iCf
Cf/2 Cf/2
_
+
iCin iCin
2Dd |-2Dd|

vin iCf vin iCf
Cf/2 Cf/2
Fig. 3.9. Possible connections in the combined Class D audio power amplifier and boost PFC
The differences in the models for positive and negative output voltages stem from the
fact that the boost PFC is asymmetrical in regard with the full-bridge Class D audio
power amplifier and this translates to slight changes in the models. Although this does
not seem to cause any problems, symmetrical operation can be achieved by using two
boost inductors in arrangement shown in Fig. 3.10.
T1 T3
Lb Lf Lf Lb
Cin
T2 Cf T4
+
~ ~
AC
mains
Fig. 3.10. Combined Class D audio power amplifier and boost PFC with two boost inductors
The DC-model of the combined Class D audio power amplifier and boost PFC devel-
oped in Appendix B.1 for positive output voltages is:
Vin
VCin =
1 − D0 + ∆D
Vo = 2∆DVCin
2∆DILf (3.19)
ILb =
1 − D0 + ∆D
Vo
ILf = = Io
R
and for negative output voltages is:
Vin
VCin =
1 − D0 − ∆D
Vo = −2∆DVCin
2∆DILf (3.20)
ILb = −
1 − D0 − ∆D
Vo
ILf = = Io
R
The maximum variation of the steady-state value of the duty cycle ∆D used to provide
the desired output voltage can be found from the second equation in (3.19):
Vo,max
∆Dmax = (3.21)
2VCin
As a result of the limitation on the maximum duty cycle ∆Dmax there is a limitation
on the maximum and minimum steady-state value of the idling duty cycle D0 :
D0,min = ∆Dmax
(3.22)
D0,max = 1 − ∆Dmax
since all realizable duty cycles are between 0 and 1. This essentially means that the idling
duty cycle D0 is free to vary in a range [D0,min , D0,max ], thus leaving enough space for the
duty cycle difference ∆D to reconstruct even the highest peaks of the output voltage.
The idling duty cycle D0 is used to shape the input current iin , while trying to maintain
as constant capacitor voltage vCin as possible, and it can be determined for positive output
voltages from the first equation in (3.19):
(1 + ∆D)VCin − Vin |Vin,pk sin(ωt)|

D0 = = (1 + ∆D) − (3.23)
VCin VCin
which gives the maximum and minimum idling duty cycles D0 for sin(ωt) = 0 and
sin(ωt) = 1, respectively:
Vin,pk Vin,pk
D0,min = 1 + ∆Dmin − =1−
VCin VCin (3.24)
limit
D0,max = 1 + ∆Dmax −−−→ 1
Comparing the results in (3.24) with (3.22) it becomes apparent that the required max-
imum idling duty cycle of D0,max = 1 cannot be reached due to the need for reproducing
audio at the same time. Using the minimum idling duty cycle in (3.24), as well as the
expressions in (3.21) and (3.22), the following relation for the minimum capacitor voltage
VCin,min can be developed:
Vin,pk Vo,max
D0,min = 1 − = ∆Dmax =
VCin 2VCin (3.25)
Vo,max
⇒ VCin,min = Vin,pk +
2
Similar analysis can be performed with the DC-model for negative output voltages,
which will give the following relationship between the idling duty cycle D0 and the input
voltage:
|Vin,pk sin(ωt)|
D0 = (1 − ∆D) − (3.26)
VCin
and the following minimum capacitor voltage VCin,min :
Vin,pk Vo,max
D0,min = 1 − ∆Dmax − = ∆Dmax =
VCin 2VCin (3.27)
⇒ VCin,min = Vin,pk + Vo,max
The final value for the capacitor voltage is the maximum of the minimums in (3.25) and
(3.27), i.e. VCin,min = Vin,pk + Vo,max .
A block diagram of the control circuit for the combined Class D audio power amplifier
and boost PFC front-end is depicted in Fig. 3.11. Unfortunately, full PFC operation
cannot be achieved due to the aforementioned limitation on the realizable duty cycles
0 ≤ d1 , d2 ≤ 1, by which the minimum and maximum idling duty cycles are d0,min = ∆dmax
and d0,max = 1 − ∆dmax . These problems are alleviated with lower output power Class D
audio power amplifiers or lower impedance loudspeakers, which results in lower peak
output voltage levels Vo,pk and subsequently lower duty cycle variations ∆dmax .
T1 +- T3
Lb Lf Lf
+ Cin
~ ~
AC T2 Cf Cf T4
iLb
mains -
}
vin d
vo
PFC Audio Audio
Controller + Controller in
vCin d0 Dd
Fig. 3.11. Control diagram of a combined Class D audio power amplifier and boost PFC
Simulation of combined Class D audio power amplifier and boost PFC
Operation of the combined Class D audio power amplifier and boost PFC from Fig. 3.8
was tested by simulation. The resulting waveforms are given in Fig. 3.12.
Inductor current [A], scaled mains voltage [V]

[V]
400 5
Cin
ind. current ref.
Output and capacitor voltage v , v out. voltage ref.
4 ind. current
o out. voltage mains voltage /100
300
cap. voltage
3
200
2
100
1
0 0
−1
0 0.01 0.02 0.03 0.04 0 0.01 0.02 0.03 0.04
time t[s] time t[s]
0.1 1
Difference duty cycle ±∆d
0.8
Idling duty cycle D0

0.05
0.6
0
0.4
−0.05
0.2
−0.1 0
0 0.01 0.02 0.03 0.04 0 0.01 0.02 0.03 0.04
time t[s] time t[s]
Fig. 3.12. Simulated waveforms of combined Class D audio power amplifier and boost PFC
The converter was operated in open loop, where the difference duty cycle ∆d was
calculated from (3.19) and (3.20) to be:
vo
∆d = ± (3.28)
2VCin
and the idling duty cycle D0 is:
(1 ± ∆d)ILb,ref ∓ 2∆d vRo
D0 = (3.29)
ILb,ref
where the reference boost inductor current ILb,ref was derived from the rectified AC mains
voltage.
The output voltage waveform in Fig. 3.12 follows the output voltage reference in a
satisfactory way, except that the output voltage ripple is excessive. If full audio bandwidth
operation and maximally linear response are required, then the output LC filter must
start attenuating at higher frequencies and is not so effective at the switching frequency.
One possible way of alleviating this is using a higher order output filter or significantly
increasing the switching frequency. The voltage ripple in the energy storage capacitor Cin
is at double frequency of the AC-mains voltage and is result of the difference between
the pulsating power delivered from the AC-mains and power consumed by the load. The
variations in the difference duty cycle ∆d follow the output voltage reference, as required.
Boost inductor current is distorted, but in principle its shape resembles the shape of
the rectified AC-mains voltage. The insufficient slope of the inductor current near the zero
of the mains voltage is a problem pertinent to every boost-type PFC, and has nothing to
do with the particular topology and the limitations imposed on the idling duty cycle D0 .
The variations in the idling duty cycle D0 are shown in the last diagram in Fig. 3.12 and
both its minimum and maximum value are clearly visible.
3.4.2 Combined Class D audio power amplifier and buck-boost PFC
The main advantage of buck-boost PFC is in the lower DC-bus voltage, which alleviates
the problems with the high input voltage Class D audio power amplifiers. Buck-boost
operation is achieved through active rectification of the net voltage by adding controlled
switches in the mains rectifier and sometimes a freewheeling diode, as shown in Fig. 3.13.
The latter switches have bidirectional voltage capability, which means that they can block
both voltage polarities, but have just unipolar current capability. One possible implemen-
tation of the switch is given in Fig. 3.13d.
S1 S3 T1 T3
AC Lb Lf Lf
mains Cin
S2 S4 Dfw T2 Cf Cf T4
a)
D1 D3 T1 T3
AC Lb Lf Lf
mains Cin
S2 S4 Dfw T2 Cf Cf T4
b)
d)
S1 D3 T1 T3
AC Lb Lf Lf
mains Cin
S2 D4 T2 Cf Cf T4
c)
Fig. 3.13. Combined Class D audio power amplifier and buck-boost PFC: a) with 4 switches and a freewheeling
diode, b) with 2 switches and a freewheeling diode, c) with 2 switches, and d) one possible realization of the
switch
Switches in the active rectifier can be operated either in synchronism with the switches
in the Class D audio power amplifier, or they can be operated independently i.e. asyn-
chronously with the same or with different switching frequency and phase. One distinct
advantage of the independent operation of the proposed buck-boost PFC, when compared
to the previously presented boost PFC and synchronously-operated buck-boost PFC, is
that the active rectifier has much greater control of the input current.
The disadvantages of this non-isolated SICAM approach lie in the active rectifier, which
necessitates few active switching devices with complex gate drives, as well as the need
for ultra-fast diodes with low reverse recovery charge, instead of using regular and cheap
mains rectifiers. At the same time, switching the active rectifier leads to interrupted input
current, which necessitates use of large EMC filters on the input side. On the other hand,
it is clear that synchronous operation of the active rectifier and Class D audio power
amplifier, although somewhat simpler than the independent control, does not allow for
very large variation of the idling duty cycle D0 since the supply voltage across Cin is
supposed to be only slightly higher than the maximum output voltage.
The analysis of the synchronous operation of combined Class D audio power amplifier
and buck-boost PFC front-end in CCM through state-space averaging is presented in
Appendix B.2. The four different connections in the operation of the combined Class D
audio power amplifier and buck-boost PFC are shown in Fig. 3.14. Stepping through the
and is shown in Fig. 3.14 with the plus and minus sign.
iCin iCin
d0-Dd 1-d0-Dd

vin iCf vin iCf
Cf/2 Cf/2
_
+
iCin iCin
2Dd |-2Dd|

vin iCf vin iCf
Cf/2 Cf/2
Fig. 3.14. Possible connections in the synchronously-operated combined Class D audio power amplifier and
buck-boost PFC
The DC-model of the combined Class D audio power amplifier and buck-boost PFC in
synchronous operation mode, developed in Appendix B.2 for positive output voltages is:
(D0 − ∆D)Vin
VCin =
1 − D0 + ∆D
Vo = 2∆DVCin
2∆DILf (3.30)
ILb =
1 − D0 + ∆D
Vo
ILf = = Io
R
and for negative output voltages is:
(D0 − ∆D)Vin
VCin =
1 − D0 − ∆D
Vo = −2∆DVin
2∆DILf (3.31)
ILb = −
1 − D0 − ∆D
Vo
ILf = = Io
R
The same limitations on the duty cycle difference ∆D and idling duty cycle D0 given
in (3.21) and (3.22) are also valid here.
In contrast to the case of the boost PFC, in synchronously-operated buck-boost PFC
the idling duty cycle D0 controls both the bucking and boosting action of the PFC. The
variations in the idling duty cycle D0 are such as to shape the input current iin according
to the input voltage, while maintaining as constant capacitor voltage vCin as possible, and
it can be determined for positive output voltages from the first equation in (3.30):
VCin VCin
D0 = + ∆D = + ∆D (3.32)
Vin + VCin |Vin,pk sin(ωt)| + VCin
which gives the maximum and minimum idling duty cycles D0 for sin(ωt) = 0 and
sin(ωt) = 1, respectively:
VCin
D0,min =
Vin,pk + VCin (3.33)
D0,max = 1 + ∆Dmax limit
−−−→ 1
Comparing the results in (3.33) with (3.22) it is again clear that the required maximum
idling duty cycle of D0,max = 1 cannot be reached due to the need for reproducing audio
at the same time.
The buck-boost PFC is capable of creating both lower and higher input capacitor
voltages vCin than the mains peak voltage Vin,pk , but the lowest input capacitor volt-
age VCin will be essentially limited by the maximum output voltage Vo,max , so that al-
ways VCin > Vo,max . When the input capacitor voltage is chosen such that it is only
slightly higher than the maximum output voltage, the maximum duty cycle difference
is ∆Dmax ≈ 0.5 and the idling duty cycle is nearly constant D0 ≈ 0.5. This, however,
prohibits the synchronously operated buck-boost PFC and Class D amplifier from accom-
modating larger variations in the input voltage. The only way of solving this problem is
by increasing the input capacitor voltage vCin to allow for bigger changes in the idling
duty cycle D0 , which by itself is very similar to the boost PFC approach and therefore is
not so interesting.
Similar analysis can be performed with the DC-model for negative output voltages in
(3.31), which will give the following relationship between the idling duty cycle D0 and the
input voltage:
VCin
D0 = (1 − 2∆D) + ∆D (3.34)
|Vin,pk sin(ωt)| + VCin
The analysis of the asynchronous operation of combined Class D audio power amplifier
and buck-boost PFC front-end in CCM is made using the connection diagrams in Fig. 3.15
and is given in detail in Appendix B.3.
The DC-model of the combined Class D audio power amplifier and buck-boost PFC
in asynchronous operation mode, developed in Appendix B.3 for positive output voltages
i.e. switching sequences I − III is:
Da Vin
VCin =
1 − D0 + ∆D
Vo = 2∆DVCin
2∆DILf (3.35)
ILb =
1 − D0 + ∆D
Vo
ILf = = Io
R
iCin iCin
1 5

vin iCf vin iCf
Cf/2 Cf/2
iCin iCin
2 6

vin iCf vin iCf
Cf/2 Cf/2
iCin iCin
3 7

vin iCf vin iCf
Cf/2 Cf/2
iCin iCin
4 8

vin iCf vin iCf
Cf/2 Cf/2
Fig. 3.15. Possible connections in the asynchronously-operated combined Class D audio power amplifier and
buck-boost PFC
and for negative output voltages varies among:

Da Vin
VCin =
1 − D0 − ∆D
Vo = −2∆DVCin
2∆DILf (3.36)
ILb = −
1 − D0 − ∆D
Vo
ILf = = Io
R
for da < (d0 − ∆d),
Da Vin
VCin =
1 − Da − 2D0
Vo = −2∆DVCin
2∆DILf (3.37)
ILb = −
1 − D0 − ∆D
Vo
ILf = = Io
R
for (d0 − ∆d) < da < (d0 + ∆d), and
3.5 Conclusion 87
Da Vin
VCin =
1 − D0 + ∆D
Vo = −2∆DVCin
2∆DILf (3.38)
ILb = −
1 − D0 − ∆D
Vo
ILf = = Io
R
for (d0 + ∆d) < da < 1.
The same limitations on the duty cycle difference ∆D and idling duty cycle D0 given
in (3.21) and (3.22) are also valid here.
As seen in (3.35), the asynchronously operated buck-boost PFC can control the input
current and the output voltage in buck mode by varying the duty cycle Da of the switches
in the active rectifier, while in boost mode the same can be done by the idling duty cycle
D0 . In buck mode of PFC operation the voltage across the input capacitor is lower than
the input voltage VCin < vin and the expression for the duty cycle Da with positive output
voltage in all switching sequences and negative output voltage in switching sequence V I
is obtained from the first equation in (3.35):
VCin
Da = (1 − D0 + ∆D) (3.39)
Vin
and in boost mode VCin > vin for the idling duty cycle D0 :
Vin
D0 = (1 + ∆D) − Da (3.40)
VCin
However, instead of using Da and D0 exclusively in buck or boost mode respectively, their
variations can be combined across operating modes in a way that assures that both duty
cycles are realizable and satisfy 0 ≤ Da ≤ 1 and ∆Dmax ≤ D0 ≤ 1 − ∆Dmax , while
improving the performance. For example, when the idling duty cycle D0 has reached its
maximum value in (3.40) with low input voltage, the duty cycle of the active rectifier
Da can be increased in order to maintain the desired input capacitor voltage VCin . In
other words, combined variations of Da and D0 lead to extended operation range of the
asynchronously-operated combined buck-boost PFC and Class D audio power amplifier,
but it essentially experiences the same limitation in the boost mode like the aforemen-
tioned boost PFC and synchronously-operated buck-boost PFC, since the maximum idling
duty cycle is limited to D0,max = 1 − ∆max .
Similar analysis can be performed with the DC-model for negative output voltages in
switching sequences IV and V , with the only difference that in the switching sequence
V the duty cycle of the active rectifier governs not only the operation in buck mode, but
also assists boosting of the output voltage.
The block diagram of the control circuit for the combined Class D audio power amplifier
and buck-boost PFC front-end is very similar to the one for the combined Class D audio
power amplifier and boost PFC, shown in Fig. 3.11.
3.5 Conclusion
The greatest challenges of the non-isolated directly mains-connected SICAMs are the rela-
tively high rectified mains voltage and the wish for providing very compact and essentially
single-stage designs with some extra features, like PFC.
It was shown in this chapter that there are ways of alleviating some of the aforemen-
tioned problems, by providing separate step-down PFC front ends which make possible
using of lower input voltage Class D audio power amplifiers. This, however, results in es-
sentially a two stage approach with all the drawbacks in terms of efficiency and complexity
which come with it.
It was also shown that by giving up on the wish to use lower input voltage Class D
audio power amplifier, combined Class D audio power amplifier and boost PFC front-
end can be built in a simple manner by just adding an additional boost inductor(s).
Eventually, by introducing active rectifier at the mains input, both PFC capability and
lower input voltage Class D audio power amplifier can be integrated in a single unit
to bring a single-stage amplification topology with built-in buck-boost PFC front-end.
Certain limitations are common to all these combined approaches and stem from reusing
the full-bridge Class D audio power amplifier and the extra degree of freedom i.e. the
varying load common-mode voltage, which can be independently set as long as it does
not interfere with the reproduction of audio signals in the differential-mode voltage.
4
SICAM for portable devices
” ... In the intuitive mind the principles are found in
common use, and are before the eyes of everybody. One
has only to look, and no effort is necessary; it is only
a question of good eyesight, but it must be good, for
the principles are so subtle and so numerous, that it is
almost impossible but that some escape notice. Now the
omission of one principle leads to error; thus one must
have very clear sight to see all the principles, and in the
next place an accurate mind not to draw false deductions
from known principles.”
- From ”Thoughts”, Blaise Pascal
According to the project description given in Section 1, SICAM is highly compact audio
power amplification solution with or without isolation and is intended for operation on AC
mains voltage. However, this does not mean that there are no problems with efficient and
compact audio power amplification in portable devices i.e. battery powered devices. The
main challenges in this area are low and strongly variable battery voltage Vbat depending on
the state of charge, which significantly affects the highest achievable audio output power
level with the common buck-type topologies, like the Class D audio power amplifiers.
Today, most of the switching solutions for portable devices consists of some type of full
bridge topology in order to maximize the load voltage swing, in this case being equal to
the battery voltage ±Vbat .
For powering loudspeakers with higher impedance or for achieving higher audio output
power levels with battery powered devices, the easiest solution seems to be using a battery
voltage booster, followed by a linear or Class D audio power amplifier. This essentially
represents a two stage approach, which is likely to have lower efficiency when compared
with some single stage topology.
This chapter deals with the development of topology and digital control principle for
a single-stage audio power amplifier for portable devices, capable of boosting the output
voltage with respect to the input battery voltage. Since all voltage step-up topologies
(boost, buck-boost, etc.) experience very nonlinear output characteristics which are only
somewhat linearized with the application of analog feedback, the main goal of the pre-
sented work is to develop a digital modulator structure that is capable of linearizing the
transfer characteristics of the proposed nonlinear amplifier in open-loop operation.
4.1 Single-stage step-up audio power amplifier topology for

portable applications
As mentioned in the introductory part, low and variable battery voltage limits the highest
achievable audio output power. For example, the common Li-Ion battery as used in today’s
mobile phones has a nominal voltage of Vbat = 3.6 V, but the actual voltage strongly
depends on the state of charge and varies from Vbat,max = 4.2 V with fully charged battery
down to Vbat,min = 2.5 V when battery is depleted. Buck-type audio power amplifiers in
90 4 SICAM for portable devices
the face of the Class D audio power amplifier can create output voltage which is always
lower than the battery voltage vo < Vbat .
The main goal of the new amplifier topology for battery-powered devices to be devel-
oped is to be able to achieve higher audio output powers and at the same time maintain
that output level despite of the decreasing battery voltage. This clearly asks for boost or
buck-boost -type topology, which can step-up the battery voltage to higher levels.
The main problem of the boost and buck-boost DC-DC converter topology with regard
to amplifier applications is that they cannot produce alternating output voltage for driving
a loudspeaker, since they perform merely a transformation of one input DC voltage level to
another output DC voltage level. However, by using two identical boost or buck-boost DC-
DC converters connected to the loudspeaker in a differential mode, load voltages of both
polarities can be easily produced by properly controlling the switching devices. While the
loudspeaker is being supplied by the amplifiers differential-mode voltage, both terminals of
the loudspeaker are riding on the amplifiers common-mode voltage. The circuit diagram
of the proposed double-boost SICAM, also known under the name of push-pull boost
converter [40], [41] is given in Fig. 4.1.
T2 T4
+ vo
Lb1 Lb2
+
vb T1 T3
Cf1 Cf2
Fig. 4.1. Double boost SICAM
Operation of the double-boost SICAM can be divided into two separate parts, depend-
ing on the output voltage polarity. For positive output voltages VCf 1 > VCf 2 , T4 is kept
turned on and T3 turned off, while switches T1 and T2 are operated in PWM fashion, thus
assuring that capacitor voltage VCf 1 is increasing over the battery voltage Vb and average
capacitor voltage VCf 2 is equal to the battery voltage VCf 2 = Vb . For negative output
voltages VCf 1 < VCf 2 , T2 is kept turned on and T1 turned off, while switches T3 and T4
are operated in PWM fashion, thus assuring that capacitor voltage VCf 2 is increasing over
the battery voltage Vb and average capacitor voltage VCf 1 is equal to the battery voltage
VCf 1 = Vb . Operation of the double-boost SICAM is summarized in Table 4.1.
Output voltage T1 T2 T3 T4
+ d (1-d) 0 1
- 0 1 d (1-d)
Table 4.1. Switching states of the double-boost SICAM
The four different connections in the operation of the combined double-boost SICAM
are shown in Fig. 4.2. Stepping through the different possible connections is performed
according to the sign of the output voltage, and is shown in Fig. 4.2 with the plus and
minus sign.
The detailed DC and small-signal AC analysis of the double-boost SICAM operation is
given in Appendix C. Especially interesting is the DC-model of the double-boost SICAM
4.2 Digital audio modulator for the double-boost SICAM 91
_
+
d d
+ vo + vo
iLb1 Lb1 io R iLb2 Lb2 iLb1 Lb1 io R iLb2 Lb2
+ +
vb vb
Cf1 Cf2 Cf1 Cf2
1-d 1-d
+ vo + vo
+ +
vb vb
Cf1 Cf2 Cf1 Cf2
Fig. 4.2. Possible connections in the double-boost SICAM
(C.13) for positive output voltages:

Vb
0 = Vb − (1 − D)VCf 1 ⇒ VCf 1 =
1−D
0 = Vb − VCf 2 ⇒ VCf 2 = Vb
VCf 1 − VCf 2 VCf 1 − VCf 2 (4.1)
0=− + (1 − D)ILb1 ⇒ ILb1 =
R (1 − D)R
VCf 1 − VCf 2 VCf 1 − VCf 2
0= + ILb2 ⇒ ILb2 = −
R R
and (C.14) for negative output voltages:
0 = Vb − VCf 1 ⇒ VCf 1 = Vb
Vb
0 = Vb − (1 − D)VCf 2 ⇒ VCf 2 =
1−D
VCf 1 − VCf 2 VCf 1 − VCf 2 (4.2)
0=− + ILb1 ⇒ ILb1 =
R R
0= + (1 − D)ILb2 ⇒ ILb2 = −
R (1 − D)R
The most important conclusion from both (4.1) and (4.2) is that:
D
Vo = VCf 1 − VCf 2 = ± Vb (4.3)
1−D
which shows that the differential mode voltage i.e. the load voltage of the double boost
SICAM can have either polarity and can be either lower for D < 0.5 or higher for D > 0.5
than the battery voltage Vb , which is beneficial for portable applications. Unfortunately,
the relation between the duty cycle D and the output voltage Vo is strongly nonlinear and
it resembles the one of the buck-boost converter, although the basic building block of the
amplifier is the boost converter.
4.2 Digital audio modulator for the double-boost SICAM

In the last few years, there has been an ongoing public discussion about whether the analog
or the digital modulating approach will prevail in the future. However, it seems that both
approaches have their distinct advantages and certain preferred types of applications,
which guarantee their presence on the market in near future. No matter what the result
of this ”battle” will be in few years, it is a fact that most of the audio sound sources
today have a digital format and coding in telecommunications is becoming almost entirely
digital. Therefore, it is of an utmost interest, especially in small form portable devices,
to perform a straightforward transformation of the PCM or other digital audio code into
PWM, capable of driving the switches in the switching-mode audio power amplifiers.
This has also some unique advantages in a sense that different digital audio processing
algorithms can be implemented in the same digital hardware to give an extra flexibility.
For most of the commercial applications, the aforementioned fully digital audio power
amplifiers are constrained to operate in open-loop mode, since adding a very fast and
high resolution analog-to-digital converter (ADC) to close the feedback loop significantly
adds to their cost.
Among the advantages of the digital modulators for switching-mode audio power am-
plifiers, one being especially appealing for the double-boost SICAM and possibly for all
other boost and buck-boost type audio power amplifiers is the ease of designing nonlinear
modulators. While in analog audio power amplifiers the modulator is essentially linear
and compensation of all the nonlinearities in the power amplifier stage is performed via
the feedback, fully digital audio power amplifiers can account and precompensate for the
nonlinearities of the subsequent stages in the digital modulator, which makes possible high
performance operation of the aforementioned strongly nonlinear amplifiers even without
any feedback.
The work presented in this section will focus entirely on the design of a nonlinear digital
modulator for the double-boost SICAM. For most of the time, the implementation of the
digital modulator follows the guidelines for the design of digital modulators for Class D
audio power amplifiers given in [14], [42], [43], [44]. This means that digital modulator is
implemented using oversampling and noise shaping within Σ − ∆ modulator to reduce
the digital code resolution without any adverse effects on the Signal-to-Noise Ratio (SNR)
within the audio band. The reduction of the resolution i.e. the number of bits b alleviates
the practical implementation of the digital PWM (DP W M ), by using lower clock rates
and reducing power consumption in the latter. In order to account for the nonlinearity of
the subsequent double-boost SICAM with nonlinear output characteristics, the design of
a special digital precompensator will be described.
4.2.1 Implementation of the digital modulator
The complete digital modulator is depicted in Fig. 4.3.
MSB Volume vb
A/D
b2-1 control
2 (-1)
Noise shaping Precompensator LUT
_
Over- d1 d2 (2
b3
-1)kdb2 d Switch Double
H(z) Q b3 round DPWM
f1,b1 sampling f2,b1 _ f2,b2 f2,b3=b2-1 (2 -1)+kdb2 selection boost amp.
_
f2,b4 error
KE
Fig. 4.3. Digital modulator for the double-boost SICAM
As shown in Fig. 4.3, the audio PCM bitstream enters the oversampler, where the
wordlength is maintained and sampling rate is changed from f1 to f2 :
f2 = OSR · f1 (4.4)
where OSR is the oversampling rate. In this way, the new sampling rate f2 becomes sig-
nificantly higher than the signal bandwidth fb , fb ≪ f2 /2, so the same quantization noise
associated with the bit resolution of b1 is evenly redistributed within the new Nyquist
bandwidth f2 /2 to yield much better SNR within the signal bandwidth fb . Another ad-
vantage of the oversampling is that there is enough space to perform noise shaping with
Σ − ∆ modulators, where the noise within the signal bandwidth fb is reduced on behalf of
large increase of the noise out of the signal bandwidth. The amount of oversampling OSR
depends on the particular application, but for the portable audio amplification there are
at least three reasons that make high OSRs appealing:
• Portable devices need low power audio power amplifiers, in a range of few Watts. For
such applications, active power devices are likely to be very small and integrated on
a single silicon chip, so they can operate with very high switching frequencies and
tolerable switching losses, which in turn reduces the size of the output filter,
• With high OSRs, the nonlinear effects of Uniform PWM (UPWM) become negligible
and there is no need for correction algorithms [14], which significantly simplifies the
whole design,
• Another advantage of the high OSRs is that very good SNR can be obtained even
with lower order of the noise filter H(z) in the Σ − ∆ modulator, which does not only
save significant amount of hardware, but also makes the modulator stable with higher
modulation indexes.
For example, the target can be to implement a digital modulator with high OSR of
64x or 128x with just a second order noise shaping, which is conditionally stable for all
modulation indexes. The use of first order noise shaping in audio applications is usually
avoided due to the pronounced idle tones.
At the output of the Σ − ∆ noise shaper, the bit resolution is decreased from b1 to b2
bits in the quantizer Q by taking just b2 of the most significant bits, usually in the range
of 4 to 8 bits. In contrast with the 1-bit Σ − ∆ modulators where the effective gain of
the quantizer Q is ill-defined and strongly depends on the dynamics of the input signals
(higher input signal amplitude ⇒ less gain), the effective gain of the quantizer Q in the
case of higher resolution Σ − ∆ noise shapers is much better defined, which alleviates the
design process and improves its stability.
So far, the proposed digital modulator has the form of a conventional digital modulator
for Class D audio power amplifier. The output of the Σ − ∆ noise shaper represents
the duty cycle d1 , which in conventional full-bridge Class D audio power amplifier is
proportional to the output voltage vo = (1 − 2d1 )Vps . This duty cycle d1 , however, cannot
be used directly in a double-boost SICAM. The polarity of the amplified signal determines
the mode of operation of the switches, according to Table 4.1, and within each mode of
operation the duty cycle d moves independently between 0 and 1, 0 ≤ d ≤ 1. Therefore,
it is of utmost importance to define the digital code which corresponds to the zero of
the audio signal, in order to select the proper mode of operation (positive or negative
output voltage) and determine the duty cycle. Duty cycle is represented by the distance
from the zero code to the waveform. For midriser ADCs, the zero of the audio signal
corresponds to two neighboring digital codes (01...1 and 10...0), while in midtread ADCs,
this corresponds to a single digital code (10...0). For midtread ADCs, situation with 4-bit
resolution is shown in Fig. 4.4. db1 and db2 are the binary, digital representations of the
duty cycles d1 and d2 , 0 ≤ d1 , d2 ≤ 1.
With midtread ADCs, where the zero code is situated at 10...0, selection of the opera-
tion mode can be made simply by looking at the Most Significant Bit (MSB). Therefore
1111
1110
1101
Positive voltages
1100
1011 d
1010 b2
1001
1000
b1
d
0111
0110 db2
0101
0100
Negative voltages
0011
0010
0001
0000
0 0.2 0.4 0.6 0.8 1
t [s] −3
x 10
Fig. 4.4. Digitized sinewave with corresponding duty cycles for double-boost SICAM
in the subsequent DPWM stage only b3 = b2 − 1 bits of the duty cycle d1 are used, but
the effective resolution is still b2 bits. Input duty cycle d2 to the precompensator module
for midtread ADC is calculated in the following way:
db1 − 2b2 −1 , db1 ≥ 2b2 −1

(
db2 = (4.5)
b2 −1 b2 −1
2 − db1 , db1 < 2
which corresponds to taking the Least Significant Bits (LSBs) after the MSB for positive
output voltages, and taking the two’s complement of the same LSBs for negative output
voltages. For midriser ADC, precompensator input duty cycle d2 is calculated by:
db1 − 2b2 −1 (−1) , db1 ≥ 2b2 −1 (−1)

(
db2 = (4.6)
2b2 −1 (−1) − db1 , db1 < 2b2 −1 (−1)
which has the same effect upon d1 like the above mentioned one, with the additional re-
mark that at each sampling instant the zero code alternates between 2b2 −1 − 1 and 2b2 −1
(01...1 and 10...0, represented by (-1) in (4.6)). This has the average effect of precisely
positioning the zero code between the two neighboring digital codes, which can be com-
pared with the effect of dithering, but in a very deterministic way. Of course, randomly
positioning the zero code between the two adjacent digital codes is also possible, with
slight complications in hardware.
Static output transfer function of the double-boost SICAM (4.3) shows strongly non-
linear behavior. In Fig. 4.5, this output characteristic is compared with the buck-type
Class D amplifier. In the same diagram, dashed line represents the desired output char-
acteristic, which is linear like in the buck-type Class D amplifier and is higher at the ends
than the battery voltage vb like in the double-boost SICAM.
In order to linearize the strongly nonlinear static transfer function of the double-boost
SICAM (4.3), a goal is set to make the output voltage vo of the double-boost SICAM
exhibit linear relationship with the duty cycle d2 :
d
vo = vb = kd2 vb (4.7)
1−d
5
4
3
o b
Output voltage v /v
2
1
0 Buck
−1
−2 desired
−3
Double−boost
−4
−5
0 5 10 15 20 25 30
Duty cycle d [binary]
Fig. 4.5. Static transfer functions of the buck converter and double-boost SICAM
which leads to the following equation for the precompensator operation:

kd2
d= (4.8)
1 + kd2
or when the duty cycle is represented by integer numbers in the digital implementation:
(2b2 −1 − 1)kdb2

db = round (4.9)
(2b2 −1 − 1) + kdb2
where db and db2 are binary, digital representations of d and d2 , and round() represents
the rounding operation.
The meaning of the parameter k is to adjust the maximum output voltage with full
duty cycle, and for boosting operation it is always selected k > 1. In Fig. 4.5, it is equal
to k = 3.
Due to the finite resolution of both db and db2 , it is not possible to accurately calculate
the division in (4.8), which inherently leads to error very similar to the quantization error.
For the case k = 3, the precompensator Look-Up Table (LUT) is given in Table 4.2, where
the exact error and the quantized errorb with b4 = 2 bits resolution are defined as:
(2b2 −1 − 1)kdb2
error = − db
(2b2 −1 − 1) + kdb2
( 1 , error > 0 (4.10)
errorb = 0 , error = 0
−1 , error < 0
The output characteristic of the precompensated double-boost SICAM is shown in

Fig. 4.6. It is visible that the linearization through precompensation is not complete, due
to the introduced error when calculating the precompensated duty cycle d.
Error caused by the division in (4.8) and finite resolution of the duty cycles is shown in
the third column of Table 4.2. It has a form of quantization error, so it is very similar to
the error caused by reducing the word length within the Σ − ∆ noise shaper. Latter error
has been effectively rejected within the signal band by feeding back the new duty cycle
db2 db error errorb (2 bits)

0 0 0 0
1 3 -0.5000 -1
2 4 0.2857 1
3 6 -0.3750 -1
4 7 -0.3333 -1
5 8 -0.5000 -1
6 8 0.1818 1
7 9 -0.2500 -1
8 9 0.2308 1
9 10 -0.3571 -1
10 10 0 0
11 10 0.3125 1
12 11 -0.4118 -1
13 11 -0.1667 -1
14 11 0.0526 1
15 11 0.2500 1
Table 4.2. Precompensator Look-Up Table (LUT) for k = 3
5
4
3
Output voltage vo/vb
2
1
Buck
0
−1
desired
−2
−3 Precompensated
−4 Double−boost
−5
0 5 10 15 20 25 30
Duty cycle d [binary]
Fig. 4.6. Static transfer functions of the buck converter and precompensated double-boost SICAM
with reduced word length back to the noise shaping filter. The same idea can be used
for the former division error error, so the digitized error errorb from the precompensator
LUT can be brought back to the Σ − ∆ noise shaper for correction, after being multiplied
with corresponding gain KE .
Digitized error errorb can be represented by arbitrary number of bits b4 , with b4 = 2
being the minimum number of bits for implementation. Digitizing the error with more
than two bits leads to better performance, but also requires bigger LUT and therefore
more hardware.
At the same time, by calculating several LUTs like the one in Table 4.2 for different
linearization coefficients k, volume control in several steps can be implemented by simply
switching among the LUTs corresponding to increasing or decreasing k. Unfortunately,
when moving to small k with input duty cycles d2 spanning the whole range, the output
duty cycle d starts to ”exercise” just few DPWM levels, which in turn significantly worsens
the resulting SNR and reduces dynamic range.
Much better approach for volume control and stabilizing the output voltage vo despite
of the changes in the battery voltage vb is to use slow and cheap A/D converter mea-
suring the battery voltage vb . By intentionally decreasing or increasing the digital code
corresponding to the measured battery voltage, the digital modulator can be ”fooled” to
reduce or increase the output duty cycle d, thus achieving effective volume control.
Finally, the switch selector block in Fig. 4.3 redirects the precompensated duty cycle
d to the selected set of switches according to the output voltage polarity, as shown in
Table 4.1. This block can also incorporate the necessary blanking or dead times, if they
are not implemented in the MOSFET drivers.
4.2.2 Precompensator noise

As it was already mentioned, the error (4.10) introduced at the output of the precom-
pensator LUT is essentially quantization noise, i.e. a result of the inability of the precom-
pensator LUT to accurately represent the result of the division in (4.8) due to the finite
resolution of the duty cycle db .
The similarity of the latter error with the quantization error at the output of the Σ −∆
noise shaper is just in the mechanism of creation, but the effects are rather different.
The usual assumption in Σ − ∆ modulators is that the quantization noise is evenly
spectrally distributed i.e. it is white noise, which becomes increasingly coarse definition
as the number of output bits in the Σ − ∆ modulator is decreased. This simplification
enables simple linear representation of the Σ − ∆ modulator as gain followed with a noise
summation point [43] and leads to rather simple derivation of the corresponding Signal
Transfer Function (ST F ) and Noise Transfer Function (N T F ).
Precompensator noise on the other hand is likely to be strongly colored, so calculating
its RMS value is not so straightforward. The approach undertaken here is to open the
error feedback loop from precompensator LUT to the Σ − ∆ noise shaper and calculate
the error RMS value as a result just of the inaccurate mapping of the input to the output
duty cycles in the precompensator. The noise due to the reduced number of bits is already
accounted for in the Σ − ∆ modulator noise and in the case of ideal precompensation of
the nonlinearity of the double-boost SICAM in (4.3) via the duty cycle transformation
(4.8), the aforementioned Σ − ∆ quantization noise will just appear in the output voltage
scaled by the amplification factor k of the power stage.
The amplitudes of the division error (4.10) at the output of the precompensator for
each and every input duty cycle can be easily calculated as shown in Table 4.2. The
only unknown when calculating the noise RMS value is therefore the time intervals of
each of the errors. The number of levels in the quantized sinusoidal waveform in Fig. 4.4
corresponding to changes in the duty cycle db2 is:
Nl = 2b2 −1 (4.11)
With midtread representation of the digital code, the zero of the reference sinewave is
situated at (10...0) i.e. at 2b2 −1 and the properly scaled sinewave function will have the
following form:
y = M (2b2 −1 − 0.5)sin(ωm t) (4.12)
where M is the modulation index, (2b2 −1 − 0.5) is the maximum value of the reference
sinewave and ωm is the modulation angular frequency.
As a result of the rounding to the nearest integer performed in the quantizer of the
Σ − ∆ noise shaper, the start time instant tns and the end time instant tne of the nth level
in the digitized sinewave coincide with the instants when the waveform encounters:
y1s = 0 y1e = 0.5

y2s = 0.5 y2e = 1.5
y3s = 1.5 y3e = 2.5 (4.13)
... ...
yns = n − 1.5 yne = n − 0.5
which leads to the following equalities:
M (2b2 −1 − 0.5)sin(2πfm tns ) = n − 1.5

(4.14)
M (2b2 −1 − 0.5)sin(2πfm tns ) = n − 0.5
and the following expressions for the time instants tns and tne :

1 n − 1.5
tns = arcsin b2 −1 − 0.5)
2πfm M (2
1 n − 0.5 (4.15)
tne = arcsin
2πfm M (2b2 −1 − 0.5)
∆tn = tne − tns
It should be noted that when complex numbers are obtained for the time instants in
(4.15) this essentially means that there is no intersection point with the sinewave and the
corresponding nth digital level is not used at all, tns = tne = 0. On other hand, for the
first level t1s = 0 and for the last used digital level l with non-zero duration tle = Tm /4.
To all of the time intervals ∆tn corresponding to the duration of the corresponding nth
digital level, division errors like those in Table 4.2 can be associated and this repeats four
times per sinewave period, due to the quarter-wave and half-wave symmetry. Thus, the
precompensator noise RMS value is calculated using the following expression:
Tm Nl
1
Z X
e2pr,rms = 2
error (t)dt = 4fm errorn2 ∆tn (4.16)
Tm 0 n=1
Precompensator RMS noise levels epr,rms with b2 = 5 as a function of the modulation

index M and the amplifier gain k are depicted in Fig. 4.7. It is clearly visible that the
error exhibits minimums for certain amplifier gains k, when the division error is minimal
because the digitized duty cycles are very close to the ideal ones obtained with infinite
resolution. This gives rise to the idea that for the same output power level, a particular
combination of modulation index M and amplifier gain G can be found which leads to
best SNR and lower THDN.
4.2.3 Simplified control block diagram
The simplified control block diagram of the proposed digital control for double boost
SICAM with all the associated transfer functions is shown in Fig. 4.8.
The main two blocks at the control diagram are the Σ − ∆ noise shaper and the
precompensator LUT.
The dynamics of the Σ − ∆ noise shaper can be easily represented by the gain of the
quantizer c and two linear transfer functions - Signal Transfer Function ST FΣ∆ and Noise
Transfer Function N T FΣ∆ :
0.8
0.7
0.6
RMS error epr,rms [V]
0.5
0.4
0.3
0.2
0.1
0
0
0.2 3
0.4 2.5
2
0.6 1.5
0.8 1
0.5
1 0
Modulation index M
Gain k
Fig. 4.7. Precompensator RMS noise levels epr,rms with b2 = 5
S-D Noise shaper eSD
NTFSD
Precompensator LUT vo
x
STFSD c K
epr
fp r(M,k)
ce
eerb
KE
Fig. 4.8. Simplified control block diagram of digitally controlled double-boost SICAM
H(z)
ST FΣ∆ (z) =
1 + H(z)
(4.17)
1
N T FΣ∆ (z) =
1 + H(z)
where H(z) is the noise loop filter from Fig. 4.3.

The useful signal x comes out of the Σ − ∆ modulator after being low-pass filtered in
the audio band by the ST FΣ∆ and amplified by the quantizer Q gain c. At the same time,
the quantization error eΣ∆ is assumed to be white noise and thus not correlated with the
input signal x, so it is represented by an independent and separate input. Before summing
it with the useful signal at the output of the Σ − ∆ noise shaper, this quantization error
is high-pass filtered by the N T FΣ∆ , which essentially removes the bulk of the noise from
the audio band and pushes it to higher frequencies in an extended range provided by the
oversampling.
As already mentioned in Section 4.2.2, it can be assumed that the high-pass filtered
quantization noise eΣ∆ from the noise shaper appears straightforward in the output volt-
age after being amplified by the linearized double-boost SICAM gain k. The division error
epr from the precompensator LUT is summed with the useful signal and the quantization
noise from the Σ − ∆ noise shaper just before the amplification k in the double-boost
SICAM, but its dependance on the precompensator input signal is a complex nonlinear
function of the modulation index M and linearized amplifier gain k, as already shown in
Section 4.2.2. Part of that division error is being returned back to the Σ − ∆ noise shaper,
but as a result of the quantization of the aforementioned error, additional noise eerb is
injected in the feedback loop. Finally, the quantized division error errorb is amplified by
the feedback gain KE and enters the Σ − ∆ noise shaper. What is expected here is that by
the action of the noise loop filter H(z) in the Σ − ∆ noise shaper some of the precompen-
sator division error will be rejected in the audio band and some of the noise will be shifted
to inaudible frequencies. Since the input signal to the precompensator contains both the
processed useful signal x and quantization error eΣ∆ from the Σ − ∆ noise shaper, they
both affect the precompensator division error epr and thus are fedback for second time to
the Σ − ∆ noise shaper. However, the effects of this additional feedback on rejection of
quantization error eΣ∆ and precompensator division error epr are very difficult to study
analytically and thus extensive simulation results will be presented in the next section.
4.3 Simulation of the double-boost SICAM with digital

modulator
In order to compare the performance of the double-boost SICAM with the proposed
digital modulator with and without feedback from the precompensator LUT to the Σ − ∆
modulator, a set of simulations in Matlab Simulink was performed. The digital modulator
uses already oversampled 1 kHz sinewave with variable modulation index, resolution of
b1 =16 bits and sampling frequency of f2 =1.024 MHz. Σ − ∆ modulator is 2nd order
with CRFB (cascade of resonators in feedback) structure shown in Fig. 4.9, reducing the
word length to b2 =5 bits. The optimal second order Noise Transfer Function (NTF)
for OSR=128 was obtained using the synthesizeN T F function from the ∆ − Σ(delsig)
toolbox for Matlab [45]:
z 2 − 2z + 1
NTF = (4.18)
z 2 − 1.225z + 0.4415
leading to the following noise-shaping filter function
0.775z − 0.5585
H= (4.19)
z 2 − 2z + 1
which encompasses one delay z −1 from the input to the output and thus renders the digital
system realizable .
CRFB noise shaper coefficients are obtained by using realizeN T F function from the
same Matlab toolbox, leading to optimal coefficients given in Table 4.3. To simplify the
practical implementation, these coefficients were rounded to the nearest fraction with
power-of-two denominator, as given in Table 4.3. NTF with rounded coefficients becomes:
z 2 − 2z + 1
NTF = (4.20)
z 2 − 1.25z + 0.5
Some of the waveforms and numerical results of the normalized output voltage vo /vb
are shown in Fig. 4.10 to Fig. 4.16, with the details for the modulation index M , coefficient
k and number of bits b4 given in the title of the figures.
By comparing Fig. 4.10 and Fig. 4.11, as well as Fig. 4.12 and Fig. 4.14, it becomes
apparent that closing the feedback with the duty cycle error from the precompensator
4.3 Simulation of the double-boost SICAM with digital modulator 101
a1 a2 g1 b1 b2 b3 c1 c2
optimal 0.2162 0.5585 0 0.2162 0.5585 1 1 1
rounded 0.25 0.5 0 0.25 0.5 1 1 1
Table 4.3. Optimal and rounded CRFB noise-shaper coefficients
in
-g1
b1 b2 b3
z c1 1 c2 out
+ z-1 + z-1 + Q
-a1 -a2
err
+
Fig. 4.9. CRFB Σ − ∆ noise-shaper structure
M=0.8, k=1.8455, b =3
4
3
2
o b
Output voltage v /v
−1
−2
−3
0 0.5 1 1.5 2
−3
time t[s] x 10
Fig. 4.10. Normalized output voltage vo /vb of the fully-digital double-boost SICAM without feedback from the
precompensator
LUT to the summing point of the Σ − ∆ noise shaper significantly improves the linearity
of the double-boost SICAM. In terms of THD+N, latter is almost halved by introducing
the feedback.
The effects of changing coefficient k on the double-boost SICAM with digital modulator
with and without feedback from the precompensator are shown in Fig. 4.13 and Fig. 4.15.
As mentioned earlier, using different LUTs calculated for different coefficients k as volume
control has an adverse effect on the THD+N results.
Finally, the performance of the digital modulator with different resolution for the di-
vision error b4 is shown in Fig. 4.16. It seems like b4 = 3 bits is the optimal choice on
”performance/size of LUT” scale.
M=0.8, k=1.8455, b =3
4
3
o b
Output voltage v /v 1
−1
−2
−3
0 0.5 1 1.5 2
time t[s] −3
x 10
Fig. 4.11. Normalized output voltage vo /vb of the fully-digital double-boost SICAM with feedback from the
precompensator
4.4 Conclusion
Switching-mode audio power amplifiers with output voltage step-up characteristics based
on the boost and buck-boost converters are very appealing solution for portable, battery
Output voltage at K=1.8455 and b4=3

4 4
2 2
M=0.1
M=0.2
0 0
THDN=15.5498% THDN=10.3707%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
4 −3 4 −3
x 10 x 10
2 2
M=0.3
M=0.4
0 0
THDN=5.7565% THDN=7.777%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
4 −3 4 −3
x 10 x 10
2 2
M=0.5
M=0.6
0 0
THDN=7.0961% THDN=4.9432%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
4 −3 4 −3
x 10 x 10
2 2
M=0.7
M=0.8
0 0
THDN=5.4492% THDN=4.5771%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
4 −3 4 −3
x 10 x 10
2 2
M=0.9
M=1
0 0
THDN=6.2885% THDN=29.4294%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
x 10 x 10
precompensator as a function of the modulation index M
4.4 Conclusion 103
Output voltage at M=0.8 and b4=3

4 4
K=0.16256
2 2
K=0.1
0 0
THDN=24.219% THDN=15.5995%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
4 x 10 4 x 10
K=0.26426
K=0.42959
2 2
0 0
THDN=14.6607% THDN=9.7809%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
4 x 10 4 x 10
K=0.69834
K=1.1352
2 2
0 0
THDN=7.0338% THDN=6.4596%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
4 x 10 4 x 10
K=1.8455
2 2
K=3
0 0
THDN=4.5771% THDN=5.6691%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
x 10 x 10
precompensator as a function of the selected linearizing coefficients k
powered devices. One of them, the so called double-boost SICAM or push-pull boost
converter was presented in this chapter. The main obstacle towards its greater acceptance
is its very nonlinear static transfer function, as well as the need for two separate inductors,
which are very difficult to integrate in Integrated Chip (IC) solution.
Along with the double-boost topology and its DC and AC small-signal analysis, a new
digital modulator was presented, which is capable of linearizing the open-loop transfer
function from the digital audio input to the output voltage. It consists of an oversampler,
Σ − ∆ noise shaper for reducing the data word length, precompensaion unit in a form of
LUT which maps the incoming duty cycles into a set of linearizing outgoing duty cycles, as
well as a DPWM unit and switch selector. In order to improve the level of linearization of
the output characteristics, the division error when calculating the linearizing duty cycles
is fed back into the Σ − ∆ noise shaper. An extensive set of simulations is performed
to verify the operation of the double-boost SICAM with the proposed digital modulator
with and without feedback from the precompensator unit.
Output voltage at K=1.8455 and b4=3

4 4
2 2
M=0.1
M=0.2
0 0
THDN=40.2667% THDN=11.485%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
4 −3 4 −3
x 10 x 10
2 2
M=0.3
M=0.4
0 0
THDN=6.8458% THDN=5.4841%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
4 −3 4 −3
x 10 x 10
2 2
M=0.5
M=0.6
0 0
THDN=3.6621% THDN=3.6596%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
4 −3 4 −3
x 10 x 10
2 2
M=0.7
M=0.8
0 0
THDN=3.1801% THDN=2.4763%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
4 −3 4 −3
x 10 x 10
2 2
M=0.9
M=1
0 0
THDN=2.3178% THDN=2.0785%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
x 10 x 10
precompensator as a function of the modulation index M
4.4 Conclusion 105
Output voltage at M=0.8 and b4=3

4 4
K=0.16256
2 2
K=0.1
0 0
THDN=22.9995% THDN=14.3197%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
4 x 10 4 x 10
K=0.26426
K=0.42959
2 2
0 0
THDN=11.6082% THDN=8.0962%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
4 x 10 4 x 10
K=0.69834
K=1.1352
2 2
0 0
THDN=4.7654% THDN=3.7301%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
4 x 10 4 x 10
K=1.8455
2 2
K=3
0 0
THDN=2.4763% THDN=3.9593%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
x 10 x 10
precompensator as a function of the selected linearizing coefficients k
Output voltage at M=0.8 and K=1.8455

4 4
2 2
b4=1
b4=2
0 0
THDN=4.5771% THDN=3.3898%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
4 x 10 4 x 10
2 2
b4=3
b4=4
0 0
THDN=2.4763% THDN=2.7927%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
4 x 10 4 x 10
2 2
b4=5
b4=6
0 0
THDN=2.4235% THDN=2.6002%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
4 x 10 4 x 10
2 2
b4=7
b4=8
0 0
THDN=2.618% THDN=2.5599%
−2 −2
−4 −4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
−3 −3
x 10 x 10
precompensator as a function of the number of bits b4
Part II
Isolated SICAMs
5
Introduction to isolated SICAMs
”How wonderful that we have met with a paradox. Now
we have some hope of making progress.”
- Niels Bohr
The greatest part of the research and prototyping work within the SICAM project was
done in the field of isolated SICAMs. And that is not peculiar, since the roads to non-
isolated single-stage switching-mode audio power amplification presented in Part I seem
somewhat straightforward. On the other hand the requirement for providing isolation in
a form of a transformer has tremendous impact on the possible SICAM solutions and the
level of engineering effort needed. Isolated SICAMs are also a safety requirement whenever
there is a possibility for the user to touch on purpose or unintentionally some of the metal
parts of the amplifier, which will be most often the case.
All of the SICAM solutions and topologies which will be subject of investigation in the
next chapters will use bridge rectifier for the AC-mains voltage and DC storage capacitor
for intermediate energy storage during the periods with low input voltage. It is believed
that this solution is the most cost effective solution for overcoming the power supply
problems from a single-phase AC-mains utility grid. Therefore the goal of constructing a
SICAM represents in fact a challenge of designing compact isolated DC-AC converters.
This introductory chapter will predominantly deal with the basic energy conversion
principles for isolated power converters utilizing small High Frequency (HF) transformers.
The structure of the proposed isolated SICAM solution based on HF-link converter will be
briefly described, with a special focus on the use of so called bidirectional or four-quadrant
(4Q) switches in the output stage. At the end, thorough patent investigation in the field
of isolated direct converters with HF-link will be given.
5.1 Conventional solution with isolated SMPS and Class D

audio power amplifier
The conventional Class D audio power amplifier with switching-mode power supply is
shown in Fig. 5.1. On the mains side, line rectifier charges a large capacitor A, which is
used to store energy from the line and overcome the problems of regular input voltage
zero-crossings, i.e. it averages the input power, as already described in Section 3.1. In
order to be able to use small isolation transformer, the inverter on the input side of
the power supply is driven with high-frequency gate signals to reduce the amount of
magnetic flux swing. On the secondary side, transformer voltage is rectified once again
and well filtered, so that the stiff intermediate DC-bus with bulky capacitor B is used to
interface with a Class D audio power amplifier. This makes it easy for the amplifier to
achieve excellent audio performance, although its Power Supply Rejection Ratio (PSRR),
which quantifies the ability of the Class D amplifier to hinder power supply perturbations
from appearing in the audio output, may be low. It is however clear that this conventional
solution features unnecessary redundancy and complexity, like for example the two energy
110 5 Introduction to isolated SICAMs
buffering capacitors A and B instead of just one on the input side, as well as multiple
and separate control loops around the power supply and the Class D amplifier. It should
be stressed that despite of the redundancy of capacitor B with regard to overcoming the
regular input voltage zero crossings, it is of ultimate importance for Class D amplifier
operation since it helps the DC bus maintain constant voltage and provide path for the
reactive load current. At the same time, the energy flow is unidirectional throughout
the whole power supply, while the bidirectional power flow is kept just between the power
supply output capacitor B and the Class D audio power amplifier. This leads to a common
problem when reproducing low frequency signals with single-ended audio power amplifiers
known as power supply pumping [46], where the capacitors B in the intermediate DC bus
are asymmetrically charged and discharged leading to imbalance and improper operation.
L
+
~ ~
A B
AC C
mains -
Inverter LPF Class D
Energy flow
Fig. 5.1. Conventional Class D audio power amplifier with isolated SMPS
5.2 Isolated audio power amplification through HF-link

conversion
The direct non-isolated energy conversion approach without any reactive components, ex-
cept for filtering purposes, has been successfully utilized in three-phase matrix converters
[19]. In the aforementioned converters the output voltage and frequency can be easily
adjusted by using bidirectional switches and the three-phase utility grid provides continu-
ous power flow. Unfortunately, the single-phase utility grid limits the applicability of the
matrix converter, since the regular zero crossings of the input voltage ask for some sort
of input side energy buffering. Therefore, SICAMs cannot be made in a single stage and
without any reactive components, but nonetheless the solution allows for direct energy
conversion in two closely dedicated and interconnected stages.
When isolation from the mains is mandatory, High Frequency (HF) -link converters
[47], [48] represent an interesting alternative, which is also applicable for a single-phase
grid. Single-phase direct converters, like the one shown in Fig. 5.2, can use the same mains
rectifier with energy storage capacitor A like the conventional audio power amplifier, but
the intermediate DC bus with the rectifiers and the associated Low-Pass Filter (LPF) on
the secondary side has been replaced with a high frequency AC link. As a result of this
transformation there is one energy conversion less when compared to the conventional so-
lution, but the audio power amplifier is more complex, since it incorporates bidirectional
switches capable of blocking both transformer voltage polarities and conducting in both
current directions. A bidirectional bridge asks for advanced control techniques for com-
mutating the load current between the incoming and outgoing switches, since there is no
diode freewheeling path as in conventional Class D amplifiers. Nonetheless, the approach
5.3 Frequency domain analysis of different PWM SICAM solutions 111
is feasible and has been reported with regard to converters for Uninterruptible Power
Supplies (UPS) and renewables [49], [50], [51].
Bidirectional
switches
+
~ ~
A
AC
mains -
Inverter Audio Amp.
Energy flow
Fig. 5.2. Direct conversion audio power amplifier
Another advantage of the direct energy conversion amplifier is that the energy flow
is bidirectional over the HF-link i.e. the isolation transformer, which makes it resistant
to the notorious problem of power supply pumping with single-ended Class D amplifiers.
On the other side, since there is no intermediate energy storage on the secondary side,
all the reactive power flow from the load to the amplifier and peak load power must
be supplied from the primary side, which leads to overdimensioned primary switching
stage. However, together with the promises of simplified design, higher efficiency, reduced
number of reactive components, less redundancy and prospects for high-level integration,
HF-link-based SICAM represents a highly competitive technology.
5.3 Frequency domain analysis of different PWM SICAM

solutions
In the following sections a frequency domain analysis of different SICAMs that utilize
PWM will be undertaken. It is by no means the only modulation approach that can
be successfully implemented in a SICAM, but when compared to some of the alterna-
tive modulation principles like for example Pulse Density Modulation (PDM), PWM can
achieve satisfactory performance and bandwidth with lower switching frequency.
5.3.1 Time domain and frequency domain operations of power electronics
For the discussions in the next few sections, it is interesting to analyze the operations
performed by half-bridge and full-bridge switching stages in time and frequency domain.
The schematics of the half-bridge and full-bridge switching stages are given in Fig. 5.3
and Fig. 5.4.
For the half-bridge switching stage, time domain and frequency domain operation rep-
resent:
• time-domain multiplication:
v1 (t) = vg (t) · s1 (t) (5.1)

• frequency-domain convolution:
Vg(jw) + S1(jw)
S1(jw) V2(jw) S2(jw)
vg(t) s1(t) s1(t) s2(t)
Vg(jw) +
v2(t)
S1(jw) V1(jw) vg(t) S1(jw) V1(jw) S2(jw)

Vg(jw) +
vg(t) s1(t) v1(t) s1(t) v1(t) s2(t)
Fig. 5.3. Half-bridge schematic with the associated Fig. 5.4. Full-bridge schematic with the associated
voltages and switching functions voltages and switching functions
Z +ω
V1 (jω) = Vg (jω) ∗ S1 (jω) = Vg (jν)S1 (jω − jν)dν (5.2)
−ω
For the full-bridge switching stage, time domain and frequency domain operation rep-
resent:
• time-domain multiplication and subtraction:
v1 (t) − v2 (t) = vg (t) · [s1 (t) − s2 (t)] (5.3)

• frequency-domain convolution and subtraction:
Z +ω
V1 (jω)−V2 (jω) = Vg (jω)∗[S1 (jω)−S2 (jω)] = Vg (jν)[S1 (jω−jν)−S2 (jω−jν)]dν
−ω
(5.4)
An example of the time domain waveforms and frequency domain spectrum of a full-
bridge with 1 kHz test signal is depicted in Fig. 5.5. It can be observed that because of
the subtraction of the frequency spectrums of the switching functions S1 and S2 there is
an effective doubling of the switching frequency in the resultant switching function S1 −S2
i.e. the switching harmonics at (2n + 1)fs are missing.
S1 S2 S1 − S2
1.5 1.5 2.5
2
1 1
1.5
1
0.5 0.5
0.5
0 0 0
−0.5
−0.5 −0.5
−1
−1.5
−1 −1
−2
−1.5 −1.5 −2.5

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
time t[s] x 10
−3 time t[s] x 10
−3
time t[s] −3
x 10
MAGNITUDE RESPONSE MAGNITUDE RESPONSE MAGNITUDE RESPONSE
5000 5000 10000
4000 4000 8000
3000 3000 6000

|H(w)|
|H(w)|
|H(w)|
2000 2000 4000
1000 1000 2000
0 0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
FREQUENCY x 10
5 FREQUENCY x 10
5
FREQUENCY 5
x 10
MAGNITUDE RESPONSE MAGNITUDE RESPONSE MAGNITUDE RESPONSE
100 100 100
50 50 50
0 0 0
DEGREES
DEGREES
DEGREES
−50 −50 −50
−100 −100 −100
−150 −150 −150
−200 −200 −200

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
FREQUENCY x 10
5 FREQUENCY x 10
5 FREQUENCY x 10
5
Fig. 5.5. Time and frequency domain analysis of full-bridge switching stage
5.3.2 Audio amplification with only a primary side switching stage
Before proceeding to the frequency domain analysis of different SICAMs, it is interesting to

analyze the possibility of building an isolated direct audio power amplifier with a switching
stage only on the primary side, as shown in Fig. 5.6. The reference audio signal with the
Signal Spectrum (SS) made entirely from the audio baseband enters the PWM modulator.
The SS of the PWM modulator output depends on the carrier shape (ex. single-sided or
double-sided) and the number of levels (ex. 2-level or 3-level), but is always including
the modulating audio signal baseband, carrier harmonics as well as their intermodulation
product sidebands [33]. When the output of the PWM modulator is directly used to
drive the input stage, the Power Spectrum (PS) of the transformer voltage has a low
frequency (LF) content that can extend down to 20 HZ and therefore demands huge
isolation transformer. Therefore this approach is regarded as economically unsound, i.e.
all of the practical SICAMs must have switching stages on both sides of the isolation
barrier in a form of a small high frequency (HF) transformer. In the following sections,
the switching stage on the primary side of the HF transformer will be referred as primary-
side stage, input stage or inverter stage, and the switching stage on the secondary side
will be referred as secondary-side stage, output stage or bidirectional bridge.
PS
Inverter
| |
Fh Fs
+
~ ~ PS
- | |
Fh Fs
SS
SS
| |
| |
+ Fh Fs
Fh Fs
-
PWM modulator
Fig. 5.6. Isolated audio power amplifier with only a primary-side switching stage
5.3.3 Coding and decoding of the audio signals for isolated amplifiers
Previous example showed that some signal processing is needed before sending the train
of PWM rectangular pulses from the PWM modulator to the gates of both switching
stages. The signal processing can be divided into two phases: coding, where the entire
LF audio baseband is inserted into the sidebands around the HF carrier harmonics and
decoding, which restores the audio baseband on the secondary side of the isolation barrier.
The following example should clarify the aforementioned concepts.
The frequency spectrum of different natural sampled PWM waveforms FN xDx has been
derived in [33]. The Fourier series of a 2-level double-sided PWM signal FN ADD is given
with the following equation:
∞
X Jo (mπ M2 ) mπ
FN ADD (t) = M cos(ωm t) + 2 mπ sin cos(mωc t)+
m=1 2
2
±∞
∞ X (5.5)
Jn (mπ M2 )

X (m + n)π
+2 mπ · sin cos(mωc t + nωm t)
m=1 n=±1 2
2
where M is the modulation index, ωm is the angular frequency of the modulating audio
signal, ωc is the angular frequency of the triangular carrier, Jn is Bessel function of the
first kind with order n, m and n are integer numbers. The PWM signal FN ADD in time
domain and frequency domain is shown in Fig. 5.7 and Fig. 5.8, correspondingly.
One possible way to eliminate the audio baseband in FN ADD is to invert the polarity
of each second PWM pulse, which is known to produce LF-free voltage waveform and
allows for building smaller isolation transformer [3]. The inversion process is equivalent to
multiplication in the time domain of the 2-level double-sided PWM signal FN ADD (t) with
a train of rectangular pulses Fr (t) synchronized with the triangular carrier, or equivalently
convolution of the corresponding magnitude and phase spectra in the frequency domain,
which effectively removes the LF audio baseband.
The Fourier series of a train of rectangular pulses synchronized with the triangular
carrier is given by:
4
Fr (t) = sin[(2k − 1)ωc t] (5.6)
(2k − 1)π
where k is an integer number. The rectangular pulse train Fr in time domain and frequency
domain is shown in Fig. 5.9 and Fig. 5.10, correspondingly.
The resultant waveform with the coded baseband becomes:
2M
FN ADD (t) · Fr (t) = {sin[(2k − 1)ωc t + ωm t] + sin[(2k − 1)ωc t − ωm t]}+
(2k − 1)π
∞
X 4Jo (mπ M2 ) mπ
+2 2
sin · {sin[(2k + m − 1)ωc t] + sin[(2k − m − 1)ωc t]}+
m=1
m(2k − 1)π 2
∞ X ±∞
4Jn (mπ M2 )

X (m + n)π
+2 2
sin ·
m=1 n=±1
m(2k − 1)π 2
· {sin[(2k + m − 1)ωc t + nωm t] + sin[(2k − m − 1)ωc t − nωm t]}
(5.7)
Equation (5.7) above shows that the LF audio baseband has been coded into the sidebands
around the HF switching harmonics. The resultant PWM signal FN ADD ·Fr in time domain
and frequency domain is shown in Fig. 5.11 and Fig. 5.12, correspondingly. Notice that
there is no LF content in the frequency spectrum of the coded waveform in Fig. 5.12.
The decoding process represents nothing else than another multiplication of the resul-
tant waveform FN ADD (t) · Fr (t) in (5.7) with the same rectangular pulse train Fr (t) in
(5.6), which is always done at the secondary side to restore the original audio baseband.
During this process the polarity of the coded pulses is inverted once again to restore the
original pulse sequence from the PWM modulator and its LF audio content. In frequency
domain this corresponds to convoluting the corresponding frequency spectra of the coded
waveform FN ADD (t)·Fr (t) and the rectangular pulse train Fr (t), which effectively extracts
the audio information from the sidebands of the switching harmonics and restores them
at the original frequencies in the audio baseband.
Looking at the constitutive parts of the coded waveform (5.7), it can be noticed that
while FN xDx (t) contains LF audio content, the rectangular pulse train Fr (t) has only
HF content, just like the coded PWM signal FN xDx (t) · Fr (t). This means that both
FN xDx (t) · Fr (t) and Fr (t) can be used to transfer energy from the mains through the
isolation barrier to the secondary side, with minimum size transformer. In the former
case, the audio coding is done on the primary side and the audio decoding and restoration
of the original LF content is performed on the secondary side of the transformer. In the
latter case, both the audio coding and the decoding are performed on the secondary side,
but supplemented with the energy-transferring HF rectangular voltage waveform on the
primary side. The analysis of the two aforementioned SICAM approaches will be subject
of the following sections.
5.3.4 SICAM with modulated transformer voltages
SICAM with modulated transformer voltages [3],[52], shown in Fig. 5.13, uses the coded
3-level double-sided PWM signal FN BDD (t)·Fr (t) to drive the primary switching stage and
the transformer. On the secondary side, the bidirectional bridge is driven with the same
rectangular pulse train Fr (t) to restore the audio baseband. The main advantage of this
approach is that the transformer voltage contains periods with zero voltage each switch-
ing period, during which the commutation of the secondary side bidirectional bridge is
performed. The aforementioned benefit is achieved by shortly turning on both the incom-
ing and outgoing bidirectional switches during the periods with zero transformer voltage,
which does not create short-circuit current on the primary side and at the same time
provides an uninterrupted path for the load current. As a side effect, output stage switch-
ing losses are decreased too. However, this approach necessitates separate transformers
and input stage for each audio channel, which is not economically feasible in the modern
multi-channel audio systems.
In order to achieve good audio performance, the switching frequency of the output
stage needs to be very high, in the order of few hundreds of kHz. Since the switching of
both stages in this approach must be simultaneous to perform load current commutation
the switching frequency of the input stage will be rather high, too, which can create
significant switching losses in the primary side active devices.
From a practical viewpoint, there are also problems with creating additional voltages
for control biasing on both the primary and the secondary, as well as creating power
supplies for the secondary-side isolated gate drives, if needed. Since the power transformer
voltages are modulated in accordance with the amplified audio signal, power flow to any
auxiliary winding put on the same leg with the main transformer will be variable and
input signal dependant. This in turn asks for adding additional auxiliary transformers
and switching stages on the primary side or using line transformers with post regulators,
which unavoidably adds to the product cost.
5.3.5 SICAM with non-modulated transformer voltages
SICAM with non-modulated transformer voltages [53], [9], shown in Fig. 5.14, is driving
the primary stage and the transformer with the 50% duty cycle rectangular waveform
Fr (t). The rest of the coding and decoding is done on the secondary side, where the
bidirectional bridge is driven with the coded PWM signal FN xDx (t) · Fr (t). The main
benefit of the presented approach is the possibility of supplying power to multiple output
stages with the same primary stage and transformer, as well as easy derivation of auxiliary
voltages for control biasing or isolated gate drive power supplies by fitting additional
MAGNITUDE RESPONSE
1.5 7000
6000
5000
1
4000
3000
|H(w)|
2000
0.5
1000
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
FREQUENCY x 10
5
0
PHASE RESPONSE
100
50
−0.5
0
DEGREES
−50
−1
−100
−150
−1.5 −200
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
5
time t[s] x 10
−3
FREQUENCY x 10
Fig. 5.7. 2-level double-sided PWM signal FN ADD Fig. 5.8. Frequency spectrum of FN ADD
MAGNITUDE RESPONSE
1.5 7000
6000
5000
1
|H(w)|
4000
3000
2000
0.5
1000
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
FREQUENCY 5
0 x 10
PHASE RESPONSE
200
150
−0.5
100
DEGREES
50
−1
0
−50
−1.5 −100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
−3 5
time t[s] x 10 FREQUENCY x 10
Fig. 5.9. Rectangular pulse train Fr Fig. 5.10. Frequency spectrum of Fr
MAGNITUDE RESPONSE
1.5 7000
6000
5000
1
4000
3000
|H(w)|
2000
0.5
1000
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
FREQUENCY 5
0 x 10
PHASE RESPONSE
200
150
−0.5
100
DEGREES
50
−1
0
−50
−1.5 −100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
5
time t[s] x 10
−3
FREQUENCY x 10
Fig. 5.11. Resultant PWM signal FN ADD · Fr Fig. 5.12. Frequency spectrum of FN ADD · Fr
PS
Inverter Audio Amp.

| |
Fh 2Fs
+
~ ~ PS
- | |
Fh 2Fs
SS j
SS j SS j
| |
| | | |
+ Fh Fs
Fh Fs Fh Fs
X -
SS -j
SS -j SS -j
| | | |
PWM modulator |
Fh
|
Fs
Fh Fs Fh Fs (3 level)
SS
| |
Synchronized
Fh Fs rectangular carrier
Fig. 5.13. SICAM with modulated transformer voltages
Fig. 5.14. SICAM with non-modulated transformer voltages
windings on the same core. It is also favorable for the conducted differential-mode Electro-
Magnetic Interference (EMI), since the full duty cycle operation causes the input stage
to draw line current almost continuously (if the short dead time is neglected), so the only
remaining problem is the common-mode noise.
However, with this approach, the commutation of the load current in the secondary
side bidirectional bridge becomes rather involved, since in principle there are no instants
with zero transformer voltage that can alleviate the commutation. Therefore, the commu-
tation of the bidirectional bridge depends heavily on using load voltage clamps [9], [54]
or advanced commutation techniques [53], [30]. Due to the numerous advantages of the
SICAMs with non-modulated voltages, this approach has been chosen for implementation
and is discussed in detail in the next sections and chapters.
5.4 Developing SICAMs from SMPSs

The simplest way of developing direct audio conversion topologies is starting with a par-
ticular power supply scheme and extending its capabilities, like shown in Fig. 5.15. Firstly,
the power supply control bandwidth is increased over the intended power bandwidth i.e.
over the highest frequency of the signal to be amplified, resulting in tracking power supply
with variable DC output voltage. This is usually done by decreasing the size of the output
low-pass filter so that its frequency response is flat over all the frequencies of interest and
then drops rapidly to attenuate the switching harmonics. At the same time, the switching
frequency of the SMPS is somewhat increased, to help achieve higher bandwidth. In order
to complete the construction of the direct audio power amplifier, bidirectional power flow
capability is added to the tracking power supply by replacing all the unidirectional com-
ponents (for example, the secondary-side rectifiers) with bidirectional switches. At the
end, a suitable controller is designed in a way that provides enough gain with sufficient
phase margin throughout the power bandwidth, so that the resultant amplifier distortion
and output impedance are kept low. These development steps are shown on the example
of half-bridge SMPS in Fig. 5.16.
Fig. 5.15. SICAM development steps
5.5 Bidirectional switches and gate drives for isolated SICAMs

5.5.1 Bidirectional switch arrangements
A single quadrant switch (1QSW) is capable of conducting in only one current direction
and blocking only one voltage polarity. Its output characteristic is therefore completely
5.5 Bidirectional switches and gate drives for isolated SICAMs 119
D21 D22
T11 T21 T22
C1
+ . . D21
L Low L
AC
~ ~ .
mains D22 C R
-
C2
T12
Low C
fs k
Higher switching
frequency
Fig. 5.16. Reworking a half-bridge SMPS for SICAM operation
placed in a single quadrant of the V-I plane. Representatives of this group are simple
switching elements like diode, BJT, IGBT etc.
A two quadrant switch (2QSW) operates in two quadrants of the V-I plane. It can be:
• Voltage 2QSW - it is capable of blocking voltages of both polarities, but it conducts
current in only one direction; voltage 2QSW is usually constructed by series connection
of a diode and a transistor (BJT,IGBT) and is shown in Fig. 5.17a; and
• Current 2QSW - it is capable of conducting current in both directions, but it blocks
voltage of only one certain polarity; this switch is usually made of an antiparallel pair
of a diode and a transistor and is shown in Fig. 5.17b.
V I V I V I V I
a) b) c) d)
Fig. 5.17. a) Voltage 2QSW, b) Current 2QSW, c) Antiparallel connection of two voltage 2QSW, d) Antiseries
connection of two current 2QSW
It should be stressed, however, that because of the MOSFET being a representative

of majority carrier devices and because of its internal antiparallel body diode, there is a
possibility of conduction of currents with both directions through the MOSFET’s single
type semiconductor channel. This makes the MOSFET itself a current 2QSW. MOSFET
voltage 2QSW can be obtained by adding a series diode, thus effectively blocking one
possible current direction.
Four quadrant switch (4QSW) or a fully bidirectional switch is constructed by antipar-
allel connection of two voltage 2QSWs as depicted in Fig. 5.17c, or by antiseries connection
of two current 2QSWs as depicted in Fig. 5.17d. In the cases where the 4QSW consists
of two anti-parallel voltage 2QSWs, the current paths for different current directions are
clearly separated, and each of the current directions can be separately controlled. This
feature is not so obvious for the 4QSW consisting of two current 2QSW, where these two
cases are distinguished:
• Both current paths are closing through the same element (for ex. MOSFET), so without
measuring the current sign one cannot determine the zero-crossing point to block a
certain current direction by turning off the element completely, or
• Both current paths are clearly separated, but one path is closing through a passive,
uncontrollable semiconductor element (diode), thus resulting in possible blocking of
only one distinctive current direction.
A way to control the current direction of a 4QSW consisting of two current 2QSW
emerges only after combining the two 2QSW together.
In SICAMs, bidirectional switches (4QSW) are required in the output stage of the HF-
link audio power amplifier. As mentioned earlier, these are capable of blocking voltages
with both polarities and conducting currents in both directions. Turning to practical
implementation, except for the JFET being a single bidirectional component shown in
Fig. 5.18d, all other bidirectional switches are comprised of few discrete components -
diodes and, for example, MOSFETs:
• Four diodes and a MOSFET in a bridge configuration, shown in Fig. 5.18a. This
arrangement requires a single MOSFET and has just a single isolated gate drive, but
necessitates 4 discrete diodes. There are always two diodes and a MOSFET in the
load current path, which creates significant conduction losses. There is no possibility
of controlling the load current direction.
• Two diodes and two MOSFET in a configuration with separate load current paths,
shown in Fig. 5.18b. This arrangement requires two MOSFETs with two isolated gate
drives, but necessitates just two discrete diodes. There is always a diode and a MOSFET
in the load current path. Load current direction can be controlled by switching on and
off the corresponding MOSFETs, since this 4QSW is antiparallel connection of two
voltage 2QSW.
• Two MOSFETs in a back-to-back i.e. common-source connection, shown in Fig. 5.18c
with or without two discrete diodes. This arrangement requires two MOSFETs with
a single isolated gate drive and if MOSFET body diodes are not good enough, two
discrete diodes. Load current path can pass through the conductive channels of both
MOSFETS, or if the voltage drop in the channel is excessive, the load current can
divert into one of the body diodes or outer discrete diodes. Load current direction can
be controlled by switching on and off the corresponding MOSFETs.
The selection of a MOSFET as an active switching element in audio power amplifiers
is due to its very high switching speed, pleasant switching characteristics as a result
of the MOSFET being majority carrier device (no minority space charge and thus no
tailing current), ease of control through the isolated gate, positive thermal coefficient
which helps paralleling of MOSFETs, as well as low conduction losses in the conductive
semiconductor channel. At the same time the diodes must be of the ultra-fast type, due
to the high switching frequency of the proposed audio power amplifiers.
For audio power amplifiers, the common-source arrangement in Fig. 5.18c without
discrete diodes seems to be the best choice from simplicity and cost/performance ratio
perspective. By wisely choosing the MOSFETs in this arrangement, load current can be
predominantly passed through the MOSFET channel and not through the body diodes,
which guarantees very good efficiency, low conduction losses and low distortion (caused
usually by body diode conduction at higher load current levels). However, going into
extremes is by no means advantageous, since choosing a large die MOSFETs, which even
at full load current have voltage drops much smaller than the body diode voltage drop,
will certainly reduce the conduction losses but will inevitably increase the switching losses
due to the much slower switching characteristics.
D1 D3 D1 D2
D1 T2
T1 J
T1 D2
D2 D4
T1 T2
a) b) c) d)
Fig. 5.18. Different arrangements of bidirectional switches (4QSW)
Another emerging technology is the power JFET, which is rather appealing since it
is a single bidirectional component with potentially very small conduction losses. Unlike
the bidirectional switches in Fig. 5.18b,c, JFET has no possibility of controlling the load
current direction and the safe-commutation switching strategies from Section 6.2.1 are
not applicable. Due to its normally-on characteristics and the existence of either rather
low breakdown voltage JFETs [55] or emerging very high voltage SiC devices [56], [57], it
has still a limited usage in the common power conversion topologies and is predominantly
used as a solid-state switch in different battery powered device. As the breakdown volt-
ages increase, it will certainly become an interesting alternative for building bidirectional
switches, but only in certain type of isolated SICAM applications where load voltage
clamps are used for commutating the load current.
The conduction performance of all 4QSWs in Fig. 5.18 in terms of audio was tested
using a linear amplifier and by measuring the corresponding THD+N before and after the
switch. The simplified diagram of the test bench is shown in Fig. 5.19, while the results are
shown in Figs. 5.20-5.23. MOSFETs used were International Rectifier’s IRF520N, discrete
diodes were On Semiconductor’s MUR820 and JFET was Lovoltech’s LD1107N.
THDN1 THDN2
Cin
Vps +
4QSW
LinAmp R
Fig. 5.19. Test bench for bidirectional switches (4QSW)
From the measured THD+N in Figs. 5.20-5.23 of the bidirectional switches in Fig. 5.18
with sinusoidal input voltage it can be concluded that the common source connection of
two MOSFETs and the single JFET 4QSW have the best prospects for audio applica-
tions, since their internal structure assures that the semiconductive medium for the largest
range of output voltages exhibits resistive characteristics. This means that when reproduc-
ing sinusoidal reference with certain frequency, the voltage drop across the on-resistance
RDS,on of the aforementioned switches will consist only of the fundamental component,
Fig. 5.20. THD+N as function of power at 1 kHz Fig. 5.21. THD+N as function of power at 1 kHz
for 4QSW with one MOSFET and four diodes in for 4QSW with two MOSFETs and two diodes in
Fig. 5.18a measured before (bottom) and after (top) Fig. 5.18b measured before (bottom) and after (top)
the 4QSW the 4QSW
Fig. 5.22. THD+N as function of power at 1 kHz Fig. 5.23. THD+N as function of power at 1 kHz
for 4QSW with two common-source connected MOS- for 4QSW with just a single Junction FET shown in
FETs in Fig. 5.18c measured before (bottom) and af- Fig. 5.18d measured before (bottom) and after (top)
ter (top) the 4QSW the 4QSW
which although decreases the fundamental of the output voltage does not severely affect
the overall THD+N.
In the cases of the single MOSFET and four diodes 4QSW or the two MOSFETs
and two diodes 4QSW with separate current paths there are always one or two diodes
in the current path. This leads to crossover distortion around 0 V with sinusoidal input
voltages because of the threshold voltage of the diode VD,th > 0 below which the diode
is not conducting. On the other hand, during conduction the diode voltage drops are
significantly nonlinear because of the nonlinear output characteristic of the diode, which
can be only approximately modelled by its dynamic resistance RD . These two effects cause
tremendous audio distortion which is visible in the measurements.
A very good review of the bidirectional switch implementation and safe commutation
is given in [30], with some subsequent modifications and improvements presented in [34],
[58], [59].
5.5.2 Gate drives for bidirectional switches
Pulse transformers for bidirectional switch gate drive
Pulse transformers are very often used for gate drive in either unipolar or bidirectional
switches. They are very simple and reliable, have small form factors and provide both
isolation and voltage level adjustment. Their speed of response is very fast and they have
high bandwidth, but their performance deteriorates in presence of leakage inductance,
which limits the rise time of the gate current.
In order to avoid DC-bias of the magnetic core, pulse transformers are usually driven
from unipolar, single-ended logic with a series DC-voltage blocking capacitor, or with a
symmetrical, bipolar gate drive. Pulse transformers are best suited for driving MOSFETs
with nearly constant or slowly varying duty cycles, which leave enough time for the tran-
sient processes in the DC-blocking capacitor to elapse without disturbing too much the
on- and off-gate voltage levels.
Generally speaking, with bidirectional switches there is no need for high level of safety
isolation, since pulse transformers perform mere voltage level shifting and generally do
not cross the mains isolation barrier. Therefore, pulse transformer can be wound with
bifilar wire to minimize the leakage inductance, as long as the turns ratio is 1:1, which is
not always the case. If there is a need for voltage level adjustment, like for example when
interfacing low voltage logic to power MOSFETs gate or when the gate voltage swing on
the primary side is reduced due to the presence of DC-voltage blocking capacitor, higher
transfer ratios 1:n are inevitable and bifilar windings do not seem realizable.
When power transfer through the pulse transformer is limited and unsatisfactory be-
cause of the leakage inductance, a possible way for alleviating it is to use the pulse trans-
former for mere gate signal transfer, while the total MOSFET gate drive is provided by a
separate, low output impedance isolated power supply and gate drive circuitry referenced
to the MOSFET source. In this way the pulse transformer can be very small, since it is
allowed to saturate during normal operation and only the timing of the rising and falling
edges matters.
In some lower performance isolated gate drives for bidirectional switches, the pulse
transformer can be used for both gate signal and power transfer, but their speed of re-
sponse can be sluggish. Therefore, they do not seem interesting for the high switching
frequencies required by audio power amplifiers.
Optocouplers for transferring gate drive signals
Optocouplers provide very high level of isolation and rejection of common mode noise,
which makes the operation of the converter much more reliable. However, they require
separate isolated power supply referenced to the MOSFET source for providing the gate
drive of the bidirectional switch, since they perform only level shifting. However, audio
power amplifiers use very high switching frequencies and therefore those optocouplers
commonly found in the error feedback of the isolated off-line SMPS cannot be used in most
of the cases. Instead, some of the faster optocouplers for telecommunication applications
are better suited, but their price is also somewhat higher.
New level shifter for bidirectional switch gate drive
Level shifters are often used in the high-side drivers of half-bridge and full-bridge topolo-
gies to transfer the signals to the higher voltage level associated with the upper MOSFET.
Gate drive power is usually obtained from a boost capacitor being charged during the con-
duction of the lower MOSFET or with some type of charge pump. However, these level
shifters are only intended for operation on positive voltages, i.e. every excessive voltage
spike below ground on the source pin of the upper MOSFET can lead to latch-up or
destruction of the driver IC.
The conventional grounding scheme of the single-ended HF-link converter is shown in
Fig. 5.24a, where the center tap of the transformer and one load terminal are grounded.
In this case, it is assumed that two isolated power supplies and gate drivers are present
and their corresponding ground points are connected to the MOSFET common-source
points of the two bidirectional switches. Voltages at the common source points of both
bidirectional switches T21 − T22 and T23 − T24 with respect to ground can be both positive
and negative, depending on the transformer voltage polarity and bidirectional switch gate
voltage. The grounding point is common for both the power amplifier and control section.
This, however, prohibits using a conventional high-side level shifter for transferring the
gate signal to the gate driver of each bidirectional switch, for the reasons of logic latch-up
or possible driver destruction mentioned in the last paragraph.
With the newly proposed grounding scheme for HF-link converters in Fig. 5.24a, level
shifting is made easier because the common-source point of both bidirectional switches
can have only negative voltages. If positive voltage is applied across the bidirectional
switch, the body diode of either T22 or T24 will immediately clamp it to the ground, while
the body diodes of T21 and T23 will block it.
D21 D22 D21 D22
+ T21 T22 + T21 T22

vHF vHF
TR TR
. . LF
. . LF
. .
+ +
vHF CF vHF CF
T23 T24 T23 T24
D23 D24 D23 D24
a) b)
Fig. 5.24. a) Conventional grounding scheme for HF-link converters and b) Newly proposed grounding scheme
for easy level shifting
New negative voltage-tolerant level shifter and gate driver is depicted in Fig. 5.25. The
heart of the level shifter is the P-type MOSFET T1 , which works together with the active
pull-down resistive divider R1 − R2 to turn on and off the bidirectional switch T23 − T24 .
BJTs T2 and T3 form the gate driver, which is supplied by an isolated power supply with
voltage VISP . Together with the control biasing voltage VCC and the power amplifier, they
all share the same ground connection.
Capacitor CF B forms a positive feedback around the gate driver that helps turning-off
the bidirectional switch, which is troublesome because of the parasitic capacitance of the
P-type MOSFET T1 . Problem is pronounced when the parasitic capacitance CDS is being
charged after bidirectional switch turn-off with negative HF-link voltage vHF < 0, which
causes capacitive current to flow through the resistive divider R1 − R2 and immediately
turn-on again the bidirectional switch.
5.6 Other possible approaches for isolated SICAMs

Some of the other possible approaches for isolated SICAMs include resonant primary
stages, where HF-link voltage has sinusoidal or nearly sinusoidal form. Due to the si-
nusoidal shape of the voltages and currents, these input stages are known to have low
ElectroMagnetic Interference (EMI) and low switching losses, as a result of the zero-
voltage switching (ZVS) and/or zero-current switching (ZCS). As another advantage of
the sinusoidal output voltage of the resonant input stage, zero voltage or near zero voltage
intervals become longer and it is much easier to commutate the load current between the
5.7 Patent investigation 125
.
VIPS
Level shifter and
gate driver TR
.
.
vHF +
VCC T2
CFB T23 D23

R1 RG
VGD
T24 D24 LF
T1
R2 CF
D1
T3
GNDISP
GNDCC GND
Fig. 5.25. Negative voltage-tolerant level shifter and gate driver
outgoing and incoming bidirectional switches in the SICAM output stage by shortly over-
lapping their conduction. This makes the resonant power supplies and resonant SICAM
input stages very interesting for high switching frequency operation.
On the other hand, resonant power converters are characterized with higher output
impedance, which makes their operation especially load dependent. This can represent a
problem when the load of the resonant input stage consists of a bidirectional output stage
performing full-bandwidth audio power amplification, since the dynamics of the load is
tremendous. And even more, by avoiding rectification on the secondary side load current
is allowed to flow both in and out of the resonant tank, which significantly perturbs the
resonant tank voltage. Control of resonant tank voltage is also challenging, since it asks
for either variable frequency operation or using phase shifted PWM in full-bridge input
stages. Some of the other problems include reduced efficiency of the resonant input stage
in case of reactive current flow, which circulates between the elements of the resonant
tank and causes losses in the switches without ever flowing to the load. Latter can be
alleviated by carefully choosing the resonant tank topology (series L − C, parallel L − C,
series-parallel L − Cp − Cs ).
Although resonant converters are used in many advanced applications and are known
technology, it was decided for the SICAM project to proceed with the hard switched power
converters. However, a short review of some resonant converter topologies for input stage
in isolated SICAMs will be given in Section 6.1.3.
5.7 Patent investigation

This section will review some of the patents in the field of isolated SICAMs for different
applications, i.e. some protected general principles for isolated DC-AC conversion in a
single stage.
Patent [2] is one of the earliest patents which deals with the so called ”Phase demodu-
lated high frequency bridge inverter” and is dated before probably the first published
scientific paper on HF-link conversion [47]. It belongs to the group of SICAMs with
non-modulated transformer voltages, where HF-link voltage has symmetrical rectangu-
lar waveform with 50% of duty cycle and no intervals with zero output voltage. Its block
diagram is shown in Fig. 5.26. Bidirectional switches in the output stage are constructed
from 4 diodes and single bipolar switch in full-bridge configuration, but no information
can be found about the way load current commutates between the switches belonging to
the same leg, except that they are driven in complementary way one immediately after the
other. Switching instants of the secondary side 4QSWs is found by phase-shifted PWM
using two PWM modulators fed with the same externally created sawtooth carrier as first
input and the reference signal or its inverse as second input correspondingly to drive each
of the switching legs.
The inventor in [3] proposes the arrangement in Fig. 5.27, which is very similar to
the previous one in the topology, but it differs a lot in the control principle since it is
SICAM with modulated transformer voltages. The HF-link voltage is three-level PWM
according to the reference voltage, but the LF content from the audio waveform is recov-
ered by inverting each second pulse from the PWM pulse train, as already explained in
Section 5.3.4. A simple push-pull input stage used on the primary side in general does not
always guarantee a 3-level PWM transformer voltage, because in HF-link converters the
reflected load current on the primary side during the dead time intervals of the input stage
will cause the input stage freewheeling diodes to conduct and clamp transformer voltage
to either polarity of the DC supply voltage. However, in this specific case, turning all
the bidirectional switches on in the full-bridge output stage during the input stage dead
time intervals is used to restrict the load current from flowing through the transformer by
freewheeling it in the output stage, thus the voltage across the transformer is supposed
to collapse to zero. This is, however, likely to be troublesome due to, firstly, the magneti-
zation current flowing in the transformer primary and the stored magnetic energy in the
leakage inductance, which is going to cause reversal of transformer voltage polarity and
conduction of one of the input stage antiparallel diodes immediately after switching off the
opposite primary switch. Secondly, the same moment when one of the primary switches
which conducted the load current is switched off there will be immediate commutation of
the load current into one of the input stage freewheeling diodes, depending on the load
current direction, and the DC supply voltage with certain polarity will be applied across
the transformer, so it is not clear how all four 4QSWs in the output stage will be turned
on at the same time to freewheel the whole load current entirely in the output stage.
Fig. 5.26. Circuit diagram from [2] Fig. 5.27. Circuit diagram from [3]
Patent application [4] is similar to the previous one in both the topology and control
principle, and it introduces a full-bridge 3-level PWM switching inverter on the primary
side to alleviate the aforementioned problems, as depicted in Fig. 5.28. Beside the pure
PWM, this patent also proposes Pulse Amplitude Modulation (PAM) by holding the width
and the frequency of the pulses the same and just switching between different taps on the
secondary winding of the transformer to change the amplitude of the applied voltage.
Inventors in [5] propose a ”Phase modulated switchmode power amplifier and waveform
generator” where both the input and the output stage are operated with full duty cycles,
and the recovery of the audio signal across the load is obtained by phase shifting the
switching of the output stage bidirectional switches with respect to the primary-side
inverter. Thus this solution, shown in Fig. 5.29, belongs to the group of SICAMs with
non-modulated transformer voltages, but the switching frequencies of both stages must
be equal. In one of the proposed embodiments, the input stage is made resonant, so that
the HF-link voltage has sinusoidal nature and therefore short zero voltage intervals for
performing output stage load current commutation. However, it is not clear how safe
load current commutation will be performed in the other half of switching instants where
transformer voltage is different than zero, and especially in the hard switched case.
Patent [6] proposes a redundant system with two low-pass output filters for reconstruct-
ing the audio signal, illustrated in Fig. 5.30, where the one operates only with positive
voltages and the other one only with negative voltages. The switching output stage then
connects directly the load terminals to the one or the other output filter, according to the
desired polarity of the output voltage. The switching of the polarity selecting switches
occurs only at zero output voltage, which significantly reduces switching losses and is
certainly beneficial from load current commutation perspective, but it is not clear how
alternatively loading and unloading the LC low-pass filters will affect the reliability of
the amplifier without any passive damping networks to reduce the presumably very high
quality factor Q of the filter.
The inventor of [7] presents a ”Power conversion system” which is in fact a SICAM
with modulated transformer voltages and is shown in Fig. 5.31. The operation of the
topology with GTOs in the output stage is explained in detail together with the control
principle, although it is mentioned that depending on the application other switch types
can be used. What essentially happens in the output stage is that by having turned on
both the outgoing and the incoming switch, the short circuit current flowing through the
secondary winding of the transformer and limited by its leakage inductance will perform
commutation of the load current to the incoming GTO switch and the outgoing GTO
switch will seize conducting naturally. When using MOSFET in the output stage this
particular solution cannot be applied to commutate the load current, because the short
circuit current can flow and increase in either direction, but there are still some periods
with zero transformer voltage which can be used for that purpose.
Patent [8] refers to ”Synchronous modulation circuit” of an isolated SICAM with non-
modulated transformer voltages shown in Fig. 5.32, where based on the HF-link voltage
polarity the PWM modulator determines the correct gate driving signals for the bidirec-
tional switches. Unfortunately, nothing is mentioned about the way 4QSW in the output
stage need to be operated in order to avoid short-circuiting of the transformer secondary
and still provide an uninterrupted path for the load current.
Inventor in [9] shows a similar invention like the phase-modulated SICAM from [5],
but now the problem of the load current commutation is solved by using a dissipative RC
clamp with rectifier diodes shown in Fig. 5.33 and connected both before and after the
switches, thus appropriately handling the stored magnetic energy in both the transformer
leakage inductance and output filter during the short dead-time intervals.
Patent [10] proposes ”Reduction of switching losses in phase-modulated switch-mode

amplifier” shown in Fig 5.34 and similar to the one presented in [5], referring to SICAMs
with modulated transformer voltages by inserting intervals with zero voltage in the trans-
former waveform, effectively using the 3-level PWM capability of a full-bridge input stage.
Patent [11] proposes a new Class N of simple and low component count audio power am-
plifiers with direct energy conversion in Fig 5.35, i.e. SICAMs with modulated transformer
voltages, which are being subsequently synchronously demodulated on the secondary side.
However, it is very difficult to avoid the impression that this simplicity is achieved on be-
half of less flexibility and reliability. In all embodiments with a single switch input stage, it
is clear that primary current can be conducted just in the direction of the antiparallel body
diode. Since in SICAMs there is no intermediate energy storage on the secondary side,
the load current with single-ended output stages must be reflected to the primary side,
but this might not be possible for one direction of the reflected current. This problem is
alleviated with some of the full bridge-type embodiments of output stages, where the load
current can be freewheeled in the output stage during the off-time of the primary switch.
Another significant drawback is that the resetting of the magnetic core with single-switch
topologies necessitates separate demagnetization winding or using two-switch topologies,
but this limits the effective duty cycle to around 50%. As a side effect, for the same out-
put power the secondary-side voltage must be around two times higher, which increases
the stress exerted on the output stage switches and dictates use of switches with higher
blocking voltage and higher on-resistance. Even in the cases when push-pull, half-bridge
or full-bridge is used in the input stage, their control is such that just one switch or set
of switches is operated on and off for certain polarity of the output voltage, which means
that the transformer polarity during the corresponding off-time will depend on the direc-
tion of the freewheeling reflected load current, which can lead to severe saturation of the
magnetic core.
The inventor of [12] proposes the system shown in Fig. 5.36 which represents SICAM
with 3-level phase-modulated PWM transformer voltage, which has intervals with zero
transformer voltage used for commutating the load current in the output stage by shortly
overlapping the conduction of two bidirectional switches. In the implementation of the
switching sequence it is very similar to [5] and [10].
Fig. 5.36. Circuit diagram from [12]

5.8 Conclusion
There are many different approaches to creating isolated SICAMs, and despite of the
minor differences between them, they can be all roughly divided into two groups: isolated
SICAMs with modulated transformer voltages and isolated SICAMs with non-modulated
transformer voltages.
It was shown that while SICAMs with 3-level PWM modulated transformer voltages
and zero voltage intervals have the advantage of alleviating the problem of load current
commutation in the output stage through overlapping the conduction of the bidirectional
switches during those intervals, they are not economically feasible for multi-channel audio
systems and have some practical implementation drawbacks.
On the other hand, SICAMs with 2-level non-modulated transformer voltages have the
advantage of reusing the primary stage and transformer in multi-channel audio systems
and alleviate the construction of additional auxiliary power supplies, but are unfortunately
characterized by troublesome commutation of the load current between the outgoing and
incoming bidirectional switch in the output stage. The topologies and control methods
which will be presented in the next two chapters will concentrate almost entirely on solving
the aforementioned load current commutation problem in SICAMs with non-modulated
transformer voltages.
In this chapter several possible arrangements of bidirectional switches were presented.
They all have distinct advantages and drawbacks, but it was shown that the 4QSW with
common-source connection of two MOSFETs is the preferred one for audio applications,
since it necessitates just two discrete components and a single isolated power supply for
the gate drive, while at the same time providing low distortion and almost linear and
purely resistive behavior at lower output levels. Even more, with a special load grounding
technique, a simple level shifter and driver can be constructed for driving the bidirectional
switches without need for expensive transformers and optocouplers.
Most of the patents in the field of HF-link converters describe isolated SICAMs with
modulated transformer voltages, which are not very appropriate for audio applications,
especially not for multichannel audio. Just few of them propose isolated SICAMs with
non-modulated voltages, but in most of the cases the commutation of the load current
in the output stage is not handled appropriately or leads to large amount of power loss.
Therefore it is believed that there is still space for improvements in the field of HF-link
conversion, as it will be shown in the following chapters.
6
Topologies for isolated SICAMs
”God does not care about our mathematical difficulties.
He integrates empirically.”
- Albert Einstein
It was already shown in Chapter 5 that the only economically feasible isolated SICAM is
the one with switching stages on both the primary and the secondary side, separated by
HF-link transformer. In this case, special modulation techniques can be used so that the
HF-link transformer does not ”see” the LF content of the audio signal to be amplified and
thus its size is decreased. It was also shown that from a multi-channel audio perspective,
as well as some already mentioned practical considerations, the SICAM approach with
non-modulated transformer voltages is advantageous.
In this chapter, main focus will be on the topologies for isolated SICAMs with non-
modulated transformer voltages. The input stage and the output stage will be dealt with
separately, but bearing in mind that they are to be dedicated one to another and connected
with an isolation transformer as HF-link.
6.1 Input stage

6.1.1 Introduction
The input stage of the isolated DC-AC SICAM shown in Fig. 5.2 should accept the
electrical energy from the grid in a form of DC voltage from a simple AC-DC power supply
(mains rectifier and storage capacitor) and transfer it through the isolation barrier, i.e.
over the HF transformer. Since in the class of DC-AC SICAMs discussed in this chapter
audio reference is not used in any way to modulate the transformer voltages, the input
stage only role is to transfer the energy received from the power supply to the secondary
side according to the output stage demands and this is what solely limits the possible
output voltage waveform.
Turning to magnetics basics and Faraday and Ampere laws, it is known that magnetic
energy can be stored in a piece of magnetic material by applying DC or AC electrical
current through an excitation coil wound around the magnetic core, called also primary
winding. It is assumed that beside the excitation winding, one or more windings are
situated on the same core too. Although the character of the current through the excitation
coil used for energy transfer can be freely selected, one should be aware that even in the
case of DC current, energy is impressed into the magnetic core during the transient process
of magnetization, which is actually characterized with variable voltages across the coil.
When the transient process has ended, in the DC steady-state situation no voltages are
induced in either the excitation winding or the rest of the windings. The internal magnetic
flux build-up Φ of the magnetic core is determined by the time integral of the induced
voltage vi :
1 t
Z
Φ= vi (τ )dτ (6.1)
N 0
132 6 Topologies for isolated SICAMs
where N is the number of turns of the excitation coil.

In the case of the electrical energy transfer through a HF isolation transformer with
two windings - primary and secondary, there is no need for storing energy in the magnetic
core, but rather transferring it over. This means that there is no need for air gaps in the
magnetic core in order to reduce the magnetization inductance and increase the stored
energy associated with it. So, a symmetrical AC voltage waveform v1 should be applied
across the transformer primary winding during one switching period Ts to cause magnetic
flux Φ reset at the end of each complete switching action of the input stage:
Z Ts
1
Φ= v1 (τ )dτ = 0 (6.2)
N1 0
where N1 is the number of turns of the primary winding.
The magnetic flux swing in the common magnetic core will induce voltage v2 across
the secondary winding, given by:
dΦ
v2 = N2 (6.3)
dt
where N2 is the number of turns of the secondary winding.
When an operational output stage is connected to the transformer secondary winding,
induced voltage will cause a current through it, in that way closing the cycle of energy
transfer through the transformer. Although this discussion may seem notorious, it leads
to an important conclusion. In this class of isolated DC-AC SICAMs, there is no known
limitation on the waveform of the AC voltage applied across the transformer primary
winding by the input stage, except for it being symmetrical, or at least having an average
value of zero during one switching cycle Ts to allow for magnetic core flux reset:
1 Ts
Z
v1,av = v1 (τ )dτ = 0 (6.4)
Ts 0
It can be, however, noted that a designer should prefer transformer waveforms which
transfer the same power with lowest peak voltage values, in this way reducing the stress on
the switches in the subsequent output stage. This means that flat rectangular waveforms
are preferred over some odd-shape waveforms with very high crest factors, except for the
cases where these waveforms have other advantages, like Zero Voltage Switching (ZVS)
or Zero Current Switching (ZCS) and reducing EMI with resonant converters.
If it is difficult to conclude about the shape of the applied primary voltage waveform, its
frequency can be certainly discussed. It is widely recognized that, regarding the magnetic
design, the switching frequency i.e. the frequency of the applied AC voltage waveform
should be increased in order to decrease the magnetic flux swing Φ (6.1) and the corre-
sponding magnetic induction swing B, which leads to smaller magnetic components and
cheaper designs. Limiting factor for the switching frequency is in the way the energy losses
are created in the combination of the input stage and the HF transformer.
As far as this basic magnetic transformer overview is concerned, it may seem that the
energy transfer is lossless. However, this is not the case, since losses are created in the
transformer magnetic core as hysteresis losses and eddy-current losses, as well as in the
windings as DC conduction losses and AC skin and proximity effects. These losses are not
constant, but they are strongly dependent and increase with the frequency and magnitude
of the voltages and currents applied to the windings, which will define the magnetic flux
levels. The applied primary voltage waveform is created by the switching action of the
switches in the input stage, which also represents a lossy process even when no load
6.1 Input stage 133
current, except the transformer magnetization current is flowing through them. These
are the so called switching losses, which are predominantly dependent on the MOSFET
parasitic components, frequency of the switching as well as on the magnitude levels of the
conducted current being switched and reverse voltage being blocked. On the other hand,
conduction losses of the saturated switches are dependent on the components internal
resistance and conducted currents, and are therefore frequency independent. Eventually, it
is concluded that the switching frequency selection of the input stage should be approached
very cautiously, and a suitable optimization method should be developed to determine
the best operating point of the compound ”input stage+transformer” which is capable of
delivering the necessary power to the output stage with minimal losses and at the same
time keeping the input stage volume and cost low.
Another important factor when discussing the input stage is the audio performance
of the output stage. Although not obvious at this point, the switching frequency of the
input stage will affect the performance of the audio amplifying output section in terms
of generated HF voltage switching harmonics, since there is no noise decoupling through
the conventional DC-bus capacitors. This will primarily depend on the type of the control
scheme used to operate the input and the output stage, but in general terms some level
of synchronized operation is preferred. This, in turn, will set a limit on the possible set of
input stage switching frequencies. In another PWM method for HF-link converters to be
presented later, the frequency of the HF-link also appears as a frequency of the output
voltage ripple. Therefore, the switching frequency of the input stage should be high enough
not to interfere with the control structure of the output stage, and to be far away from
the baseband of interest. Otherwise, audio performance deterioration should be expected
or even instability can be induced by severe switching within the output stage closed-loop
control bandwidth.
6.1.2 Topologies for the input stage
It is certainly advantageous to create an input stage which would operate with higher
switching frequencies (hundreds of kiloHertz), leading to smaller HF transformer and
EMI filter on the mains side, and at the same time having low losses, thus improving
the efficiency of the overall SICAM. Taking a look at the input stage only, an important
limiting factor are the switching losses, which can become especially severe when con-
sidering the magnitude of the DC voltage rectified directly from the mains. Therefore,
special attention should be payed to those topologies or control strategies which can pro-
vide lower switching losses on expense of minor extra cost or extra control effort. On the
other hand, hard-switched inverter topologies with advanced switching components can
provide a simple and reliable solution with comparable performance.
Following topologies were found interesting for further research:
• Resonant converters: series, parallel or series-parallel (LCC) - especially popular for
high frequency and lower power converters, offering very low switching losses and sinu-
soidal output waveforms with low THD and EMI, but lack of suitable design techniques
as well as some application-specific drawbacks make them a less preferable choice,
• Soft-switched ZVS PWM inverters with an emphasis on phase-shift control - an
extension to the classical full-bridge PWM converters which can provide near zero
switching losses (ZVS) for a wide range of load currents, only with minor changes in
the control algorithm and possible addition of capacitors and inductor, and
• Hard-switched PWM inverters found in many conventional SMPS for commercial
applications.
6.1.3 Resonant converter as input stage

When compared to the ”classical” class D audio power amplifiers, the unrestricted SICAM
structure itself should provide topological means for lowering the losses and improving
efficiency. That is why the resonant converters, which are known for their energy efficiency
and compact design at high switching frequencies, appear to be an interesting alternative
to investigate for an input stage. Associated voltage and current waveforms are almost
purely sinusoidal, so it is possible to use a train of this sinusoidal voltage pulses in the
output stage to construct the desired audio output voltage using PDM or to create larger
pulses with variable width to resemble traditional PWM.
Resonant converters can be found in several different topologies, depending on the
topology of the switches or the resonant tank structure. Apart from resonant-switch con-
verters, which are not investigated herein, the most popular switching topologies for res-
onant converters are class E, class D, half-bridge and full-bridge [13]:
• Class E resonant converters comprise of only one active switch, but its high volt-
age and current stress (peak switch voltage Usw,p ≈ 3.5Vd and peak voltage current
Isw,p ≈ 3Id ) severely aggravate the practical implementation, especially when the con-
verter is supposed to switch the DC input voltage rectified directly from the AC mains.
• Class D i.e. totem pole resonant converter combines lower voltage and current stress
with low component count - only one switch more than the class E resonant converter.
• Half-bridge and full-bridge resonant converter topologies also have lower component
stress like the Class D resonant converter, but the component count increases.
Due to the aforementioned advantages, Class D resonant switching converter is pre-
ferred over all of the other resonant approaches.
In the basic resonant converters, the resonant tank can consist from: series LC in
Fig. 6.1a, parallel LC in Fig. 6.1b and series-parallel LCC in Fig. 6.1c.
However, some problems associated with the implementation of resonant converters
appear right away. For example, a lack of suitable ”engineering” time-domain design
methods for exact representation of resonant converter waveforms leads to using approx-
imate frequency-domain methods [60], [61], [62], [63], [64], i.e. sinusoidal analysis at the
dominant frequency, depending on the excited modes of the resonant tank by the switch-
ing action of the converter itself. Time-domain approaches [65], [66] are found to be too
complex, offering accuracy and flexibility (both continuous and discontinuous conduction
modes of the resonant converter) which is for most of the times actually not needed.
Beside the analysis problem, some technical and performance problems were found
even more restrictive and this will be explained in detail in few subsections, regarding the
corresponding resonant converter topology.
It should be emphasized, however, that all of the authors of resonant converter ref-
erences found in the literature were using resonant converters in rectification schemes,
so there is actually little reference [67] to resonant converters used in combination with
subsequent bidirectional bridge or cycloconverter for creating AC waveforms.
Series resonant converter (SRC)

In the SRC shown in Fig. 6.1a, both resonant elements L, Cs are in series with the load.
This has an advantage of having a DC blocking capacitor in series with the HF trans-
former, thus successfully avoiding any DC saturation. The efficiency at idle is very high,
since there can be no circular current through the resonant tank at no load. SRC can only
step down the output voltage, which for a converter operated from rectified AC mains
voltage is not a disadvantage, since the desired output voltage will be always lower.
6.1 Input stage 135
T1 D1
L Cs
+ TR
Vd
T2 D2
a)
T1 D1
L
+ TR
Vd
Cp
T2 D2
b)
T1 D1
L Cs
+ TR
Vd
Cp
T2 D2
c)
Fig. 6.1. Class D resonant converter types: a) series LC, b) parallel LC and c) series-parallel LCC
The main disadvantages are caused by the same elements, which were regarded as the
major benefit of the topology. When reconsidering higher power levels and higher ripple
load currents, the series capacitor Cs can become bulky, thus compromising the light
design of the SICAM. Output voltage control at lighter loads is problematic, so a wide
range of switching frequencies is required in order to compensate for small load variations.
When operating near the resonant frequency fs ≈ fr , output short circuit can result in
huge overvoltages because of the undamped resonant tank, so a fast control loop is a
necessity.
Parallel resonant converter (PRC)

In the PRC shown in Fig. 6.1b, the capacitor Cp appears in parallel to the load. The
converter itself has a voltage step-up and voltage step-down properties, depending on the
switching frequency fs to resonant frequency fr ratio fs /fr , which is certainly an advantage
over the SRC. And even more: output voltage control with wide range of load variation is
achieved with smaller switching frequency adjustments. This means that even at light load,
output voltage control can be unaffected. Another important feature of PRC is that even
when operating at switching frequencies near the resonant frequency of the resonant tank
fs ≈ fr , output short circuit current is essentially limited by the inductor L impedance.
The major drawback of PRC is due to the circular currents flowing in the resonant
tank L, Cp even without any load applied, resulting in very low power efficiency at idle.
On the other hand, at light load the quality factor of the resonant tank Q rises, so fast
output voltage control must be used to avoid any possible overvoltages.
Series-parallel resonant converter (SPRC)
SPRC shown in Fig. 6.1c attempts to take advantage of the best features of SRC and PRC
and at the same time mitigate some of their drawbacks. That is why a Class D SPRC is a
resonant converter of choice for many rectifying HF applications [29], [63], [64], [65], [68],
[69], [70]. Therefore, a series-parallel LCC resonant converter was reconsidered for use in
an isolated DC-AC SICAM, instead of the simpler SRC and PRC.
From an analysis point of view, SPRC is desirable since all the transformer parasitics
can be suitably incorporated in the calculations by moving all the transformer leakage
inductance to the primary and adding it to the inductor L and at the same time moving
the parasitic winding capacitance to the secondary side and adding it to the capacitor Cp .
Characteristics of resonant converters when used in a SICAM
It is clear that the use of any resonant converter in an isolated DC-AC SICAM is far
more demanding than the use of latter in a rectifier. Using a bidirectional bridge in the
output stage, loaded with an output low pass filter and a loudspeaker essentially emerges
as a widely and rapidly varying load, depending on the audio reference. One important
example is the use of 2-level or 3-level PWM [14]. When using 2-level modulation, the
combination of output filter and loudspeaker is always connected to the both ends of
the resonant converter, thus resulting in higher no-load losses, but the resonant tank is
never unloaded. The case of 3-level modulation is shown in Fig. 6.2, where a series-parallel
LCC resonant converter is loaded with bidirectional full-bridge amplifier, just to get rid
of these losses, but on expense of introducing some common-mode noise. The direction
of the load current is the same in all of the depicted cases. In the ”normal” case, current
is being delivered from the resonant tank to the load, like when switches S1 − S4 are
turned on. Sometimes the combination of the output filter and the loudspeaker will be
connected to the same upper or lower rail essentially unloading the resonant converter
and causing overvoltages on the parallel tank capacitor Cp , like when switches S1 − S3
are turned on. And even more, when returning the stored energy in the output filter and
load to the resonant converter through the output stage bidirectional bridge, like when
switches S2 − S4 are turned on, load current can charge the capacitors Cp , Cs to even
greater voltage values and also cause unexpected rise of output voltage. Latter voltage
variations happen at very short timescale and are very hard to compensate for, no matter
how fast the control loop is.
S2-S3
T1 D1
L Cs S1-S3
+ TR S1 S3
Vd Cp
T2 D2 S2 S4
S1-S4
Fig. 6.2. Series-parallel LCC resonant converter loaded with bidirectional full-bridge amplifier
In conclusion: the resonant converter load current can have any direction and magni-
tude sustained by the loudspeaker output low-pass filter and a bidirectional bridge state,
which from the resonant converter control perspective can not be predicted. Resonant
6.1 Input stage 137
tank components L, Cs , Cp cause the resonant converter to have high output impedance,
resulting in rapid output voltage perturbations which are strongly dependent on the vary-
ing load characteristics, i.e. on the switching action of the subsequent output stage. This
is a major drawback which makes the use of a resonant converter without fast output
voltage feedback control loop almost impossible to manage.
SPRC’s output impedance Zo (s) is obtained by short-circuiting the voltage source,
which essentially connects the series combination of L and Cs in parallel with Cp :
1
sCp
(sL + sC1 s ) s2 LCs + 1
Zo (s) = = (6.5)
sL + sC1 s + sC1 p s3 LCp Cs + sCs (1 + Cp
Cs
)
which is shown graphically for L = 11.6µH and Cs = Cp = 5.88nF in Fig. 6.3 and is
significant even at frequencies comparable to the switching frequency.
Resonant tank output impedance Zo(ω)

200
Magnitude [dBΩ]
100
−100
5
10
Angular frequency ω [rad/s]
Fig. 6.3. Output impedance of an SPRC for L = 11, 6µH and Cs = Cp = 5, 88nF
The following means for control of the resonant converter output voltage are feasible:
• Frequency control - widely used method for creating variable output voltage, due to
the frequency dependant output characteristics of the resonant converters; generally
this is not a desired solution since almost constant frequency operation is preferred to
guarantee the same performance of the input stage all over the possible operational
range and to obtain pulses with the same width or same area (Volt-seconds) for use in
PDM output stage,
• Duty cycle control - this type of control is reported in [29], but it fails to achieve the
desired performance, since for switching duty ratios different from D = 0.5 DC-offset is
introduced to the resonant tank input voltage, i.e. the totem pole switches start acting
as rectifiers with variable output voltage, and
• Phase control - introduced in [71]; consists of two phase-shifted PWM totem-poles
forming a class D inverter with the resonant tank and the HF transformer connected
in between the middle points of the poles or with two resonant tanks starting from the
poles and connecting the HF transformer to the ground.
When the method of frequency control is used upon some of the resonant converters,
the preferred working frequency is usually above the resonant frequency. By switching the
converter at a fixed frequency higher than the resonance point of the resonant tank, the
L − Cs − Cp combination appears as predominantly inductive load, causing the current to
lag the applied input voltage. Because of the load current conduction through the diode
antiparallel to the observed transistor whenever the opposite transistor switches off, ZVS
is obtained at turn-on. By applying small capacitor in parallel to the transistor, ZVS at
turn off can be achieved as well, due to the time needed for the load current to charge
this dummy capacitor. Therefore, operating the resonant converters above the resonant
frequency is superior in terms of switching losses and performance [61].
The method of phase control certainly looks appealing, since full control of the resonant
converter output voltage can be achieved by changing the amount of energy injected into
the resonant tank, and not actually changing the frequency of switching. However, this
is done on expense of additional totem pole with two active switches and still the large
output impedance of the resonant tank limits the performance of the input stage, making
it a less preferable choice for a SICAM.
6.1.4 Soft-switched ZVS PWM inverter as input stage

Introduction to ZVS PWM inverters
Decreasing the energy loss in the input stage of a SICAM is a desirable feature, so instead
of using a hard-switched PWM inverter a soft-switched ZVS PWM inverter can be im-
plemented [72], [73], [74]. It has completely the same structure as a hard-switched PWM
inverter, but the switching events are little bit altered. ZVS results in decreased switch-
ing losses, as well as reduced transistor voltage resonant ringing, which can be observed
during rapid hard switching. The principle of operation will be described using Fig. 6.4.
CDS1 CDS3 CDS1 CDS3

T1 D1 D3 T3 T1 D1 D3 T3
Vd
+
. Vd
+
.
CDS2 . CDS4 CDS2 . CDS4
T2 D2 D4 T4 T2 D2 D4 T4
a) b)
CDS1 CDS3 CDS1 CDS3

T1 D1 D3 T3 T1 D1 D3 T3
Vd
+
. Vd
+
.
T2 D2 D4 T4 T2 D2 D4 T4
c) d)
Fig. 6.4. ZVS PWM inverter: a) power delivered to the load, b) capacitance of T3 gets discharged, c) freewheeling
cycle and d) capacitance of T2 gets discharged
The main benefit of the ZVS PWM inverter results from the intentionally programmed
delay between the turn-off of one transistor and the turn-on of other transistor in a sin-
gle bridge leg. During this time, no transistor in that leg conducts, and the freewheeling
current sustained by the inductive nature of the load, the transformer magnetizing in-
ductance and the transformer leakage inductance discharges the drain-to-source parasitic
capacitance of one of the MOSFETs, and charges the other, allowing the ZVS. The phases
of one half-cycle of output voltage are shown in Fig. 6.4 and are described as follows:
6.1 Input stage 139
a. Diagonal transistors T1 and T4 are conducting, so power is delivered from the source
and through the transformer to the load. Drain-to-source capacitance CDS3 of T3 is
charged to +Vd and voltage across the drain-to-source capacitance CDS4 of T4 is almost
zero, i.e. CDS4 is discharged. Current flowing through the transistors consists from the
reflected load current (N2 /N1 )Iload and the magnetizing current Im .
b. T4 turns off, so the capacitance CDS4 gets charged and CDS3 gets discharged by the
primary current, raising the voltage of the middle point from 0V to +Vd . This action
continues until the body diode of T3 or external diode D3 turn on to clamp the voltage
across it to one voltage drop. Turn-off of transistor T4 is lossy, but adding an additional
small external capacitance across it can keep the voltage to near zero Volts until the
current through the MOSFET channel is completely switched off.
c. As soon as the voltage across T3 reaches zero volts, transistor T3 is turned on, producing
no switching loss, i.e. ZVS at turn-on occurs. Applied voltage across the transformer
is zero.
d. Transistor T1 is now turned off, so the primary current is now diverted into the parasitic
capacitances of T1 and T2 , charging the CDS1 and discharging the CDS2 . When the
voltage across T2 reaches zero volts, it will be turned on in a non-dissipative manner,
so a programmed delay must be provided for ZVS at turn-on to take place. Again, T1
turn-off is lossy and T2 turn-on is lossless.
It should be noted that the nature of ZVS of the two switching legs differs. In the right
one the primary current consists of the reflected load current and the magnetizing current,
while in the left one the dominant role in the ZVS is played by the energy stored in the
primary leakage inductance of the transformer, since load current is freewheeled by the
secondary side rectifiers, as described in [72].
This description corresponds to the case of switching only one leg at a time. Assuming
that before switching of one inverter leg, the voltage across the transformer primary
was equal to the DC bus voltage +Vd , then after the process of charge displace and
transistor turn-off has ended the primary voltage will be zero. This situation will last
until switching is performed in the second leg, resulting in reverse DC bus voltage −Vd
across the transformer primary. The output voltage average can be controlled by altering
the delay in switching the second leg, so the converter operated in this way is referred
as Phase-shift ZVS PWM inverter. The advantage of this approach is that only one
MOSFET is to be turned-off and only one to be turned-on, resulting in electrical charge
being displaced using the primary current between only these two parasitic drain-source
capacitances. Phase-shift ZVS PWM inverter output voltage v1 and associated switching
waveforms for T1 , T2 , T3 and T4 are shown in Fig. 6.5a.
When both legs are switched at the same time - simultaneously, the same action of
displacing the electrical charge between the MOSFET parasitic capacitances occurs. How-
ever, in this case instead of two, all of the MOSFET parasitic capacitances play a signifi-
cant role at the same time. Eventually, this leads to even higher demand for energy stored
in the transformer leakage and magnetizing inductances. Actually, the same switching
action occurs in classical PWM inverters using the dead time instead of the programmed
delay. Whenever both legs of the PWM inverter are switched simultaneously in a pre-
scribed way using previously calculated delays to facilitate the ZVS by the freewheeling
of the primary current, it will be referred as Simultaneous ZVS PWM inverter. Simul-
taneous ZVS PWM inverter output voltage v1 and associated switching waveforms for
T1 , T2 , T3 and T4 are shown in Fig. 6.5b.
At this point, a very important remark should be made. In the presently available
references [72], [73], [74], soft-switched ZVS PWM inverter is used in conjunction with a
v1 v1
T1 T1
T2 T2
T3 T3
T4 T4
a) b)
Fig. 6.5. ZVS PWM inverter output voltage v1 and switching waveforms: a) phase-shift ZVS PWM inverter and
b) simultaneous ZVS PWM inverter
rectifier on the secondary side, which results in a highly predictable primary and secondary
winding current direction. In this case, energy is always transferred from the source to
the secondary side rectifier. Reflected load current, as shown in Fig. 6.4 always helps the
magnetizing current to displace the charge between the MOSFETs output capacitances,
thus leading to ZVS at turn-on. As already mentioned in the description of the switching
process, MOSFET turn-off is still lossy except in the cases when small capacitive snubbers
are added in parallel to the MOSFETs.
When soft-switched ZVS PWM inverter is used with bidirectional bridge as an out-
put stage, rectifier diodes are removed, so the primary and secondary winding current
directions depend on the applied audio reference, as well as the load current direction
in the output low-pass filter prior to the switching instant. Now the energy transfer can
be in either direction, i.e. energy can be also regenerated from the load to the energy
storage capacitor on the primary side. This makes the analysis more complex, since the
primary current can be also in opposite direction from the magnetizing current, effectively
aggravating the ZVS at turn-on. In this limit case, when the load current reflected to the
transformer primary dominates over the magnetizing current causing total current in the
opposite direction, instead of two diagonal MOSFETs, current is conducted using the cor-
responding antiparallel or MOSFET body diodes. This in turn results in ZVS at turn-off,
and turn-on becomes a lossy process. This obviously has a resemblance with ZVS and
ZCS of the resonant converter, in which it depends upon the leading/lagging character of
the resonant current. The phases of one half-cycle of output voltage with a large reflected
load current in opposite direction from the magnetizing current are shown in Fig. 6.6 and
are described as follows:
a. Diagonal transistors T1 and T4 are turned on, which results in positive voltage applied
across the transformer primary, but the reflected load current is flowing through the
diodes D1 and D4 in opposite direction. This means that energy is regenerated from
the load at the secondary side via the transformer to the energy storage capacitor at
the primary side. Drain-source capacitance CDS3 of T3 is charged to +Vd and voltage
across the drain-source capacitance CDS4 of T4 is equal to the diode D4 voltage drop
(VD4 ≤ 1V ), i.e. CDS4 is discharged. Current flowing through the diodes consists from
the reflected load current (N2 /N1 )Iload minus the magnetizing current Im .
6.1 Input stage 141
b. T4 turns off, but the capacitance CDS4 can not get charged since reflected load current
is flowing through the antiparallel diode D4 , keeping the voltage at near zero Volts.
Turn-off of transistor T4 is therefore lossless (ZVS) at turn-off.
c. Transistor T3 is turned on, producing switching loss because of the voltage across it
VT3 = Vd − VD4 ≈ Vd . Reflected load current is diverted to discharge the parasitic
output capacitance CDS3 of transistor T3 and at the same time charge the capacitance
CDS4 . As soon as this transient process has ended, the applied voltage across the
transformer is zero.
d. Transistor T1 is turned off in a lossless manner (ZVS at turn-off) and the reflected
load current continues to freewheel through T3 and D1 . Transistor T2 is now turned on
with the full DC bus voltage across it, causing large switching loss at turn-on. Current
is diverted from the diode D1 to the opening channel of transistor T2 , charging CDS1
and discharging CDS2 .
CDS1 CDS3 CDS1 CDS3

T1 D1 D3 T3 T1 D1 D3 T3
Vd
+
. Vd
+
.
T2 D2 D4 T4 T2 D2 D4 T4
a) b)
CDS1 CDS3 CDS1 CDS3

T1 D1 D3 T3 T1 D1 D3 T3
Vd
+
. Vd
+
.
T2 D2 D4 T4 T2 D2 D4 T4
c) d)
Fig. 6.6. ZVS PWM inverter with reflected load current in opposite direction from the magnetizing current:
a) power regenerated from the load through D1 and D3 , b) T4 is turned off with ZVS, c) capacitance of T4 gets
charged and T3 gets discharged and d) capacitance of T1 gets charged and T2 gets discharged
What happens in between these limit cases, when the reflected load current is opposing
the magnetizing current, but is not enough to cause the total current in opposite direction
and ZVS at turn-off? Obviously, the switching losses at turn-on will be reduced but
not completely eliminated, if the magnetizing current was designed to solely displace
the charge between the parasitic capacitances without any help from the load current.
From this perspective, an intention is to have large magnetizing inductance yielding small
magnetizing current, since this will make the region of partly lossy switching transitions
smaller in width. As a result ZVS will depend mostly on the load current reflected to
the transformer primary side. Switching losses regions in relation with the load current
magnitude and direction for two different magnetizing currents Im1 = 2Im2 are shown in
Fig. 6.7.
Compared with the resonant converters where operation above resonance is preferred,
in the ZVS PWM inverters preferred state of operation is ZVS at turn-on i.e. energy
transfer from the source to the load. In this case ZVS at turn-off can be achieved by
ZVS Partly ZVS

turn-on ZVS turn-off
1
Im1
Im2
-Im2
-Im1
2 I’load
′
Fig. 6.7. Soft-switched PWM inverter switching losses dependance on reflected load current Iload for two different
magnetizing currents Im1 = 2Im2
adding small external capacitors in parallel with the MOSFETs, which is usually done in
the resonant converters too.
Analysis of ZVS in soft-switched full-bridge PWM inverters

In order to simplify the analysis, in the following section only the case when the load
current facilitates the ZVS at turn-on or the load current being zero will be investigated.
Several problems become clear right away: if in the classical full-bridge PWM converters
the aim is to moderately increase the magnetizing inductance in order to decrease the
magnetizing current and the conduction losses associated with it, in the case of ZVS
PWM converter magnetizing current must be of a certain level to facilitate the ZVS when
the load current is insufficient to do so. If this is not done, at light loads the input stage
will experience high switching losses and low conduction losses, while at heavy loads the
input stage will be in ZVS offering low switching losses, while the conduction losses will
increase. Sometimes, in order to allow ZVS at turn-off, additional external capacitances
can be added to keep the drain-source voltage near zero until the MOSFETs completely
turn off.
Charging/disharging of parasitic CDS and any other external capacitances is done using
the transformer primary current. One can distinguish the following cases:
• Input stage was delivering power to the output stage just prior to switching. The pri-
mary current consists from the reflected secondary (load) current and the magnetizing
current. This is the most favorable case, resulting in almost sure ZVS of the input
soft-switched PWM stage.
• Output stage disconnected the load prior to the switching action (freewheeling in the
output stage, if provided, ceased to transfer energy back to the input stage), but the
core itself is still magnetized since no opposite direction Volt-seconds were applied to
reset it. Only magnetizing current is flowing through the transformer primary, and if
designed properly, this should be enough to guarantee ZVS of the primary stage.
• The worst case appears when the output stage has disconnected the load, and the core
itself is reset prior to the switching due to the, for example, freewheeling action of the
output stage effectively shortening the secondary. In this case there is no magnetizing
current, so the ZVS must be accomplished by the resonant action of energy stored in
the transformer leakage inductance.
The necessary switching delay time for each of the legs will be calculated for the
worst case, where only the energy in the leakage inductance facilitates the ZVS of the
input stage. In this case, the leakage inductance plus any additional inductance of the
6.1 Input stage 143
leads in the input stage forms a resonant circuit with the output parasitic drain-source
capacitances of the turning-off and turning-on transistors. The process of charge displace
is finished in a time interval equal to one-fourth of the resonant period:
√
T 2π Lr Cr πp
td,res = = = Lr Cr (6.6)
4 4 2
where Lr = Ll + Ladd is the resonant inductance, consisting of the leakage inductance Ll
and any additional inductance in the loop Ladd and Cr is the resonant capacitance.
Special attention should be payed to determine the resonant capacitance Cr . It con-
sists from the paralleled output capacitances of two affected transistors as well as the
parasitic capacitance of the transformer primary (usually very low). Simple derivation in
[73] followed also herein, but with a slight alteration at the end can determine it very
precisely.
The output capacitance of a MOSFET Coss is usually given in a datasheet for applied
drain-source voltage of Voss = 25V , but it is far away from being constant. It is depletion
dependent capacitance and therefore decreases nonlinearly with increase of drain-source
voltage:
n
Voss
CDS (VDS , n) = Coss (6.7)
VDS
where n is usually between 1/2 and 1/3.

Energy stored in the output capacitance can be calculated in the following way:
dQ
Z Z Z Z
E = vidt = v dt = vdQ = VDS CDS (VDS , n)dVDS (6.8)
dt
which using the equation (6.7) transfers to:

n 2−n
Coss Voss VDS
Z
n 1−n
E = Coss Voss VDS dVDS = (6.9)
2−n
Taking n=1/2:
2 1 3
E = Coss Voss
2
VDS
2
(6.10)
3
or when having two output capacitances in parallel, like in the case of the switching instant
shown in Fig. 6.8a being investigated now:
4 1 3 1 8 1 3
E = Coss Voss
2
VDS
2
= · Coss Voss
2
VDS
2
(6.11)
3 2 3
which, when compared with the widely known expression for the energy stored in a ca-
pacitor E = 1/2 · CV 2 , leads to the final result for the resonant capacitance:
8
Cr = Coss + Cadd (6.12)
3
where Cadd represents the additional interwinding capacitance of the primary.
When switching both inverter legs at the same time (simultaneous ZVS PWM), drain-
source capacitances appear on the place of each of the MOSFETs in the full bridge, like
shown in Fig. 6.8b. This essentially connects the paralleled output capacitances of each
leg in series together and with the resonant inductance Lr , which results in two times
lower resonant inductance compared with (6.12):
4
Cr,sim = Coss + Cadd (6.13)
3
√ Although this means that the resonant time td,res in (6.6) has decreased for a factor of
2, the actual demand of magnetic energy stored in the resonating inductance for charge
displace has increased by a factor of 2, since now there are two MOSFET capacitances
which should be discharged and their charge displaced. It should be noticed, however,
that the role of the DC-blocking capacitor CDC during these transitions is only marginal,
since its high capacitance keeps it discharged during normal operation and experiencing
very low impedance at the high switching frequencies.
CDS1 CDS3 CDS1 CDS3

TR TR
CDC CDC
CDS2 RDS4 CDS2 CDS4
a) b)
Fig. 6.8. Determining the resonant capacitance Cr when switching: a) single leg and b) both legs at the same
time
After the initial resonant delay time td,res has been determined, the minimum value
of the magnetizing current Im,min can be calculated, which can store enough magnetic
energy in the leakage inductance of the transformer to perform the charge displace. Using
the equation (6.11) and the magnetic energy stored in the leakage inductance:
1 2 4 1 3
Ll Im,min = Coss Voss
2
VDS
2
(6.14)
2 3
the final expression for the minimum magnetizing current becomes:
s
1 3
2 Coss Voss
2
VDS
2
Im,min = 2 (6.15)
3 Ll
Minimum magnetizing current Im,min will be achieved with a maximum magnetizing
inductance Lm,max :
Φ Vin ton
Lm,max = = (6.16)
Im,min Im,min
where the leakage inductance Ll has been neglected.
In most of the cases, the transformer is designed using some method where the total
losses in the transformer, consisting of core and copper losses, are minimized choosing
the number of primary windings and the wounding technique (interleaving, paralleling
several windings with smaller diameter -Litz wire etc.). Of course, this may lead to a
design where the minimum leakage inductance and maximum magnetizing inductance are
already set, and the latter is too large to cause enough magnetizing current to facilitate
the ZVS. Gapping the magnetic core will help to increase the leakage inductance and
decrease the magnetizing inductance, which in turn has a positive effect upon the mag-
netic energy stored in the transformer leakage inductance. This will also lead to slight
6.1 Input stage 145
linearization of the magnetic core characteristic, making it less susceptible to DC satu-

ration and flux creepage. However, the energy efficiency will be compromised due to the
increased magnetizing current at all output powers, but especially at idle. So, a sort of
an optimization procedure should be undertaken to determine the optimal ratio of the
switching and conduction losses, which will lead to lowest overall losses at idle.
Other approaches has been investigated in literature too, like adding an inductor or
even saturable inductor in series with the transformer primary winding [72], which allows
ZVS operation of the converter down to very low loads. In the first approach the amount
of stored magnetic energy in the primary path i.e. the resonant inductance Lr is increased
by adding extra inductance and not by increasing the transformer magnetizing current,
like in the case of gapping the magnetic core. In the latter case, the saturable inductor
used in conjunction with a DC-blocking capacitor is released during freewheeling when
the primary current reaches zero Amperes and it holds it that way, so ZCS at both turn-on
and turn-off of particular switches is observed [75].
No matter the means used to achieve ZVS, caution should be exercised not to rely solely
on the calculated values for the resonant delay. This is especially true in the unloaded
output stage case. In the cases where the implemented resonant delay td,res , calculated
according to (6.6) is low, and the magnetizing current is unable to perform the charge
displace in the programmed time due to the unrealistically low maximum magnetizing in-
ductance Lm,max , the transistor in one leg is turned-on although the output capacitance of
the other transistor is not fully charged. This means that a large inrush source current will
flow through the output capacitance of the turning-off transistor, which will facilitate the
complete discharge displacement and eventually lead to complete turn-off of the desired
transistor. This is certainly not desired, but otherwise very conservative delays should be
implemented resulting in huge performance degradation. Therefore, some trade-offs must
be done and this is especially important at higher DC-bus voltages, when the charge
stored in the MOSFET’s output capacitance is correspondingly large.
One possible approach is the following: calculate the maximal (very conservative) delay
time td,max to discharge one output capacitance and compare it with the resonant delay
time td,res (6.6). An assumption is made, that the input stage is unloaded, so that the
constant magnetizing current Im is the only current performing the charge displace.
Z Vin Z Vin
Q 1 2Lm Voss n
td,max = = CdV = Coss dV =
Im Im 0 Vin Ts 0 V (6.17)
1−n 1−n
2Lm n V Vin = 2Lm Coss Voss n Vin 2Lm Coss Voss n
= Coss Voss =
Vin Ts 1−n 0 Vin Ts 1−n Ts (1 − n) Vin
which for n = 1/2 becomes:

r
4Lm Coss Voss
td,max = (6.18)
Ts Vin
In the cases where this maximum delay time td,max is several times bigger than the res-
onant delay time td,res , it makes no sense in using either of them, since using td,max results
in huge performance degradation and using td,res results in large capacitive inrush current
and stress. Therefore, letting the half of the charge stored in the output capacitance to
be displaced by the magnetizing current Im and and the rest of it with the short-circuit
current Isc makes an interesting alternative. Because of the nonlinear dependance of the
output capacitance from the applied voltage (6.7), a coefficient a is introduced which
determines at which drain-source voltage VDS = aVin the half of the charge Q is already
displaced:
Z aVin Z Vin
Q Voss n Voss n
= Coss ( ) dV = Coss ( ) dV
2 0 V aVin V
Z aVin Z Vin
−n
V dV = V −n dV
0 aVin
V 1−n aVin V 1−n Vin
= (6.19)
1−n 0 1 − n aVin
1−n
(aVin ) = Vinn+1 − (aVin )1−n
2a1−n Vin1−n = Vin1−n
1 1−n
1
⇒ a=
2
which for n = 1/2 gives:
2
1
a= = 0, 25 (6.20)
2
Following the same procedure in (6.17), the half-charge delay time td,hc can be deter-
mined:
Z aVi n Z aVi n
Q 1 2Lm Voss n
td,hc = = CdV = Coss ( ) dV =
Im Im 0 Vin Ts 0 V
Z aVi n 1−n
2Lm n 2Lm n V aVin =
= Coss Voss V −n dV = Coss Voss (6.21)
Vin Ts 0 Vin Ts 1−n 0
1−n 1−n
2Lm n a Vin 2Lm Coss 1−n Voss n
= Coss Voss = a
Vin Ts 1−n Ts (1 − n) Vin
which for n = 1/2 becomes:

r r
4Lm Coss √ Voss 1 4Lm Coss Voss 1
td,hc = a = · = td,max (6.22)
Ts Vin 2 Ts Vin 2
So, reducing the maximum delay time to half allows the inrush capacitive current to
displace the other half of the charge stored in the output capacitance of the MOSFET
much faster than the magnetizing current itself.
Utilization of the primary side DC-blocking capacitor in series with the transformer is
usually referred as unsuitable engineering practice. Leaving aside the increased volume and
price of the product, adding a series capacitor to cope with any primary side imbalance is
potentially dangerous in terms of unequal charging (i.e. voltage) of the capacitor during
the positive and negative half-cycles, thus resulting in uneven alternate primary voltage
pulses applied across the secondary side load. Therefore, larger blocking capacitance Cb
is needed to mitigate the situation and lower the imbalance voltage ∆V as a result of
unequal charging ∆Q during each of the half periods (∆V = ∆Q/Cb ). Although the
wish is to avoid this approach, it is still a practice of choice when compared with the
other techniques to cope with the imbalance problem, like the current-mode control and
different balancing techniques for the primary current, which necessitate use of current
transformers [76].
At the end, it is emphasized that the necessary delays for the legs of the ZVS PWM
inverter largely depend on the character of the output stage. In the case of a simple rectifier
like in [72], [73], [74], both legs can have different delays due to the different currents which
displace the charge in each of them: in one leg the charge displacement is always done
6.1 Input stage 147
with the reflected load current through the output inductor (current source) plus the
magnetizing current and in the other leg the charge displacement is always resonant with
the leakage inductance. However, in the case of an output stage in a form of a bidirectional
bridge governed by a superimposed audio reference, input stage can not know what is the
exact configuration of the initiated bidirectional switches, so the necessary delay times
may vary at a large scale. Designing it conservatively for the worst case seems to be the
only solution, which tends to fit all of the cases, except maybe for the lightest loads,
when the load current actually is not so large and the conduction and switching losses are
already low.
6.1.5 Hard-switched DC-AC inverter as input stage
The topology of the full-bridge hard-switched DC-AC inverter is the same as the one shown
in Fig. 6.4 for the ZVS PWM inverter, except that there are no additional capacitors and
inductors to reduce the switching losses and the necessary blanking (dead) time is much
lower than resonant delay time td,res . Other commonly used hard-switched DC-AC inverter
topologies include the push-pull and half-bridge topologies, where the component stress
is generally lower and performance is higher than the simple single switch topologies.
As already mentioned in previous sections, many advanced soft-switched inverter
topologies like the resonant converters and ZVS PWM inverters have found wide usage
in conventional isolated SMPS and other DC-DC converters. Not many applications are
reported with the latter technologies in DC-AC converters, and especially not in the very
challenging HF-link converters this part of the thesis is dealing with, where no DC-bus is
existing on the secondary side. The main advantage of the HF-link converter, but also its
Achilles’ heel, is the non-existence of intermediate energy storage on the secondary side,
which can dampen any difference between the energy sourced by the input stage and con-
sumed by the output stage. This was shown to be, for example, the greatest problem with
the resonant input stages, where the unrestricted load current flow between the input and
the output stage becomes a large source of perturbations of the resonant tank voltage. On
the other hand, ZVS PWM inverter without any capacitor on the secondary side will have
HF-link voltage with shape far from rectangular, since all those (relatively) long charging
and discharging processes of the switches’ parasitic capacitances will immediately be seen
by the output stage and the load. Due to the high switching frequency of the input and
output stage in a SICAM audio power amplifier, this ZVS operation and the associated
load voltage disturbances can potentially lead to lower audio performance.
When compared to all the previous technologies, it is believed that the hard-switched
DC-AC inverter input stage can provide the most uniform voltage levels and continuous
power flow needed by the output stage for best audio performance. Together with the wide
variety of topologies suited for each and every output power level, simple control principles,
as well as the continuous development of better power semiconductor components for
improved efficiency, hard-switched inverters were selected as input stage in SICAM.
6.1.6 Integration of the inverter input stage within the SICAM
DC-AC inverters being either push-pull, half-bridge or full-bridge, have a desirable prop-
erty of low output impedance, which makes the output voltage almost unaffected even by
large load current variations. The output voltage they produce has a rectangular form,
which results in two possible implementations:
• PDM - AC HF rectangular-shape pulses are created on the secondary side of the HF
transformer, which are then used by the PDM output stage to create train of positive
and negative voltages across the load to resemble the desired audio signal, as shown in
Fig. 6.9a, or
• PWM - AC rectangular-shape pulses with a frequency chosen to optimize the losses
and the volume of the input stage and HF transformer are transferred to the output
stage, then subsequently chopped and inverted by the bidirectional bridge according
to the audio reference in a PWM manner, as depicted in Fig. 6.9b.
vinput vin vinput vin
-vin -vin
voutput voutput
a) b)
Fig. 6.9. Input and output stage output voltage waveforms: a) PDM and b) PWM, with the dashed line showing
the desired output stage output voltage
For PDM SICAM, a phase-shifted version of the full-bridge HF ZVS PWM inverter
input stage can be advantageous, since the duration of the power pulses can be altered
according to the input voltage magnitude to deliver the same pulse area (Volt-seconds)
at any moment, which will decrease the burden imposed on the output stage control
circuitry. For the approaches with modulated transformer voltages, modulating the pulse
width can give another additional degree of freedom to improve the audio performance
and reconstruct the desired audio waveform, beside the pulse density variable.
For a simple PWM SICAM, ZVS PWM inverter with medium switching frequency and
maximum duty cycle can be used, since energy must be transferred to the output stage
continuously all the time. This makes it also easier for obtaining auxiliary power supplies
for control biasing and isolated gate drives.
For satisfactory audio performance it is necessary that the switching frequency is very
high, which makes possible to achieve control bandwidth several times higher than the
audio signal bandwidth. What is the exact switching frequency needed will primarily
depend on the selected modulation and control principle, but it is widely known that
PWM compared to PDM requires much lower switching frequency for providing the same
control bandwidth, which makes PWM a preferred choice over PDM.
6.1.7 Overdimensioning of the input stage in SICAMs
One very important issue to be discussed at this point is the need for overdimensioning
the input stage in isolated SICAM based on the HF-link conversion principle [77], in order
to be able to handle the reactive power flow from the load back to the output stage. In
the conventional solution with a separate SMPS and Class D audio power amplifier, this
reactive energy is stored in the DC-link capacitors, and its flow back to the primary side
is prohibited by the presence of the secondary-side rectifiers. These two quite different
cases are shown in Fig. 6.10 with half-bridge on the primary side and single-ended audio
power amplifier on the secondary side.
6.1 Input stage 149
i21 L21 iL21 i2p
+ T21
+ C1 T11 D11 i1 TR V2 C21 D
~ ~ . . vo +
LF
AC
mains
. io
- C2 T12 D12 n:1 V2 C22 CF
T22
1-D
+ L22
i22 iL22 i2n
a)
D21 D22
i21
+ T21 T22
+ C1 T11 D11 i1 TR V2
~ ~ . . vo +
LF
AC
.
io
mains +
- C2 T12 D12 n:1 V2 CF
T23 T24
i22
D23 D24
b)
Fig. 6.10. Electrical scheme: a) Conventional SMPS + Class D audio power amplifier and b) SICAM
Calculation of the input stage overdimensioning factor ODF for SICAM with regard
to the conventional SMPS and Class D audio power amplifier solution can be performed
by comparing the currents drawn from the input stage in both cases:
I1,SICAM
ODF = (6.23)
I1,SM P S
It is expected that the input stage overdimensioning factor is bigger than 1, ODF > 1,
since the input stage in SICAMs must handle both the active and reactive power flow.
In the case of the conventional SMPS and Class D audio power amplifier shown in
Fig. 6.10a, average currents through the upper and lower MOSFET are defined as:
I2p = DIo
(6.24)
I2n = −(1 − D)Io
where D is the upper MOSFET duty cycle and the load current Io through a resistive
load R for a sinusoidal reference is:
Vo Vm sin(2πfm t)
Io = = (6.25)
R R
where Io and Vo are equal to the load current io and load voltage vo with neglected
switching ripple, while Vm and fm are the modulating sinewave magnitude and frequency
correspondingly.
Output voltage of the Class D audio power amplifiers is:
Vo = (2D − 1)V2 (6.26)
which leads to the following expression for the duty cycle D:

1 Vo
D= 1+ (6.27)
2 V2
Combining equations (6.25) and (6.27), following expressions for the average MOSFET
currents in (6.24) are obtained [78]:

1 Vo Vo
I2p = 1+
2 V2 R
(6.28)
1 Vo Vo
I2n = − 1 −
2 V2 R
The waveforms of the average MOSFET currents of the Class D audio power amplifier
I2p and I2n with R = 8 Ω, V2 = 45 V, Vm = 40 V and fm = 1 kHz are depicted in Fig. 6.11.
It is visible that during half of the modulating period Tm = 1/fm there is current flow
from the load to the capacitors C21 and C22 on the secondary-side DC-bus.
5
I I
2p 2n
4
3
I2p, I2n [A]
2
I2,SICAM
1 I
2,SMPS
−1
0 0.2 0.4 0.6 0.8 1
t [s] −3
x 10
Fig. 6.11. Class D audio power amplifier average MOSFET currents and average secondary-side SMPS and
SICAM currents
If the operation of the conventional SMPS and Class D audio power amplifier is ana-
lyzed in steady-state, there must be a charge balance on both capacitors in order to obtain
the same capacitor voltage after each of the modulating periods Tm . This means that the
regenerated charge from the load to the capacitors compensates some of the charge being
transferred from the capacitors to the load during the generating mode, so that the input
stage needs to supply just their difference. In this way, the average SMPS output inductor
current IL2 = IL21 = IL22 is calculated to be:
Z Tm Z Tm
Vo2 Vm2 sin2 (2πfm t)

1 1 1
IL2 = Vo + dt = Vm sin(2πfm t) + dt =
Tm 0 2R V2 2RTm 0 V2
Tm 2 2
Tm
V2

1 Vm Tm V m Tm Vm Tm
= m

= − cos(2πfm t) + − sin(4πfm t)
2RTm 2π 0 2V2 8πV2 0 4RV2
(6.29)
Assuming input stage operation with 50% duty cycle, average primary side current in
the case of conventional SMPS and Class D audio power amplifier is:
Vm2

1 1 IL21 IL22 1
I1,SM P S = I2,SM P S = + = IL2 = (6.30)
n n 2 2 n 4nRV2
where n = N1 /N2 is the transformer turns ratio.
6.2 Output stage 151
When doing the same calculation for the SICAM case, it becomes clear that both
the active and the reactive portion of the switch currents i21 and i22 are processed by
the input stage. To simplify the analysis, first it will be neglected for a moment that
the HF-link voltage is alternating, which results in the bidirectional switches currents i21
and i22 being equal to the Class D currents i2p and i2n correspondingly. Afterwards it is
recognized that when the HF-link voltage starts perpetually to change the polarity the
equality does not hold anymore, but the Class D currents can still be associated with
the equivalent positive and negative voltage sources in the HF-link. This means that the
average secondary-side SICAM current during a modulating period Tm can be calculated
from the average MOSFET current values of the Class D audio power amplifier I2p and
I2n from (6.28) as:
|I21 | + |I22 | |I2p | + |I2n |

I2,SICAM = = =
2 2
Z Tm /2 Z Tm
Vo2 Vo2

1
= Vo + dt − Vo + dt =
2RTm 0 V2 Tm /2 V2
Tm /2 Tm /2
Vm2 Tm Vm2 Tm

1 Vm Tm
= − cos(2πfm t) + − sin(4πfm t) +
2RTm 2π 0 4V2 8πV2 0
Tm 2 2
Tm
Vm Tm V m T m V m Tm Vm
+ cos(2πfm t) − + sin(4πfm t) =
2π Tm /2 4V2 8πV2 Tm /2 πR
(6.31)
and the average primary-side SICAM current is:

1 Vm
I1,SICAM = I2,SICAM = (6.32)
n πnR
From equations (6.30) and (6.32), the SICAM input stage overdimensioning factor
ODF in (6.23) becomes:
I1,SICAM 4V2 4
ODF = = = (6.33)
I1,SM P S πVm πMmax
where Mmax is the maximum modulation index. The lowest achievable ODF is
ODFmin = 4/π = 1.27 for Mmax = 1.
For the example shown in Fig. 6.11, I2,SM P S =1.11 A, I2,SICAM =1.59 A and ODF=1.43,
which equals to 43% overdimensioning of the SICAM input stage when compared to the
input stage of the conventional SMPS and Class D audio power amplifier with the same
specifications.
6.2 Output stage

6.2.1 Commutation of the load current in the output stage through
safe-commutation switching sequences
In order to be able to block both voltage polarities that appear on the AC HF-link, the
output stage of a SICAM must consist from bidirectional switches i.e. 4QSWs already
presented in Section 5.5. However, due to the specific implementation of 4QSW, the
freewheeling path for the load current which is pertinent to the Class D amplifier active
switch with antiparallel diode is lost. This means that during the switching between
the outgoing and the incoming 4QSW, the designer must provide an uninterrupted load
current path without short circuiting the transformer secondary, if there is voltage across
it. If the load current is disrupted, dangerously large induced voltage spikes will develop
across the output filter inductor, which can drive the MOSFETs in the bidirectional
switches into avalanche mode or even destroy them.
The scheme of a full-bridge output stage with clearly separated and controllable
load current paths (4QSW is antiparallel connection of two voltage 2QSWs) is given
in Fig. 6.12.
D1 T3 D5 T7
TR T1 D3 T5 D7
. .+ LF LF
vHF
io
D2 T4 D6 T8
CF
T2 D4 T6 D8
Fig. 6.12. Full-bridge bidirectional SICAM output stage
This bidirectional bridge can be also referred to as a single-phase to single-phase matrix

converter. This makes the matrix converter commutation techniques applicable to the
aforementioned audio output stage. However, some limitations when transferring from
the largely exploited three-phase case [30], [34], [58], [59] to a single-phase are observed.
The simplest strategies for commutation of the load current in the bidirectional
switches, which consist of providing a dead-time between the switching of the outgo-
ing and incoming switch or allowing an overlap, result in disrupted load current or short
circuited source voltage correspondingly, so they are both theoretically and practically
unusable. The only case where overlap in the conduction of the incoming and outgoing
bidirectional switch is allowed is in the intervals with zero voltage across the transformer
when 3-level PWM HF-link voltage is used.
The basic commutation strategies therefore are:
• Current controlled - the commutation strategy is relying on accurate determination
of the load current io direction, so that the switching sequence provides continuous
current path without allowing a short circuit of the source; and
• Voltage controlled - the commutation strategy is based on the HF-link voltage vHF
polarity, so that right switches are chosen which not result in any violation of the
electrical laws.
Regarding the structure of the bidirectional bridge in Fig. 6.12, current controlled
commutation can be accomplished using the switching pattern in Table 6.1 and voltage
controlled commutation using the switching pattern in Table 6.2. Stepping through the
switching sequences is performed with a short delay in order of several tens of nanoseconds,
just to allow the load current to commutate from the outgoing set to the incoming set of
switches.
outgoing switches io off ց on ր off ց on ր incoming switches

1,6 & 3,8 >0 3,8 4,7 1,6 2,5 2,5 & 4,7
<0 1,6 2,5 3,8 4,7
2,5 & 4,7 >0 2,5 1,6 4,7 3,8 1,6 & 3,8
<0 4,7 3,8 2,5 1,6
Table 6.1. Current controlled commutation sequence of the bidirectional bridge in Fig. 6.12
outgoing switches vHF on ր off ց on ր off ց incoming switches

1,6 & 3,8 >0 4,7 1,6 2,5 3,8 2,5 & 4,7
<0 2,5 3,8 4,7 1,6
2,5 & 4,7 >0 3,8 2,5 1,6 4,7 1,6 & 3,8
<0 1,6 4,7 3,8 2,5
Table 6.2. Voltage controlled commutation sequence of the bidirectional bridge in Fig. 6.12
Both presented strategies have some practical pitfalls. Current controlled commuta-
tion strategies are very popular in the motor drives community, since the load current
is a measured quantity in order to accomplish field oriented control and for protection
purposes. However, large current measurement and accurate current zero-crossing detec-
tion in a same current sensor are two counteracting goals, since for current measurements
(for ex. in motor drives) a wide range of load currents should be accommodated, while
for zero current detection very low noise and high accuracy environment with very small
currents should be provided. Therefore, poor results in whole range operation are reported
with current controlled commutation only because of the low sensitivity, high noise and
offset levels of the present state-of-the-art current sensors. Significant advantage of this
approach is that load current can change its direction even when the commutation process
has started. In that case, the other current direction will be usually prohibited, so the
load current will settle at zero until the commutation process has ended.
Voltage controlled strategies are facing the same problems of inadequate measuring
sensors like the current controlled strategies, despite of the additional volume and price
burden imposed by their installation. However, they have an another disadvantage - input
voltage reversal during a commutation is not allowed since this can result in having wrong
switches turned on with possible disastrous results.
Combination of both techniques are also investigated in some references. In these ap-
proaches the alternative strategy is used whenever the first strategy enters into the un-
certainty region where the voltage/current sign can not be accurately determined. Unfor-
tunately, in the case of both voltage and current sign being uncertain, further switching
can be catastrophic. To avoid this some retarding or prohibition techniques are executed
where the switching is avoided as long as the voltage and/or current signs are uncertain,
but the quality of the output voltage and input current are therefore compromised.
There are some three-phase techniques which can be used to overcome the pitfalls of
the aforementioned strategies, like replacement [59] and prevention [58]. These consist of
a smart commutation algorithm which changes the order of switching between the phases
where the input line voltage sign is not certain by putting the third phase for safe com-
mutation in between. Basically this results in shifting from one uncertain commutation to
two certain, but more lossy commutations. Since in the case of the single-phase bidirec-
tional bridge for audio-output stage there is no other phase to safely commute to, another
approach must be found.
Voltage controlled commutation is usually regarded as inferior to the current controlled
commutation because of the incapability of successfully finishing the commutation if the
D21 D22
+ T21 T22
+ C1 T11 D11 vHF
TR
~ ~ . . LF
AC .
mains iout
- +
C2 T12 D12 vHF CF
T23 T24
D23 D24
Fig. 6.13. Scheme of SICAM with single-ended output stage
input voltage sign changes during the process. This problem is especially emphasized in
the case of three-phase matrix converters, since the input voltage is taken right from the
utility grid as it is, so there is nothing the converter on the user side can do to mitigate the
commutation. However, in the particular case presented in this thesis, the output stage of
the SICAM is actually powered by the output voltage of the DC-AC inverter input stage,
operation of which is completely under user control. This means that by wisely operating
the input stage, every possible HF-link voltage polarity change during an output stage
commutation can be avoided. Therefore, the only safe-commutation switching algorithm
to be investigated herein is the voltage controlled sequence.
The voltage controlled switching sequence for the case of single ended output stage
with common-source bidirectional switches in Fig. 6.13 is shown in Table 6.3. The depicted
SICAM topology with a half-bridge inverter on the primary side and single-ended amplifier
on the secondary side is found very appropriate and simple enough for the intended output
power range and includes common-source bidirectional switches, which are characterized
with probably the best characteristics for audio applications of all other bidirectional
switches presented in Section 5.5.
Table 6.3. Voltage controlled commutation sequence - natural commutation (◦) and forced commutation (•)
outgoing switch vHF io on ր off ց on ր off ց incoming switch
21,22 >0 >0 23 21 • 24 22 23,24
<0 23 21 24 ◦ 22
<0 >0 24 22 23 ◦ 21
<0 24 22 • 23 21
23,24 >0 >0 22 24 21 ◦ 23 21,22
<0 22 24 • 21 23
<0 >0 21 23 • 22 24
<0 21 23 22 ◦ 24
The voltage controlled commutation sequence presented in Table 6.3 depends only on
the polarity of the HF-link voltage vHF . The table, however, includes also the direction
of the load current io which determines whether the load current commutation will be
forced or natural.
In other words, output stage switches are operated on and off in a prescribed manner
that provides alternative path for the load current without short-circuiting the transformer
at all times. Except for the short periods when the input stage is switching, the transformer
voltage i.e. the voltage of the HF-link vHF has known and easily determinable polarity,
so the switching of the output stage can safely proceed through the voltage controlled
commutation sequence given in Table 6.2. Stepping through the latter sequence is done
by inserting short delays ∆td , as shown in Fig. 6.14.
VHF>0
23 24 22 21
21 22 24 23
21,22 21,22
Vs
i>0 Dtnc
-Vs
23,24
Dtd Dtd Dtd Dtd Dtd Dtd
21,22 21,22
Vs
i<0 Dtnc
-Vs
23,24
23 24 22 21
21 22 24 23
VHF<0
21 22 24 23
23 24 22 21
23,24 23,24
Vs
i>0 Dtnc
-Vs
21,22
Dtd Dtd Dtd Dtd Dtd Dtd
23,24 23,24
Vs
i<0 Dtnc
-Vs
21,22
21 22 24 23
23 24 22 21
Fig. 6.14. Commutation diagrams with positive and negative HF-link voltages and load currents
Commutation of the load current from the outgoing to the incoming switches can be
done either in a forced way, by turning off the switch which is conducting the load current,
or in a natural way, by turning on one of the incoming switches and applying the correct
transformer voltage that causes transfer of the load current from the outgoing to the
incoming switch. The slew rate of the load current during natural commutation is limited
by the leakage inductance of the transformer secondaries and the applied voltage and this
determines the time it will take for the natural commutation to finish:
|io | Lsl |io |
∆tnc = 2Lsl = (6.34)
2Vs Vs
where Lsl is the leakage inductance of a single secondary, io is the instantaneous value of
the load current and Vs is the value of the HF-link voltage. During natural commutation,
bridge output voltage is equal to zero, since the equal leakage inductances in each of the
switching branches act as an inductive voltage divider.
With regard to switching losses, the forced current commutation is lossy since it rep-
resents hard switching of the MOSFET which was conducting the whole load current.
However, natural current commutation is lossless because of the fact that the current
rise in the switch is limited by the transformer secondary leakage inductances, so that
incoming switch is turning on with essentially zero current (ZCS). However, if the du-
ration of the natural commutation is longer than the inserted delay time, ∆tnc > ∆td ,
when the current-carrying outgoing switch is turned off the natural commutation will turn
into forced commutation, with just a fraction of the load current being switched off. It is
therefore beneficial to keep the leakage inductance of the transformer secondary to a low
value, in order to speed up the commutation process and decrease the associated voltage
distortion.
It can be concluded that the voltage controlled commutation sequence represents a
very simple way of implementing safe-commutation techniques in SICAMs, but the only
thing that needs to be resolved is avoiding simultaneous switching of the input and the
output stage, i.e. guaranteeing constant polarity of the HF-link voltage during the whole
commutation sequence. This will be subject of investigation in some of the control methods
presented in Chapter 7.
Regarding the practical implementation of the safe-commutation switching sequence
from Table 6.3, it represents a finite state machine shown on the right-hand side in
Fig. 6.15. It has two stable states S1 and S2 , which depend on the polarity of the PWM
modulator output Vpwm and possibly on the polarity of the HF-link voltage VHF (VHF
shown in parenthesis at S1 and S2 ). This possibility is to include changeover of the bidi-
rectional bridge state immediately after the change of the HF-link polarity, or at another
instant within the switching period to decrease the switching frequency, as shown in the
optimized PWM control method in Section 7.2.2. The safe-commutation finite state ma-
chine has also six astable states, in which the direction of the movement depends on
the polarity of the PWM modulator output and HF-link voltage but the actual stepping
through the states is determined by the time delay td . The two states P1 and P2 on the
left-hand side in Fig. 6.15 just change between each other according to the output voltage
polarity and can be used for selecting and multiplexing the outputs from different PWM
modulators in the optimized PWM control method in Section 7.2.2.
Vhf>0 Vhf>0
Vhf>0 A1 A2 A3
Vpwm<0 Vpwm<0
Td Td
Switch State Switch State Switch State
P1 21 1 21 0 21 0
22 1 22 1 22 1
(Vhf>0) Vhf>0 23 1 23 1 23 1 Vhf>0 (Vhf>0)
Vpwm>0 Vpwm<0 24 0 24 0 24 1 Vpwm<0 Vpwm<0
Vpwm >>> Td Td
PWM_POS
S1 Vhf>0 Vhf>0 S2
Vpwm>0 Vpwm>0
Vhf>0 Td Td Vhf>0
Switch State Switch State
Vpwm>0 Vpwm>0
21 1 Td Td 21 0
22 1 22 0
Vhf>0 Vhf<0 23 0 23 1
24 0 Vhf<0 Vhf<0 24 1
Vpwm>0 Vpwm>0
Td Vhf<0 Vhf<0 Td
Vpwm>0 Vpwm>0
Td Td
Vpwm >>> Switch State Switch State Switch State Vhf<0
(Vhf<0) Vhf<0 (Vhf<0)
PWM_NEG 21 1 21 1 21 1 Vpwm<0
Vpwm>0 Vpwm<0 Vpwm<0
22 1 22 0 22 0 Td
Td
23 0 23 0 23 1
24 1 24 1 24 1
P2
Vhf<0 Vhf<0
Vpwm<0 Vpwm<0
A4 Td
A5 Td
A6
Vhf<0
Fig. 6.15. State diagram of the safe-commutation switching sequence
The most flexible implementation of the finite state machine is in Programable Logic
Device (PLD) in a synchronous way or asynchronous way. In the synchronous way, step-
ping through the safe-commutation switching sequence is performed synchronously with a
fixed external clock and that is why this implementation requires least hardware resources.
The clock rate of the external clock determines the commutation time delay ∆td = 1/fclk .
Unfortunately, clock impulses are not synchronized with the PWM modulator output,
so there can be different time intervals from the moment the PWM modulator output
changes state till the moment the commutation sequence actually starts. On the other
hand, the asynchronous finite state machine has the commutation time delays ∆td be-
tween the corresponding commutation steps implemented in hardware as gate logic delays,
and although it is supposed to be the best performer it also requires most hardware from
the PLD chip.
Effects of commutation delay on audio distortion

The ideal PWM amplification process is linear and does not introduce any distortion
within the audio baseband. However, the PWM process as implemented in real hardware
is far from ideal and its audio performance can suffer from nonlinearities introduced either
in the PWM modulator or the power amplifier section. Looking at the PWM modulator,
performance can suffer from carrier nonlinearity through acceleration or deceleration of the
slopes i.e. carrier distortion, caused either by intrinsic nonlinear slope generation or ripple
voltage feedback from the power section, which cannot be distinguished from the actual
modulating signal by the PWM modulator comparator itself [79]. In the conventional
Class D switching power stage [80], errors arise as a result of the blanking i.e. dead -
time, delays and finite rise and fall times, known as Pulse Timing Errors (PTE), as well
as power supply perturbations and finite switch impedances, known as Pulse Amplitude
Errors (PAE). The switching power stage of the proposed SICAM amplifier is prone to all
the aforementioned errors, except for the blanking error, which due to the specific safe-
commutation switching strategy appears as commutation delay error and features slightly
different characteristics. These will be topic of the present section.
By inspection of the commutation diagram in Fig. 6.14 for the case with positive and
negative current, it turns out that the average voltage error ve is given by:
( − (2∆td + ∆tnc )Vs , i > 0

0
Tc2
ve = (6.35)
(2∆td + ∆tnc )Vs
, i0 < 0
Tc2
where the natural commutation interval ∆tnc is given in (6.34) and depends on the load
current, which causes the distortion to appear as load dependent. The time period T in
equation (6.35) stands for the switching period of the output stage, and in the case of the
optimized PWM method from Section 7.2.2 it is equal to the time period of the PWM
modulator triangular carrier Tc2 .
The two different cases of distortion, where the maximum natural commutation in-
terval ∆tnc,max occurring at maximum load current is either shorter or longer than the
commutation delay ∆td , are given in Fig. 6.16. The hatched area corresponds to the bridge
voltage distortion in a conventional Class D audio amplifier [80], while the rest of it is
specific to the safe-commutation switching strategy with the proposed SICAM.
Fourier series coefficients for the non-hatched area under the voltage error curve in
Fig. 6.16 with ∆tnc,max > ∆td are:
a1,0 = 0
a1,n = 0
2π 2π 2π
2Lsl Im sin[(2n − 2) Tm t10 ] sin[2n Tm t10 ] 4∆td Vs cos[(2n − 1) Tm t10 ]

b1,n = + +
πTc2 Vs 2n − 2 2n πTc2 2n − 1
ve
Dtnc, max<Dtd
3DtdVs/Tc2
2DtdVs/Tc2
-2DtdVs/Tc2
-3DtdVs/Tc2
ve
Dtnc, max>Dtd
t10 t20
3DtdVs/Tc2
2DtdVs/Tc2
-2DtdVs/Tc2
-3DtdVs/Tc2
Fig. 6.16. Average voltage error with ∆tnc,max < ∆td (above) and ∆tnc,max > ∆td (below)
(6.36)
where Lsl is the secondary-side leakage inductance, Im = M Io,max is the peak value of the
load current, Vs = |vHF | is the secondary-side absolute voltage value, Tm is the period of
the modulation signal, n ∈ Z+ , t10 and t20 are the instants when ∆tnc = ∆td :

1 ∆td Vs
t10 = arcsin
ωm Lsl Im
(6.37)
Tm
t20 = − t10
2
In the case when ∆tnc,max < ∆td there is no distortion introduced by the non-hatched
area in Fig. 6.16, except for the linear error causing change of the fundamental value by
a factor of −(Lsl Im )/(Tc2 Vs ).
Fourier series coefficients for the hatched area in Fig. 6.16, corresponding to conven-
tional Class D amplifier distortion, are given by:
a2,0 = 0
a2,n = 0
(6.38)
∆td sin(n π2 ) ∆td (−1) n
b2,n = −2 Vs =2 Vs
Tc2 n π2 Tc2 (2n − 1) π2
In general, the total harmonic distortion (THD) caused by the commutation delay is
given by:
v
uNmax
uX
t (b1,i + b2,i )2
i=2
T HD = (6.39)
M Vs + b1,1 + b2,1
which in the case of ∆tnc,max < ∆td leads to:
v
uNmax
uX
t (b2,i )2
i=2
T HD1 = (6.40)
Lsl Im 4∆td V s
M Vs − −
Tc2 Vs πTc2
and in the case of ∆tnc,max > ∆td to:
v
uNmax
uX
t (b1,i + b2,i )2
i=2
T HD2 = (6.41)
4∆td Vs
M Vs + b1,1 −
πTc2
The presence of filter ripple current causes the THD of the SICAM to decrease as the
output current i.e. the modulation index M decreases. This is result of the fact that within
one carrier period Tc2 in Fig. 6.14 the switch current changes the polarity, thus effectively
cancelling the voltage error of two subsequent commutations and giving no average voltage
error. Therefore, the reduced THD of the SICAM at low modulation indexes can be taken
into account the same way as in the conventional Class D amplifier [80]:
v
uNmax
uX
∆(αI )t (b1,i + b2,i )2
i=2
T HD = (6.42)
M Vs + ∆(αI )(b1,1 + b2,1 )
where αI is the ripple current factor, which depends on the modulation index M and the
maximum values of the load current Io,max and filter ripple current If r,max in the following
way:
If r,max If r,max
αI = = (6.43)
Im M · Io,max
and the THD correction factor ∆(αI ) is:
( 0 , Im ≤ If r,max
π
∆(αI ) = 2 − arcsin(αI ) (6.44)
π , Im > If r,max
2
THD vs. power curves for a SICAM with safe-commutation and no additional control
feedback loops in a case when Vs = 71 V, filter inductance L = 42 µH, modulation index
M =0-0.65 and four different secondary-side leakage inductances Lsl =0, 1 µH, 2 µH and
5 µH are depicted in Fig. 6.17. It can be noticed that the presence of leakage inductance in
the secondary-side winding of the transformer causes additional distortion of the output
voltage due to the natural commutation delay ∆tnc , which can not be longer than the
commutation delay ∆td . Therefore, the SICAM THD cannot be lower than the THD of a
Class D amplifier with similar specifications (bottom curve Lsl = 0 µH in Fig. 6.17), but
also not higher than the case with very large leakage inductance (top curve Lsl = 5 µH in
Fig. 6.17), when the natural commutation is rather slow and is essentially replaced entirely
by forced commutation after the commutation delay ∆td . The small circles on the curves
show the moment when the natural commutation turns into partly forced commutation
∆tnc > ∆td , resulting in sudden increase of the THD. The curves in Fig. 6.17 also show
the need for adding a control with feedback, which will linearize the output stage and
effectively decrease the distortion by the amount of gain within the frequency band of
interest.
THD of safe−commutated SICAM

8
Lsl=5µH
Lsl=2µH
6
5
L =1µH
sl
THD [%] 4
L =0µH
3 sl
0
0 20 40 60 80 100 120 140
Output power Po [W]
Fig. 6.17. THD of a safe-commutated SICAM with different secondary-side leakage inductances
6.2.2 Commutation of the load current in the output stage with load clamps
The main drawback of the load current commutation with safe-commutation switching
sequence is the involved control strategy which needs to guarantee that switching the
input and the output stage is not simultaneous. At the same time the intentionally in-
serted commutation delay times when advancing through the safe-commutation switching
sequence give additional rise to output voltage distortion. On the reliability side, the pro-
posed safe-commutation switching sequence alone does not allow for safe shutdown of the
amplifier, if the secondary side gate-drive of the bidirectional switches is suddenly lost
when there is a large amount of stored magnetic energy in the output filter and the load.
The simplest load current commutation strategy for the output stage of a SICAM would
ideally resemble switching of the Class D audio power amplifier with blanking (dead) time
tbl . The biggest problem with this approach is that in Class D audio power amplifiers the
load current continues to freewheel through the MOSFET antiparallel diodes during the
dead time, while bidirectional switches in SICAM output stage do not possess such a
freewheeling path. In order to create it, there must be an output filter and loudspeaker
clamp added to the output stage, which will provide an alternative path for the load
current and clamp the load voltage when all the switches are turned off. The load clamp,
being a clamp of both the output filter and the loudspeaker, is shown as a block diagram
in Fig. 6.18.
As depicted in Fig. 6.18, when both bidirectional switches are turned off, load current
is diverted through a fast rectifier bridge to a clamp capacitor C3 , while the load voltage
is clamped to latter capacitor voltage. In order to keep the complexity of the clamp low,
direction of the power flow during the dead time is always from the load to the clamp
capacitor and not vice versa, because of the rectifier bridge. Limiting the capacitor voltage
to reasonable levels by maintaining a charge balance is very important in this case, so
a dissipative clamp with a parallel resistor [9] or active clamp with an isolated SMPS
returning the energy back to the primary side DC-bus [54], [81] is necessary. For more
demanding applications, load clamp can be made bidirectional [49] and then power is
regenerated back from the clamp capacitor to the same place where it was harnessed, i.e.
on the secondary side.
D21 D22
+ T21 T22
+ T11 D11 vHF
TR io
~ ~ . . LF
AC .
mains
- +
io
C2 T12 D12 vHF CF
T23 T24
D23 D24
Dissipative R or
Active SMPS
io +
C3
~ ~
-
Load voltage clamp
Fig. 6.18. Isolated SICAM with output filter and load clamp
The arrangement of the clamp and its connection to the output stage shown in Fig. 6.18
assumes that the secondary transformer leakage inductance is negligible, or similar clamp
or snubber circuitry is present across the secondary winding. An extension of the clamp
with different connection points can be used to receive the energy stored in both the
secondary leakage inductance and load [9].
Another advantage of the clamping technique for commutating the load current in
the output stage is the possibility of using a JFET as bidirectional switch, as already
mentioned in Section 5.5. In the output stage with JFETs, there is no way of implementing
safe-commutation switching techniques, since turning off the JFET results in immediate
blocking of all current directions.
The implementation of the capacitive voltage clamp offers some unique benefits, which
are not found elsewhere. The most prominent one is the increased safety against induced
overvoltages in the case of loosing a secondary side gate-drive for bidirectional switches or
other malfunctions that interrupt the usual load current path, which is functionally anal-
ogous to the three-phase matrix converter dissipative safety clamp. Another disputable
advantage of the active capacitive voltage clamp, which returns the clamped energy back
to the primary side energy storage capacitor, is the marginally improved ride-through ca-
pability of the SICAM in the case where AC mains input voltage is decreased or even lost
for a very short period of time, during which the auxiliary converter feeds some charge
from the clamp capacitor-dump to the primary side storage capacitor and supports the
amplifier operation.
Comparing the lossy dissipative clamp with the ideally lossless active clamping tech-
nique, it becomes clear right away that the former is not suitable for the SICAM solution,
which promotes simplicity and compactness together with high efficiency. Therefore, the
rest of this chapter will deal with the active clamping technique, its operation principles,
design issues and control techniques.
D21 D22
+ T21 T22
+ T11 D11 vHF
TR
~ ~ . . LF
AC .
mains
- +
C2 T12 D12 vHF CF
T23 T24
D23 D24
D13
TR aux
.
+
.
C3
~ ~
T3 D3 -
Active capacitive voltage clamp
Fig. 6.19. Isolated SICAM with an active capacitive voltage clamp
6.2.3 SICAM with active capacitive voltage clamp
Topology and operation basics
The proposed SICAM with active capacitive voltage clamp, shown in Fig. 6.19, solves
the commutation problem by allowing very short dead or blanking time tbl between the
outgoing and incoming switches, and in the meantime clamping the output filter and load
voltage by diverting the load current io into the clamp capacitor C3 through a very fast
full-bridge rectifier. This creates clamp current icl with pulse shape, shown on the top
diagram of Fig. 6.20, where the pulse magnitude is equal to the instantaneous value of
the load current and pulse duration is equal to the blanking time tbl .
The clamp itself is called active, since the energy dumped in the clamp capacitor
during the short dead time intervals of the secondary side switches is not dissipated, but
is instead returned to the primary side with a simple, small, isolated single-switch auxiliary
converter, shown in the lower right corner in Fig. 6.19 as a flyback converter. The auxiliary
converter is operated in a way that regulates the clamp capacitor voltage Vcl to a value
that is slightly higher than the highest transformer secondary voltage expected during
high voltage on the input line Vs,max , so that the clamp capacitor is charged only during
the dead time interval and not throughout the rest of the switching interval. Although
the task looks almost the same as in a common flyback converter, the regulated quantity
is not the output voltage but the voltage of the clamp capacitor. Therefore, this active
clamping technique poses some new challenges in the design of the auxiliary converter.
Since the clamp is connected in parallel with the combination of only the output filter
and the loudspeaker, it is very important to keep the transformer secondary side leakage
inductance as low as possible, which will limit the ringing during the dead time intervals
due to the stored magnetic energy to a minimum.
Although the particular implementation of the SICAM with active capacitive voltage
clamp depicted in Fig. 6.19 features half-bridge inverter on the primary side and single-
ended amplifier on the secondary side, the selection of input and output stage topologies is
performed separately for each design case to minimize component stress and is depending
predominantly on the input voltage and output power levels.
Qtr
{
io
icl
Ts2
Iaux, pk
iL
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Q
aux
DiL
t
Taux
Fig. 6.20. Time waveforms of the active clamp
Clamp and auxiliary converter design

When compared to similar dissipative solutions [9] where a properly chosen resistor is
used to dissipate the energy dumped in the clamp capacitor and keep the clamp voltage
from raising abnormally even at highest loading, the active clamp approach gives much
higher efficiency. This is done, however, on expense of increased complexity and cost due
to several additional power components, but the auxiliary converter itself processes only
a small fraction of the total audio power amplifier power, so it is rather small and cheap
to implement.
For comparison purposes, the power dissipated in a dissipative clamp resistor Rcl is
almost independent of the SICAM instantaneous output voltage, since the clamp capacitor
is always charged through the clamp rectifier to at least the transformer secondary voltage:
Vs2
Pdis = (6.45)
Rcl
On the other hand, using an active load voltage clamp with auxiliary converter pre-
serves and regenerates the charge dumped in the clamp capacitor. By regulating the clamp
capacitor voltage to values slightly higher than the HF-link voltage vcl > vHF , charge is
being dumped into the clamp capacitor only during the blanking (dead) time periods
and not directly from the primary side during normal operation, except for the start of
operation. These blanking time periods happen twice per switching period of the output
stage, so the duty cycle of the clamp current can be defined as Dcl = 2tbl /Ts2 . Assuming
that sinusoidal load current with peak value of Io,pk and variable modulation index M is
diverted into the clamp at the switching frequency of the bidirectional bridge fs2 = 1/Ts2
and with duration equal to its blanking time tbl , the average current into the clamp Icl,av
is:
2
Icl,av = Dcl Io,av = 2tbl fs2 M Io,pk (6.46)
π
and its RMS value Icl,rms is:
p 2 p
Icl,rms = Io,av Dcl = M Io,pk 2tbl fs2 (6.47)
π
Power handled by the auxiliary converter Pcl of the active clamp is calculated as:
2
Pcl = Vcl Icl,av = 2Vcl tbl fs2 M Io,pk (6.48)
π
and the active clamp power loss is just a fraction of Pcl , depending on the efficiency of
the active clamp converter ηcl :
Ploss,cl = ηcl (Pcl ) · Pcl (6.49)
The design of the clamp starts with the selection of the clamp capacitor Ccl = C3 . The
primary task of the selection process is to limit the voltage ripple ∆Vcl during normal
operation or emergency shutdown. By assuming that the bulk of the clamp capacitor
voltage ripple in normal operation is due to its internal equivalent series resistance (ESR),
the following selection rule can be written for the clamp capacitor ESR:
∆Vcl,max
ESRmax = (6.50)
Io,pk
During emergency shutdown all the stored energy in the output filter inductor is con-
verted into electrostatic energy in the clamp capacitor. The worst case for this situation
is when the converter is shut down at the peak value of the inductor current Io,pk , when
the magnetic energy stored in the inductor Lf is largest:
1 2
EL,pk = Lf Io,pk (6.51)
2
Neglecting the presence of the auxiliary converter due to the unavoidable time delay
before it catches up with the increased clamp voltage, as well as the output filtering
capacitor which is much smaller in size than the clamp capacitor, the inductor current
will divert entirely into the clamp capacitor and cause increase of its voltage ∆Vcl and its
stored energy amounting to:
1
∆ECcl = Ccl ∆Vcl2 (6.52)
2
If the maximum allowed increase of clamp capacitor voltage during emergency shut-
down is ∆Vcl,max , from (6.51), (6.52) and EL,pk = ∆ECcl the clamp capacitor capacitance
is limited to:
2
Io,pk
Ccl,min = Lf (6.53)
∆Vcl,max
At the same time, the clamp capacitor must be able to handle the maximum RMS
capacitor current ICcl,rms , which comprises of the RMS clamp current Icl,rms and RMS
capacitor discharge current Idis,rms :
q
2 2
ICcl,rms = Icl,rms + Idis,rms (6.54)
The design of the clamp auxiliary converter is started by selecting an appropriate

isolated converter topology and mode of operation. In most of the cases discontinuous
conduction mode (DCM) flyback converter will be the best choice, since it is the sim-
plest isolated converter topology and the discontinuous mode operation allows for low
inductance value of the flyback transformer, leading to minimum size magnetics.
After the topology and the operating mode of the auxiliary converter have been chosen,
the inductance value Laux of the inductor in the auxiliary converter, i.e. the flyback
transformer magnetizing inductance in this particular case, is to be calculated. The most
important quantity for its selection is the maximum transferred charge Qtr,max from the
load to the clamp capacitor during one period of the auxiliary converter operation Taux =
1/faux . Due to the discontinuous conduction mode of the auxiliary converter and the
steady-state balance of the clamp capacitor voltage, the transferred charge from the load
to the clamp which is the sum of the hatched areas on the top diagram in Fig. 6.20 is
equal to the transferred charge from the clamp to the primary side, which is represented
by the crosshatched area on the bottom diagram in Fig. 6.20. Maximum transferred charge
occurs at maximum output:
fs2
Qtr,max = Io,pk tbl (6.55)
faux
The maximum charge Qaux,max which can be transferred from the clamp capacitor to
the primary side with DCM auxiliary converter is calculated by using its peak inductor
current Iaux,pk and the maximum duty cycle Dmax :
2
1 Vcl Dmax
Qaux,max = Iaux,pk Dmax Taux = 2
(6.56)
2 2Lfaux
This limits the maximum inductance Lmax of the auxiliary converter operating in DCM
needed to entirely regenerate the maximum dumped charge Qtr,max :
2 2
Vcl Dmax Vcl Dmax
Laux,max = 2
= (6.57)
2Qtr,max faux 2fs2 faux Io,pk tbl
Other operating modes of the auxiliary converter are also possible, like combining
continuous conduction mode CCM with large load currents and DCM with low load
currents, but as already mentioned pure DCM operation leads to smallest size magnetics.
Control of the active clamp auxiliary converter
In order to synthesize the controller for the clamp auxiliary converter, it is necessary
to have its dynamics in a form of a small-signal AC model. Derivation of the latter
is significantly affected by the fact that the controlled quantity is the clamp capacitor
voltage i.e. the source voltage, instead of the load voltage as with the conventional SMPS.
+ iC + iL nig niR
2
icl vC C vL L + vg/n -R/n
-
Fig. 6.21. Buck-boost auxiliary converter
The small-signal AC model of the aforementioned flyback auxiliary converter can be

developed by using the converter diagram in Fig. 6.21, where n represents the transfer ratio
of the flyback transformer and negative resistance −R models the whole HF-link converter
with its control loops. The transfer functions of the continuous conduction mode (CCM)
and the discontinuous conduction mode (DCM) flyback auxiliary converter differ, so they
will be developed separately. The development of the equations for the CCM flyback
auxiliary converter is given in Appendix D.1 and for the DCM flyback auxiliary converter
in Appendix D.2.
By following the same steps like in [60], after the performed averaging of the equations
during d and d′ and perturbation of the variables, neglecting the second order terms
leads to the following AC and DC equations for the CCM flyback auxiliary converter in
Fig. 6.21:
diL D′ Vg
AC : L = DvC + VC d + vg − d
dt n n
dvC
C = −DiL − IL d + icl
dt
n
nig = D′ iL − IL d − vg
R
′ (6.58)
D
DC : VC = − Vg
nD
Icl
IL =
D
D′ Vg
Ig = IL −
n R
By rewriting the AC equations (6.58) in Laplace s-domain and setting vg = icl = 0,
the CCM control-to-clamp-voltage transfer function Gvcd,ccm is obtained:
snLIcl
Vg 1 − DVg

vc
Gvcd,ccm = = · (6.59)
d vg =icl =0 nD2 1 + s2DLC
2
DCM control-to-clamp-voltage transfer function Gvcd,dcm is obtained through the small-

signal averaged switch model of the DCM flyback auxiliary converter, depicted in Fig. 6.22.
Switching cell
i1 i2
+ +
v1 v2 nig niR
+
2
icl vC + vg/n -R/n
+ -
C
vL L
iL
Fig. 6.22. Averaged switch model of the DCM flyback auxiliary converter
The control-to-clamp-voltage transfer function Gvcd,dcm of the DCM flyback auxiliary

converter is calculated in the Appendix D.2 and is repeated here:

vc f1 (1 − h2 ) + j2 (r1 + sL)
Gvcd,dcm = = (6.60)
d vg =icl =0 (1 − kC )(1 − h2 ) − (r1 + sL)(gc − sC)
where the coefficients in (6.60) are obtained by differentiating the input voltage v1 and
the output current i2 of the averaged switch network:
vg 2LiL vg
v1 = (1 − d)vC + d − = γ1 (vg , vC , iL , d) = kg vg + kC vC + r1 iL + f1 d
n ndTs vC

∂γ1 (vg , VC , IL , D) D 2LIL
kg = = −
∂vg
v =V n nDTs VC
g g
∂γ1 (Vg , vC , IL , D) 2LIL Vg
kC = = (1 − D) +
∂vC
v =V nDTs VC2 (6.61)
C C
∂γ1 (Vg , VC , iL , D) 2LVg
r1 = =−
∂iL
i =I nDTs VC
L L
∂γ1 (Vg , VC , IL , d) Vg 2LIL Vg
f1 = = −VC + +
∂d
d=D n nD2 Ts VC
and:
d2 Ts vc
i2 = iL − = γ2 (vC , iL , d) = gC vC + h2 iL + j2 d
2L
D2 Ts

∂γ2 (vC , IL , D)
gC = = −
∂vC
v =V 2L
c C (6.62)
∂γ2 (VC , iL , D)
h2 = =1
∂iL
iL =IL

∂γ2 (VC , IL , d) DTs VC
j2 = =−
∂d
d=D L
The small-signal equivalent model of the DCM flyback auxiliary converter is depicted
in Fig. 6.23.
+ v1 - + v2 -
+
+
-
i1 gCvC i2
kgvg kCvC r1iL f1d
+ iC h2iL nig niR
iL +
2
icl vC C + j2d - vg/n -R/n
vL L
Fig. 6.23. Small-signal AC model of DCM flyback auxiliary converter
The use of current-mode control simplifies the control synthesis by essentially remov-
ing the pole associated with the inductor dynamics and making the inductor current a
controlled quantity. This is, however, more important with the CCM auxiliary flyback con-
verter where the inductor pole appears at lower frequencies, than with the DCM auxiliary
flyback converter, where the inductor pole is already shifted to high frequency comparable
to the switching frequency.
From the practical viewpoint, increase in the clamp capacitor voltage should result
in larger duty cycle as to regenerate more charge from the clamp, i.e. the controller
should be built around a non-inverting amplifier. To alleviate the control design, current-
mode control of the auxiliary converter can be implemented on a standard SMPS control
VCL
Clock
R1 E/A
+ CS S
Gate
- - Drive
R2 R
R4 ISW +
R3 C4
+ VRef
Fig. 6.24. Current-mode control of the auxiliary converter

ve
i<0
2tblVcl/Ts2
Tm
-2tblVcl/Ts2
i>0
Fig. 6.25. Average voltage error ve of the SICAM with active capacitive voltage clamp
chip, like shown in Fig. 6.24, where both the inverting and non-inverting pin of the error
amplifier are accessible to build a non-inverting compensator.
Audio distortion in SICAMs with active capacitive voltage clamp

The distortion mechanism in the SICAM with active capacitive voltage clamp is very
similar to the one in the conventional Class D amplifiers [80]. The only difference is that
during the blanking time periods tbl the load voltage is equal to the clamp capacitor
voltage Vcl and the average voltage error ve , shown in Fig. 6.25 is:
( − 2tbl Vcl , i > 0
0
Ts2
ve = (6.63)
2tbl Vcl
, i0 < 0
Ts2
Fourier coefficients of the voltage error in (6.63) are given by the following equations:
a0 = 0
an = 0
(6.64)
tbl sin(n π2 ) tbl (−1) n
bn = −2 Vcl =2 Vcl
Ts2 n π2 Ts2 (2n − 1) π2
and the Total Harmonic Distortion (THD) of the open-loop SICAM power stage with
active capacitive voltage clamp is:
v
uNmax
uX
t b2i
i=2
T HD = (6.65)
4tbl Vcl
M Vs −
πTs2
6.3 Output impedance of isolated SICAMs 169
THD of SICAM with active capacitive voltage clamp

6
THD [%]
3
0
0 50 100 150
Output power Po [W]
Fig. 6.26. THD of SICAM with active capacitive voltage clamp
The presence of filter ripple current causes the THD of the SICAM to decrease as
the output current i.e. the modulation index M decreases. This is result of the fact that
within one switching period Ts2 the switch current changes the polarity, thus effectively
cancelling the voltage error of two subsequent load current commutations and giving no
average voltage error. Therefore, the reduced THD of the SICAM at low modulation
indexes can be taken into account the same way as in the conventional Class D amplifier
[80].
THD simulation of the SICAM with active capacitive voltage clamp operating in open
loop with constant output stage switching frequency fs2 = fc2 = 300 kHz and modulation
signal of fm = 1 kHz is shown in Fig. 6.26. In the simulation secondary-side voltage is
Vs = 45 V, clamp voltage is Vcl = 50 V and blanking time is tbl = 75 s.
6.3 Output impedance of isolated SICAMs

One of the distinct advantages of the conventional amplifier solution with isolated SMPS
and Class D audio power amplifier connected via DC-bus is that the bulky decoupling
capacitors on the DC-bus act as a very low impedance for a wide range of frequencies.
This has a very positive effect on the audio performance of the Class D audio power
amplifier, where the closed-loop gain additionally decreases the output impedance of the
Class D audio power amplifier to provide very high damping ratio, being a ratio of the
load to output impedance.
The situation with SICAM is much worse, since there is no DC-bus with low impedance
on the secondary side. Simplified schematic of SICAM up to the output of the bidirec-
tional bridge, with an equivalent scheme of the transformer T R and switch impedances
ZSW 1 , ZSW 2 referred to the secondary side, is shown in Fig. 6.27. Low impedance voltage
source can only be found on the primary-side DC-bus with energy storage capacitors,
which for the purpose of the following discussion will be regarded as ideal voltage source
vin . From that point up to the output of the bidirectional bridge and further to the loud-
speaker there are several impedances on the current path which create certain voltage
drops. Even more, due to the finite impedances of the transformer and the switches,
at each switching instant there are significant oscillations in the bridge output voltages
as a result of reactive energy circulation between inductive and capacitive elements in
transformer and active switches.
TR
2 2 2
n ZSW1 n Rp n Lpl Lsl Rs ZSW2
2 +
2
n vin n Lm vo
Fig. 6.27. Simplified schematic of SICAM for determining output impedance
The resultant output impedance looked from the output of the bidirectional bridge is:
q
p
Zout,bb = n2 · 2
ZSW 2 2 2 2 2 2
1 + (Rp + ω Lpl ) || n ω Lm + 2
ZSW 2 2 2
2 + (Rs + ω Lsl ) ≈
p
2 2
≈ n4 ZSW 2 2 2 2 2
1 + ZSW 2 + (n Rp + Rs ) + ω (n Lpl + Lsl ) ))
(6.66)
where n = N2 /N1 is the transformer transfer ratio, ZSW 1 and ZSW 1 are the switch
impedances in the input and the output stage respectively, Rp and Rs are the resis-
tances of the primary and secondary winding of the transformer, Lpl and Lsl are the
leakage inductances of the primary and secondary winding of the transformer and Lm is
the magnetizing inductance of the transformer.
Especially problematic part of the output impedance is the secondary-side leakage in-
ductance of the transformer Lsl , which creates problems with the switching of the output
stage and commutation of the load current with both the safe-commutation switching
strategies and load voltage clamps. Reducing the transformer leakage inductance is pos-
sible through interleaving of the transformer windings and increasing the height of the
winding window, to increase the magnetic reluctance of the leakage magnetic path.
From audio performance perspective, the finite output impedance of the input stage
and transformer creates additional problems in the case of multichannel SICAM, where
all the channels share the same input stage and transformer primary, as already described
in Section 5.3.5. In this case, the common coupling point of all audio channels is by no
means a low impedance point, so there can be significant channel crosstalk caused by
voltage drops created from the channel currents flowing through the input stage switch
impedances ZSW 1 , primary winding resistance Rp and leakage inductance Lpl on Fig. 6.27.
6.4 Power losses and efficiency calculation in SICAMs

In the following sections the efficiency of different SICAM approaches will be compared
through calculating the power losses in different stages. Calculations will be focused on the
case with half-bridge input stage and single-ended bidirectional output stage, as showed
previously in Fig. 6.13 and Fig. 6.19. Extending the presented equations for other topolo-
gies is straightforward and is not reconsidered herein.
6.4.1 Current and voltage levels in SICAMs
Each audio design starts with some specifications, and the most important are:
• Input voltage range - AC mains (Ex. Vin,rms = 200 − 250 V)
• Sinusoidal output power (Ex. Po = 100 W)
• Load impedance (Ex. Z = R = 8 Ω)
6.4 Power losses and efficiency calculation in SICAMs 171
The RMS output voltage Vo,rms is calculated using the output power Po and the load
impedance Z = R:
p
Vo,rms = Po R (6.67)
The peak value of the output voltage for sinusoidal waveform is:
√ p
Vo,pk = 2 · Vo,rms = 2Po R (6.68)
The peak value of the output (load) current for sinusoidal waveform is:
Vo,pk
Io,pk = (6.69)
R
Assuming sinusoidal audio signal reference, the RMS value of the load current is found
to be:
Io,pk
Io,rms = √ (6.70)
2
and the average value of the rectified sinewave current is:
2
Io,av = Io,pk (6.71)
π
In order to determine the maximum voltage on the secondary side of the transformer
V2,max , peak output voltage Vo,pk is divided by the maximum achievable modulation index
Mmax (limited by, for example, the requirement for avoiding simultaneous switching of
the input and the output stage in the optimized PWM in Section 7.2.2 or performance
constraints in self-oscillating modulators in Section 7.3) plus additional voltage ∆V2 for
compensating voltage drops throughout the switches, transformer and output filter para-
sitics::
Vo,pk
V2,max = + ∆V2 (6.72)
Mmax
On the primary side, the minimum voltage on the DC-bus is:
√
Vdc,min = 2 · Vin,min − ∆Vdc (6.73)
where Vin,min is the minimum RMS input voltage and ∆Vdc is the allowed voltage drop
on the DC-bus at maximum output power.
Due to the half-bridge topology of the input stage, only half of that DC-bus voltage is
applied across the primary winding, resulting in:
Vdc,min
V1,min = (6.74)
2
The transformer voltage turns ratio n thus becomes:
N1 V1,min
n= = (6.75)
N2 V2,max
After calculating the load quantities, voltage levels and transformer turns ratio, all
SICAM currents can be calculated by going backwards from the filter to the input termi-
nals.
The peak-to-peak filter ripple current flowing through the output filter capacitor can
be found by multiplying the slope of the filter ripple current (V2 −vo )/Lf by the on-time of
the secondary side switches. Taking into account the relation between the output voltage
and the duty cycle in (6.26), this gives the following peak value for the filter ripple current
of a single-ended amplifier:
(V2 − vo ) · DTs V2 D(1 − D) (V 2 − vo2 )
If r,pk = = = 2 (6.76)
2Lf Lf fs2 4V2 Lf fs2
which is depicted in Fig. 6.28, normalized with the peak load current for the specific case,
and has maximum for D = 0.5 i.e. at zero output voltage Vo = 0 as mentioned in [14].
Normalized filter ripple current Ifr,rms, Ifr,av/Io,pk

Normalized peak filter ripple current Ifr,pk/Io,pk
0.16 0.1
0.14 RMS I
0.08 fr,rms
0.12
0.1 0.06
0.08 Average Ifr,av
0.06 0.04
0.04
0.02
0.02
0 0
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
Duty cycle D Modulation index M
Fig. 6.28. Relationship between the duty cycle and Fig. 6.29. Relationship between the modulation in-
the normalized peak filter ripple current dex and the normalized average and RMS filter ripple
current
Assuming linear character of the filter ripple current, giving it a triangular form with
constant peak value If r,pk = const, its RMS value is:
If r,pk
If r,rms = √ (6.77)
3
and its average value is:
If r,pk
If r,av = (6.78)
2
In the case of sinusoidal output voltage vo , with modulation index M and modulation
angular frequency ωm given with the following equation:

2π
vo = Vm sin(ωm t) = M V2 sin t (6.79)
Tm
the RMS value of the filter ripple current in (6.77) by using (6.76) becomes:
s Z Tm s Z Tm 2
1 2 1 If r,pk
If r,rms = if r,rms dt = dt =
Tm 0 Tm 0 3
s
Z Tm
V2 1 [1 − M 2 sin2 (ωm t)]2
= dt =
4Lf fs2 Tm 0 3
s
2 2
r
[1 − M2 + M2 cos(2ωm t)]2
Z Tm
V2 1 V2 1 − M2 M4
= dt = +
4Lf fs2 Tm 0 3 4Lf fs2 3 8
(6.80)
Tm Z Tm Z Tm
1 1 If r,pk V2
Z
If r,av = if r,av dt = dt = [1 − M 2 sin2 (ωm t)]dt =
Tm 0 Tm 0 2 8Tm L f fs2 0
Z Tm
M2 M2 (2 − M 2 )V2

V2
= 1− + cos(2ωm t) dt =
8Tm Lf fs2 0 2 2 16Lf fs2
(6.81)
After calculating the filter ripple current RMS and average value, the RMS and average
values of the secondary-side transformer current and output stage switch current can
be calculated by adding together the corresponding values of the load and output filter
current. Output stage switch current is:
q
2
Isw2,rms = I2,rms = Io,rms + If2r,rms (6.82)

Isw2,av = I2,av = Iout,av + If r,av (6.83)
The RMS value of the reflected load and filter ripple current I1,rms is therefore:
I2,rms
I1,rms = (6.84)
n
and the average primary current is:
I2,av
I1,av = (6.85)
n
The RMS value of the magnetizing current Im,rms , assuming linear magnetization, is:
Im,pk
Im,rms = √ (6.86)
3
Im,pk
Im,av = (6.87)
2
where the peak value of the magnetizing current Im,pk is:
Φmax V1,max · DTs
Im,pk = = (6.88)
Lm 2Lm
Current flowing through the input stage switches represents a sum of the reflected load
and filter ripple current and the transformer magnetizing current. Thus, the input stage
switch RMS current is:
2 2 2
Isw1,rms = I1,rms + Im,rms (6.89)
Isw1,av = I1,av + Im,av (6.90)
All these quantities will be used for calculating the power losses in the SICAM stages
and overall efficiency.
6.4.2 Power losses in SICAM components and stages

Mains rectifier and input energy storage capacitors
The calculation of power losses in the mains rectifier and the input energy storage capaci-
tor is rather straightforward when knowing the characteristics of the components and the
corresponding current levels, determined in Section 3.1.
The losses in the full-bridge mains-rectifier are calculated by multiplying the diode
forward voltage drop Vf d with the average charging current of the input energy storage
capacitors Idc :
PCin = 2Vf d Idc (6.91)
where the average charging current of the input energy storage capacitors Idc is:
2
Idc = ichg tc (6.92)
Tac
and ichg is given by (3.6).
The losses in the input energy storage capacitors Cin are dissipated in the internal
equivalent series resistance (ESR) of the electrolytic capacitors when the capacitor ripple
current ICin flows through them:
2
PCin = 2(ESR)ICin,rms (6.93)
where the RMS value of ICin is given in (3.8) with the RMS capacitor charging current
Ichg,rms given in (3.7) and RMS capacitor discharging current equal to the input stage
switch RMS current Idis,rms = Isw1,rms from (6.89). Factor 2 in (6.93) stands for the two
capacitors in the half-bridge input stage configuration.
Input stage
As already mentioned before, input stage is the primary-side switching part of a SICAM
with non-modulated transformer voltages, which operates with constant duty cycle equal
to D = 0.5.
Looking closely at the input stage conduction losses, two cases from all possible current
conduction situations are very simple:
1. Primary current has the same direction throughout one switching period - assuming
that the load current keeps the same direction, this corresponds to the situation where
the output stage is not performing any switching for load current commutation during
that interval; and
2. Primary current reverses after D=0.5 - switching of the input stage happens simul-
taneously with the switching of the output stage, therefore the reflected load current
changes the direction on the primary side.
All other cases fall in between these two limit cases.
In the first case, if the primary current is conducted through the upper MOSFET in the
input stage switching leg during 0 < t < DTs , for DTs < t < Ts the same primary current
is conducted by the lower freewheeling diode. In the second case, if for 0 < t < DTs
primary current is flowing through the upper MOSFET then for DTs < t < Ts current
is flowing through the lower MOSFET, or if for 0 < t < DTs primary current is flowing
through the lower freewheeling diode then for DTs < t < Ts current is flowing through the
upper freewheeling diode. These latter two cases are probably two extremes in terms of
power dissipation in the switching components of the input stage and neither is dominant,
so only the first case with constant direction of the primary current will be discussed.
The conduction loss in a single MOSFET, conducting the primary current for a half
of the switching interval is:
1 2
Pcon1,T = RDS Isw1,rms (6.94)
2
and in the diode for the same time:
1
Pcon1,D = VF Isw1,av (6.95)
2
where RDS is the on-resistance of the MOSFET and VF is the forward voltage drop of the
MOSFET body diode (or discrete diode, if used) at current of Isw1,av .
Total conduction losses in the input stage represent sum of (6.94) and (6.95):
1 2 1
Pcon1 = Pcon1,T + Pcon1,D = RDS Isw1,rms + VF Isw1,av (6.96)
2 2
Switching losses in the input stage at high switching frequencies and with the voltage
levels in excess of several hundreds of Volts can be quite high. MOSFETs’ switching
waveforms and power losses are dependent on several nonlinear parameters at the same
time: the output and input parasitic capacitance of the MOSFETs, Miller charge, inserted
dead time, as well as the magnetizing and reflected load current. The same problem can
be solved in an approximative way, if the losses associated with the non-zero voltage and
current during transition are separated from the losses arising from the finite parasitic
output capacitance.
First the switching transitions will be analyzed and all relevant time intervals given
in Fig. 6.30 will be determined, for the case where the gate drive vg of both MOSFETs
continuously changes between 0 V and +VG using some semiconductor MOSFET driver.
Because of the specified positive current direction, when switching off the upper MOSFET
load current I commutates to the lower freewheeling diode. This leads to time intervals
equations similar to those given in [14].
The time delay before rise tdr is found by solving the following exponential equation:
t
−R
vg = −VG e G Ciss + VG
I (6.97)
t = tdr =⇒ vg = VGS,th +
gf s
which results in:
VG
tdr = RG Ciss ln I
(6.98)
VG − VGS,th − gf s
The time delay before fall tdf is found by solving the following exponential equation:
t
−R
vg = VG e G Ciss
I (6.99)
t = tdf =⇒ vg = VGS,th +
gf s
which results in:
VG
tdf = RG Ciss ln I
(6.100)
VGS,th + gf s
Vin
CGD CDS
RG
vg
VDS
+ Vin
CGS
VG I
I VG vg I/gfs
VGS, th
RG
+
VG tcr tcf
tdr tr tdf tf
0
a) b)
Fig. 6.30. Switching transitions of the upper MOSFET in a switching leg driven with 0, VG : a) schematic and
b) waveforms
tdr and tdf represent the time delays from the moment the transition is initiated until
the moment the corresponding transition is actually started and is visible as a change
in the MOSFET voltage. It is clear from the equations that these times depend on the
electrical characteristics of the MOSFET (Ciss , VGS,th , gf s ), current I being switched, as
well as the driving circuitry (VG , RG ).
The rise time tr and the fall time tf on the other hand represent the time needed
to accomplish the desired transition of the switch drain-source voltage and are equal to
the time the gate driver current ([VG , 0] − vg )/RG needs to charge/discharge the Miller
capacitance CGD :
QGD RG
tr = I
QGD RG (6.101)
tf =
VGS,th + gIf s
tcr and tcf represent the time intervals for the switch current to rise/fall from 0/I to
I/0 correspondingly. The current rise time interval tcr is found by solving the following
exponential equation:
t
−R
vg = (−VG + VGS,th )e G Ciss + VG
I (6.102)
t = tcr =⇒ vg = VGS,th +
gf s
which results in:
VG − VGS,th
tcr = RG Ciss ln (6.103)
VG − VGS,th − gIf s
The current fall time interval tcf is found by solving the following exponential equation:
I − R Ct
vg = (VGS,th + )e G iss
gf s (6.104)
t = tcf =⇒ vg = VGS,th
which results in:

I
VGS,th + gf s
tcf = RG Ciss ln (6.105)
VGS,th
In one slightly different case, pulse transformers are used to transfer the driving pulses
to the gates of the MOSFETs and the gate drive voltage continuously changes the sign
±VG . This leads to different equations for the switching time intervals from those presented
above and given in [14]. However, it should be noticed that due to the parasitic resistance
and leakage inductance of the pulse transformer and the tracks used to connect it with
the associated gate resistor and gate/source pins of the MOSFET, real switching time
intervals are likely to be somewhat larger. Therefore, calculations made here tend to be
approximative to a certain degree. The switching waveforms are given in Fig. 6.31.
Vin
CGD CDS
RG
vg
VDS
+ Vin
CGS
VG I
I VG vg I/gfs
VGS, th
RG
-VG
+
VG tcr tcf
tdr tr tdf tf
0
a) b)
Fig. 6.31. Switching transitions of the upper MOSFET in a switching leg driven with ±VG : a) schematic and
b) waveforms
The time delay before rise tdr is found by solving the following exponential equation:
t
−R
vg = −2VG e G Ciss + VG
I (6.106)
t = tdr =⇒ vg = VGS,th +
gf s
which results in:
2VG
tdr = RG Ciss ln I
(6.107)
The time delay before fall tdf is found by solving the following exponential equation:
t
−R
vg = 2VG e G Ciss − VG
I (6.108)
t = tdf =⇒ vg = VGS,th +
gf s
which results in:
2VG
tdf = RG Ciss ln I
(6.109)
VG + VGS,th + gf s
The rise time tr and the fall time tf on the other hand represent the time needed to
accomplish the desired transition of the switch voltage and are equal to the time the gate
driver current (±VG − vg )/RG needs to charge/discharge the Miller capacitance CGD :
QGD RG
tr =
QGD RG (6.110)
tf =
VG + VGS,th + gIf s
The current rise time interval tcr is found by solving the following exponential equation:
t
−R
vg = (−VG + VGS,th )e G Ciss + VG
I (6.111)
t = tcr =⇒ vg = VGS,th +
gf s
which results in:

VG − VGS,th
tcr = RG Ciss ln (6.112)
The current fall time interval tdf is found by solving the following exponential equation:
I − R Ct
vg = (VG + VGS,th + )e G iss − VG
gf s (6.113)
t = tcf =⇒ vg = VGS,th
which results in:

I
VG + VGS,th + gf s
tcf = RG Ciss ln (6.114)
VG + VGS,th
As already mentioned, switching losses are result of two effects: the first effect is the fi-
nite voltage and current rise and fall time intervals associated with real switching elements,
and the second one is the charging effect of the parasitic and nonlinear drain-to-source ca-
pacitance CDS of the MOSFETs. Assuming sinusoidal load current, switch average value
Isw1,av can be used to calculate the switching loss during one period of the modulating
signal.
When the reflected load current to the primary side is positive, from the topology of the
half-bridge in the input stage it is clear that there will be one hard turn-on and turn-off
for the upper MOSFET and one soft and lossless (ZVS) turn-on and turn-off of the lower
MOSFET, due to the clamping action of the freewheeling diode. Hard switchings will cause
switching loss, since the voltage across the switch and current through the switch are non-
zero for a short time interval (tr + tcr ) during rise and (tf + tcf ) during fall. The switching
losses due to the finite time transitions of the MOSFETs are found by multiplying the
area under the curve vsw · isw (triangle within a linear approximation) representing the
switching loss per cycle with the switching frequency fs1 of the half-bridge:
1
Psw1,tr = fs1 Vin,max Isw1,av (tr + tcr + tf + tcf ) (6.115)
2
The second term of the switching losses corresponding to the parasitic drain-to-source
capacitance CDS can be found by noticing that every switching period each of the MOS-
FETs’ parasitic output capacitances has been charged and discharged. Taking into account
the nonlinear nature of the output capacitance CDC (VDS ) with changing drain-source volt-
age VDS , the energy lost during these transitions in an ordinary MOSFET is given by the
following equation [73]:
2 1 3
E = Coss Voss
2
VDS
2
(6.116)
3
However, due to the altered structure of some newer Power MOSFET structures like,
for example, the p/n column structure of CoolMOS, the resulting output capacitance CDS
is even more nonlinear i.e. starting from a significantly higher value at VDS = 0 V, break-
ing at around VDS = 50 V and going much lower at higher voltages than compared to
the ordinary technologies.
p In these cases the output capacitance cannot be approximated
simply as CDS = Coss Voss /VDS , so some other way of calculating the stored energy in
the output parasitic capacitance must be found. Fortunately, the manufacturer is pro-
viding a fixed energy related output capacitance Co,er , which eventually gives the same
stored energy for charging to 80% of the maximum reverse voltage as the variable output
capacitance Coss . This energy related output capacitance can be used for calculating the
switching losses:
1 2
E = Co,er VDS (6.117)
2
The associated switching losses due to the finite parasitic output capacitance of the
MOSFETs in the case of a half-bridge input stage are:
2
Psw1,cds = 2fs1 E1 = fs1 Co,er VDS (6.118)
Total switching losses in the input stage are simply the sum of (6.115) and (6.118):
Psw1 = Psw1,tr + Psw1,cds (6.119)
Total losses in the input stage are found by summing the conduction and switching
losses in (6.96) and (6.119):
Ptot1 = Pcon1 + Psw1 (6.120)
Transformer design and losses

Transformer design is performed at the switching frequency of the input stage fs1 . Some
of the transformer quantities have been already determined in the previous sections:
• transfer (turns) ratio n = V1 /V2 = N1 /N2
• primary RMS current (6.84): I1,rms
• output stage RMS current (6.82): Isw2,rms √
• secondary winding RMS current from (6.82): I2,rms = Isw2,rms / 2
There are several different methods for design of magnetic components, like those based
on the area product Ap , core geometry Kg and maximum flux density ∆Bmax (saturation-
limited design), but only the design based on the minimum of total loss Pcu + Pf e yields
the most efficient transformer.
The design of the transformer according to the minimum of total loss approach starts
by selecting the magnetic core based on the expected transformer losses in amount of, for
example, 1% of the total transformed power and for simplicity neglecting the losses in the
output stage and in the output filter:
PT R,exp = 0.01Pout (6.121)
When choosing the appropriate magnetic core, one should reconsider the power capac-
ity which the transformer wound on that core can handle, which is in fact dependant on
its thermal resistance Rth as a quantity expressing the capability of the magnetic core
to exchange the heat with the ambient and the allowed temperature rise ∆T over the
ambient temperature, which depends primarily on the magnetic material properties.
In order to determine the number of primary turns N1 , magnetic core losses Pf e and
copper losses Pcu are calculated as a function of N1 and their sum is subsequently opti-
mized.
Core losses Pf e at certain frequency are given by the following equation [60]:
Pf e = kf e (∆B)β Ae lm = kf e (∆B)β Vm = pf e Vm (6.122)
where coefficients kf e and β are properties of the magnetic material, ∆B is the magnetic
induction (flux density) swing, Ae is the equivalent cross area of the core perpendicular
to the direction of the magnetic field, lm is the mean magnetic path length, pf e is the
characteristic core loss (core losses per unit volume) and Vm is the magnetic core volume.
Magnetic induction swing can be determined by noting that during the on-time of the
upper MOSFET switch in the half-bridge input stage, the magnetic induction B increases
twice the value of the magnetic inductance swing ∆B:
λ V1 DTs
∆B = = (6.123)
2N1 Ae 2N1 Ae
where λ is flux linkage and N1 is the number of primary turns.
Equation (6.123) is put into (6.122) to obtain:
β
V1 DTs
Pf e = kf e Vm (6.124)
2N1 Ae
Coefficients kf e and β are determined from the diagram of the specific power losses
pf e = pf e (f, ∆B) for the corresponding magnetic material at the desired switching fre-
quency, by taking two points with different flux density swing ∆B and fitting the curve
(6.124). This procedure results in the following equations for the coefficients:
ln (p∆B ∆B1

fe
2
)/(p fe )
β=
ln (∆B2 )/(∆B1 )
(6.125)
p∆B
fe
1
kf e =
∆B1β
If the temperature of the core in operation is not known in advance because of, for
example, ambient temperature variations, it makes sense to average the results of kf e and
β for two different temperatures commonly given in the datasheet.
Copper losses are easily calculated using [60]:
ρ(M LT )N12 Itot

2
Pcu = kac (6.126)
Wa ku
where kac is the lumped increase of the DC resistance due to skin and proximity effect
(the primary and the secondary side together), ρ = 23 · 10−9 Ωm is the characteristic
resistance
P of copper, (MLT) is the mean length of a turn, Wa is the core window area,
Itot = Nj Ij /N1 is the total current referred to the primary, ku is the filling factor of
the core window area. Since the AC resistance factor kac strongly depends on the actual
arrangement of windings, it can be initially set to kac = 3 in the provisional calculation
for selecting the primary number of windings N1 , to account for extra resistance when
the copper winding is exposed to an alternating electromagnetic field. Filling factor is
usually chosen to be around ku = 0.5, due to the additional insulation layers between the
windings to fulfil the safety requirements. The actual values for the AC-resistance of the
particular windings kac1 and kac2 can be determined after the initial transformer design is
done and the calculation of copper losses in (6.126) can be refined for the next round of
the design process.
Total transformer losses PT R equal to:
PT R = Pf e + Pcu = Pf e + Pcu1 + Pcu2 (6.127)
Building a center-tapped transformer presents some unique challenges in determining

the allowed volume for the primary winding and each of the secondaries windings, which
eventually affects the distribution of the copper losses. Using the results of the copper loss
optimization in [60], the recommended winding area is:
√
N 1 I1 N 1 I1 2
α1 = = 1 =√ ≈ 0.41
N1 I1 + 2N2 I2 N1 I1 + 2N1 I1 √2 2+2
(6.128)
N 2 I2 N 2 I2 1
α2 = = √ =√ ≈ 0.29
N1 I1 + 2N2 I2 N2 I2 2 + 2N1 I1 √12 2+2
The result in (6.128) is logical, since both secondary windings in average conduct
current for half of the time and optimally each of them should occupy less volume then
the continuously conducting primary winding. On the other hand, the RMS value of the
current
√ in each of the secondaries is lower than the output stage current only for a factor
of 2, so both secondaries must occupy a little bit more space than the single primary
winding.
Graph of the transformer power losses, like the one given in Fig. 6.32, can be used to
select the optimal number of primary turns N1 .
Primary number of turns N1 can be chosen slightly away from the optimal number of
turns, just to obtain secondary windings with an integer number of turns N2 or to account
for some additional copper or core losses.
After the number of turns in both windings have been determined, it is decided about
the actual arrangement of the windings in a way that reduces proximity losses and stray
fields, usually by interleaving the windings and maybe even using Litz wire. Afterwards it
is possible to determine the AC resistance factor kac = Rac /Rdc using the Dowell’s curves
for eddy current and proximity losses in [82], [60] to calculate copper losses in the primary
and secondary windings:
ρ(M LT )N1 2
Pcu1 = 4kac1 I1,rms
πd21
(6.129)
ρ(M LT )N2 2
Pcu2 = 4kac2 I2,rms
πd22
Core losses Pfe, copper losses Pcu and total losses Pfe+Pcu
3
Pfe
Pcu
2.5 Pfe+Pcu
Losses P [W] 1.5
0.5
0
0 20 40 60 80 100
Number of primary turns N1
Fig. 6.32. Core losses Pf e , copper losses Pcu and total losses PT R as a function of the primary number of turns
N1
Output stage
To simplify the output stage analysis, positive direction of the load current throughout
the switching period will be adopted, like in the case of the input stage. One pair of
series-connected common-source MOSFETs is conducting for half of the period followed
by conduction of the other pair of series MOSFETs supporting the same load current
direction for the other half period.
When the load current direction is fixed during one switching period, in the bidirec-
tional switch one MOSFET is conducting the load current in the forward direction and
the other one is conducting the current in reverse direction, either through the MOSFET
channel or through the parasitic diode. Therefore it is difficult to calculate exactly the
conduction losses, but analysis can be simplified by looking at the voltage drop across
the reverse conducting MOSFET during one half-period of the audio output voltage at
maximum output power and neglect the switching action, as shown in Fig. 6.33.
VSD
VD
D21 D22
VSD Vd, min
ISDRDS t
ISD T/2
tsd/2 tdd tsd/2
T21 T22
t1
a) b)
Fig. 6.33. a) Bidirectional switch and b) Voltage drop across the reverse conducting MOSFET
Commutation of the load current from the N channel of the MOSFET to the PN
junction of the parasitic diode occurs at some minimum current level ISD,min , when the
corresponding diode voltage drop is Vd,min as shown in Fig. 6.33:
Vd,min = RDS ISD,min (6.130)

Through inspection of the V-I curves of the MOSFET parasitic diode (or an antiparallel
discrete diode) and knowing the on-resistance of the MOSFET N channel, the minimum
current ISD,min can be found.
Time intervals tsd and tdd corresponding to the conduction intervals of the N channel
of the MOSFET and the parasitic diode can be found by noting that t1 is the time instant
when the load current reaches Io = ISD,min :
ISD,min = Io,pk sin (ωm t1 )

1 ISD,min (6.131)
t1 = arcsin
2πf Io,pk
The corresponding duty cycles of the N channel of the MOSFET Dsd and of the para-
sitic diode Ddd are:
2tsd 4t1
Dsd = =
T T
(6.132)
2tdd 2( T − 2t1 )
Ddd = = 2
T T
The conduction losses in the MOSFETs are therefore calculated as a sum of fixed
losses in the forward conducting MOSFET as well as the losses in the other MOSFET
distributed between the N channel and the PN-junction of the parasitic diode (neglecting
dynamic resistance RD ):
2 2

Pcon2 = RDS Isw2,rms + RDS Isw2,rms Dsd + VF Isw2,av Ddd =
2
(6.133)
= RDS Isw2,rms (1 + Dsd ) + VF Isw2,av Ddd
Switching losses in SICAMs with load clamps
While the mechanism of creating conduction losses is the same in both the SICAM with
safe-commutation switching strategy and the SICAM with load clamp, switching losses
are very different because of the essential differences in the switching methods. Therefore,
they will be analyzed separately in the aforementioned two cases.
On the other hand, it will be assumed that the leakage inductances of the secondary
side transformer windings can be neglected, so the energy stored in them is very small.
This is very important, since whenever there is hard switching of the output stage with
an abrupt interruption of the load current path through the bidirectional switch, the
energy stored in the leakage inductances must be released in some way, which is usually
done by some violent oscillatory actions between the leakage inductance and parasitic
capacitance of the MOSFETs, creating losses on the resistive elements in the circuit
or through avalanching of the MOSFETs, if the voltage blocking rating of the active
devices is inadequate. This emphasizes the need for reducing the secondary-side leakage
inductance of the transformer through interleaving of windings and selecting transformer
magnetic cores with higher winding windows, choosing control methods which guarantee
soft-switching of the output stage for most of the time or control methods where the
load current continues to flow through another secondary winding in the SICAMs with
central-tapped transformer secondary and tightly coupling these two secondary windings
to reduce their leakage inductances. In practical implementations, in most of the cases
there will be special RC-snubbers across the transformer secondary to handle the stored
magnetic energy in the leakage inductance during the switching instants.
Switching of the bidirectional switches in the output stage of a SICAM with load
clamps represents hard-switching, where a blanking (dead) time is inserted between the
outgoing and the incoming switch during which load current is diverted into the clamp.
Similar to the input stage, during the switching of the output stage there are two lossy
mechanisms: one corresponds to the finite transition times during which both current
and voltage are non-zero and the other one is the energy stored in the parasitic output
capacitances of the MOSFETs, which is eventually dissipated when the MOSFETs are
turned on.
The switching process in the output stage is also similar to the one described for the
input section, with several minor differences:
• Both gate driving circuits for the upper and lower bidirectional switch are driving two
input gate capacitances Ciss in parallel, giving a resultant gate capacitance of 2Ciss .
This eventually result in longer delays tdr , tdf and longer current rise/fall time intervals
tcr , tcf ;
• In a bidirectional switch with two common-source connected MOSFETs, one of the
MOSFETs always has a forward biased parasitic diode, so there are no losses associated
with the switching of that particular MOSFET neither due to the switching transition
nor due to the stored charge in the output capacitance;
• Regarding the previous remark, gate driving circuitry should only discharge or charge
a single Miller capacitance QGD of the MOSFET doing the voltage blocking, i.e. the
voltage rise/fall time intervals tr , tf for a 4QSW stay eventually the same as for a single
MOSFET.
It should be noted, however, that the aforementioned characteristics are pertinent to the
bidirectional switch with common-source connection of the individual MOSFETs. These
conclusions and the calculation presented below are likely to be different for every other
combination of switches, but the development will always follow the same lines.
The switching losses due to finite time transitions Psw2,tr of two 4QSWs, with blocking
voltage in excess of 2V2,max will amount to:
1
Psw2,tr = 2· fs2 (2V2 )Isw2,av (tr +tcr +tf +tcf ) = 2fs2 V2 Isw2,av (tr +tcr +tf +tcf ) (6.134)
2
where the switching time intervals are given with the same equations like for the input
stage section, with two times larger input capacitance Ciss and I = Isw2,av .
The switching loss mechanism regarding the stored charge in the finite parasitic output
capacitances of the MOSFETs CDS becomes more complex in the case of the bidirectional
bridge in the output stage. These losses are created in two ways:
• When the output stage switches, which is similar to the case of conventional Class D
audio power amplifiers operating from a DC power supply, and
• When the input stage switches, which causes reversal of voltage polarity across the
HF-link and thus reversal of the voltage across the blocking pair of MOSFETs.
The latter effect results in additional switching losses associated with discharging one
and charging the other parasitic output capacitance CDS of the MOSFETs in the same
blocking bidirectional switch when the input stage has switched.
When looking at the switching losses in the output stage of a SICAM with a load clamp
and caused by the switching of the output stage itself, these additional switching losses
due to parasitic output capacitance of the bidirectional switches (4QSWs) are observed
during the dead time periods when the voltage across the load and the output filter i.e.
the bridge voltage is clamped to the capacitive clamp voltage. The polarity of the bridge
voltage vbr depends on the load current io direction and for example in Fig. 6.19 for io > 0
it is vbr = −Vcl and for io < 0 it is vbr = Vcl . Due to this, when one of the 4QSWs is
turned on and has zero voltage across it, the other one has 2V2,max across it; but as soon
as both 4QSWs are turned off and bridge voltage is clamped to ±Vcl , the blocked voltages
of 4QSWs will become VDS = Vcl ± V2 during the whole dead time, if the load current
keeps the same direction. One possible switching sequence of the output stage in a SICAM
with load clamp, together with the drain-source voltage VDS of the blocking MOSFET
for vHF = +V2 and Vcl > V2 (as proposed in SICAMs with active capacitive load voltage
clamps) is given in Table 6.4.
Table 6.4. One possible switching sequence of the output stage in SICAM with load clamp with vHF = +V2
T21 − T22 on VDS = 0 before switching off T21 − T22
T23 − T24 off VDS = 2V2
T21 − T22 off VDS = Vcl + V2 io > 0
T23 − T24 off VDS = Vcl − V2
T21 − T22 off VDS = Vcl − V2 io < 0
T23 − T24 off VDS = Vcl + V2
T21 − T22 off VDS = 2V2 after switching on T23 − T24
T23 − T24 on VDS = 0
From Table 6.4 it becomes clear that with certain load current direction and HF-link
voltage polarity, one of the bidirectional switches experiences maximum blocking voltage
of VDS = 2V2 and the other one VDS = Vcl + V2 . Due to the symmetrical modulating wave
and symmetrical HF-link voltage, these blocking voltages change between the bidirectional
switches on a regular basis to average and equalize these switching losses between them.
The maximum energy which is stored in the parasitic capacitance of a single MOSFET
of a bidirectional switch during switching of the output stage of a SICAM with load clamp
at drain-source voltage of VDS = Vcl + V2 can be found using (6.116):
2 1 3
E22,max = Coss Voss
2
(Vcl + V2 ) 2 (6.135)
3
and the minimum stored energy at drain-source voltage of VDS = 2V2 is similarly:
2 1 3
E22,min = Coss Voss
2
(2V2 ) 2 (6.136)
3
As mentioned earlier, switching losses due to the parasitic output capacitances of
4QSWs in the output stage of a SICAM are created also as a result of the switching
of the input stage which changes the polarity of the HF-link voltage. The amount of en-
ergy stored in CDS during these changes of the HF-link polarity are given with the same
equation (6.136):
2 1 3
E21 = Coss Voss
2
(2V2 ) 2 (6.137)
3
The switching loss in the output section, caused by switching of both the input and
the output section Psw2,cds is obtained in the following way:
Psw2,cds = 2fs1 E21 + fs2 (E22,min + E22,max ) (6.138)
Total switching losses in the output stage are simply the sum of (6.134) and (6.138):

Switching losses in SICAMs with safe-commutation switching strategy
As already shown in Table 6.3, switching of the bidirectional switches in the output stage
of a SICAM with safe-commutation switching strategy is much more complicated than in
the case of a SICAM with load clamp. Commutation of the load current can be forced
and thus lossy, or natural and therefore lossless, but it depends on the duration of the
natural commutation ∆tnc in (6.34) and the allowed commutation delay ∆td .
Similar to the output stage of SICAM with load clamp, during the switching of the
output stage there are two lossy mechanisms: one corresponds to the finite transition times
during which both current and voltage are non-zero and the other one is the energy stored
in the parasitic output capacitances of the MOSFETs, which is eventually dissipated when
the bidirectional switches are turned on or when input stage changes the polarity of the
HF-link voltage. There is, however, one important difference: the gate driving circuits for
the upper and lower bidirectional switch are now driving each of the individual MOSFETs
separately i.e all input gate capacitances Ciss are driven independently via separate gate
resistors.
In the case when the commutation delay ∆td between different steps in the commuta-
tion process is longer than the natural commutation time interval ∆tnc , there is enough
time for the load current to commutate from the outgoing switch to the incoming switch,
so there is just one lossy turn-off (from the forced commutation) and one almost ZCS and
lossless turn-on (from the natural commutation) during a switching period. In the case
when the commutation delay ∆td is smaller than the natural commutation time interval
∆tnc , there is one lossy turn-off (from the forced commutation) and one almost ZCS and
lossless turn-on, followed by partially lossy turn-off (from the natural commutation) with
the rest of the load current which was naturally commutating.
The only problem when calculating the switching losses caused by the naturally com-
mutating load current is that, in contrast with the switching waveforms in Fig. 6.30 and
Fig. 6.31, the switch current limited by the leakage inductance continues increasing or
decreasing during the intervals tr and tf when the drain-source voltage decreases or in-
creases. This leads to the following energy loss in the naturally commutating incoming
switch at turn-on:
Z tr Z tr
t t
Enc,on = vds (t)isw (t)dt = 1− V · Iin,nc dt =
0 0 tr tr
Z tr 2 (6.140)
t t 1
= V Iin,nc − dt = V Iin,nc tr
0 tr t2r 6
where the current in the naturally commutating incoming switch iin,nc is limited by the
secondary-side leakage inductance and is increasing linearly to its final value Isw2,av , so
that its value at the end of the rise time tr is:
tr
Iin,nc = Isw2,av (6.141)
∆tnc
Similarly, the energy loss in the naturally commutating outgoing switch with not com-
pletely commutated switch current Iout,nc at turn-off is:
1 1
Enc,of f = V ∆Iout,nc tf + V (Iout,nc − ∆Iout,nc )(tf + tcf ) (6.142)
6 2
where ∆Iout,nc is the decrease of the naturally commutating current in the outgoing switch
during the fall time tf :
( 0 , ∆td > ∆tnc

∆Iout,nc = tf (6.143)
Isw2,av , ∆td < ∆tnc
∆tnc
and the current in the hard-switched outgoing switch Iout,nc with partially naturally com-
mutated current is:
( 0 , ∆td > ∆tnc
Iout,nc = ∆td (6.144)
1− Isw2,av , ∆td < ∆tnc
∆tnc
leading to the final expression for the energy loss in the naturally commutating outgoing
switch:
1 tf 1 tf
Enc,of f = V Isw2,av tf + V (Iout,nc − Isw2,av )(tf + tcf ) (6.145)
6 ∆tnc 2 ∆tnc
It should be noted that because of the definition of the outgoing switch currents in (6.143)
and (6.144), the energy loss at turn-off in (6.145) can be zero if the load current has
naturally commutated to the incoming switch before the outgoing switch has been turned
off.
The two situations with commutation delay ∆td longer or shorter than the natural
commutation interval ∆tnc can be therefore represented with the same equation:
1 1
Psw2,tr = fs2 (2V2 )Isw2,av (tf + tcf ) + fs2 (2V2 )Iin,nc tr +
2 6
1 1
+ fs2 (2V2 )∆Iout,nc tf + fs2 (2V2 )(Iout,nc − ∆Iout,nc )(tf + tcf ) =
6 2 (6.146)
1
= fs2 V2 Isw2,av (tf + tcf ) + fs2 V2 Iin,nc tr +
3
1
+ fs2 V2 ∆Iout,nc tf + fs2 V2 (Iout,nc − ∆Iout,nc )(tf + tcf )
3
where the switching time intervals are given with the same equations like for the input
stage section.
It should be noted that in the theoretical case when there is no leakage inductance on
the secondary side, natural commutation happens immediately ∆tnc = 0 and there will
be switching loss only at turn-on of the incoming switch, while turn-off of the outgoing
switch will be lossless:
1 1
Psw2,tr = fs2 (2V2 )Isw2,av (tf + tcf ) + fs2 (2V2 )Isw2,av (tr + tcr ) =
2 2 (6.147)
= fs2 V2 Isw2,av (tf + tcf + tr + tcr )
When looking at the switching losses due to parasitic output capacitance of the bidirec-
tional switches (4QSWs) in the output stage of a SICAM with safe-commutation switching
strategy and caused by the switching of the output stage itself, there is one important
difference when compared to the SICAM with load clamp.
In the output stage of a SICAM with load clamp, bidirectional switches are operated
with dead time and afterwards both MOSFETs in one of the bidirectional switches are
turned on, thus creating a path for capacitive inrush current which is immediately dis-
charging the MOSFET which was performing the whole blocking. There is no specific
mechanism for decreasing these switching losses, because during the dead time load cur-
rent is diverted into the clamp due to nonexistence of freewheeling current path through
the bidirectional switches.
On the other hand, in SICAMs where the load current is commutated using a safe-
commutation switching strategy, MOSFETs in the bidirectional switches are turned on
and off independently in a way that assures there is no short circuit on the transformer
secondary during switching, which essentially leaves some spaces for the load current to
perform lossless charging/discharging of the parasitic output capacitances. If the load
current is insufficient to perform this function and there is no natural commutation, then
the turn-on of the second MOSFET in the incoming bidirectional switch will cause the
aforementioned capacitive inrush current to immediately charge the output capacitances
of the MOSFETs being switched-off previously.
Calculating the switching losses due to the finite parasitic output capacitances of the
bidirectional switches due to the switching of the output stage will be facilitated by the
diagram in Fig. 6.34. It represents the time waveform of the energy stored in the parasitic
output capacitance given by (6.137) as being constant, since constant peak HF-link voltage
has been assumed, while the energy stored in the leakage inductance of the transformer
secondary follows the shape of the sinusoidal load current. The filter ripple current is also
a part of the secondary-side transformer current, but it has been neglected in order to
simplify the mathematical development. The instant t1 at which these energies are equal
is the first moment when there will be no switching losses due to the latter effect:
2 1 3 1
Coss Voss
2
(2V2 ) 2 = Lsl M 2 Io,pk
2
sin2 (ωm t1 ) (6.148)
3 2
leading to:

1 8 1 3
t1 = arccos 1 − 2
Coss Voss (2V2 )
2 2 (6.149)
4πfm 3Lsl M 2 Io,pk
Average switching losses due to the finite parasitic output capacitance of the bidirec-
tional switches in the output stage of a SICAM with safe-commutation switching strategy
as a result of the switching of the output stage are given by the following integral:
Z t1
4 2 1 3 1 2 2 2
E22 = Coss Voss (2V2 ) − Lsl M Io,pk sin (ωm t) dt =
2 2
Tm 0 3 2
Z t1
4 2 1 3 t1 2 2 1 2 2
= Coss Voss (2V2 ) 2 t1 −
2
Lsl M Io,pk + Lsl M Io,pk cos(2ωm t)dt =
Tm 3 Tm Tm 0
4 2 1 3 t1 1
= Coss Voss
2
(2V2 ) 2 t1 − Lsl M 2 Io,pk
2
+ Lsl M 2 Io,pk
2
sin(2ωm t1 )
Tm 3 Tm 4π
(6.150)
E ELsl
ECds
t
Tm/2
t1
Fig. 6.34. Energy stored in the parasitic output capacitance ECds and energy stored in the transformer secondary
leakage inductance ELsl
Switching losses due to the parasitic output capacitances of 4QSWs in the output stage
of a SICAM with safe-commutation switching strategy as a result of the alternating HF-
link voltage are created in a same way like in the SICAM with load clamp, so they are
expressed with the following relation:
2 1 3
E21 = Coss Voss
2
(2V2 ) 2 (6.151)
3
The switching loss in the output section, caused by switching of both the input and
the output section Psw2,cds is obtained in the following way:
Psw2,cds = 2fs1 E21 + 2fs2 E22 (6.152)
Total switching losses in the output stage are simply the sum of (6.146) and (6.152):
Total losses in the output stage are found by summing the conduction and switching
losses in (6.133) and (6.139) or (6.153):
Ptot2 = Pcon2 + Psw2 (6.154)
Output filter design and calculation of losses
The output filter starts with the analysis of a half circuit output filter, with half of the
load impedance (resistance Rh ), like shown in Fig. 6.35a. The transfer function Hh (s) of
this half circuit is:
Rh
(Rh || sC1 h ) sCh 1
Hh (s) = = = (6.155)
sLh + Rh || sC1 h sRh Lh + CLhh + Rh
sCh
Lh
s2 Ch Lh + s R +1
h
Lh Lf
+ +
vi Ch Rh vo Cf R
Lf
a) b)
Fig. 6.35. Output filter: a) half circuit and b) full circuit
There are different possibilities for choosing the output filter type, but the most com-
mon are:
• Butterworth filter (2nd order):
1
Hh,But (s) = s2
√ s (6.156)
ωc2
+ 2 ωc + 1
where ωc = ω−3dB is the filter cut-off angular frequency (-3 dB).

• Bessel filter (2nd order):

1
Hh,Bes (s) = 1 s2
(6.157)
3 ωc2
+ ωsc + 1
where ωc = ω−3dB /1.36165 is the filter characteristic angular frequency, which needs
to be scaled by 1.36165 to arrive at the cut-off angular frequency ω−3dB (-3 dB).
Like stated in [83], Butterworth design is characterized by maximally flat magnitude
response in the frequency pass-band, and the attenuation in the transition frequency
band is better than Bessel. However, in time domain Butterworth filter step response
experiences some overshoot and ringing and therefore Bessel filter is generally preferred.
Comparing (6.155) with (6.157) leads to the following results:
Lh 1 Rh Rh
= =⇒ Lh = =
Rh ωc ωc 2πfc
1 1 (6.158)
Ch Lh = =⇒ Ch =
3ωc2 6πfc Rh
The final values for the inductors Lf and the capacitor Cf of the full circuit output filter
shown in figure 6.35 are found by recognizing that R = 2Rh , Cf = Ch /2 and Lf = Lh :
R R
Lf = =
2ωc 4πfc
(6.159)
1 1
Cf = =
3ωc 6πfc R
The characteristic Bessel frequency fc is connected with the the cut-off frequency f−3dB
in the following way:
f−3dB
fc = (6.160)
1.361654
Copper losses in the output filter inductor are found by multiplying the winding resis-
2
tance RL with the square of the secondary switch current RMS value Isw2,rms , comprising
of load and filter ripple current:
4ρ(M LT ) 2
Pcu,Lf = RLf Isw2,rms = N Isw2,rms (6.161)
πd2f
To simplify the investigation of the core losses, zero modulation is assumed and thus
zero output power, resulting in maximum ripple current If r,max . This means that rectan-
gular voltage with magnitude V2 and duty cycle D = 0.5 is applied to the filter inductor
L, resulting in magnetic induction swing:
λ V2 DTs Vout,max
∆B = = = (6.162)
2N Ae 2N Ae 4N fs2 Ae
After the magnetic induction swing ∆B has been determined, one can proceed to the
core loss tables to determine the corresponding specific core loss pf e . Then the total core
loss is obtained by multiplying the specific core losses pf e with the core volume Vm :
Pf e,Lf = pf e Vm (6.163)
With the most usual designs of output filter inductors on powdered iron toroids with
low permeability, the core losses are only a small fraction of the losses in the winding.
However, it is a common practice to tolerate even 20%/80% distribution between the

copper and core losses, since in the inductors wound on toroidal iron powder cores, the
heat removal is far more easier from a single layer winding than from the inner parts of
the core itself.
The total losses in the output filter inductor are obtained by summing up the copper
and core losses in equations (6.163) and (6.161):
PLf = Pcu,Lf + Pf e,Lf (6.164)
Calculation of the losses dissipated in the output capacitor equivalent series resistance
(ESR) is very hard without making assumptions, like assuming that the whole HF ripple
current If r,rms is flowing entirely through the capacitor, leaving the LF modulated current
flow through the load. The ESR can be found using the tangent of loss angle tan δ supplied
by the manufacturer:
tan δ
ESR = tan δ · XC = (6.165)
2πf C
The losses in the capacitor ESR due to the filter ripple current If r,rms are thus:
PCf = (ESR) · If2r,rms (6.166)
Total losses in the output filter represent a sum of the losses in the filter inductor
(6.164) and filter capacitor (6.166):
Ptot,f = PLf + PCf (6.167)
Losses in gate drivers

The losses in a combined high-side/low-side gate driver can be divided into high voltage
and low voltage static and dynamic losses [84].
The static driver losses are result of the flow of quiescent current or leakage currents
through the different power supplies or level shifting stages of the driver IC and are
generally very low, in the order of few mW and therefore can be neglected.
Low voltage (LV) dynamic losses in the MOSFET gate resistance in both the driving
IC and the external gate resistor in the input and the output stage are function of the
switching frequency fs1 , fs2 , gate voltage levels VG1 , VG2 , as well as the MOSFET gate
charge QG1 , QG2 in the input and the output stage, respectively:
Pdr1,LV = 2fs1 VG1 QG1
(6.168)
Pdr2,LV = 4fs2 VG2 QG2
where the difference in this two equation is from the fact that the output stage has two
bidirectional switches with two MOSFETs each. Another low voltage dynamic losses are
due to the switching of the internal CMOS circuitry and amount to few tens of mW, so
they can be neglected too.
High voltage (HV) dynamic losses happen in high-side gate driver ICs in the input
stage. These are created as power is dissipated in the level shifter to transfer the driving
signal from ground referenced control circuitry to the floating driver on the upper rail, or
with the cyclical charging and discharging of the parasitic well capacitance between the
substrate and the floating driver, which amount to:
Pdr1,HV ls = fs1 (Vdc + VG1 )Qp
(6.169)
Pdr1,HV well = fs1 Vdc Qw
where Vdc is the voltage of the upper rail, Qp is the charge absorbed by the level shifter
and Qw is the well charge, usually both in a range of few nC.
Losses in the active load voltage clamp
Losses in the active load voltage clamp can be calculated in the same way like in the
conventional SMPS, by paying attention to the amount of charge dumped in the clamp
capacitor during the operation of the SICAM and its transfer to the primary side to
maintain charge balance. For completeness, some guidelines will be given in this section.
Conduction losses in the clamp rectifier depend on the average value of the clamp
current Icl,av in (6.46) and diode voltage drop at that current level VF :
Prect,cl = 2VF Icl,av (6.170)
The losses in the clamp capacitor due to its ESR can be calculated by using the RMS
clamp capacitor current ICcl,rms from (6.54) in the following way:
2
PCcl = (ESR) · ICcl,rms (6.171)
Conduction losses in the active switch are found using, for example, equation (6.94)
for a single switch and taking the flyback converter RMS current If b,rms into account:
Pcon,f b = RDS If2b,rms (6.172)
and the flyback converter RMS current is equal to the discharging current of the clamp
capacitor If b,rms = Idis,rms from (6.54).
Switching losses due to switching transitions of the voltage and current in the active
switch are found using, for example, equation (6.115):
1
Psw,f b,tr = fsf b Vcl If b,av (tr + tcr + tf + tcf ) (6.173)
2
where fsf b is the switching frequency of the flyback converter, If b,av is the average value
of the flyback converter current and the switching times are the same as for the input
stage.
Switching loss due to the stored energy in the parasitic output capacitance Coss of the
active switch is found in a similar way as the one presented in the input stage. The only
difference is in the number of switches which are affected, and in the case of a flyback
converter it is only one:
2 1 3
Psw,f b,cds = fsf b Ef b = fsf b Coss Voss
2
Vcl2 (6.174)
3
Total switching losses in the flyback converter are simply sum of (6.173) and (6.174):
Psw1,f b = Psw1,f b,tr + Psw1,f b,cds (6.175)
Total losses in the active switch are found as a sum of the conduction losses in (6.172)
and switching losses in (6.175):
Pas,f b = Pcon1,f b + Psw1,f b (6.176)
Core losses in the flyback transformer are found in a similar way like in Section 6.4.2,
using (6.122) and (6.123) for calculating the core loss:
β
β Vcl Df b Ts,f b
Pf e,f b = kf e (∆B) Vm = kf e Vm (6.177)
2N1 Ae
6.5 Conclusion 193
and (6.129) for copper losses:
ρ(M LT )N1 2 ρ(M LT )N2 2

Pcu,f b = Pcu1,f b + Pcu2,f b = 4kac1 2
If b1,rms + 4kac2 If b2,rms (6.178)
πd1 πd22
to give the total transformer losses PT R,f b equal to:
PT R,f b = Pf e,f b + Pcu,f b (6.179)
Finally, conduction losses in the output rectifier are calculated using the average value
of the flyback converter current on the secondary side If b2,av and the corresponding diode
voltage drop VF 2 :
Prect2,cl = VF 2 If b2,av (6.180)
Total losses in the active load voltage clamp are sum of (6.170), (6.171), (6.176),
(6.179), (6.180) and amount to:
Pcl = Prect,cl + PC,cl + Pas,f b + PT R,f b + Prect2,cl (6.181)
6.5 Conclusion
This chapter reviewed several different topologies of SICAM input and output stages and
compared their advantages and drawbacks.
On the input side, resonant converters were found inappropriate for building SICAM
input stage because of their relatively higher output impedance and large output voltage
perturbations they experience when connected directly to audio power amplifiers with
bidirectional power flow. ZVS PWM full-bridge inverters were also found less attractive
when supplying power directly to SICAM output stage without any rectification and
intermediate energy storage on the secondary side, beside of requiring a full-bridge input
stage which is not economically appealing for lower output powers. Hard-switched DC-
AC inverters with rectangular output voltage are reconsidered as the most suitable choice
and best performer for SICAM input stage with the output power levels and switching
frequencies considered in this case.
One of the disadvantages of HF-link conversion with regard to the conventional solution
with isolated SMPS and Class D audio power amplifier is the need for overdimensioning
the input stage, since it is required to handle both the active and reactive load power
flow.
For the SICAM output stage, the commutation of the load current was pointed out
as the main problem when building the amplifier with bidirectional switches. Similarities
with the three-phase matrix converters were used to develop safe-commutation switching
strategies, which lead to reliable operation of the output stage without any additional
power components, but on behalf of more complex control requirements. On the other
hand, it was shown that adding a load clamp can simplify the control of the SICAM
output stage and make it similar to the Class D audio power amplifier, where blanking
time is added when moving from the outgoing to the incoming switch.
Thorough analysis of the power losses in all SICAM components and stages was pre-
sented in this chapter, and will be used in the subsequent chapters for benchmarking
different topologies and control methods.
7
Control methods for isolated SICAMs
”I consider that I understand an equation when I can
predict the properties of its solutions, without actually
solving it.”
- Paul Dirac
As mentioned in the introductory Chapter 1, SICAMs need centralized control methods

which are capable of operating both the input and the output stage in a way that makes
possible to harness the advantages of the high level of dedication pertinent to SICAM
definition. Chapter 6 showed that this control methods are very important in providing
basic conditions for performing safe commutation of the load current in the SICAM out-
put stage, like avoiding simultaneous switching in both stages. At the same time, control
methods should provide simple means for reducing switching losses through decreasing the
switching frequency of the output stage, without any adverse effects on the audio quality
and control bandwidth. Ultimately, new and advanced control methods for SICAMs can
combine the advantages of the best performing self-oscillating modulators from conven-
tional Class D audio power amplifiers with the compact SICAM topologies presented in
previous chapters, to get the best from both worlds.
All control methods presented in this chapter assume that the input stage on the
primary side of the HF transformer operates with 50% duty cycle, creating non-modulated
rectangular voltage on the HF-link. One possible division of these control methods is
whether the operation of the input and the output stage is synchronized by locking their
switching frequencies or not.
SICAMs with load voltage clamps can use many different control methods, since they
do not rely on the control method to provide conditions for safe load current commutation,
but have the load voltage clamp to perform this important function. On the other hand,
SICAMs with safe-controlled switching strategies must be used in conjunction with smart
control techniques that guarantee non-simultaneous switching of the stages, in order to
keep the polarity of the HF-link voltage the same during the whole transition process
of the output stage. Therefore in this section the main focus will be put predominantly
on special control methods for SICAMs with safe-commutation switching strategy, but it
goes without saying that SICAMs with load voltage clamps can use all of the presented
methods as well, maybe with slight modifications in order to remove the unnecessary
feature of non-simultaneous switching of the stages.
At the end, several closed-loop control schemes suitable for SICAM implementation
are discussed.
7.1 Unsynchronized control of both stages in isolated SICAMs

7.1.1 Simple PWM modulator for unsynchronized operation
The simplest PWM modulator for HF-link converters and SICAMs in Fig. 7.1 resem-
bles in its structure the PWM modulator with externally generated triangular carrier for
common power converters with DC-bus. It uses the same double-sided triangular carrier
196 7 Control methods for isolated SICAMs
with a constant carrier frequency fc2 and amplitude Vc , introducing almost constant gain
KP W M = 1/Vc up to the carrier frequency. The only difference is that in SICAMs, HF-link
voltage is alternating and therefore the output of the comparator cannot be send directly
to the gates of the bidirectional switches, but instead it needs some further processing.
This is done by additional logical gates to obtain the correct gate signals, according to
the instantaneous HF-link polarity, which changes with the switching frequency of the
inverter stage fs1 i.e. the frequency of the HF-link fHF . Therefore, the actual switching
frequency of the bidirectional bridge fs2 is:
fs2 = fs1 + fc2 (7.1)
which means that the switching frequency of the bidirectional bridge does not depend
solely on the triangular carrier frequency fc2 , like in the conventional PWM modulators
for Class D audio power amplifiers, but also on the HF-link frequency fHF .
vc +
- 23 & 24
fc2
HF-link 21 & 22
+/-
Fig. 7.1. Modified PWM modulator for SICAM
Modifications of the proposed PWM method in Fig. 7.1 are possible, which guarantee
that the switching frequency of the output stage is the same as the PWM triangular
carrier frequency fs2 = fc2 and therefore lower switching losses than the present one, but
on behalf of slightly more complex modulator scheme [85] presented in Section 7.2.2.
In this open-loop PWM control method, the switching frequency of the primary-side
input stage is not related to the one of the output stage in any way, which makes this
method essentially unsynchronized. However, switching of the input stage is immediately
followed by switching of the output stage, to reconstruct the desired voltage polarity across
the load. The biggest advantage of such unsynchronized operation of the stages is that
the switching frequencies can be selected independently one from another. For the input
stage, the switching frequency fs1 can be selected in a way that optimizes the amount of
power losses and minimizes the size of the transformer, according to the available thermal
interface, i.e. heat sink. On the other hand, the switching frequency of the output stage fs2
is usually chosen to obtain the desired control bandwidth with the minimum switching
losses. Another significant advantage of the unsynchronized control is the much easier
start-up of the SICAM, since both stages can start operating independently one from
another. Due to the necessary level of isolation between the primary i.e. the utility grid
side and the secondary i.e. the user side, usually the input stage will be the one to start
first and then supply the necessary power for the control and gate driving functions of
the output stage.
However, it was discovered in the practical implementations of the presented control
method that unsynchronized operation gives rise to audio distortion due to idling (spu-
rious) tones as intermodulation products of the input and the output stage switching
frequencies, which are constantly shifting in the frequency domain as the device gets
heated and changes slightly its characteristics. As an example, measured FFT of output
noise with no input and THD+N at three different output levels of a SICAM with active
capacitive voltage clamp and simple unsynchronized PWM control is given in Fig. 7.2. On
7.1 Unsynchronized control of both stages in isolated SICAMs 197
the diagrams on the left-hand side the switching frequencies of the stages were slightly
different than the desired values, while on the right-hand side a tight adjustment of the
switching frequencies was performed to simulate synchronized control. It is clear that when
the switching frequencies of the stages are left unsynchronized, they will start crawling
around their desired values and will start to create spurious components within the au-
dio band which will eventually reduce performance. Therefore, synchronized operation
of SICAM input and output stage is preferred, despite of the aforementioned increased
design flexibility of the unsynchronized control method.
Unsynchronized fs1 = 102.3 kHz, fs2 = 201 kHz Unsynchronized fs1 = 100 kHz, fs2 = 225 kHz
Top to bottom: 10 W, 50 W, 75 W Top to bottom: 10 W, 50 W, 75 W
Fig. 7.2. FFT (top) and THD+N (bottom) of two unsynchronized SICAMs with and without tight control of
switching frequencies
7.1.2 Master/Slave operation of the input/output stage to accomplish output

stage safe commutation
One of the main problems with unsynchronized control of the input and the output stage
is finding a way to guarantee non-simultaneous switching, which is necessary to under-
take load current commutation with the presented voltage-controlled safe commutation
switching sequence in Section 6.2.1. This problem is nonexistent in the SICAMs with load
clamps, where during output stage switching the load current is diverted into the clamp.
The simplest approach for avoiding simultaneous switching of the input and the output
stage with unsynchronized control is the Master/Slave operation of the input/output
stage.
The premises for master/slave operation of this compound input/output stage are like
follows:
1. Each of the stages can be either a master or a slave,
2. Both stages can not be masters in the same moment,
3. It is possible for both stages to reside in a slave mode at the same time,
4. Transition of one stage from slave to master is done only if the other stage is in slave
mode,
5. Transition back from master to slave of one stage does not depend on the internal
events in the other stage, but it allows the latter to transfer from slave to master, if it
was waiting for permit.
The block diagram of the proposed master/slave control of isolated SICAMs to achieve
safe commutation of the load current is depicted in Fig. 7.3. The input and the output
stage in SICAM are sharing the same single logic ”master/slave” line, which can have
two possible states. If it is implemented with positive logic, than logic one (”1”) means
that one of the stages is in master mode and logic zero (”0”) means that both stages
are slaves. Each of the stages becomes a master, if premise 4 is satisfied and a command
is issued from the control unit of the corresponding stage to make a transition: for the
input stage it means that the voltage across the transformer primary is to be reversed
and for the output stage it means that a commutation of the bidirectional bridge is to
be undertaken in order to accommodate the audio reference. Whenever a transition is to
be made and the master/slave line is idling at ”0”, the corresponding stage is pulling the
master/slave line up to ”1” occupying it for the time of its transition. Master/slave line
will be released as soon as the transition has ended, but according to premise 5 this is
done without any regards to the other slave stage. In this way, the ”master” stage can
take all the time needed to finish the transition safely. This is, however, done on expense
of increased distortion, sacrificing some performance. Due to the premise 1, both stages
can not be in master mode at the same time, so transitions in both stages can not occur
simultaneously, thus effectively avoiding any possible dangerous commutation.
When implementing the aforementioned master/slave control algorithm, the only thing
the output stage control unit still needs to know is the polarity of the HF-link voltage
i.e. the primary side inverter state, so that each of the commutation commands proceeds
according to the safe commutation switching pattern in Table 6.3. This is done by using
a single unidirectional logic-level line from the input to the output stage, or by directly
sensing the transformer voltage polarity.
Input stage Output stage

. .
S1 S3 S21 S23
. . .
LF LF
.
CF CF
S2 S4 S22 S24
. .
Voltage
polarity
Control unit for Control unit for
input stage output stage
Master/Slave
Fig. 7.3. Master/slave control of isolated SICAM with safe commutation switching strategy
7.2 Synchronized control of both stages in isolated SICAMs 199
By using the HF-link voltage-controlled safe-commutation sequence in Table 6.3, the

use of expensive or noisy current and/or voltage sensors, which are otherwise needed
in all of the other commutation methods, is avoided, but on behalf of little performance
degradation. In the case of the input stage, if the transition is needed and the output stage
is already making the load current commutation, thus being a master, prolonged voltage
pulse will be applied which can cause increased flux in the transformer magnetic core,
maybe even causing saturation if there is only a minor safety margin. In order to avoid any
imbalance in the applied Volt-seconds, the control algorithm should be supplemented with
a possibility to apply an equally large pulse of opposite polarity for balancing purposes,
otherwise the applied DC offset will emerge across the DC blocking capacitor, causing a
difference in the HF-link voltage during the positive and negative half-cycles. On the other
hand, when talking about the output stage, any delay in the transition command will cause
output voltage distortion, which should be subsequently compensated by the feedback
control loop. Therefore, it is of prime interest to keep the transition or commutation
delay times low, thus effectively avoiding larger performance degradation.
7.2 Synchronized control of both stages in isolated SICAMs

Safe-commutation sequence in Table 6.3 alone is not enough to guarantee proper opera-
tion of the amplifier at all times, since HF-link voltage is changing very fast during the
switching of the input stage and can cause malfunctioning of the algorithm. Therefore it
is important that the switching of the input and output stage is not done simultaneously,
and this condition is taken care of in the open-loop control design.
To avoid simultaneous switching of both stages, unsynchronized switching can be com-
bined with master-slave operation from the previous section and [53] that prohibits the
slave stage to switch when the master stage is already performing transition. However, it
was already mentioned that due to the non-ideality of the switching stages, unsynchro-
nized operation can give rise to intermodulation harmonics that fall into the audio band
and spoil performance.
When the operation of the stages is synchronized, the switching frequency of the output
stage fs2 is an integer multiple of the switching frequency of the input stage fs1 :
fs2 = nfs1 (7.2)
where n ∈ Z+ , i.e. there is switching frequency locking between the stages. Beside the im-
proved audio performance, synchronization makes it easier to avoid simultaneous switching
of both stages, by performing transitions of the primary stage only at the peak or the
valley of the triangular carrier in the PWM modulator and switching the output stage
anywhere else by essentially limiting the modulation index of the audio signal.
The aim of the proposed synchronized PWM methods is therefore twofold: on one
hand, the triangular carrier is used in the PWM modulator to compare to the reference
voltage and decide the switching instants of the output stage, while on the other hand, the
triangular carrier governs the transition of the input stage and HF-link voltage change, in
a way that secures switching does not overlap. Furthermore, it is desirable to decrease the
switching frequency of the output stage and make it ideally equal to the frequency of the
triangular carrier used in the PWM modulator, which is also appealing for the SICAM
with load clamp.
In the following sections, the PWM methods will be derived and thoroughly analyzed
in a case when the PWM modulator triangular carrier frequency fc2 is two times higher
than the switching frequency of the input stage fs1 . The characteristics of any other
configuration can be determined by following the same approach.
PWM modulator
1
Tc2
0
−1
0 0.5 1 1.5
−5
1 x 10
HF link
0
−1
0 0.5 1 1.5
−5
1 x 10
Gate drive
−1
0 0.5 1 1.5
−5
1 x 10
Bridge voltage
−1
0 0.5 1 1.5
time t[s] −5
x 10
Fig. 7.4. PWM method with 3 switchings during one carrier period Tc2
7.2.1 Simple synchronized PWM method

Synchronized operation of the SICAM with non-modulated transformer voltages in
Fig. 5.14, is shown in Fig. 7.4 in the case of fc2 = 2fs1 . The switching frequency of
the input stage is fs1 = 150 kHz and the PWM modulator triangular carrier frequency is
fc2 = 300 kHz. With this modulation scheme, output stage is switched in a way that the
bridge voltage applied across the output filter and the loudspeaker resembles the PWM
modulator output ideally. For this purpose, the output stage switch gate drive must be
a product of the PWM modulator output FN ADD in (5.5) and the rectangular waveform
Fr in (5.6), so the effective switching frequency of the output stage is fs2 = fs1 + fc2
instead of just fs2 = fc2 , as one would normally expect. In Fig. 7.4, this PWM method
results in three switchings of the output stage during one period of the carrier Tc2 , which
increases the switching losses in the output stage and reduces efficiency. On the other
hand, the input stage is driven only by the synchronized rectangular waveform Fr and
the switching of both stages can happen simultaneously, if it is not intentionally delayed.
It can be therefore concluded that this straightforward approach complicates the SICAM
design and results in number of disadvantages.
The structure of the PWM modulator is essentially the same like in Fig. 7.1, with
a remark that the switching of the input stage and thus HF-link voltage changes occur
simultaneously with the triangular carrier peak and/or valley.
7.2.2 Optimized PWM method with synchronization and lower output stage
switching frequency
The switching frequency of the output stage fs2 can be made equal to the carrier frequency
fc2 and therefore result in only two switchings per carrier period Tc2 by giving up on the
desire to exactly restore the PWM modulator output in the bridge voltage across the
output filter and instead choosing a switching waveform that will give the same average
value of the bridge output voltage, like the original PWM modulator waveform. This
means that the switching of the output stage is not performed as soon as the HF-link
changes polarity, but the switching time instants are readjusted. Looking at Fig. 7.5, this
means that the average values of the bridge output voltage in the first two carrier periods
PWM mod. +
1
Mmax
0
t1 t2
−1
0 0.5 1 1.5
PWM mod. −
−5
1 x 10
t3 t4 Mmax
0 Tc2 Tc2
−1
0 0.5 1 1.5
−5
1 x 10
HF link
0
−1
0 0.5 1 1.5
−5
1 x 10
Gate drive
−1
0 0.5 1 1.5
Bridge voltage
−5
1 x 10
−1
0 0.5 1 1.5
time t[s] −5
x 10
Fig. 7.5. Proposed PWM method with 2 switchings during one carrier period Tc2
are the same, despite the fact that the exact waveform is different. Time instants t1 and
t2 during the half-period with positive HF-link voltage are given by:
Tc2 2vref
t1 = 1+
4 Vcmax
(7.3)
Tc2 2vref
t2 = 3−
4 Vcmax
where vref is the reference voltage and Vcmax is the maximum carrier voltage. From (7.3),
the time interval ∆t− during which negative bridge voltage is applied across the output
filter while the HF-link voltage is positive is:
Tc2 2vref
∆t− = t2 − t1 = 1− (7.4)
2 Vcmax
During the second period Tc2 when the HF-link voltage is negative, negative bridge
voltage is symmetrically applied at both ends of the carrier period and in order to have
the same average output voltage like in the first period Tc2 , the time instants t3 and t4
must be equal to:
∆t− Tc2 −2vref
t3 = = 1+
2 4 Vcmax
(7.5)
∆t− Tc2 −2vref
t4 = Tc2 − = 3−
2 4 Vcmax
From (7.5) it becomes apparent that the average voltage during either polarity of the
HF-link voltage in Fig. 7.5 will be equal, if the actual reference voltage is used in the
PWM modulator during positive HF-link voltages and negative reference voltage is used
in the PWM modulator during negative HF-link voltages, with the same form of the
carrier. As long as the frequency of the reference voltage waveform is much lower than the
frequency of the carrier, there will be no output voltage distortion originating from this
signal manipulation. The proposed optimized PWM modulator is depicted in Fig. 7.6.
To make possible the safe-commutation of the output stage, the modulation index is
limited to Mmax < 1 in Fig. 7.5, so that the maximum reference voltage is slightly lower
Synchronization
+
HF-link
vc +/-
-
fc2 -1
21 & 22
-vc +
-
23 & 24
Fig. 7.6. Optimized PWM modulator for SICAM
than the peak value of the carrier voltage Vcmax . In this way the switching of the in-
put stage, which is always happening at the peak or the valley of the carrier waveform,
cannot be simultaneous with the switching of the output stage. The maximum modu-
lation index Mmax is chosen taking into account the propagation time delay ∆t1 from
the secondary-to-primary-side synchronization signal is given to the moment the HF-link
voltage changes, propagation time delay ∆t2s from the PWM modulator output to the
start of the bidirectional bridge switching sequence and propagation time delay ∆t2f from
the PWM modulator output to the finish of the same sequence, according to the following
equation:
Mmax = inf{1 − 4fc2 (∆t1 − ∆t2s ), 1 − 4fc2 (∆t2f − ∆t1 )} (7.6)
Frequency spectrum of the new PWM method in the case of fc2 = 2fs1
It is rather interesting to compare the frequency spectrum of the bridge voltage of the
conventional PWM method shown in Fig. 7.4, which is equal to FN ADD in (5.5), with
the frequency spectrum of the bridge voltage in the case of the proposed PWM method
in Fig. 7.5. The analysis will focus on the case where the carrier frequency in the PWM
modulator is two times the input stage switching frequency. Thorough mathematical de-
velopment of the PWM waveforms is given in Appendix E.1.
The frequency spectrum of the proposed PWM method in Fig. 7.5 can be found by
breaking the PWM pulse train into two separate groups of pulses that correspond to the
periods with positive and negative HF-link voltage, correspondingly, as shown in Fig. 7.7.
These separate PWM trains are result of the same PWM process FN ADD,xh with every
second pulse skipped, where for the first pulse train the actual reference voltage and
for the second pulse train the negative reference voltage with subsequent reversal of the
PWM pulses polarity due to the negative HF-link voltage is being used. At the end, the
frequency spectra of the two PWM pulse trains are summed together to give the final one
FN P W M . The approach will be explained in the following paragraphs.
The double Fourier series of a two-level, double-sided PWM with every second pulse
skipped and pulses only in the odd half-periods is developed in Appendix E.1.3 and is
repeated here:
FN ADD,1h (t, ϕ) = 4kM cos(ωm t + ϕ)+

∞
2 cos(2πmk − π2 ) cos(4πmk + π2 )
X
+2 J0 (2πmkM ) + · cos(mωHF t)+
m=1
mπ mπ
∞ X ∞
X cos(2πmk + (n−1)π
2
− nϕ)
+4 · Jn (2πmkM ) cos(mωHF t + nωm t + nϕ)
m=1 n=±1
mπ
(7.7)
Bridge voltage FNPWM(t,φ)

1
0.5
−0.5
−1
0 0.5 1 1.5
−5
x 10
1
FNADD,1h(t,φ)
0.5
−0.5
−1
0 0.5 1 1.5
−5
x 10
1
−FNADD,2h(t,φ+π)
0.5
−0.5
−1
0 0.5 1 1.5
time t[s] −5
x 10
Fig. 7.7. The new PWM pulse train (top) and its two constitutive parts (below)
where ωm and ϕ are the angular frequency and the phase of the modulating signal, ωHF
is the angular frequency of the triangular carrier and k = Tc2 /(4 · THF ) is a ratio of the
carrier and input stage switching period, equal to k = 0.125 for the case with two times
higher carrier frequency then the input stage switching frequency.
The double Fourier series of a two-level, double-sided PWM with every second pulse
skipped and pulses only in the even half-periods is developed in Appendix E.1.4 and is
given by the following expression:
FN ADD,2h (t, ϕ) = 4kM cos(ωm t + ϕ)−

∞
X 2 cos(6πmk − π2 )
−2 J0 (2πmkM )+
m=1
mπ
cos(4πmk + π2 ) + cos(8πmk + π2 )

· cos(mωHF t)−
mπ
∞ X ∞
2
− n(ϕ + π))
−4 · Jn (2πmkM ) cos(mωHF t + nωm t + nϕ)
m=1 n=±1
mπ
(7.8)
From Fig. 7.7 it can be noticed that the pulse train FN ADD,2h can be obtained from
FN ADD,1h by simple pulse train shifting by −0.5 · (2π)/ωHF , i.e.:
2π
FN ADD,2h (t, ϕ) = FN ADD,1h (t − 0.5 , ϕ) (7.9)
ωHF
which can simplify calculation of the Fourier series of the resultant pulse trains.
The double Fourier series given in the equations (7.7) and (7.8) can be used as constitu-
tive parts to calculate the double Fourier series of the conventional two-level double-sided
PWM bridge voltage shown at the bottom diagram in Fig. 7.4, as follows:
Frequency spectrum of two−level, double−sided PWM − F

NADD
0
−10
−20
−30
−40
|H(w)| [dB]
−50
−60
−70
−80
−90
−100
0 1 2 3 4 5 6 7 8 9 10
FREQUENCY [Hz] 5
x 10
Fig. 7.8. Frequency spectrum of the conventional PWM method FN ADD with M = 0.1, fm = 10 kHz,
fs1 = 150 kHz, fc2 = 300 kHz
FN ADD (t, ϕ) = FN ADD,1h (t, ϕ) + FN ADD,2h (t, ϕ) = 8kM cos(ωm t + ϕ)−

∞
4 sin(4πmk − π2 ) sin(2πmk) cos(8πmk + π2 )
X
−2 J0 (2πmkM ) + · cos(mωHF t)−
m=1
mπ mπ
∞ X ∞
X sin(4πmk + (n−1)π
2
− n(ϕ + π2 ))
−8 ·
m=1 n=±1
mπ
nπ
· sin(2πmk + )Jn (2πmkM ) cos(mωHF t + nωm t + nϕ)
2
(7.10)
The magnitude diagram of the frequency spectrum of the conventional PWM bridge
voltage FN ADD with modulation index equal to M = 0.1, modulation frequency
fm = 10 kHz, input stage switching frequency fs1 = 150 kHz and carrier frequency
fc2 = 300 kHz is shown in Fig. 7.8.
For calculating the double Fourier series of the newly proposed PWM method for
the SICAM bridge voltage FN P W M shown at the bottom diagram in Fig. 7.5, previously
developed equations (7.7) and (7.8) are summed in the following way:
FN P W M (t, ϕ) = FN ADD,1h (t, ϕ) − FN ADD,2h (t, ϕ + π) = 8kM cos(ωm t + ϕ)+
∞
X 4 cos(4πmk − π2 ) cos(2πmk)
+2 J0 (2πmkM )+
m=1
mπ
2 cos(4πmk + π2 ) + cos(8πmk + π2 )

+ · cos(mωHF t)+ (7.11)
mπ
∞ X ∞
2
− nϕ)
+8 ·
m=1 n=±1
mπ
· cos(2πmk)Jn (2πmkM ) cos(mωHF t + nωm t + nϕ)
The magnitude diagram of the frequency spectrum of the new PWM bridge voltage
FN P W M with modulation index of M = 0.1, fm = 10 kHz, fs1 = 150 kHz and
fc2 = 300 kHz is shown in Fig. 7.9.
Frequency spectrum of the new two−level, double−sided PWM − F

NPWM
0
−10
−20
−30
−40
|H(w)| [dB]
−50
−60
−70
−80
−90
−100
0 1 2 3 4 5 6 7 8 9 10
FREQUENCY [Hz] 5
x 10
Fig. 7.9. Frequency spectrum of the new PWM method FN P W M with M = 0.1, fm = 10 kHz, fs1 = 150 kHz,
fc2 = 300 kHz
It becomes apparent from Fig. 7.8 that the frequency spectrum of the conventional
PWM method FN ADD in Fig. 7.4 comprises only of the modulating signal baseband,
switching harmonics at multiples of the carrier frequency and their sidebands as in-
termodulation product of the modulation baseband with the switching harmonics, like
suggested in the more compact form of FN ADD (5.5). As long as the PWM modulator
triangular carrier frequency is substantially higher than the maximum modulating fre-
quency ωc ≫ ωm,max , there are no switching frequency sidebands interfering with the
audio baseband, and the modulation process is essentially linear. The switching harmon-
ics amplitudes at the loudspeaker are suppressed by the output low-pass filter attenuation
at those specific frequencies.
On the other hand, by closely inspecting Fig. 7.9 one can notice that the frequency
spectrum of the proposed PWM for SICAMs FN P W M has intermodulation sidebands
at the multiples of the input stage switching frequency i.e. HF-link frequency, which
are not present in the conventional PWM FN ADD , while some of the harmonics and
sidebands associated with the PWM modulator carrier frequency have disappeared. Since
the frequency of the HF-link is usually selected lower than the carrier frequency, these
components are likely to cause larger ripple voltage across the loudspeaker, since the low-
pass output filter is less effective at the HF-link frequency. Fortunately, the magnitude of
the first harmonic of the HF-link voltage at the loudspeaker terminal is lower than the
third harmonic, which the output filter can attenuate more effectively. The magnitudes of
the first 9 switching harmonics as function of the modulation index are given in Fig. 7.10.
7.2.3 Frequency spectrum of the new optimized PWM method in general

case
The double Fourier series (7.7) of the two-level double-sided PWM signal in the beginning
of the switching interval can be used to develop the double Fourier series of the new PWM
with the desired even integer ratio r of the triangular carrier fc2 and the HF-link frequency
fHF , fc2 = r · fHF :
Switching harmonics magnitude vs. modulation index with F

NPWM
1.4
Normalized harmonic magnitude

1.2
1
3rd
0.8
5th
0.6
1st
0.4
7th
0.2 9th
0
0 0.2 0.4 0.6 0.8 1
Modulation index M
Fig. 7.10. Magnitudes of the switching harmonics in FN P W M with varying modulation index
FN P W M (t, ϕ) =
r/2 r (7.12)
X 2π X 2π
FN ADD,1h [t − (i − 1) , ϕ] − FN ADD,1h [t − (i − 1) , −ϕ]
i=1
rωHF rωHF
i=r/2+1
7.3 Self-oscillating modulators for isolated SICAMs - SOHF

7.3.1 Application and limitations
The most common modulator for direct conversion audio power amplifiers, i.e. SICAMs
[3], [9], [53], [54], [85], has up till now been the PWM modulator with externally generated
carrier. Reasons for this are mainly twofold and arise from the fact that self-oscillating
modulators have variable switching frequency which decreases with increasing modulation
index and the inability to predict and steer switching instants, due to the hysteretic-type
control. On one hand, when using self-oscillating modulators in SICAMs with PWM
modulated transformer voltages [3], variable switching frequency causes the transformer
design to be suboptimal and its dimensions must be chosen to bare the largest magnetic
flux at lowest switching frequency without going into saturation. On the other hand, when
PWM modulation is used only on the secondary side of the transformer in conjunction
with some safe-commutation principle in Section 6.2.1 and [85], random switching of the
self-oscillating modulator makes it very difficult to synchronize the operation of the input
stage to the output stage. However, this does not mean that self-oscillating modulators
are completely useless in SICAMs, but rather that they are applicable just with certain
SICAM topologies and usually with active [54] or dissipative clamps [9], or conditionally
with safe-commutation strategies [85] as means for commutating the load current in the
output bidirectional bridge.
In the next sections, the use of self-oscillating modulators will be analyzed with respect
to SICAMs with non-modulated transformer voltages [85], [86], where the input inverter
stage on the primary side of the transformer is operated with 50% duty cycle to create
rectangular transformer voltage with maximum width. The operation of the input stage is
not synchronized to any control signal from the secondary side, and therefore the operation
of the input stage is referred as free-running. The proposed solution is named SOHF -
Self-Oscilating High Frequency-link converters.
7.3 Self-oscillating modulators for isolated SICAMs - SOHF 207
HF-link
. .
sgn (v) = +/-1 AC
Vref fa
-2
+ f
_ LC
Hysteresis Amplifier Output filter
MFB
1
f
Z fa
Fig. 7.11. GLIM SOHF
7.3.2 Operation fundamentals
Self-oscillating modulators can be roughly divided into two groups: current mode and
voltage mode modulators [15]. There is not bigger difference in their principal operation,
except that the measured inductor current in the former group is used directly in the
modulator, while in the latter group the measured bridge voltage must be first integrated
or processed in some way in the control section [87] or in both control section and power
stage [88], [89].
One other possible division of self-oscillating modulators is according to the way self-
sustained oscillation is created. In one group of self-oscillating modulators the limit cycling
is created by hysteresis window [89], [90], [91], usually made from the amplifier output
to improve the PSRR. In another group of self-oscillating modulators, the necessary loop
gain of 0 dB at phase-shift of 180◦ at the switching frequency is created by active and
passive phase-shift control with RC-networks in the feedforward and feedback path [88],
[92].
The approach presented in the following few paragraphs can be used to modify particu-
lar self-oscillating modulator for SICAM operation in a straightforward manner. Without
loss of generality, the discussion will deal just with the Global Loop Integrating Modulator
(GLIM) [89], where the integrating transfer function from the bridge voltage to the input
of the hysteresis block is obtained by combining the poles of the output filter in the power
stage with the zero in the modulator feedback block (MFB) at the output filter cut-off
frequency. The hysteresis block itself is created from the power stage bridge voltage using
a resistive divider, as an input to the comparator.
In all self-oscillating modulators, the polarity of the bridge voltage which is being
applied across the output filter and loudspeaker is determined solely by the state of the
comparator i.e. the output from the hysteresis block, since the power supply voltage
has constant polarity. In SICAMs, bridge voltage essentially represents a product of the
HF-link voltage and the state of the comparator. Changing the HF-link polarity causes
immediate change in the bridge voltage and hysteresis window polarity bound to it, which
will surely bring the power stage into stall due to the ill-posed hysteresis limits. Therefore,
any change in the HF-link voltage polarity must be followed by corresponding change in
the direction of integration, which essentially means that the polarity of the feedforward
and feedback signals entering the comparator must be reversed. The block diagram of the
proposed GLIM self-oscillating SICAM is given in Fig. 7.11. For comparison purposes,
diagrams of practical implementations of GLIM modulators for Class D audio power
amplifier and SICAM are given in Fig. 7.12. The actual circuit schematic of a GLIM
modulator for Class D audio power amplifier is depicted in Fig 7.13.
Since the operation of the proposed self-oscillating modulator for SICAMs seems to
be determined by the quantities characteristic for the basic self-oscillating modulator
intended for operation with Class D audio power amplifiers, quantities associated with
the latter will be called basic quantities and will be given asterisk ”*” as superscript.
Notice that most of these quantities are severely affected and altered when the SICAM
HF-link is included in the modulator.
The operation of the self-oscillating modulator for SICAMs depends on the modulation
∗
index M of the reference voltage signal at the input of the modulator. Let Mlim denote
the modulation index limit at which the frequency of the basic self-oscillating modulator,
∗
equal to the output stage switching frequency fs2 is two times the switching frequency of
the free-running input stage fs1 :
∗ ∗
fs2 (Mlim ) = 2 · fs1 (7.13)
∗
For modulation indexes smaller than the modulation index limit M < Mlim operation
∗
of the self-oscillating modulator is called normal operation and for M ≥ Mlim it is referred
as locked operation. These notions will be explained in detail in the following sections.
DC SMPS HF-link
. .
DC AC
Vref - Vref -
_ fa _ fa
-2 -2
+ + f + + f
LC LC
Amplifier with
Comparator Amplifier Output filter Comparator Output filter
bidirectional switches
MFB Comparator
1
-
f +
fa MFB
Z
1
f
Z fa
a) b)
Fig. 7.12. Practical implementation of GLIM modulator for: a) Class D audio power amplifier and b) SOHF
Hysteresis
R1 R2
Comparator Amplifier Output filter + load

vc+
+ Ka va Lf v o
-
vc- Cf R
MFB
Rfb
Rfw
vr
Cfb
Fig. 7.13. Schematic of GLIM for Class D audio power amplifier

7.3.3 Normal operation with M < Mlim

∗
Normal operation of the self-oscillating modulator in Fig. 7.11, which occurs for modu-
∗
lation indexes M < Mlim is shown in Fig. 7.14. The operation is called normal since it
resembles very much the operation of a conventional Class D audio power amplifier with
∗
self-oscillating modulator. With low modulation indexes M < Mlim , the slopes of both
the rising portion and the falling portion of the carrier are steep and the output stage
performs several switchings within each period of the HF-link voltage vHF . The nature
of the operation makes it very difficult to determine the exact switching frequency of the
output stage, since it depends not only on the feedback quantities but also on the instants
when HF-link changes its polarity. It can be, however, assumed that with sufficient level of
accuracy the average switching frequency of the output stage fs2 is equal to the switching
∗
frequency of the basic self-oscillating modulator fs2 , developed in Appendix E.2:
Vs 1 − M 2

∗
fs2 (M ) = fs2 (M ) = (7.14)
4 τint Vh + td Vs M <M ∗
lim
where Vs = |vHF | is the absolute value of the HF-link voltage, Vh is the hysteresis window
width, td is the modulator loop delay and τint is the integrator time constant which is equal
to the output filter cut-off frequency in the GLIM case. In all practical implementations,
the hysteresis window is formed using the HF-link voltage:
Vh = kh · Vs (7.15)
and MFB in Fig. 7.11 features attenuation equal to the gain of the SICAM amplifier ka ,
leading to switching frequency of the output stage fs2 which is independent of the supply
voltage Vs and significantly improving the PSRR:
1 1 − M 2

∗
fs2 (M ) = fs2 (M ) = (7.16)
4 τint kh ka + td M <M ∗
lim
The idling switching frequency with M = 0 is:

1 1
fs2,0 = (7.17)
4 τint kh ka + td
Transition from normal to locked mode of operation happens when the modulation
∗
index M is equal to Mlim , which in the case of the GLIM modulator is obtained by
combining equations (7.13) and (7.16) and becomes:
∗
p
Mlim = 1 − 8fs1 (τint kh ka + td ) (7.18)
7.3.4 Locked operation with M ≥ Mlim

∗
The real difference in the operation between the conventional self-oscillating modulator
for Class D audio power amplifiers and the one for use with SICAMs is observed with
∗
modulation indexes larger than the modulation index limit M ≥ Mlim . As shown in
∗
Fig. 7.15, the bridge voltage of the self-oscillating SICAMs with M ≥ Mlim turns into
2-level phase-shifted PWM with constant frequency two times the HF-link frequency:
fbr = 2 · fs1 (7.19)

HF-link HF-link
voltage voltage
Load voltage Load voltage

Carrier Carrier
Hysteresis Hysteresis
t+
Bridge voltage Bridge voltage
Tbr
Secondary Secondary
gate drive gate drive
∗ ∗
Fig. 7.14. Normal operation with M < Mlim Fig. 7.15. Locked operation with M ≥ Mlim
while the output stage switching frequency is exactly equal to the input stage switching
frequency i.e. the HF-link frequency:

fs2 (M ) = fs1 (7.20)
∗
M ≥Mlim
With the duty cycle D defined as ratio between the time interval with high voltage on
the bridge output t+ and its period Tbr , equal to half the HF-link period:
t+
D= = 2t+ fs1 (7.21)
Tbr
the SICAM output voltage is calculated to be:
vo = DVs − (1 − D)Vs = (2D − 1)Vs (7.22)
and the duty cycle dependance on the modulation index:

1±M
D= (7.23)
2
where ”+” sign is used for positive and ”-” sign is used for negative reference voltages
vref .
As implied in equations (7.19) and (7.20), the frequency of quantities associated with
the secondary stage becomes locked to the primary side and the HF-link, since the slope
of either the rising portion or the falling portion of the carrier has reduced as a result
∗
of the large modulation index M ≥ Mlim . In this situation, the regular changes in the
HF-link polarity interrupt the slower slope of one of the carrier portions before it hits
the other wall of the hysteresis block, causing a sort of carrier reset. The time interval
between the phase-shifted waveforms created by the switching of the output stage and the
subsequent switching of the HF-link is essentially equal to the time interval with positive
bridge voltage t+ and its dependance on the modulation index is:
1±M
t+ = DTbr = (7.24)
4fs1
The phase locking property of the self-oscillating SICAM can be shown to be asymp-
totically stable. When disturbance voltage ∆v is added to the carrier voltage, causing
HF-link
voltage
1 2 3 4
Dv
Load voltage
Bridge voltage Dt
Carrier
Hysteresis
Fig. 7.16. Asymptotic stability of the locked operation
corresponding timing error ∆t at the first switching of the output stage, like shown in
Fig. 7.16, then the following equations for the subsequent errors are valid:
∆t1 = ∆t ∆v1 = ∆v
1−M 1−M

∆t2 = 1+M ∆t ∆v2 = 1+M ∆v
2 1−M 2
∆t3 = 1−M

1+M
∆t ∆v3 = 1+M ∆v (7.25)
... ...
n 1−M n
∆tn+1 = 1−M

1+M
∆t ∆v n+1 = 1+M
∆v
Because of the fact that:

1−M
<1 (7.26)
1+M
the asymptotic stability of the timing interval t+ for the phase-shifted PWM is proven:
n n→∞
∆tn+1 = 1−M
1+M
∆t −→ 0
n n→∞
(7.27)
∆vn+1 = 1−M

1+M
∆v −→ 0
With maximum modulation index Mmax =1, the time interval t+ of the phase shifted
PWM approaches Tbr and 0 with positive and negative voltages respectively, which means
that at one instant close to the maximum modulation the switching of the input and
output stage will start to overlap and the resultant bridge voltage will have switching
frequency equal to the HF-link voltage fbr = fs1 = fs2 .
It is interesting to notice that, if the self-oscillating modulator is designed to have basic
∗
idling switching frequency lower than two times the HF-link frequency fs2,0 < 2 · fHF ,
∗
i.e. Mlim ≡ 0, then the corresponding self-oscillating SICAM will be in locked operation
all the time. Even more, if the maximum modulation index is limited to value less than
unity Mmax < 1, then the switching of both stages is not simultaneous. This means
that many other SICAM topologies which utilize safe-commutation strategies, presented
in Section 6.2.1 and in [53], [85] can be used in conjunction with the proposed self-
oscillating modulator because of the natural synchronization between the stages during
locked operation. This saves some power components on behalf of slightly more complex
control circuitry for implementing the safe-commutation switching sequence.
7.3.5 Output stage switching frequency

To summarize, the switching frequency of the output stage fs2 in the self-oscillating
SICAM differs when operating in normal or locked mode and can be described with
the following equation:
( 1 1 − M2
∗
, M < Mlim
fs2 = 4 τint kh ka + td (7.28)
∗
fs1 , M ≥ Mlim
and represents a discontinuous function, shown in Fig. 7.17. The same figure shows the
transferred charge to the clamp and its power in the case of a SICAM with active capac-
itive voltage clamp from Section 6.2.3, operated with the modified GLIM self-oscillating
modulator for SICAMs.
1200 5
Q
tr
1000 4
fs2 [kHz], Qtr[nC]
800
3
Pcl[W]
600 P
cl
2
400
f 1
s2
200
M
lim
0 0
0 0.2 0.4 0.6 0.8 1
Modulation index M
Fig. 7.17. Output stage switching frequency, transferred charge and clamp power (in SICAMs with load voltage
clamp)
7.3.6 Audio distortion of self-oscillating SICAM

THD of SICAMs depends predominantly on the used topology and it was already calcu-
lated for the two most common SICAM output stages using safe-commutation switching
sequence and active capacitive voltage clamp in Sections 6.2.3 and 6.2.1, correspond-
ingly. However, in both cases the switching frequency of the output stage was selected as
constant, like using some of the aforementioned synchronized or unsynchronized PWM
methods from the previous sections.
THD of the SICAM with active capacitive voltage clamp with self-oscillating GLIM
modulator, operating in open loop control with modulation signal of fm = 1 kHz is
shown in Fig. 7.18. In the simulation secondary-side voltage is Vs = 59 V, clamp voltage
is Vcl = 65 V, maximum modulation index is Mmax = 0.8, modulator loop delay is
td = 150 ns, blanking time is tbl = 75 s, modulator window is kh = 1/151 and amplifier
gain is ka = 20. THD gradually decreases with higher modulation indexes as the result of
the falling switching frequency and the increased switching period Ts2 , while the blanking
time tbl stays essentially the same.
7.4 Closed-loop control schemes

As shown in the previous sections, in every switching-mode audio power amplifier notice-
able distortion within the audio band is introduced as a result of the nonlinearities in the
7.4 Closed-loop control schemes 213
14
12
10
THD [%]
8
0
0 50 100 150
Output power Po [W]
Fig. 7.18. THD of SICAM with active capacitive voltage clamp
power stage. Therefore, various kinds of closed loop control are utilized to diminish the
effects of power supply variations, noise and error sources, parameter variations, as well
as to decrease the amplifier output impedance. In control systems with negative feedback
all the aforementioned negative effects are decreased by the amount of gain in the open
loop transfer function L [60]:
L 1 Gvg Zo
vo = vref + vg − io (7.29)
1 + L Hv 1+L 1+L
where vo is the output voltage, vref is the reference voltage, vg is the amplifier input
voltage, io is the load current, Hv is the voltage feedback coefficient, Gvg is the transfer
function from the input voltage vg to the output voltage vo and Zo is the amplifier output
impedance.
The demand for high open loop gain within the audio bandwidth, known also as power
bandwidth, coincides with the demand for having much higher control bandwidth fc ,
defined as a frequency at which the open loop transfer function L has a gain of one. This
is however not easy to achieve because of the 180◦ phase shift introduced by the output
filter, that spoils the phase margin and threatens stability.
The selection of control approach usually represents a trade-off between simplicity and
performance. The block diagram of simple output voltage control through single closed
feedback loop is presented in Fig. 7.19. The presence of the output filter double poles makes
it very difficult to achieve simultaneously proper phase margin and high control bandwidth
i.e. the loop gain within the desired power bandwidth must be kept to reasonable values
for robust and reliable operation.
Other options are also possible, like cascade control with fast inner current loop and
slower outer voltage loop. The inner current loop can be based on the real load current
measurement or load current estimator, like shown in Fig. 7.20, with the parameters ex-
plained in Table 7.1. What the inner current loop effectively does is that it eliminates the
pole associated with the output filter inductor from the open loop transfer function up to
the bandwidth of the inner current loop, thus making it much easier to close the outer
voltage feedback loop and provide sufficient gain through integrating action. Since the
simplicity of the solution is of utmost interest, complex, expensive and dissipative induc-
tor current sensing through current sense resistors can be replaced with simple inductor
current estimator.
Power
PWM amplifier Output filter
Reference shaper Compensator modulator
Ga(s) Gf(s)
vref + e 1
__ L vout
R(s) Gc(s)
VC
_
C
vmeas
Hfb(s)
Voltage feedback
Fig. 7.19. Block diagram of simple output voltage control

SICAM Power stage
iO 1
__
Reference Voltage Current
PWM ZO
shaper compensator compensator
Ka _ _
vref ev iref ei vc 1
__ vbr vL 1
__ iL iC 1
__ vC vO
R CV CI VC sL sC
_ _ _
vfb ifb RL RC
Current
estimator
N
__E
GE NL
HV
Fig. 7.20. Control block diagram of cascade control
Inductor current estimator is built with additional winding put on the inductor core
and sensing the inductor voltage vL , which bears information about the inductor current
iL :
1 t
Z
iL = vL (τ )dτ (7.30)
L 0
Unfortunately, due to the voltage offsets of the common operational amplifiers it is
impossible to build an ideal integrator, which will not saturate when put in a real noisy
circuit. In order to alleviate these problems, integrator is replaced with a low pass filter,
which has a finite gain at DC and therefore does not saturate, except maybe for some DC
offset in the output voltage. The transfer function of the inductor current estimator is:
Ne ki,est
Gi,est = (7.31)
NL 1 + sτi,est
Selection of estimator bandwidth is trade-off between the size of the low pass filter and
cut-off frequency of the output filter. If the main purpose of closing the inner feedback
loop is to dampen the resonance of the output filter by removing the pole associated
with the inductor to higher frequencies, then this can be achieved with inductor current
estimator which does not reproduce the low frequency content of the inductor current
very well, but still captures the high frequency content around the filter resonance very
accurately.
7.5 Conclusion
This chapter presented several open-loop and closed-loop control methods for achieving
reliable and safe operation of different SICAM topologies presented in the previous chap-
7.5 Conclusion 215
Table 7.1. Explanation of the parameters in Fig. 7.20

Parameter Description Comment
R Reference shaper Limits the bandwidth of the input signal
CV Voltage compensator With its PI-element characteristics reduces
the errors in the outer loop
CI Current compensator With its PI-element characteristics reduces
the errors in the inner loop
VC Carrier amplitude External triangular carrier generator
with fixed frequency is used
Ka Amplifier gain Proportional to the secondary-side voltage
L, C Output filter components The output filter has low-pass filter
characteristics
RL , RC Output filter parasitics Resistance of the inductor wire and ESR
of the capacitor
Zo Amplifier output impedance At higher frequencies is dominated by
the output filter inductor
NL , N E Number of turns on the inductor The inductor has one operational and
one estimator winding
GE Current estimator transfer function Integrates or low-pass filters
the inductor voltage
Hv Voltage feedback coefficient Reciprocal of the closed-loop system gain
ter. It was emphasized that although unsynchronized control methods give some extra
flexibility in selecting independently the switching frequencies of the input and the out-
put stage, they give rise to intermodulation harmonics in the audio band and therefore
result in lower performance. At the same time, optimized PWM control methods with
synchronization can provide lower switching frequency of the output stage and therefore
lower switching losses, as well as the required non-simultaneous switching of the stages
for safe commutation of the load current in the output stage.
SICAMs can be also controlled by self-oscillating modulators commonly found in
Class D audio power amplifiers, by doing some simple modifications in their structure
to account for the alternating polarity of the HF-link voltage. Thus, the radically new
and compact way of building isolated audio power amplifiers through HF-link converters
is combined with the state-of-the-art self-oscillating modulators for Class D audio power
amplifiers to create high-performance audio power amplifiers with smaller form factors.
At the end, several simple closed-loop control methods suitable for SICAMs are pre-
sented, capable of suppressing the adverse effects of variable HF-link voltage and nonide-
alities of the power stage, rejecting undesired perturbances in the output voltage as well
as reducing the output impedance.
8
Prototypes of isolated SICAMs with non-modulated
transformer voltages
”I hope that posterity will judge me kindly, not only as
to the things which I have explained, but also to those
which I have intentionally omitted so as to leave to
others the pleasure of discovery. ”
- René Descartes
In this chapter, several prototypes of isolated SICAMs with non-modulated transformer

voltages will be presented. They will represent a mixture of different SICAM topologies
from Chapter 6 and different control principles from Chapter 7.
8.1 Isolated SICAM with master/slave operation for achieving

safe commutation
One of the first prototypes in the project was the 100 W @ 8 Ω isolated SICAM with
master/slave operation to enable reliable safe commutation of the output stage, shown
in Fig. 8.1. Its circuit schematics can be found in Appendix F.1. The output stage has a
full-bridge configuration and consists of bidirectional switches as antiparallel connection
of two voltage 2QSW, as depicted in Fig. 6.12. The implemented voltage-controlled safe-
commutation switching sequence is given in Table 6.2 and was implemented with simple
digital logic, where all commutation delays were implemented as resistor-capacitor-diode
(RCD) combinations. Therefore the implementation of the safe-commutation switching
sequence was not flexible and changing the commutation delays required substantial re-
work. The primary switching frequency was selected to be fs1 = 100 kHz to optimize
the transformer weight vs. losses, while the secondary-side PWM triangular carrier was
chosen to be fc2 = 200 kHz. The implemented PWM has simple structure described in
Section 7.1.1. No frequency locking and synchronization between the input and the out-
put stage existed, thus substantial amount of intermodulation harmonics within the audio
band could be expected due to slight variations in the switching frequency of the stages.
Detailed operation of the master/slave SICAM is shown in Fig. 8.2. Both stages share
a common M/S digital line, which represents enabling signal for the latches corresponding
to the gate drivers of the switches in the input and the output stage. In this way, whenever
one of the stages pulls the M/S line low and performs transition, the other stage cannot
switch due to lack of enabling signal. Each switching of the input stage causes reversal of
the HF-link voltage polarity and thus immediate switching of the output stage, since the
operation of the PWM modulator is not optimized. These two events are clearly visible
in traces 1 and 2 in Fig. 8.2.
The driving signals for the MOSFETs 1&6, 2&5, 3&8 and 4&7 in the output stage
shown in Fig. 6.12 are given in Fig. 8.3. This transition occurs due to change of the HF-
link voltage polarity from positive to negative (upper rail negative), according to Table 6.2
and starting from 1,6&3,8 turned on.
218 8 Prototypes of isolated SICAMs with non-modulated transformer voltages
Fig. 8.1. Photograph of the prototype master/slave-operated SICAM
Fig. 8.4 depicts open-loop operation of the M/S SICAM, while Fig. 8.5, Fig. 8.6 and
Fig. 8.7 show the closed-loop operation with different output power levels. The FFT of the
output voltage is given on the same diagrams. Looking at the waveforms of output voltage
and its FFT at different power levels, it is clearly visible that there is significant amount
of distortion. This is likely due to many different issues, like noise problems, relatively
low ratio of switching frequency to modulating frequency, PWM modulator nonlinearity
and distorted triangular carrier in closed loop operation by fedback switching noise. No
further measurements were made for audio performance and conversion efficiency.
8.2 Isolated SICAM with simple PWM modulator and active

capacitive load voltage clamp
In order to test the feasibility of the proposed approach, a 100 W prototype of the isolated
SICAM with active capacitive voltage clamp was constructed, as shown in Fig. 8.8. Its
circuit schematics can be found in Appendix F.2. The primary switching frequency was
selected to be fs1 = 100 kHz to optimize the transformer weight vs. losses, while the
secondary-side PWM triangular carrier was chosen to be fc2 = 225 kHz, in order to avoid
having too many primary-secondary intermodulation harmonics within the audio range.
Independent primary and secondary switching frequencies lead to simpler design with
much easier start-up circuitry and possibility to optimize the losses and dimensions of
both the input stage and the transformer, but from purely audio perspective frequency
locking and synchronizing the operation of the input and the output stage is necessary to
improve the audio performance by avoiding intermodulation cross-products.
Operation of the SICAM with active capacitive voltage clamp with more and less
detail is shown in Fig. 8.9 and Fig. 8.10 respectively. Notice that the HF-link voltage has
rectangular waveform with duty cycle of 50%, while the bridge voltage applied across the
combination of the output filter and loudspeaker is chopped from the HF-link voltage in
a PWM manner.
The THD+N vs. frequency measurement in Fig. 8.11, THD+N vs. power measurement
in Fig. 8.12, intermodulation distortion in Fig. 8.13 and FFT measurement in Fig. 8.14
show the promising audio performance of the prototype.
8.2 Isolated SICAM with simple PWM modulator and active capacitive load voltage clamp 219
Fig. 8.2. Detailed master/slave SICAM operation: Fig. 8.3. Safe-commutation switching sequence:
1) Input stage M/S line driver base voltage, 2) out- 1) MOSFETs 1&6 driving signal, 2) MOSFETs 2&5
put stage M/S line driver base voltage, 3) M/S line driving signal, 3) MOSFETs 3&8 driving signal, and
voltage, and 4) input stage voltage polarity (T1 /T4 4) MOSFETs 4&7 driving signal for negative rail volt-
driving signal) (all probes 10x) age (all probes 10x)
Fig. 8.4. Open-loop operation with 10 kHz reference: Fig. 8.5. Closed loop operation at Pout =0 W with
1) load voltage, 2) bridge voltage, and 3) reference 10 kHz reference: 1) load voltage, 2) reference signal,
signal (probes 1 and 2 - 50x, 3 - 10x) and M1) FFT (probe 1 - 50x, probe 2 - 10x)
Fig. 8.6. Closed loop operation at Pout =1 W with Fig. 8.7. Closed loop operation at Pout =10 W with
10 kHz reference: 1) load voltage, 2) reference signal, 10 kHz reference: 1) load voltage, 2) reference signal,
and M1) FFT (probe 1 - 50x, probe 2 - 10x) and M1) FFT (probe 1 - 50x, probe 2 - 10x)
Fig. 8.8. Photograph of the prototype SICAM with active capacitive voltage clamp
The distribution of power losses in the prototype SICAM components and stages and its
efficiency are calculated based on the theory presented in Section 6.4 and are presented
in Fig. 8.15 and Fig. 8.16. Measured efficiency of the prototype is given in Fig. 8.17.
The theoretical efficiency curve in Fig. 8.16 does not account for the power losses in the
auxiliary power supplies and the control biasing i.e. the idling losses are not included.
This explains the difference in the theoretically calculated efficiency and the measured,
together with some neglected loss contributors.
8.3 Isolated SICAM with optimized PWM modulator and

safe-commutation switching sequence
To test the SICAM approach with the proposed safe-commutation strategy and the new
PWM method, a 100 W @ 8 Ω laboratory prototype according to Fig. 6.13 was built and
measured. Its circuit schematics can be found in Appendix F.3. The final primary switch-
ing frequency was selected to be fs1 = 150 kHz and the secondary switching frequency
is two times higher i.e. fs2 = 300 kHz. Some of the first measurements were made with
primary switching frequency of fs1 = 100 kHz and the secondary switching frequency of
fs2 = 200 kHz. The safe-commutation switching sequence in Table 6.3 is programmed into
a programmable logic device (PLD), together with the part of the PWM modulator which
selects the correct PWM sequence according to the polarity of the HF-link and the input
stage switching frequency prescaler. The safe-commutation state machine in Fig. 6.15 is
implemented as synchronous with the clock at frequency of fclk = 20 MHz, so the com-
mutation delay is ∆td = 50 ns. Both the synchronization signal between the stages and
the gate signals to the bidirectional switches are transferred using fast optocouplers. The
main transformer is used for both energy transfer to the output stage as well as deriving
control power supplies and isolated gate drive supplies on the secondary side. Sensing the
inductor voltage for the current estimator is done with additional isolated winding on
the inductor core, thus very effectively avoiding the problems with signal referencing and
conditioning. The prototype is shown in Fig. 8.18.
Fig. 8.19 and Fig. 8.20 show the safe-commutation switching sequence from Table 6.3
into action with more and less detail. Commutation delay is set here to ∆td = 100 ns to
clearly separate each switching transition in the figure.
8.3 Isolated SICAM with optimized PWM modulator and safe-commutation switching sequence 221
Fig. 8.9. Detailed SICAM operation: 1) HF-link volt- Fig. 8.10. SICAM operation: 1) HF-link voltage
age (100V/div), 2) bridge voltage (100V/div), 3) volt- (100V/div), 2) bridge voltage (100V/div), 3) voltage
age reference (2V/div), 4) output voltage (5V/div) reference (2V/div), 4) output voltage (5V/div) with
with 10 kHz reference 10 kHz reference
Fig. 8.11. THD+N versus frequency (BW=22kHz Fig. 8.12. THD+N versus power (BW=22kHz and
and AES17 filter): top - 10 W, bottom - 50 W, middle AES17 filter): bottom - 100 Hz, middle - 1 kHz, top -
- 75 W 6.67 kHz
Fig. 8.13. Intermodulation distortion Fig. 8.14. FFT at 50 W with a signal of 1 kHz
The selection of different PWM modulators according to the polarity of the HF-link
voltage, as described in Section 7.2.2 is depicted in Fig. 8.21. This multiplexing of the
PWM modulator outputs can be also observed in Fig. 8.22, together with the synchro-
nization of the HF-link voltage changes with the valleys of the triangular carrier.
All previous measurements were made with switching frequency of 100 kHz for the
input stage and 200 kHz for the output stage.
The SICAM waveforms with reference voltage of 1 kHz at Po =25 W with more and
less detail are shown in Fig. 8.23 and Fig. 8.24 respectively.
The total harmonic distortion plus noise (THD+N) measurement of the SICAM vs.
frequency for output power of 10 W and 40 W is given in Fig. 8.25.
The THD+N vs. power measurement of the SICAM at 100 Hz, 1 kHz and 6.67 kHz is
given in Fig. 8.26.
Finally, the intermodulation distortion of the SICAM is given in Fig. 8.27.
The FFT of the output voltage at output power of Po =25 W, with a reference set to
100 W is given in Fig. 8.28.
The distribution of power losses in the components and stages of the prototype SICAM
and its efficiency are calculated based on the theory presented in Section 6.4 and are shown
in Fig. 8.29 and Fig. 8.30. It can be seen that, at least theoretically, the efficiency at full
power is supposed to be higher than the targeted one, but the theoretical calculations
do not take into consideration the power losses in the auxiliary power supplies and the
control biasing i.e. the idling losses. The measured efficiency of the prototype is given in
Fig. 8.31 and is significantly lower than the calculated efficiency in Fig. 8.30, which is
likely due to some neglected loss contributors, parasitic ringing/oscillations and possible
shoot-through conditions.
All presented results show that the proposed SICAM approach is capable of reproducing
audio with a sufficient level of fidelity, which makes it an attractive solution for the lower
end of the market. The efficiency is somewhat lower than expected, but this is likely to
be improved in future.
8.4 Isolated self-oscillating SICAM with GLIM modulator

The 100 W @ 8 Ω laboratory prototype of isolated self-oscillating SICAM with GLIM
modulator according to Fig. 7.12b was built to tryout the proposed self-oscillating modu-
lators for SICAMs in Section 7.3. Its circuit schematics can be found in Appendix F.4. The
switching frequency of the free-running input stage was selected to be fs1 = 150 kHz. Mul-
tiplexing the outputs of the two comparators for positive and negative HF-link voltages is
implemented in the digital logic of the PLD. The latter also houses the safe-commutation
switching sequence from Table 6.3 in locked operation mode and the blanking time gen-
eration for the output stage when active clamp is used in combined normal and locked
operation mode. The safe-commutation state machine on Fig. 6.15 is implemented as syn-
chronous with the clock at frequency of fclk = 20 MHz, so either the commutation delay
or the blanking time is equal to 50 ns. All measurements in this section were made in
combined normal and locked operation mode with the usage of the active clamp. Clamp
voltage is set to Vcl = 65 VS. The prototype is shown in Fig. 8.32.
The detailed self-oscillating SICAM waveforms with 0 V and 10 V output voltage are
shown in Fig. 8.33 and Fig. 8.33. The ringing in the bridge voltage due to the switch
parasitics and nonzero output impedance of the input stage, as well as its clamping to
the voltage of the clamp capacitor are clearly visible.
8.5 Conclusion 223
The operation of the self-oscillating SICAM with sinusoidal references of 1 kHz and
10 kHz are shown on a larger time scale in Fig. 8.35, Fig. 8.36 and Fig. 8.37. The output
voltage is inverted due to the specific GLIM design and the reduced number of used
operational amplifiers. Again the clamping action of the active clamp is clearly visible.
The total harmonic distortion plus noise (THD+N) measurement of the SICAM vs.
frequency for output power of 6 W is given in Fig. 8.38. No further audio and efficiency
measurements were performed.
In conclusion, the audio performance of the prototype is low and total harmonic dis-
tortion and noise is excessive. However this is characteristic of the test prototype itself
and is likely due to unresolved noise issues, so it is by no means a general conclusion. The
presented waveforms show the viability of the self-oscillating approach for SICAMs.
8.5 Conclusion
The prototypes presented in this chapter combined the load current commutation tech-
niques presented in Chapter 6 with some of the control methods described in Chapter 7.
The design process for these SICAM prototypes turned to be an involved task, since be-
hind the simple and low component count power topologies shown on the previous figures
lie hidden plenty of construction details. The resulting prototypes were functional and
operated as expected, as shown in the numerous oscillograms.
The measured audio performance and efficiency of the prototypes were found to be
less than the targeted ones in the project description. Somewhat lower efficiency of the
SICAM approach can be explained with the increased component voltage and current
stress of the proposed single-stage audio amplification topologies. This problem seems
to be very similar to the lower efficiency of single-stage PFC rectifiers when compared
to their two-stage counterparts. It is believed, however, that the measured results are
prototype specific and can be by all means improved in future with more careful design and
selection of better components. Introduction of soft-switching techniques (ZVS and ZCS)
through alternative input stage topologies like those reviewed in the beginning sections
of Chapter 6 and using switch snubbers and clamps can give those extra efficiency points
needed to make SICAM even more attractive.
SICAM power losses SICAM efficiency

15 100
Rectifier bridge
Storage capacitor
Input stage 80
[W]
Transformer
10 Output stage
Efficiency [%]
loss
Output filter 60
Power losses P
Clamp
Total
40
5
20
0 0
0 20 40 60 80 100 0 20 40 60 80 100
Output power Po[W] Output power Po[W]
Fig. 8.15. Distribution of power losses in prototype Fig. 8.16. Theoretical efficiency of the prototype
SICAM with active clamp SICAM with active clamp (”T”-shaped markings rep-
resent the targeted minimum efficiency)
Efficiency of SICAM prototype

100
80
Efficiency [%]
60
40
20
0
0 20 40 60 80 100
Output power Po [W]
Fig. 8.17. Measure efficiency of the SICAM prototype with active clamp (”T”-shaped markings represent the
targeted minimum efficiency)
Fig. 8.18. Photo of the prototype SICAM with safe-commutation switching sequence
8.5 Conclusion 225
Fig. 8.19. SICAM safe-commutation switching se- Fig. 8.20. SICAM safe-commutation switching se-
quence with vHF > 0: 1) SW21, 2) SW22, 3) SW23, quence with vHF > 0: 1) SW21, 2) SW22, 3) SW23,
4) SW24 4) SW24
Fig. 8.21. Optimized PWM method for SICAMs: Fig. 8.22. SICAM safe-commutation switching se-
1) PWM with positive signal, 2) PWM with negative quence with vHF > 0: 1) reference voltage, 2) trian-
signal, 3) resultant PWM, 4) HF-link voltage gular carrier, 3) bridge voltage, 4) HF-link voltage
Fig. 8.23. SICAM waveforms at Po =25 W: 1) ref- Fig. 8.24. SICAM waveforms at Po =25 W: 1) ref.
erence voltage, 2) output voltage 3) bridge voltage, voltage, 2) out. voltage 3) bridge voltage, 4) HF-link
4) HF-link voltage(50x) voltage(50x)
Fig. 8.25. THD+N vs. frequency at Po =10 W (top) Fig. 8.26. THD+N vs. output power at fo =100 Hz
and Po =40 W (bottom) (bottom), fo =1 kHz (middle) and fo =6.67 kHz (top)
Fig. 8.27. Intermodulation distortion Fig. 8.28. FFT of the output voltage at Po =25 W
(100 W reference)
SICAM efficiency
SICAM power losses
100
Rectifier bridge
Storage capacitor
Input stage 80
15
[W]
Transformer
Output stage
Efficiency [%]
loss
Output filter 60
Power losses P
Total
10
40
5
20
0 0
0 20 40 60 80 100 0 20 40 60 80 100
Output power Po[W] Output power Po[W]
Fig. 8.29. Distribution of power losses in prototype Fig. 8.30. Theoretical efficiency of the prototype
SICAM with safe-commutation switching sequence SICAM with safe-commutation switching sequence
(”T”-shaped markings represent the targeted mini-
mum efficiency)
8.5 Conclusion 227
Efficiency of SICAM prototype

100
80
Efficiency [%]
60
40
20
0
0 20 40 60 80 100
Output power Po [W]
Fig. 8.31. Measured efficiency of the SICAM prototype with safe-commutation switching sequence (”T”-shaped
markings represent the targeted minimum efficiency)
Fig. 8.32. Photo of the prototype self-oscillating SICAM with GLIM modulator
Fig. 8.33. Self-oscillating SICAM waveforms with Fig. 8.34. Self-oscillating SICAM waveforms at Vo =
zero reference: 1) carrier, 2) out. voltage 3) bridge 10 V: 1) carrier, 2) out. voltage 3) bridge voltage,
voltage, 4) HF-link voltage(50x) 4) HF-link voltage(50x)
Fig. 8.35. Self-oscillating SICAM waveforms with Fig. 8.36. Self-oscillating SICAM waveforms at Po =
zero reference: 1) ref. voltage, 2) out. voltage 3) bridge 6 W with 1 kHz reference: 1) ref. voltage, 2) out.
voltage, 4) HF-link voltage(50x) voltage 3) bridge voltage, 4) HF-link voltage(50x)
Fig. 8.37. Self-oscillating SICAM waveforms at Po = Fig. 8.38. THD+N vs. frequency at Po =6 W
6 W with 10 kHz reference: 1) ref. voltage, 2) out.
voltage 3) bridge voltage, 4) HF-link voltage(50x)
9
4Q flyback SICAM with modulated transformer
voltages
”Science is a differential equation. Religion is a
boundary condition.”
- Alan Turing
Flyback converter presents the simplest isolated power supply topology, where the filter-
ing inductor is actually integrated into the isolation transformer and represents means of
transferring the energy from the primary-side voltage source to the secondary-side load.
Consequently, the flyback converter saves the designer one magnetic component, but it
increases the size and the stress exerted upon the other components, like the output ca-
pacitor that is to supply the whole load current for the periods when the main switch is
turned on. On the other hand, there is just single-order filtering of the current switching
harmonics at the output, performed solely by the output capacitor, which leads to sub-
stantial voltage ripple on the output. Therefore this topology is used only at lower power
levels, when its benefits are most pronounced.
4Q flyback SICAM is a representative of the isolated SICAMs with modulated trans-
former voltages, which means that the primary side switches perform all the audio mod-
ulation of the voltages/currents, while the secondary side switches represent kind of syn-
chronous rectifiers and perform the demodulation on the load side.
9.1 Operation and design of 4Q flyback SICAM

The two-switch four-quadrant (4Q) flyback SICAM is shown in Fig. 9.1. It is derived
from the two-switch flyback converter by using the principles for developing SICAMs
from conventional isolated SMPS topologies laid in Section 5.4 and depicted in Fig. 5.15.
The secondary side consists of two windings and two bidirectional switches: T21 − T22 with
antiparallel diodes D21 − D22 and T23 − T24 with antiparallel diodes D23 − D24 , while the
primary side stays essentially the same like in the two-switch flyback SMPS.
D21 D22
TR & IND
T11 T21 T22

+ D11 io
~ ~ . vo +
. .
AC
mains
C1 .
- CF
io T23 T24
D12
T12
D23 D24
Fig. 9.1. Two-switch 4Q flyback SICAM

230 9 4Q flyback SICAM with modulated transformer voltages
The amplifier is operated in a way that the primary side switches are turned on until
enough energy has been stored in the magnetizing inductance of the flyback transformer,
which is afterwards released either through T21 − T22 or T23 − T24 to charge the output
capacitor to the desired voltage across the load. When the energy has been delivered to the
load the current is allowed to reverse so that part of the capacitor charge is delivered back
to the magnetizing inductance and returned to the primary side during the on-time of the
main switches. This allows the flyback converter to operate in continuous conduction mode
like a ”rocking chair”, where first the energy is delivered to the load side and then maybe
it is partly returned back to the primary side. Current through the primary-side switches
i1 , currents through the secondary-side switches i21 , i22 , output voltage vo , control voltage
vc , state of the 1-bit quantizer Q and reference current iref of the 4Q flyback SICAM are
all given in Fig. 9.2.
T11-T12 T21-T22 T11-T12 T23-T24

i1
to n to ff Ts
i2 1, i2 2
i2 1 i2 2
v0
vc,Q, iref
Q iref
vc
Fig. 9.2. Waveforms of the 4Q flyback SICAM
The 4Q flyback SICAM can be constructed as either single-switch or two-switch. In

the practical implementations of single-switch DC-DC flyback converters, it is necessary
to use a clamp on the primary side of the transformer to dissipate the energy stored in
the primary-side leakage inductance. However, the voltage across the transformer during
the off-time of the main switch can have either polarity and therefore the primary side
clamp can be charged from the load side whenever the output voltage reflected to the
primary side is higher than the clamp voltage. The two-switch 4Q flyback SICAM does
not experience the same problem, since the transformer primary side during the off-time
of the main switch is clamped to the rectified input voltage by using the two freewheeling
diodes D11 and D12 . This voltage is always bigger than the reflected load voltage since it is
limited by the design i.e. the duty cycle is less than 50%. Because of the same reason, the
primary side switches do not need to have bidirectional voltage blocking capability, but
must have bidirectional current capability (ex. MOSFETs) to allow continuous current-
mode operation. Taking into account the additional benefit that the two-switch flyback
converter requires switches with just half the voltage blocking capability of the one-switch
flyback converter, it can be concluded that the two-switch topology represents a very
feasible choice for bidirectional converters from cost and implementation perspective.
9.1 Operation and design of 4Q flyback SICAM 231
The disadvantages of the flyback converter with regard to the large output capacitance
needed for filtering the switching harmonics of the inductor current become even more
pronounced in its bidirectional implementation. The output capacitor is supplying the
whole load current during the on-period of the main switches, therefore the demands
set upon it are very stringent. Due to the bipolar nature of the output voltage, the
unipolar aluminium electrolytic type capacitors found in conventional switching-mode
power supplies cannot be used and the size of the output section is inevitably increased.
Therefore, the flyback topology for SICAMs is limited to low power levels.
The most difficult part of the design of the 4Q flyback SICAM power section is the
selection of the output capacitor and the flyback transformer magnetizing inductance.
The minimum output capacitor is determined by the desired maximum output voltage
ripple:
Q Io,max Dmax
Cmin = = (9.1)
∆Vmax ∆Vmax fs
where Io,max is the maximum load current, Dmax is the maximum duty cycle, ∆Vmax is
the maximum voltage ripple and fs is the switching frequency.
Although Cmin is the minimum output capacitance needed with regard to the output
voltage ripple limit, it is also the optimal since increasing that value significantly over
Cmin will result in slower response. It will be shown in the next section that the actual
output voltage ripple can also depend on the bandwidth of the outer voltage loop, with
the proposed control methods.
Choosing the optimal value of the inductance represents slightly greater challenge.
One way of choosing the magnetizing inductance is by determining the maximum slope
of the average output current io = Io sin(2πf t) and associated average inductor current
iL = io /(1 − D):
SIo ,max = 2πfmax Io cos(2πfmax t)|t=0 = 2πfmax Io
SIo ,max (9.2)
SIL ,max =
1 − Dmax
and choosing the instantaneous rising slope of the inductor current Vg /L to be at least 20
times higher than the average inductor current slope SIL ,max .
The other preferred way of selecting the magnetizing inductance is by noting that it is
limiting the minimum frequency of the right-half plane zero fRHP Z [60]:
′2
Dmin R R
fRHP Z,min = = 0.5 (9.3)
2πDmax Lmax 2πLmax
It is known that the maximum usable control bandwidth of a system is limited to
approximately one third of the frequency of the right half-plane zero [93] and one tenth
of the switching frequency fs . This leads for example to the following selection rule:
R R
Lmax = 0.5 = 0.5 (9.4)
2π · fRHP Z,min 2π · 0.3fs
Slightly different 4Q flyback converter has been presented in [94], where it is built
around a dedicated chipset for ring generators. Its operation principles differ from the
proposed simple solution, since during the off-time of the main switch, the secondary side
switches are operated in a PWM manner and energy is transferred to the primary side
via a separate winding with series rectifier. Another difference is that the secondary side
switches can block both voltage polarities, but the current can only be unidirectional and
the flyback converter operates in discontinuous conduction mode without the aforemen-
tioned ”rocking chair” effect.
9.2 Control of 4Q flyback SICAM

The selection of the control algorithm for the 4Q flyback SICAM represents a trade-off
among many different objectives, like stability, low distortion and simplicity of implemen-
tation.
The simplest way of control is single loop output voltage control, where the only feed-
back is taken from the load voltage and is used afterwards to derive the main switch duty
cycle. The main disadvantages with this approach are the involved second order transfer
function with the continuous mode operation, which makes it very difficult to make sat-
isfactory control synthesis, as well as the inability to correct for input line perturbations
until changes are observed in the output voltage.
Much better performance can be achieved with current-mode control, where the inner
current loop and the outer voltage loop are simultaneously used to derive the duty cycle
of the main switch. While the voltage loop is always taken from the load, the selection of
current for closing the inner current loop can ask for careful consideration. In the buck
derived topologies, where the second order LC output filter is placed across the load, the
inductor current is essentially the load current and by controlling directly the inductor
current, the dynamics of the load current is being governed too. On the other hand, the
flyback output current is different than the inductor current by a factor which depends
on the duty cycle and it can be disputed which of these two is to be controlled. However,
if the goal of the current selection is to simplify the control synthesis of the outer voltage
loop, then by controlling the inductor current the pole associated with the inductor is
moved to higher frequencies. Even more, sensing inductor current is sometimes easier due
to its continuity and can be done in many different ways, some being more simple than
the others. Therefore, in the following sections will be dealt only with inductor current
control in the inner loop.
There are many different ways to implement current-mode control, among which the
peak and average current-mode control are probably the most applicable ones. They have
some distinct advantages and pitfalls, which define their specific application areas. They
can be both used in 4Q flyback SICAMs and their implementation is subject of the next
few sections.
9.2.1 Peak current-mode control
The block scheme of the control section of the 4Q flyback SICAM with peak current-mode
control is given in Fig. 9.3. As shown, it is a cascade system where the inner loop sets the
inductor current and the outer loop controls the output voltage. The absolute value of the
control voltage vc gives the reference current iref , while its sign given by the comparator i.e.
1-bit quantizer Q determines which secondary-side bidirectional switch will be turned on
during the off-time of the primary side switches. The reference current iref is subsequently
compared with the instantaneous value of the switch current to determine the switching-off
instant, resulting in peak current-mode control. Beside the aforementioned simplification
of the transfer function, the peak current-mode control yields a simple solution with fast
response, high rejection ratio of the input voltage perturbations and cycle-by-cycle current
limiting.
In order to avoid output voltage zero-crossing distortion i.e. crossover distortion, there
must be some minimum inductor current delivered to the output even at idle. During this
idling time, the 1-bit quantizer is likely to be stuck in a certain state of the output stage,
which means that the output voltage will continue to increase in one direction. With other
words, 4Q flyback SICAM does not have any stable equilibrium state corresponding to
9.2 Control of 4Q flyback SICAM 233
idle, which represents a strong contrast to the conventional Class D audio power amplifier,
where operation with duty cycle of 50% assures zero average output voltage with certain
predetermined and limited output filter ripple. In the 4Q flyback SICAM it is up to the
outer voltage loop to sense this excessive voltage ripple at idle and prohibit it by changing
the sign of the control voltage vc and the associated output stage state. Therefore, in this
implementation it is very important to have shorter time delays within the control loop and
provide high control bandwidth, by increasing the gain of the phase compensator Gv (s).
The highest possible gain of the compensator at the switching frequency, which does not
cause instability is determined by matching the up-slope of the increasing inductor current
and the down-slope of the falling output voltage, like shown in Fig. 9.4:
Vg vo
RCS =A
L RC
(9.5)
RCS · R · C · Vg,min
Amax =
L · Vo,max
where RCS is the current sense resistor, Vg is the DC source voltage, R is the load resistance
and A is the gain from the output voltage to the input of the current controller at fs .
Design of the phase compensator Gv (s) is performed by shaping the overall loop transfer
function L so that both sufficient gain throughout the desired signal frequency range and
high bandwidth are obtained. The plotting of the loop transfer function is alleviated
by assuming that the inner current loop operates ideally and the inductor current iL is
following the reference current iref with a high degree of accuracy, although this essentially
depends on the level of inductor current ripple ∆iL . The loop gain L and its constitutive
parts are:
i vo
D21 D22
TR & IND
T11
Ton Ton
T21 T22
{
+ D11 i21 +1
~ ~ . vo +
. . +
AC
mains
C1 . CF
-1 Vg L C R
-
{
T12 i22
D12 T23 T24
D23 D24
X
_i vo
_
e
+1 RS-FF G(s)
iref vref
-1
Q
vo
_i _
e
RS-FF ABS Gv(s) iref iref
iref vc i i
vref
Ton Ton
Fig. 9.3. Peak current-mode control stable unstable

Fig. 9.4. Slope matching
L(s) = Gv (s)GiL c (s)GoiL (s)Gopto (s)Hv (s)

1
Gv (s) = K(1 + )
sτi
1
GiL c (s) =
nRCS KCS
(9.6)
R
GoiL (s) =
1 + sRC
Gopto (s) = Ki
1
Hv (s) =
Kv
where Gv is the transfer function of the PI voltage phase compensator, GiL c is the transfer
function from the reference current to the inductor current, GoiL is the transfer function
from the inductor current to the output voltage, Gopto is the gain of the linear optocoupler
transferring the current reference from the primary to the secondary side and Hv is the
gain f the voltage feedback. Control block diagram of the 4Q flyback SICAM with peak
current-mode control is given in Fig. 9.5.
Fig. 9.5. Peak current-mode control block diagram
It is interesting to note that, although the 4Q flyback converter has much simpler
power section than the Class D amplifier with separate power supply, the control section
shown in Fig. 9.3 tends to be involved and is further aggravated by the need for crossing
the isolation barrier. The way this is usually done in a conventional flyback SMPS is
to transfer the current reference using a simple optocoupler, which often has a highly
nonlinear current transfer ratio (CTR) when looked in a large signal sense. On the other
hand, the operation of a 4Q flyback SICAM involves largely varying control signals and
the current reference iref must be transferred to the isolated primary side with high degree
of accuracy to avoid excessive distortion. The easiest way to do that is to use a linear
optocoupler with servo loop built around it for linearizing its CTR. This results in a
combined primary and secondary side control, where the phase compensator of the outer
voltage loop resides on the secondary side and the phase compensator of the inner current
loop is implemented on the primary side together with the sensing of the switch current.
As an option, switch current can be sensed and transferred to the secondary side with a
current transformer, so that all the control is located on the secondary side. However, the
gate drive signals for the primary side switches still need to be transferred back with a
separate pulse transformer, thus complicating this option even further.
9.3 Measurements on a 4Q flyback SICAM prototype with average current-mode control 235
9.2.2 Average current-mode control

Beside the aforementioned advantages of the peak current-mode control with regard to
its simplicity, speed and cycle-by-cycle current limiting, there are also some serious draw-
backs. The most important drawback is the fact that controlling the peak value of the
inductor current does not necessarily mean that the average inductor current value fol-
lows the current reference, which becomes especially pronounced in the continuous mode
operation with large ripple current and even more in the discontinuous mode. For exam-
ple, if the peak inductor current follows perfectly the sinewave current reference of the
audio amplifier, the actual average inductor current is likely to be much different than the
reference, depending on the amount of current ripple. As a side effect of this problem, the
low frequency gain of the peak current-mode controller is limited and does not guarantee
high performance throughout the whole power bandwidth.
Operation of the 4Q flyback SICAM with large inductor ripple current is desired for
at least two reasons. Firstly, large ripple is a result of low flyback transformer inductance
which allows for much smaller size of the magnetics. On the other hand, low inductance
is also a must, since for proper operation of the audio power amplifier the current level
must be changed sufficiently fast to achieve the desired dynamics of the converter. This
means that correct control of the average inductor current with low distortion will be
nearly impossible with peak current-mode control.
In order to reduce the distortion, average current-mode control can be implemented and
optimized by slope matching for achieving optimal speed of the response [95], comparable
to peak current-mode control. By proper design of the phase compensator in the inner
current loop, sufficient gain can be provided even at low frequencies where peak current-
mode control is unable to deliver the same performance when large inductor current ripple
is present.
Average current-mode control also enables use of non-dissipative techniques for induc-
tor current sensing, in contrast to the usual current sense resistor technique. The inductor
current can be estimated by putting additional winding on the flyback transformer and
ideally integrating the transformer voltage with electronic components. In this case all the
control can be done on the secondary side, and it is just the main switches gate drive that
needs to be transferred to the primary side. In practice, integration of the transformer
voltage is impossible due to the non-zero offset of operational amplifiers, and what is
usually done is low pass filtering to derive exactly the high frequency content of the in-
ductor current. This essentially means that the DC value of the inductor current with this
method can not be recovered. Thus the low frequency performance of the control circuit
is left to the outer voltage loop. The control block diagram of the 4Q flyback SICAM with
average current-mode control is given in Fig. 9.6 and the complete schematic is given in
Fig. 9.7. Inductor current estimator transfer function is:
Ne 1
Gi,est (s) = Ki,est · · (9.7)
Nl 1 + sτi,est
where Ki,est and τi,est represent the estimator gain and time constant, and Ne and Nl are
the estimator and inductor number of turns respectively.
9.3 Measurements on a 4Q flyback SICAM prototype with

average current-mode control
To test the feasibility of the proposed simple approach to building isolated SICAMs with
modulated transformer voltages, an 80 W into 8 Ω two-switch 4Q flyback subwoofer
Fig. 9.6. Average current-mode control block diagram

D21 D22
TR & IND
T11
T21 T22
{
+ D11 i21 vo +1
~ ~ . vo +
. .
AC
mains
C1 . CF
-1
-
{
T12 i22
D12 T23 T24
D23 D24
X
Giest(s) +1
-1
PWM
Q
+
-
vo
_iest _
e
Gc(s) ABS Gv(s)
iref vc
vref
Fig. 9.7. Average current-mode control
SICAM prototype with average current-mode control was constructed and its photo is
shown in Fig. 9.8. Its circuit schematics can be found in Appendix F.5. The switching
frequency is set to fs = 150 kHz. The prototype resembles the structure shown in Fig. 9.7.
It also incorporates integrated magnetics structure for deriving all the auxiliary voltages
on the secondary side as explained in Section 10.2 and depicted in Fig. 10.5.
Fig. 9.8. 4Q flyback SICAM prototype

9.3 Measurements on a 4Q flyback SICAM prototype with average current-mode control 237
Fig. 9.9 shows in detail the operation of the 4Q flyback SICAM with zero reference. The
short on-periods of the primary side switches represent some minimum allowed on-time
being intentionally inserted even with no error voltage on the input of the controller, just
to avoid zero-crossing distortion of the output voltage. The state of the one-bit quantizer
Q determines the secondary side bidirectional switch, which will be turned on right after
the primary side switches seize conducting. The selected bidirectional switch is turned
on for the rest of the time until the primary side switches conduct again, although the
state of the one-bit quantizer Q maybe has changed in the meantime. Due to the fast
outer voltage loop even this small ripple in the output voltage is sensed and is causing
an immediate change in the control voltage sign, so that the selected bidirectional output
switch alternates each period to yield minimum ripple voltage. Making the outer voltage
loop slow will cause the output voltage ripple to be large, since the guaranteed minimum
inductor current with the same output switch turned on during few periods will continue
charging the output capacitor to large values.
Fig. 9.10 depicts the operation of the 4Q flyback SICAM with constant DC-reference,
leading to output voltage of around Vo =16 V at output power of Po =32 W. It can be seen
that the width of the gate-drive pulses on the primary side has increased compared to the
idling width in Fig. 9.9, to deliver the necessary power to the load side.
Fig. 9.11 shows the operation of the 4Q flyback SICAM at output power of Po =50 W
with 200 Hz reference voltage. The shape of the output voltage looks very good, but a
measurement with audio equipment revealed THD+N of few percents in the whole audio
range, which is not very close to the desired levels for the application.
The efficiency of the prototype η as function of the output power Po is given in Fig. 9.12
and the idling losses are approximately Pidle =9 W. This particular realization of SICAM
has lower efficiency than the targeted one according to the project description, which is
not very strange for flyback implementation where the components are extremely stressed.
However, it is believed that a major part in the lower efficiency of the prototype itself
is played by poor synchronization of the primary and secondary switches, which leads to
certain short shoot-through events, as well as the relatively high idling power losses.
Fig. 9.9. Waveforms with zero reference: 1) ref. volt- Fig. 9.10. Waveforms with DC-reference: 1) ref. volt-
age vref , 2) output voltage vo , 3) comparator Q out- age vref , 2) output voltage vo , 3) comparator Q out-
put, 4) primary gate drive put, 4) primary gate drive
Efficiency of 4Q flyback SICAM prototype

100
90
80
70
Efficiency [%]
60
50
40
30
20
10
0
0 20 40 60 80
Output power Po [W]
Fig. 9.11. Waveforms at Po =50 W with 200 Hz refer-
ence: 1) ref. voltage vref , 2) output voltage vo , 3) com- Fig. 9.12. Efficiency of the 4Q flyback SICAM pro-
parator Q output, 4) primary gate drive totype (”T”-shaped markings represent the targeted
minimum efficiency)
9.4 Conclusion
4Q flyback SICAM is the simplest isolated SICAM topology with modulated transformer
voltages, where the inductor is integrated in the main transformer and filter capacitor is
the only discrete filtering component at the output. It operates in a similar way to the
common flyback SMPS topology, except that the secondary-side winding has a central
tap and two bidirectional switches to redirect the magnetizing current to the either end
of the load. The operation of the primary and secondary switches, described as ”rocking
chair” to symbolize the flow of energy in both directions, must be fairly synchronized in
order to avoid significant flow of energy in the primary-side clamp or back to the grid.
Although 4Q flyback represents a very simple topology, the output filtering capacitor
is bulky and is subject to high component stress, since it supplies the whole load current
during the periods when the primary-side switches are turned on. Because of the same
reason, output voltage ripple is also high. One additional problem is created by the right-
half plane zero pertinent to the flyback topology, which significantly limits the highest
achievable control bandwidth.
Two control methods being extensions of the common current mode control are pre-
sented: simple peak current mode control, which lacks low frequency gain and average
current mode control, which is desirable also for the possibility of easily integrating in-
ductor current estimator in the control scheme.
The presented measurement results of a prototype prove the feasibility of the 4Q flyback
SICAM for audio power amplification. Its application is intended for lower output power
levels and lower audio frequency range with limited performance requirements i.e. for not
very high-demanding application, like for example subwoofer applications.
10
Integrated magnetics for isolated SICAMs
”He who loves practice without theory is like the sailor
who boards ship without a rudder and compass and
never knows where he may cast.”
- Leonardo Da Vinci
This chapter presents a new integrated magnetics design for HF-link converters, which
can significantly improve the compactness and reduce component count by placing the
magnetic components from the auxiliary power supply or having some design-specific
functions on the same magnetic core with the main transformer. The proposed integrated
magnetics can be built around all standard three-leg cores used in power electronics, which
have the possibility for putting bobbins on each of the legs. The only additional burden
is the somewhat increased winding, manufacturing and assembling complexity, as well as
a possible requirement for slightly increasing the volume of the original magnetic core.
The main difference of the proposed solution when compared with other integrated
magnetics designs for switching-mode power supplies [96], is that the windings of the
corresponding structures do not belong to the same voltage loop and do not share the
same voltage waveforms, which opens some new application areas.
The proposed integrated magnetics concept is very similar to patent [97] citing some
possible SMPS applications, but it was developed totally independently from it and with
having just the SICAM applications in mind.
10.1 Analysis of the integrated magnetics

In order to develop the proposed integrated magnetics design for HF-link converters, it
is important to analyze the three-winding transformer, shown in Fig. 10.1. By having
three transformer legs, the equivalent electrical circuit introduces two loops i.e. contours,
characterized by two independent fluxes Φ′ and Φ′′ . These fluxes are functions of the
magnetomotive forces (MMF) Fi in the corresponding contours and are used to calculate
the fluxes Φi :
(R2 + R3 )F1 − R3 F2 − R2 F3
Φ1 =
R1 R2 + R3 (R1 + R2 )
−R3 F1 + (R1 + R3 )F2 − R1 F3
Φ2 = (10.1)
R1 R2 + R3 (R1 + R2 )
−R2 F1 − R1 F2 + (R1 + R2 )F3
Φ3 =
R1 R2 + R3 (R1 + R2 )
Beside the general case in Fig. 10.1, especially interesting is one specific transformer
design depicted in Fig. 10.2. As a result of the equal number of turns in the outer windings
and their series connection, the magnetomotive forces F1 and F3 are equal by amplitude
and with opposite signs F1 = −F3 = Fl . The central leg magnetomotive force is likely to
be different F2 = Fc . It is also assumed that the transformer core is ideally symmetrical,
which means that the magnetic reluctances of the outer legs are equal R1 = R3 = Rl and
240 10 Integrated magnetics for isolated SICAMs
F1 F3
F2 F1 F2 F3
R1 R2 R3
N1 N2 N3 F’ F’’
+ + +
F1 F2 F3
Fig. 10.1. Three-winding transformer and its equivalent electrical circuit
different from the reluctance of the central leg R2 = Rc , resembling many of the standard
ferrite cores. In this case the leg fluxes become:
(Rl + 2Rc )Fl − Rl Fc

Φ1 =
Rl (Rl + 2Rc )
2Fc
Φ2 = (10.2)
Rl + 2Rc
−(Rl + 2Rc )Fl − Rl Fc
Φ3 =
Rl (Rl + 2Rc )
F1 F3
F2
N1 N2 N3=N1
Fig. 10.2. Special design of the three-winding transformer
From (10.2) it is clear that under ideally symmetrical conditions, the center leg flux Φ2
is not affected by the magnetomotive forces Fl in the outer legs. Even more, the induced
voltage in the two series outer windings does not have any component associated with the
center leg flux:

dΦ1 dΦ3 d Fl
vi = N1 − N3 = N1 (10.3)
dt dt dt Rl
Simulation of the MMFs and the induced voltages in the central leg and outer legs
windings of an E42/21/15 core under ideally symmetrical conditions is given in Fig. 10.3.
In reality, it is very difficult to achieve total symmetry due to manufacturing and

assembling tolerances, so it is interesting to challenge the above conclusions. Assuming
that there is a slight difference between the magnetic reluctances of the outer legs in excess
of 2∆R due to, for example, slightly different core dimensions or non-equal air-gapes, leg
fluxes become:
10.2 Application to HF-link converters 241
(2Rc + Rl − ∆R)Fl − (Rl − ∆R)Fc

Φ1 =
(Rl + ∆R)Rc + (Rl − ∆R)(Rl + ∆R + Rc )
2∆RFl + 2Rl Fc
Φ2 = (10.4)
(Rl + ∆R)Rc + (Rl − ∆R)(Rl + ∆R + Rc )
−(2Rc + Rl + ∆R)Fl − (Rl + ∆R)Fc
Φ3 =
(Rl + ∆R)Rc + (Rl − ∆R)(Rl + ∆R + Rc )
The relationships in (10.4) for the non-ideal case show that when ∆R ≪ Rl , the center
leg flux is still affected only by the center leg magnetomotive force Fc . The resultant
induced voltage in the series windings of the outer legs is equal to the derivative of the
outer fluxes sum:

d d 2N1 (2Rc + Rl )Fl + 2N1 ∆RFc
vi = (Φ1 + Φ3 ) = (10.5)
dt dt (Rl + ∆R)Rc + (Rl − ∆R)(Rl + ∆R + Rc )
which is not significantly affected by the central leg MMF if ∆R ≪ 2Rc + Rl . The
aforementioned conditions in practice are not too difficult to obey and do not represent a
limiting factor. Simulation of the MMFs and the induced voltages in the central leg and
outer legs windings under asymmetrical conditions with ∆R = 10% is given in Fig. 10.4,
showing just a slight induced voltage modulation.
It is of ultimate importance to carefully design the proposed integrated magnetics with
regard to saturation, since the resultant flux Φ2 ±Φ1 /2 in the outer rim can easily saturate
the outer legs, which usually have only half of the effective cross-section area of the center
leg. Another important issue is to limit the integrated magnetics operation to only the
linear part of the magnetization characteristics, since operating it on the saturated part
will introduce cross-coupling effects among the fluxes in the respective legs.
10.2 Application to HF-link converters

The block scheme of the direct energy conversion switching-mode audio power amplifier
with HF-link shown, i.e. a SICAM in Fig. 5.2 introduces much simpler power conversion
topology than the conventional approach in Fig. 5.1 comprising of a separate switching-
mode power supply and a Class D audio power amplifier connected to its DC-link. How-
ever, what is not immediately clear from these simplified block diagrams is that SICAM
requires many magnetic components with different functions:
∆R=0% ∆R=0%
10 10
MMF [A turns]
MMF [A turns]
central central
leg leg
0 outer 0 outer
legs legs
−10 −10
0 1 2 3 4 5 6 0 1 2 3 4 5 6
−5 −5
x 10 x 10
Induced voltages [V]
Induced voltages [V]
500 500
central central
leg leg
0 0
outer outer
legs legs
−500 −500
0 1 2 3 4 5 6 0 1 2 3 4 5 6
time [s] −5 time [s] −5
x 10 x 10
Fig. 10.3. MMFs and induced voltages under sym- Fig. 10.4. MMFs and induced voltages under asym-
metrical conditions ∆R = 0% metrical conditions ∆R = 10%
• main power transformer - with all topologies,

• auxiliary power transformer - for control biasing and maybe for isolated gate drives,
especially in SICAMs with modulated transformer voltages,
• output filter inductor - with all topologies,
• signal transformers - for transfer of signals between the input and the output stage,
• impulse transformers for bidirectional switch gate drive, and
• power transformer for the active clamp circuit - with certain SICAM topologies.
In one implementation of SICAM with modulated transformer voltage [3], transformer
voltages are PWM modulated by the input switching stage according to the reference
signal. This means that the transformer flux and subsequently the power flow to any
secondary winding are dependent on the reference signal and are far from constant. This
makes it impossible to put any auxiliary windings on the transformer central leg for pro-
viding control biasing and/or isolated gate drive supplies. However, by using the proposed
integrated magnetics and a simple switching converter on the primary, many symmetrical
windings can be fitted on the outer legs to derive auxiliary voltages. This is shown in
Fig. 10.5, in the case of a 2-switch four-quadrant flyback audio power amplifier, whose
transformer voltages are modulated by the reference.
In order to improve the efficiency of SICAMs with dissipative clamp for commutating
the load current in the output stage [9], SICAM with active capacitive voltage clamp
from Section 6.2.3 which returns the clamped energy from the secondary side back to
the primary side capacitor can be implemented by using a simple single-switch isolated
converter. With the proposed integrated magnetics, the active clamp converter can be
implemented on the same core with the main transformer, as shown in Fig. 10.6.
All isolated SICAMs have two switching stages and their operation usually is synchro-
nized in order to avoid any possible intermodulation products in the output voltage or to
achieve safe commutation of the load current in the output stage, as already described
in Section 7.2.2. In most of the cases, switching instants of the primary stage are derived
from the triangular carrier of the PWM modulator placed in the secondary side controller.
Instead of using additional optocouplers or signal transformers for transferring the switch-
ing command to the primary, the latter can be achieved simply by putting two sets of
symmetrical windings on the power transformer outer legs, as shown in Fig. 10.7.
As an ultimate task of magnetic integration, the output filter inductor can be integrated
in the HF-link transformer. Since the inductor necessitates substantial gapping of the
ferrite core in order to be able to store enough magnetic energy, it is appropriate to fit the
inductor on the center leg and the transformer on the outer legs, as depicted in Fig. 10.8.
This is likely to necessitate larger core to accommodate both fluxes and fit both windings,
but on the other hand it is a single magnetic component.
10.2.1 Practical investigation of the proposed integrated magnetics

The proposed integrated magnetics was implemented in several isolated SICAM proto-
types with different topologies and with different goals for the integration, like presented
above. In this section, some measurement results of the integrated magnetics within the
4Q flyback SICAM prototype from Section 9.3 will be presented.
Fig. 10.9 shows the voltage waveforms across the auxiliary power supply secondary-
side winding and main secondary-side winding, in the case when only the auxiliary power
supply primary-side winding is driven with rectangular voltage. It can be observed that
this has almost no effect on the voltage induced in the main secondary-side winding,
except for some oscillations which are likely minor resonance of the main winding leakage
inductance with the oscilloscope probe parasitic capacitance.
10.3 Conclusion 243
D21 D22
T11 T21 T22

D11
+
~ ~ .
C1
AC
mains
- CF
D12 T23 T24
T12
D23 D24
Daux
C13 T13
Caux
C14 T14
Fig. 10.5. 2-switch 4Q flyback SICAM with integrated magnetics for auxiliary power supplies
D21 D22
T21 T22
+ C1 T11 D11
~ ~ LF
AC
mains
-
C2 T12 D12 CF
T23 T24
D23 D24
~
D13
+ -
~
C3
D3
Fig. 10.6. SICAM with active capacitive voltage clamp using integrated magnetics
Fig. 10.10 shows the voltage waveforms across the auxiliary power supply secondary-
side winding and main secondary-side winding, in the case when both the main primary-
side winding and auxiliary power supply primary-side winding are driven with rectangular
voltage. It is clear that now the operation of the main primary-side winding can be sensed
in the slightly distorted rectangular voltage of the auxiliary power supply secondary-side
winding, but nonetheless the operation of the auxiliary power supply is not being adversely
affected.
10.3 Conclusion
In this chapter a new integrated magnetics design was proposed for SICAMs, where both
magnetic components placed on a common three-leg core are entirely independent and
do not share the same voltage waveforms. It is shown that decoupling of the integrated
D21 D22
T21 T22
+ C1 T11 D11
~ ~ LF
AC
mains
-
C2 T12 D12 CF
T23 T24
D23 D24
Primary-side Secondary-side
control control
Fig. 10.7. SICAM with safe commutation and synchronization through integrated magnetics
+ C1 T11 D11
T21 D21 T25 D25
~ ~ T22 D22 T26 D26

AC
mains
- T23 D23 T27 D27
C2 T12 D12 CF
T24 D24 T28 D28
Fig. 10.8. SICAM with output filter inductor integrated on the main transformer
Fig. 10.9. Voltage waveforms across: 1) auxiliary Fig. 10.10. Voltage waveforms across: 1) auxiliary
power supply secondary-side winding (5 V/div), and power supply secondary-side winding (5 V/div), and
2) main secondary-side winding (1 V/div) 2) main secondary-side winding (20 V/div)
magnetic components is satisfactory even in the case of slight imbalance due to manu-
facturing and material tolerances, as long as the magnetic reluctances of the legs and
the intentional air gaps are larger than the assembly asymmetries. SICAMs are complex
power conversion systems which need many magnetic components for proper operation
and they can significantly benefit from the proposed integrated magnetics concept.
11
General conclusion about SICAMs
This Ph.D. thesis defined the notion of SICAM - SIngle Converter stage AMplifier as a
single-stage approach to building isolated and non-isolated audio power amplifiers. They
strive for as direct energy conversion from the mains to the audio output as possible, by
dedicating the operation and functions of the constitutive parts one to another. This in
turn results in significant simplifications of the whole power conversion chain and topolo-
gies with lower reactive component count, but on behalf of using more fully controlled
silicon components and complex control methods. This evolvement of the audio power am-
plification technology is justified by the ever increasing performance of the silicon power
components, while the reactive components have reached the flat end of their development
curve due to the natural limits of the dielectric and magnetic materials today.
The challenges in building both isolated and non-isolated SICAMs were clearly em-
phasized on several occasions.
In the non-isolated mains-connected case, the most natural way to follow is to use a
simple full-bridge rectifier with a bulky energy storage capacitor to create a stiff DC-bus,
and then use a high voltage Class D audio power amplifier. While this approach exhales
in simplicity, the high input voltage creates several problems like decreased audio per-
formance and using suboptimal switching power components with much higher blocking
voltage than the output voltage. Therefore, the most interesting approach for the non-
isolated mains-connected SICAMs is to use a voltage-step-down PFC front end, or even
incorporating the step-down PFC functions as part of the full-bridge Class D amplifier by
using the presented advanced control techniques.
In the non-isolated SICAMs for portable applications powered by batteries, the main
challenge is to provide output voltage levels that are higher and lower, respectively, than
the battery voltage, which is changing in a large range during the typical discharge cycle. It
was concluded that in order to maintain the single-stage approach, it is necessary to build
a buck-boost-type audio power amplifier with strongly nonlinear output characteristics.
The presented digital precompensation control techniques provide a neat way for partial
linearization of the aforementioned output characteristic even in open loop operation.
The most challenging task was however the development of isolated SICAMs, which are
equally applicable to single and multichannel audio systems and feature high enough level
of simplicity and innovation. For this application inspiration was found in HF-link power
converters, well known from converters for alternative energy sources and uninterruptible
power supplies (UPSs). Two main classes of isolated SICAMs were identified: isolated
SICAMs with modulated and non-modulated transformer voltages. In the former, the
PWM modulation of the transformer voltage is done with regard to one audio reference
and therefore building a multichannel audio system requires using separate SICAM for
each channel. Despite of some advantages like the much simplified load current commu-
tation in the output stage, this approach was not investigated herein, partly due to the
246 11 General conclusion about SICAMs
large amount of patents in the area. SICAMs with non-modulated transformer voltages
have the problem of reliable load current commutation in the output stage, but they are
much more appealing for multichannel audio systems, where each additional channel can
reuse the same input stage and transformer, thus adding to the product just the cost of
a new output stage and slight overdimensioning of the preceding stages.
The main problem with the isolated SICAMs with non-modulated transformer volt-
ages is the commutation of the load current in the output stage. This can be done either
by using advanced safe-commutation switching sequences which turn on and off the bidi-
rectional switches in the output stage in a prescribed manner, or by using dissipative
and active clamping techniques. Both techniques have their own pros and cons which
were clearly presented in the text. The safe-commutation switching technique is how-
ever preferred because there are no additional power components needed for performing
the load current commutation. Several advanced control techniques for isolated SICAMs
were presented as an improvement of the simplest PWM control technique, which take
into consideration the specifics of the HF-link power conversion or even enable the use of
safe-commutation switching techniques.
The simplest isolated SICAM can be obtained by reworking the simplest isolated DC
power supply i.e. the flyback converter, by increasing its control bandwidth and adding
bidirectional power capability. The obtained SICAM is essentially characterized by modu-
lated transformer voltages, and all the filtering at the output is done with single capacitor.
Due to the high component stress, the 4Q flyback SICAM is intended just for low-end
and low power amplifiers.
Further simplifications in the practical implementation of the isolated SICAMs can be
obtained by introducing integrated magnetics, which makes it possible to integrate two
independent magnetic components on the same three-leg magnetic core. Several possible
applications have been proposed in the thesis.
When compared to the conventional solution with separate SMPS and Class D ampli-
fier, the proposed compact direct energy conversion switching-mode audio power amplifier
i.e. SICAM introduces much simpler and much more compact power topology. Together
with the promises of higher efficiency, less heatsinking material, less volume and board
space, reduced number of reactive components and prospects for high-level integration,
leading subsequently to lower cost, SICAM represents a highly competitive technology for
the lower-end and cost-driven segment of the audio market.
A
Analysis of matrix SICAM
A.1 Time domain analysis of the two load combinations

During the operation of a matrix SICAM with LC-network there are two possible load
combinations LkR and CkR, shown in Fig. A.1b and c. The circuit combination where
the LC-network is unloaded is not interesting, since it is characterized with large voltage
and current stress of the resonant network.
R
L L L
vin C R vin C vin C
R
a) b) c)
Fig. A.1. General topologies: a) vin kR, b) LkR and c) CkR (same as Fig. 2.25)
In the following the two aforementioned load combinations will be analyzed in time
domain.
A.1.1 Time domain analysis of CkR combination
Voltage across the inductor L is given by:

diL
vL = L = vin − vC (A.1)
dt
which leads to the following expression for the inductor current first derivative:
diL 1 1
= − vC + vin (A.2)
dt L L
Current through the capacitor C is given by:
dvC 1
iC = C = iL − iR = iL − v C (A.3)
dt R
which leads to the following expression for the capacitor voltage first derivative:
dvC 1 1
= iL − vC (A.4)
dt C RC
248 A Analysis of matrix SICAM
After making another time derivation of (A.4):
d2 vC 1 diL 1 dvC
2
= − (A.5)
dt C dt RC dt
and substituting the equation (A.2) for the first derivative of inductor current, the follow-
ing second order differential equation is obtained:
d2 vC 1 dvC 1 1
2
+ + vC = vin (A.6)
dt RC dt LC LC
Define the following angular frequencies:
1
ωR = RC
(A.7)
ωL = √1
LC
Now the differential equation for the CkR case can be rewritten as following:
d2 vC dvC
2
+ ωR + ωL2 vC = ωL2 vin (A.8)
dt dt
Solution to the differential equation (A.8) can be found as a linear combination of
the homogenous solution vCh = vCh (t) when vin (t) ≡ 0 and one particular solution
vCp = vCp (t) (for the sake of simplicity the time variable t is omitted):
vC = vCh + vCp (A.9)
Homogenous differential equation has the form:
d2 vCh dvCh
2
+ ωR + ωL2 vCh = 0 (A.10)
dt dt
Using the Euler substitution of form vCh = est the following quadratic equation is
obtained:
s2 + ωR s + ωL2 = 0 (A.11)
with solutions:
p
−ωR ± ωR2 − 4ωL2
s1,2 = (A.12)
2
and the time constants being:
1
τ1,2 = (A.13)
s1,2
Finally, homogenous solution has the form:

t t
vCh (t) = AC es1 t + BC es2 t = AC e τ1 + BC e τ2 (A.14)
where AC and BC represent constants, which can be determined from the differential
equationś initial conditions. Index letter C in the constants is used to represent the CkR
configuration.
Particular solution vCp = vCp (t) is a solution to the following differential equation:
A.1 Time domain analysis of the two load combinations 249
d2 vCp dvCp
2
+ ωR + ωL2 vCp = ωL2 vin (A.15)
dt dt
Since the input has the form of a sine function:
vin (t) = Vin sin ωin t (A.16)
the particular solution consists of both sine and cosine functions:

vCp = DC sin ωin t + EC cos ωin t
dvCp
= −ωin EC sin ωin t + ωin DC cos ωin t (A.17)
dt
d2 vCp 2 2
= −ωin DC sin ωin t − ωin EC cos ωin t
dt2
Substituting the vCh and its first two derivatives from (A.17) to (A.15) the following
equation is obtained:
2
(−ωin DC − ωR ωin EC + ωL2 DC ) sin ωin t + (−ωin
2
EC + ωR ωin DC + ωL2 EC ) cos ωin t =
= ωL2 Vin sin ωin t
(A.18)
Comparing both sides of the equation (A.18), the following system of two equations
for determining the unknown constants is obtained:
(ωL2 − ωin
2
)DC − ωR ωin EC = ωL2 Vin
(A.19)
ωR ωin DC + (ωL2 − ωin
2
)EC = 0
After expressing EC from the second equation and substituting it in the first equation
for determining DC , the following expressions for the constants are obtained:
ωL2 (ωL2 − ωin
2
)
DC = 2 2 2
Vin
(A.20)
ωR ωL2 ωin
EC = − 2 2 2
Vin
Complete solution (A.9) is like the following:
vC (t) = AC es1 t + BC es2 t + DC sin ωin t + EC cos ωin t (A.21)
Using the following initial conditions for the moment t = 0:

vC (0) = vC0
dvC (0) dvC0 (A.22)
=
dt dt
the following linear system with two unknown constants AC and BC is obtained:
vC0 = AC + BC + EC
dvC0 (A.23)
= AC s1 + BC s2 + DC ωin
dt
After expressing BC from the first equation and substituting it in the second equation
to determine AC , the following expressions for the constants are obtained:
− dvdtC0 + vC0 s2 − EC s1 + ωin DC

AC =
s2 − s1
dvC0 (A.24)
− vC0 s1 + EC s2 − ωin DC
BC = dt
s2 − s1
√
In the case of resonance ωL = ωin = 1/ LC constants DC and EC become:
DC = 0
(A.25)
EC = − ωωin
R
Vin
A.1.2 Time domain analysis of LkR combination
Time domain analysis of LkR general topology follows the same path as in the CkR case.
Voltage across the inductor L is given by:
diL
vL = L = vin − vC (A.26)
dt
which leads to the following expression for the inductor current first derivative:
diL 1 1
= − vC + vin (A.27)
dt L L
Current through the capacitor C is given by:
dvC 1
iC = C = iL + iR = iL + (vin − vC ) (A.28)
dt R
which leads to the following expression for the capacitor voltage first derivative:
dvC 1 1 1
= iL − vC + vin (A.29)
dt C RC RC
After making another time derivation of (A.29):
d2 vC 1 diL 1 dvC 1 dvin

2
= − + (A.30)
dt C dt RC dt RC dt
and substituting the equation (A.27) for the first derivative of inductor current, the fol-
lowing is obtained:
d2 vC 1 dvC 1 1 1 dvin
2
+ + vC = vin + (A.31)
dt RC dt LC LC RC dt
Using the angular frequencies defined in (A.7) the differential equation for the LkR
case can be rewritten as following:
d2 vC dvC 2 2 dvin
+ ωR + ωL v C = ωL v in + ωR (A.32)
dt2 dt dt
Solution to the differential equation (A.32) can be found as a linear combination of the
homogenous solution vCh = vCh (t) when vin ≡ 0 and one particular solution vCp = vCp (t)
(for the sake of simplicity the time variable t is omitted):
vC = vCh + vCp (A.33)

A.1 Time domain analysis of the two load combinations 251
Homogenous differential equation has the same form as in the CkR case:
d2 vCh dvCh
+ ωR + ωL2 vCh = 0 (A.34)
dt2 dt
Using the Euler substitution of form vCh = est the following quadratic equation is
obtained:
s2 + ωR s + ωL2 = 0 (A.35)
with the same solutions as in the CkR case:

p
−ωR ± ωR2 − 4ωL2
s1,2 = (A.36)
2
and the time constants being also the same:
1
τ1,2 = (A.37)
s1,2
Finally, homogenous solution has the form:
t t
vCh (t) = AL es1 t + BL es2 t = AL e τ1 + BL e τ2 (A.38)
where AL and BL represent constants, which can be determined from the differential
equationś initial conditions. Index letter L in the constants is used to represent the LkR
configuration.
Particular solution vCp = vCp (t) is a solution to the following differential equation:
d2 vCp dvCp 1 dvin

2
+ ωR + ωL2 vCp = ωL2 vin + (A.39)
dt dt RC dt
Since the input has the form of a sine function and its first derivative as cosine function:
vin (t) = Vin sin ωin t

dvin (t) (A.40)
= ωin Vin cos ωin t
dt
the particular solution is a combination of sine and cosine functions:
vCp = DL sin ωin t + EL cos ωin t

dvCp
= −ωin EL sin ωin t + ωin DL cos ωin t (A.41)
dt
d2 vCp 2 2
= −ωin DL sin ωin t − ωin EL cos ωin t
dt2
Substituting the vCh and its first two derivatives from (A.41) to (A.39) the following
equation is obtained:
2
(−ωin DL − ωR ωin EL + ωL2 DL ) sin ωin t + (−ωin
2
EL + ωR ωin DL + ωL2 EL ) cos ωin t =
= ωL2 Vin sin ωin t + ωR ωin Vin cos ωin t
(A.42)
Comparing both sides of the equation (A.42), the following system of two equations
for determining the unknown constants is obtained:
(ωL2 − ωin
2
)DL − ωR ωin EL = ωL2 Vin
(A.43)
ωR ωin DL + (ωL2 − ωin
2
)EL = ωR ωin Vin
After expressing EL from the second equation and substituting it in the first equation
for determining DL , the following expressions for the constants are obtained:
ωL2 (ωL2 − ωin
2
) + (ωR ωin )2
DL = Vin
(ωL2 − ωin
2 2
) + (ωR ωin )2
3 (A.44)
ωR ωin
EL = − 2 2 2
Vin
Complete solution (A.33) is like the following:
vC (t) = AL es1 t + BL es2 t + DL sin ωin t + EL cos ωin t (A.45)
Using the following initial conditions for the moment t = 0:

vC (0) = vC0
dvC (0) dvC0 (A.46)
=
dt dt
the following linear system with two unknown constants AL and BL is obtained:
vC0 = AL + BL + EL
dvC0 (A.47)
= AL s1 + BL s2 + DL ωin
dt
After expressing BL from the first equation and substituting it in the second equation
to determine AL , the following expressions for the constants are obtained:
− dvdtC0 + vC0 s2 − EL s1 + ωin DL
AL =
s2 − s1 (A.48)
dvC0
− v C0 1 + EL s2 − ωin DL
s
BL = dt
s2 − s1
√
In the case of resonance ωL = ωin = 1/ LC constants DL and EL become:
DL = Vin
(A.49)
EL = − ωωin
R
Vin
A.2 State-space model of matrix SICAM

One can pursue a state-space approach to characterize each of the different possible con-
figurations/topologies of the MC-based SICAM using an LC-network. Inductor current iL
and capacitor voltage vC are chosen as state variables and output voltage vout and input
current iin as output variables. The general form of state-space equations is:
dx
= Ai x + bi vin
dt (A.50)
y = Ci x + di vin
where x = [iL vC ]T is the state vector, y = [vout iin ]T is the output vector, Ai , bi , Ci and
di are the system matrix, the input vector, the output matrix and the input-to-output
vector, i=2, -2, 1-2 or 2-1.
A.2 State-space model of matrix SICAM 253
State-space equations
Exact equations for each of the cases are presented herein.

• 2 corresponding to duty cycle d2
diL
L = vin − vC
dt
dvC vC
C = iL − iout = iL − (A.51)
dt R
vout = vC
iin = iL
diL
0 − L1
1
dt
iL
dvC= 1 1 + L vin (A.52)
dt C
− RC
v C 0

vout 0 1 iL 0
= + v (A.53)
iin 10 vC 0 in
So the system matrix A2 , input vector b2 , output matrix C2 and input-to-output
vector d2 are:
0 − L1

A2 = 1 1
C
− RC
1
b2 = L
0
(A.54)
0 1
C2 =
10

0
d2 =
0
• -2 corresponding to duty cycle d−2
diL
L = vin − vC
dt
dvC vC
C = iL + iout = iL − (A.55)
dt R
vout = −vC
iin = iL
diL
0 − L1
1
dt
iL
dvC= 1 1 + L vin (A.56)
dt C
− RC
v C 0

vout 0 −1 iL 0
= + v (A.57)
iin 1 0 vC 0 in
So the system matrix A−2 , input vector b−2 , output matrix C−2 and input-to-output
vector d−2 are:
0 − L1

A−2 = 1 1
C
− RC
1
b−2 = L
0
(A.58)
0 −1
C−2 =
1 0

0
d−2 =
0
• 1-2 corresponding to duty cycle d1−2
diL
L = vin − vC
dt
dvC vC vin
C = iL + iout = iL − +
dt R R (A.59)
vout = vin − vC
vC vin
iin = iL + iout = iL − +
R R
diL
0 − L1
1
dt
iL
dvC = 1 1 + 1L vin (A.60)
dt C
− RC
v C RC

vout 0 −1 iL 1
= 1 + 1 vin (A.61)
iin 1 −R vC R
So the system matrix A1−2 , input vector b1−2 , output matrix C1−2 and input-to-
output vector d1−2 are:
0 − L1

A1−2 = 1 1
C
− RC
1
b1−2 = 1L
RC
(A.62)
0 −1
C1−2 =
1 − R1

1
d1−2 = 1
R
• 2-1 corresponding to duty cycle d2−1
diL
L = vin − vC
dt
dvC vC vin
C = iL − iout = iL − +
dt R R (A.63)
vout = vC − vin
vC vin
iin = iL − iout = iL − +
R R
diL
0 − L1
1
dt
iL
dvC = 1 1 + 1L vin (A.64)
dt C
− RC
v C RC
A.2 State-space model of matrix SICAM 255

vout 0 1 iL −1
= 1 + 1 vin (A.65)
iin 1 −R vC R
So the system matrix A2−1 , input vector b2−1 , output matrix C2−1 and input-to-
output vector d2−1 are:
0 − L1

A2−1 = 1 1
C
− RC
1
b1−2 = 1L
RC
(A.66)
0 −1
C2−1 =
1 − R1

1
d2−1 = 1
R
State-space averaging
Averaging of the state-space equations presented in the previous section during one switch-
ing interval Ts leads to filtering of the switching frequency harmonics [60]. Since the switch-
ing interval Ts is very small compared to the AC-mains voltage period
Ts ≪ Tin = 1/50Hz = 20ms, AC-mains input voltage vin remains unaffected.
Averaged state-space equations can be written like the following:
dx
= (d2 A2 + d−2 A−2 + d1−2 A1−2 + d2−1 A2−1 )x
dt
+(d2 b2 + d−2 b−2 + d1−2 b1−2 + d2−1 b2−1 )vin
(A.67)
y = (d2 C2 + d−2 C−2 + d1−2 C1−2 + d2−1 C2−1 )x
+(d2 d2 + d−2 d−2 + d1−2 d1−2 + d2−1 d2−1 )vin
The averaged system matrix A, the averaged input vector b, the averaged output
matrix C and the averaged input-to-output vector d are:
A = d2 A2 + d−2 A−2 + d1−2 A1−2 + d2−1 A2−1

b = d2 b2 + d−2 b−2 + d1−2 b1−2 + d2−1 b2−1
(A.68)
C = d2 C2 + d−2 C−2 + d1−2 C1−2 + d2−1 C2−1
d = d2 d2 + d−2 d−2 + d1−2 d1−2 + d2−1 d2−1
Next step is to introduce small perturbations in all of the time variable quantities:
x = x̄ + x̃
y = ȳ + ỹ
vin = v̄in + ṽin
d2 = d¯2 + d˜2 (A.69)
d−2 = d¯−2 + d˜−2
d1−2 = d¯1−2 + d˜1−2
d2−1 = d¯2−1 + d˜2−1
where the bar ( ¯ ) over the quantities represents their stationary, operating point values
and the tilde (˜) represents their perturbations.
It is worth pointing out that the operating point value of the input voltage v̄in dif-
fers from one to another switching interval, but because of the high switching frequency
it can be approximated with a constant value during a single switching interval Ts
k
(v̄in = Vin sin (ωin kTs ) for the k-th switching interval).
When small perturbations are introduced in all of the quantities and all of the second
order products of small perturbations are neglected, it is arrived at the following DC
operating point mathematical model:
0 = Ax̄ + bv̄in
(A.70)
ȳ = Cx̄ + dv̄in
and the following linearized AC small signal mathematical model:

dx̃
= Ax̃ + bṽin + (d˜2 A2 + d˜−2 A−2 + d˜1−2 A1−2 + d˜2−1 A2−1 )x̄+
dt
+(d˜2 b2 + d˜−2 b−2 + d˜1−2 b1−2 + d˜2−1 b2−1 )v̄in (A.71)
ỹ = Cx̃ + dṽin + (d˜2 C2 + d˜−2 C−2 + d˜1−2 C1−2 + d˜2−1 C2−1 )x̄+
+(d˜2 d2 + d˜−2 d−2 + d˜1−2 d1−2 + d˜2−1 d̃2−1 )v̄in
Although this state-space averaging technique will not be investigated in detail any
further and will not be used for developing the MC-based SICAM transfer functions,
it is important for providing insight in the creation of the audio band output voltage.
Even more, since the averaging is made in a short time interval Ts and the sine wave
quantities with frequency equal to the AC-mains input voltage frequency remain intact,
this averaging principle can be further extended to the sine waves maximum (max), root
mean square (rms) and average (av) values.
B
Analysis of combined mains-connected Class D audio
power amplifier and PFC
B.1 Analysis of combined Class D audio power amplifier and

boost PFC
The analysis of operation of the combined Class D audio power amplifier with boost PFC
front-end in Continuous Conduction Mode (CCM) through state-space averaging will be
presented in this section. The four different connections in the operation of the combined
Class D audio power amplifier and boost PFC are shown in Fig. B.1. Stepping through
the different possible connections is performed according to the sign of the output voltage,
and is shown in Fig. B.1 with the plus and minus sign.
iCin iCin
d0-Dd 1-d0-Dd

vin iCf vin iCf
Cf/2 Cf/2
_
+
iCin iCin
2Dd |-2Dd|

vin iCf vin iCf
Cf/2 Cf/2
Fig. B.1. Possible connections in the combined Class D audio power amplifier and boost PFC (same as Fig. 3.9)
For positive output voltages:

• during interval d0 − ∆d:
258 B Analysis of combined mains-connected Class D audio power amplifier and PFC
diLb
Lb = vin
dt
diLf
2Lf = −vo
dt (B.1)
dvCin
Cin =0
dt
Cf dvCf vo
= iLf −
2 dt R
i.e.:
1
i̇Lb = vin
Lb
1
i̇Lf = − vo
2Lf (B.2)
v̇Cin = 0
2 vo
v̇Cf = (iLf − )
Cf R
• during interval 2∆d:

diLb
Lb = vin − vCin
dt
diLf
2Lf = vCin − vo
dt (B.3)
dvCin
Cin = iLb − iLf
dt
Cf dvCf vo
= iLf −
2 dt R
i.e.:
1
i̇Lb = (vin − vCin )
Lb
1
i̇Lf = (vCin − vo )
2Lf
1 (B.4)
v̇Cin = (iLb − iLf )
Cin
2 vo
v̇Cf = (iLf − )
Cf R
• during interval 1 − d0 − ∆d:

diLb
Lb = vin − vCin
dt
diLf
2Lf = −vo
dt (B.5)
dvCin
Cin = iLb
dt
Cf dvCf vo
= iLf −
2 dt R
i.e.:
B.1 Analysis of combined Class D audio power amplifier and boost PFC 259
1
Lb
1
i̇Lf = − vo
2Lf
1 (B.6)
v̇Cin = iLb
Cin
2 vo
v̇Cf = (iLf − )
Cf R
For negative output voltages, only the time interval in the middle is different from the
positive output voltage:
• during interval | − 2∆d|:
diLb
Lb = vin
dt
diLf
2Lf = −vCin − vo
dt (B.7)
dvCin
Cin = iLf
dt
Cf dvCf vo
= iLf −
2 dt R
i.e.:
1
i̇Lb = vin
Lb
1
i̇Lf = − (vCin + vo )
2Lf
1 (B.8)
v̇Cin = iLf
Cin
2 vo
v̇Cf = (iLf − )
Cf R
In the next step, averaging of the state-space equations is performed to remove the
switching harmonics present in the waveforms and reveal the low frequency content. For
the positive output voltages this corresponds to summing up equations (B.2), (B.4) and
(B.6) weighted by their respective duty cycles:
vin vCin
i̇Lb = − (1 − d0 + ∆d)
Lb Lb
vo 2∆dvCin
i̇Lf = − +
2Lf 2Lf
iLb 2∆diLf (B.9)
v̇Cin = (1 − do + ∆d) −
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R
where all the states are represented by their average values.

For the negative output voltages averaging corresponds to summing up equations (B.2),
(B.8) and (B.6) weighted by their respective duty cycles:
vin vCin
i̇Lb = − (1 − d0 − ∆d)
Lb Lb
vo 2∆dvCin
i̇Lf = − −
2Lf 2Lf
iLb 2∆diLf (B.10)
v̇Cin = (1 − do − ∆d) +
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R
where all the states are again represented by their average values.
Perturbations are subsequently added to each state to perform linearization of the
model around the operating point, so that each of the states become X + x̃, where X
represents the operating point and x̃ is a small perturbation around the operating point.
It is assumed that all cross-products of the perturbation are so small, so they can be easily
neglected without significant adverse impact on the accuracy.
For positive output voltages, the perturbed average model becomes:
Vin VCin ṽin (1 − D0 + ∆D)ṽCin − (d˜0 − ∆d)V

˜ Cin
ĩ˙ Lb = − (1 − D0 + ∆D) + −
Lb Lb Lb Lb
Vo 2∆DVCin ṽo ˜
2∆DṽCin + 2∆dVCin
ĩ˙ Lf = −

+ + − +
2Lf 2Lf 2Lf 2Lf
I Lb 2∆DI Lf
ṽ˙ Cin = (1 − Do + ∆D)

− +
Cin Cin
(1 − D0 + ∆D)ĩLb − (d˜0 − ∆d)I ˜ Lb 2∆DĩLf + 2∆dI ˜ Lf
+ −
Cin Cin
2 Vo 2 ṽ o
ṽ˙ Cf =

(ILf − ) + (ĩLf − )
Cf R Cf R
(B.11)
and for negative output voltages:
Vin VCin ṽin (1 − D0 − ∆D)ṽCin − (d˜0 + ∆d)V

˜ Cin
ĩ˙ Lb = − (1 − D0 − ∆D) + −
Lb Lb Lb Lb
Vo 2∆DVCin ṽo ˜ Cin
2∆DṽCin + 2∆dV
ĩ˙ Lf = −

− + − −
2Lf 2Lf 2Lf 2Lf
ILb 2∆DILf
ṽ˙ Cin = (1 − Do − ∆D)

+ +
Cin Cin
(1 − D0 − ∆D)ĩLb − (d˜0 + ∆d)I ˜ Lb 2∆DĩLf + 2∆dI ˜ Lf
+ +
Cin Cin
2 Vo 2 ṽ o
ṽ˙ Cf =

(ILf − ) + (ĩLf − )
Cf R Cf R
(B.12)
DC-model of the combined Class D audio power amplifier and boost PFC is obtained
by equating the DC quantities on both sides of (B.11) for positive output voltages:
Vin
0 = Vin − (1 − D0 + ∆D)VCin ⇒ VCin =
1 − D0 + ∆D
0 = −Vo + 2∆DVCin ⇒ Vo = 2∆DVCin
2∆DILf (B.13)
0 = (1 − D0 + ∆D)ILb − 2∆DILf ⇒ ILb =
1 − D0 + ∆D
Vo Vo
0 = ILf − ⇒ ILf = = Io
R R
and (B.11) for negative output voltages:
Vin
0 = Vin − (1 − D0 − ∆D)VCin ⇒ VCin =
1 − D0 − ∆D
0 = Vo + 2∆DVCin ⇒ Vo = −2∆DVCin
2∆DILf (B.14)
0 = (1 − D0 − ∆D)ILb + 2∆DILf ⇒ ILb = −
1 − D0 − ∆D
Vo Vo
0 = ILf − ⇒ ILf = = Io
R R
AC-model of the combined Class D audio power amplifier and boost PFC is obtained
by equating the AC quantities on both sides of (B.11) for positive output voltages:
vin (1 − D0 + ∆D)vCin − (d0 − ∆d)VCin

i̇Lb = −
Lb Lb
vo 2∆DvCin + 2∆dVCin
i̇Lf = − +
2Lf 2Lf
(B.15)
(1 − D0 + ∆D)iLb − (d0 − ∆d)ILb 2∆DiLf + 2∆dILf
v̇Cin = −
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R
vin (1 − D0 − ∆D)vCin − (d0 + ∆d)VCin

i̇Lb = −
Lb Lb
i̇Lf = − −
2Lf 2Lf
(B.16)
(1 − D0 − ∆D)iLb − (d0 + ∆d)ILb 2∆DiLf + 2∆dILf
v̇Cin = +
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R
where ∼ is omitted for brevity.

AC small-signal model for positive output voltages (B.15) can be rewritten in the
following state-space form:
1 − D0 + ∆D
 
0 0 − 0

 Lb 
 
∆D 1
  
iLb   iLb
 0 0 − 
d  i Lf
 
= Lf 2Lf   iLf 
·
  vCin  +
 
 1 − D0 + ∆D
dt  vCin   −
2∆D
0 0 
vCf 
 Cin Cin  vCf

 2 2 
0 0 −
Cf RCf
1 VCin VCin
 
 Lb −
Lb Lb 
VCin
   

 0
 v in
0 
+ Lf  ·  d0 
ILb ILb − 2ILf
 
  ∆d
 0 − 
 Cin Cin 
0 0 0
1 0 0 0
   
  iLb  
iin    iLf  vin
vCin  =  0 0 1 0 
 ·  vCin  + 0 · d0
   

vo ∆d
0 0 0 1 vCf
(B.17)
So the system matrix Ab+ , input matrix Bb+ , output matrix Cb+ and input-to-output
matrix Db+ are:
1 − D0 + ∆D
 
0 0 − 0

 Lb 

 ∆D 1 
 0 0 − 
 L f 2L f 

Ab+ =  1 − D0 + ∆D 2∆D 
 − 0 0 

 Cin Cin 

 2 2 
0 0 −
Cf RCf
1 VCin VCin
 
 Lb −
Lb Lb 
VCin (B.18)
 
 
 0 0 
Bb+ =  Lf 
ILb ILb − 2ILf 
 

 0 − 
 Cin Cin 
0 0 0
1 0 0 0
 
 
Cb+ =  0 0 1 0 

0 0 0 1
Db+ = 0
The desired output quantities for the state-space representation are the input current
iin , DC-bus capacitor voltage vCin and output voltage vo , being equal to the boost inductor
current iLf , DC-bus capacitor voltage vCin and filter capacitor voltage vCf as system
states, correspondingly.
AC small-signal model for negative output voltages (B.16) can be rewritten in the
1 − D0 − ∆D
 
0 0 − 0

 Lb 
 
∆D 1
  
iLb   iLb
 0 0 − − 
d  iLf  
  Lf 2Lf   iLf 
= 
  vCin  +
· 
dt  vCin    1 − D0 − ∆D 2∆D
0 0 
vCf 
 Cin Cin  vCf

 2 2 
0 0 −
Cf RCf
1 VCin VCin
 
 Lb −
Lb Lb 
VCin
   

 0
 v in
0 − 
+ Lf  ·  d0 
ILb 2ILf − ILb
 
  ∆d
 0 − 
 Cin Cin 
0 0 0
1 0 0 0
   
  iLb  
iin    iLf  vin
vCin  =  0 0 1 0 
 ·  vCin  + 0 · d0
   

vo ∆d
0 0 0 1 vCf
(B.19)
So the system matrix Ab− , input matrix Bb− , output matrix Cb− and input-to-output
matrix Db− are:
1 − D0 − ∆D
 
0 0 − 0

 Lb 

 ∆D 1 
 0 0 − − 
 Lf 2Lf 
Ab− =  
1 − D 0 − ∆D 2∆D 
 0 0 

 C in Cin


 2 2 
0 0 −
Cf RCf
1 VCin VCin
 
 Lb −
Lb Lb 
VCin (B.20)
 
 
 0 0 − 
Bb− =  Lf 
ILb 2ILf − ILb 


 0 − 
 Cin Cin 
0 0 0
1 0 0 0
 
 
Cb− =  0 0 1 0 

0 0 0 1
Db− = 0
System matrices in (B.18) and (B.20) can be used to develop small-signal transfer
functions for positive and negative output voltages by recognizing that:
   
iin v in
vCin  = Cb+ (sI − Ab+ )−1 Bb+ + Db+ ·  d0  =
vo ∆d
    (B.21)
Giin vin ,b+ (s) Giin d0 ,b+ (s) Giin ∆d,b+ (s) vin
= GvCin vin ,b+ (s) GvCin d0 ,b+ (s) GvCin ∆d,b+ (s) ·  d0 
Gvo vin ,b+ (s) Gvo d0 ,b+ (s) Gvo ∆d,b+ (s) ∆d
and:
   
iin vin
vCin  = Cb− (sI − Ab− )−1 Bb− + Db− ·  d0  =
vo ∆d
    (B.22)
Giin vin ,b− (s) Giin d0 ,b− (s) Giin ∆d,b− (s) vin
= GvCin vin ,b− (s) GvCin d0 ,b− (s) GvCin ∆d,b− (s) ·  d0 
Gvo vin ,b− (s) Gvo d0 ,b− (s) Gvo ∆d,b− (s) ∆d
B.2 Analysis of the synchronous operation of the combined

Class D audio power amplifier and buck-boost PFC
The analysis of the synchronous operation of combined Class D audio power amplifier
and buck-boost PFC front-end in CCM through state-space averaging will be presented
in this section. The four different connections in the operation of the combined Class D
audio power amplifier and buck-boost PFC are shown in Fig. B.2. Stepping through the
and is shown in Fig. B.2 with the plus and minus sign.
iCin iCin
d0-Dd 1-d0-Dd

vin iCf vin iCf
Cf/2 Cf/2
_
+
iCin iCin
2Dd |-2Dd|

vin iCf vin iCf
Cf/2 Cf/2
Fig. B.2. Possible connections in the synchronously-operated combined Class D audio power amplifier and buck-
boost PFC (same as Fig. 3.14)

• during interval d0 − ∆d:
B.2 Analysis of the synchronous operation of the combined Class D audio power amplifier and buck-boost PFC 265
diLb
Lb = vin
dt
diLf
2Lf = −vo
dt (B.23)
dvCin
Cin =0
dt
Cf dvCf vo
= iLf −
2 dt R
i.e.:
1
i̇Lb = vin
Lb
1
i̇Lf = − vo
2Lf (B.24)
v̇Cin = 0
2 vo
v̇Cf = (iLf − )
Cf R
• during interval 2∆d:

diLb
Lb = −vCin
dt
diLf
2Lf = vCin − vo
dt (B.25)
dvCin
Cin = iLb − iLf
dt
Cf dvCf vo
= iLf −
2 dt R
i.e.:
1
i̇Lb = − vCin
Lb
1
2Lf
1 (B.26)
Cin
2 vo
v̇Cf = (iLf − )
Cf R
• during interval 1 − d0 − ∆d:

diLb
Lb = −vCin
dt
diLf
2Lf = −vo
dt (B.27)
dvCin
Cin = iLb
dt
Cf dvCf vo
= iLf −
2 dt R
i.e.:
1
i̇Lb = − vCin
Lb
1
i̇Lf = − vo
2Lf
1 (B.28)
v̇Cin = iLb
Cin
2 vo
v̇Cf = (iLf − )
Cf R
For negative output voltages, only the time interval in the middle is different from the
positive output voltage:
• during interval | − 2∆d|:
diLb
Lb =0
dt
diLf
2Lf = −vCin − vo
dt (B.29)
dvCin
Cin = iLf
dt
Cf dvCf vo
= iLf −
2 dt R
i.e.:
i̇Lb = 0
1
2Lf
1 (B.30)
v̇Cin = iLf
Cin
2 vo
v̇Cf = (iLf − )
Cf R
the positive output voltages this corresponds to summing up equations (B.24), (B.26) and
(B.28) weighted by their respective duty cycles:
vin vCin
i̇Lb = (d0 − ∆d) − (1 − d0 + ∆d)
Lb Lb
vo 2∆dvCin
i̇Lf = − +
2Lf 2Lf
iLb 2∆diLf (B.31)
v̇Cin = (1 − do + ∆d) −
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R

For the negative output voltages averaging corresponds to summing up equations
(B.24), (B.30) and (B.28) weighted by their respective duty cycles:
vin vCin
i̇Lb = (d0 − ∆d) − (1 − d0 − ∆d)
Lb Lb
vo 2∆dvCin
i̇Lf = − −
2Lf 2Lf
iLb 2∆diLf (B.32)
v̇Cin = (1 − do − ∆d) +
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R
(D0 − ∆D)Vin VCin

ĩ˙ Lb = − (1 − D0 + ∆D) +
Lb Lb
(D0 − ∆D)ṽin + (d˜0 − ∆d)V ˜ in (1 − D0 + ∆D)ṽCin − (d˜0 − ∆d)V
˜ Cin
+ −
Lb Lb
ĩ˙ Lf = −

+ + − +
2Lf 2Lf 2Lf 2Lf
I Lb 2∆DI Lf
ṽ˙ Cin = (1 − Do + ∆D)

− +
Cin Cin
+ −
Cin Cin
2 Vo 2 ṽo
ṽ˙ Cf =

(ILf − ) + (ĩLf − )
Cf R Cf R
(B.33)
Vin VCin
ĩ˙ Lb = (D0 − ∆D)

− (1 − D0 − ∆D) +
Lb Lb
(D0 − ∆D)ṽin + (d˜0 − ∆d)V ˜ in (1 − D0 − ∆D)ṽCin − (d˜0 + ∆d)V
˜ Cin
+ −
Lb Lb
ĩ˙ Lf = −

− + − −
2Lf 2Lf 2Lf 2Lf
I Lb 2∆DI Lf
ṽ˙ Cin = (1 − Do − ∆D)

+ +
Cin Cin
(1 − D0 − ∆D)ĩLb − (d˜0 − ∆d)I ˜ Lb 2∆DĩLf + 2∆dI ˜ Lf
+ +
Cin Cin
2 Vo 2 ṽo
ṽ˙ Cf =

(ILf − ) + (ĩLf − )
Cf R Cf R
(B.34)
DC-model of the combined Class D audio power amplifier and buck-boost PFC is ob-
tained by equating the DC quantities on both sides of (B.33) for positive output voltages:
(D0 − ∆D)Vin
0 = (D0 − ∆D)Vin − (1 − D0 + ∆D)VCin ⇒ VCin =
1 − D0 + ∆D
2∆DILf (B.35)
0 = (1 − D0 + ∆D)ILb − 2∆DILf ⇒ ILb =
1 − D0 + ∆D
Vo Vo
0 = ILf − ⇒ ILf = = Io
R R
(D0 − ∆D)Vin
0 = (D0 − ∆D)Vin − (1 − D0 − ∆D)VCin ⇒ VCin =
1 − D0 − ∆D
0 = Vo + 2∆DVCin ⇒ Vo = −2∆DVin
2∆DILf (B.36)
0 = (1 − D0 − ∆D)ILb + 2∆DILf ⇒ ILb = −
1 − D0 − ∆D
Vo Vo
0 = ILf − ⇒ ILf = = Io
R R
AC-model of the combined Class D audio power amplifier and buck-boost PFC is ob-
tained by equating the AC quantities on both sides of (B.33) for positive output voltages:
(D0 − ∆D)vin + (d0 − ∆d)Vin (1 − D0 + ∆D)vCin − (d0 − ∆d)VCin

i̇Lb = −
Lb Lb
i̇Lf = − +
2Lf 2Lf
(B.37)
(1 − D0 + ∆D)iLb − (d0 − ∆d)ILb 2∆DiLf + 2∆dILf
v̇Cin = −
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R
(D0 − ∆D)vin + (d0 − ∆d)Vin (1 − D0 − ∆D)vCin − (d0 + ∆d)VCin

i̇Lb = −
Lb Lb
i̇Lf = − −
2Lf 2Lf
(B.38)
(1 − D0 − ∆D)iLb − (d0 − ∆d)ILb 2∆DiLf + 2∆dILf
v̇Cin = +
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R
iin , DC-bus capacitor voltage vCin and output voltage vo , where vCin and vo are readily
available and are equal to the state quantities vCin and vCf , while the DC and AC value
of the input current are:
Iin = (D0 − ∆D)ILb (B.39)
and
iin = (D0 − ∆D)iLb + (d0 − ∆d)ILb (B.40)

AC small-signal model for positive output voltages (B.37) can be rewritten in the
1 − D0 + ∆D
 
0 0 − 0

 Lb 
 
∆D 1
  
iLb   iLb
 0 0 − 
d  iLf  
  Lf 2Lf   iLf 
= 
  vCin  +
· 
dt  vCin    1 − D0 + ∆D −
2∆D
0 0 
vCf 
 Cin Cin  vCf

 2 2 
0 0 −
Cf RCf
D0 − ∆D Vin + VCin Vin + VCin
 
−
 Lb Lb Lb 
VCin
   
  v in
 0 0 
+ Lf  ·  d0 
ILb ILb − 2ILf
 
  ∆d
 0 − 
 Cin Cin 
0 0 0
(D0 − ∆D) 0 0 0
   
  iLb
iin    iLf 
vCin  =  0 0 1 0 
 ·  vCin  +
 

vo
0 0 0 1 vCf
0 ILb − ILb
 
 
  v in
 0 0 0
+  ·  d0 

∆d
0 0 0
(B.41)
So the system matrix Abb+ , input matrix Bbb+ , output matrix Cbb+ and input-to-
output matrix Dbb+ are:
1 − D0 + ∆D
 
0 0 − 0

 Lb 

 ∆D 1 
 0 0 − 
 Lf 2Lf 
Abb+ =  
1 − D 0 + ∆D 2∆D 
 − 0 0 

 Cin Cin 

 2 2 
0 0 −
Cf RCf
 
−
 Lb Lb Lb 
VCin
 
 
 0 0 
Bbb+ =  L f

(B.42)
 

 0 − 
 Cin Cin 
0 0 0
(D0 − ∆D) 0 0 0
 
 
Cbb+ =  0 0 1 0 

0 0 0 1
0 ILb − ILb
 
 
 0
Dbb+ =  0 0 

0 0 0
AC small-signal model for negative output voltages (B.38) can be rewritten in the
1 − D0 − ∆D
 
0 0 − 0

 Lb 
 
∆D 1
  
iLb   iLb
 0 0 − − 
d  iLf  
  Lf 2Lf   iLf 
= 
  vCin  +
· 
dt  vCin    1 − D0 − ∆D 2∆D
0 0 
vCf 
 Cin Cin  vCf

 2 2 
0 0 −
Cf RCf
 
−
 Lb Lb Lb 
VCin
   
  v in
 0 0 − 
+ Lf  ·  d0 
ILb ILb + 2ILf
 
  ∆d
 0 − 
 Cin Cin 
0 0 0
(D0 − ∆D) 0 0 0
   
  iLb
vCin  =  0 0 1 0 
 ·  vCin  +
 

vo
0 0 0 1 vCf
0 ILb − ILb
 
 
  v in
 0 0 0
+  ·  d0 

∆d
0 0 0
(B.43)
So the system matrix Abb− , input matrix Bbb− , output matrix Cbb− and input-to-
output matrix Dbb− are:
1 − D0 − ∆D
 
0 0 − 0

 Lb 

 ∆D 1 
 0 0 − − 
 L f 2L f

Abb− =  1 − D0 − ∆D 2∆D


 0 0 

 Cin C in


 2 2 
0 0 −
Cf RCf
 
−
 Lb Lb Lb 
VCin
 
 
 0 0 − 
Bbb− =  Lf 
(B.44)
ILb ILb + 2ILf 


 0 − 
 Cin Cin 
0 0 0
(D0 − ∆D) 0 0 0
 
 
Cbb− =  0 0 1 0  
0 0 0 1
0 ILb − ILb
 
 
 0
Dbb− =  0 0 

0 0 0
The differences in the models for positive and negative output voltages stem from
the fact that the buck-boost PFC is asymmetrical in regard with the full-bridge Class D
audio power amplifier and this translates to slight changes in the models. Like in the
case of a combined Class D audio power amplifier and boost PFC, this asymmetry can
be alleviated by having two buck-boost inductors, connected to the middle points of the
switching totem poles.
System matrices in (B.42) and (B.44) can be used to develop small-signal transfer
   
iin vin
vCin  = Cbb+ (sI − Abb+ )−1 Bbb+ + Dbb+ ·  d0  =
vo ∆d
    (B.45)
Giin vin ,bb+ (s) Giin d0 ,bb+ (s) Giin ∆d,bb+ (s) vin
= GvCin vin ,bb+ (s) GvCin d0 ,bb+ (s) GvCin ∆d,bb+ (s) ·  d0 
Gvo vin ,bb+ (s) Gvo d0 ,bb+ (s) Gvo ∆d,bb+ (s) ∆d
and:
   
iin v in
vCin  = Cbb− (sI − Abb− )−1 Bbb− + Dbb− ·  d0  =
vo ∆d
    (B.46)
Giin vin ,bb− (s) Giin d0 ,bb− (s) Giin ∆d,bb− (s) vin
= GvCin vin ,bb− (s) GvCin d0 ,bb− (s) GvCin ∆d,bb− (s) ·  d0 
Gvo vin ,bb− (s) Gvo d0 ,bb− (s) Gvo ∆d,bb− (s) ∆d
B.3 Analysis of the asynchronous operation of the combined Class D audio power amplifier and buck-boost PFC 273
B.3 Analysis of the asynchronous operation of the combined

Class D audio power amplifier and buck-boost PFC
The analysis of the asynchronous operation of combined Class D audio power amplifier
and buck-boost PFC front-end in CCM through state-space averaging will be performed
using the connection diagrams in Fig. B.3. In this mode of operation there is one additional
degree of freedom in the freely selectable duty cycle of the active rectifier da . Depending
on the duration of this duty cycle da compared to the corresponding duty cycles of the
Class D audio power amplifier, there are six possible switching sequences, three for each
polarity of the output voltage. These are explained in Table B.1, where the duration of
each switching combination from Fig. B.3 is given in parenthesis.
iCin iCin
1 5

vin iCf vin iCf
Cf/2 Cf/2
iCin iCin
2 6

vin iCf vin iCf
Cf/2 Cf/2
iCin iCin
3 7

vin iCf vin iCf
Cf/2 Cf/2
iCin iCin
4 8

vin iCf vin iCf
Cf/2 Cf/2
Fig. B.3. Possible connections in the asynchronously-operated combined Class D audio power amplifier and
buck-boost PFC (same as Fig. 3.15)
The state-space equations for each of the switching combinations in Fig. 3.15 are:
• combination 1:
Positive output voltage

I = da < (d0 − ∆d) 1 (da ) 5 (d0 − ∆d − da ) 6 (2∆d) 8 (1 − d0 − ∆d)
II = (d0 − ∆d) < da < (d0 + ∆d) 1 (d0 − ∆d) 2 (da − d0 + ∆d) 6 (d0 + ∆d − da ) 8 (1 − d0 − ∆d)
III = (d0 + ∆d) < da < 1 1 (d0 − ∆d) 2 (2∆d) 4 (da − d0 − ∆d) 8 (1 − da )
Negative output voltage
IV = da < (d0 − ∆d) 1 (da ) 5 (d0 − ∆d − da ) 7 (2∆d) 8 (1 − d0 − ∆d)
V = (d0 − ∆d) < da < (d0 + ∆d) 1 (d0 − ∆d) 3 (da − d0 + ∆d) 7 (d0 + ∆d − da ) 8 (1 − d0 − ∆d)
V I = (d0 + ∆d) < da < 1 1 (d0 − ∆d) 3 (2∆d) 4 (da − d0 − ∆d) 8 (1 − da )
Table B.1. Switching sequences of the asynchronously-operated combined Class D audio power amplifier and
buck-boost PFC
1
i̇Lb = vin
Lb
1
i̇Lf = − vo
2Lf (B.47)
v̇Cin = 0
2 vo
v̇Cf = (iLf − )
Cf R
• combination 2:
1
Lb
1
2Lf
1 (B.48)
Cin
2 vo
v̇Cf = (iLf − )
Cf R
• combination 3:
1
Lb
1
2Lf
1 (B.49)
v̇Cin = iLf
Cin
2 vo
v̇Cf = (iLf − )
Cf R
• combination 4:
1
Lb
1
i̇Lf = − vo
2Lf
1 (B.50)
v̇Cin = iLb
Cin
2 vo
v̇Cf = (iLf − )
Cf R
• combination 5:
i̇Lb = 0
1
i̇Lf = − vo
2Lf
(B.51)
v̇Cin = 0
2 vo
v̇Cf = (iLf − )
Cf R
• combination 6:
1
i̇Lb = − vCin
Lb
1
2Lf
1 (B.52)
Cin
2 vo
v̇Cf = (iLf − )
Cf R
• combination 7:
i̇Lb = 0
1
2Lf
1 (B.53)
v̇Cin = iLf
Cin
2 vo
v̇Cf = (iLf − )
Cf R
• combination 8:
1
i̇Lb = − vCin
Lb
1
i̇Lf = − vo
2Lf
1 (B.54)
v̇Cin = iLb
Cin
2 vo
v̇Cf = (iLf − )
Cf R
switching harmonics present in the waveforms and reveal the low frequency content. This
is done by taking into account the duration of each of the switching combinations 1-8 in
the switching sequences I − V I given in Table B.1:
• sequence I:
vin vCin
i̇Lb = da − (1 − d0 + ∆d)
Lb Lb
vo 2∆dvCin
i̇Lf = − +
2Lf 2Lf
iLb 2∆diLf (B.55)
v̇Cin = (1 − do + ∆d) −
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R
• sequence II:
vin vCin
i̇Lb = da − (1 − d0 + ∆d)
Lb Lb
vo 2∆dvCin
i̇Lf = − +
2Lf 2Lf
iLb 2∆diLf (B.56)
v̇Cin = (1 − do + ∆d) −
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R
• sequence III:
vin vCin
i̇Lb = da − (1 − d0 + ∆d)
Lb Lb
vo 2∆dvCin
i̇Lf = − +
2Lf 2Lf
iLb 2∆diLf (B.57)
v̇Cin = (1 − do + ∆d) −
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R
• sequence IV :
vin vCin
i̇Lb = da − (1 − d0 − ∆d)
Lb Lb
vo 2∆dvCin
i̇Lf = − −
2Lf 2Lf
iLb 2∆diLf (B.58)
v̇Cin = (1 − do − ∆d) +
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R
• sequence V :
vin vCin
i̇Lb = da − (1 + da − 2d0 )
Lb Lb
vo 2∆dvCin
i̇Lf = − −
2Lf 2Lf
iLb 2∆diLf (B.59)
v̇Cin = (1 − do − ∆d) +
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R
• sequence V I:
vin vCin
i̇Lb = da − (1 − d0 + ∆d)
Lb Lb
vo 2∆dvCin
i̇Lf = − −
2Lf 2Lf
iLb 2∆diLf (B.60)
v̇Cin = (1 − do − ∆d) +
Cin Cin
2 vo
v̇Cf = (iLf − )
Cf R

The perturbed average models for the six switching combinations are given with the
following differential equations:
• sequence I:
Da Vin VCin
ĩ˙ Lb = − (1 − D0 + ∆D) +
Lb Lb
Da ṽin + dã Vin (1 − D0 + ∆D)ṽCin − (d˜0 − ∆d)V ˜ Cin
+ −
Lb Lb
ĩ˙ Lf = −

+ + − +
2Lf 2Lf 2Lf 2Lf (B.61)
I Lb 2∆DI Lf
ṽ˙ Cin = (1 − D0 + ∆D)

− +
Cin Cin
+ −
Cin Cin
2 V o 2 ṽ o
ṽ˙ Cf =

(ILf − ) + (ĩLf − )
Cf R Cf R
• sequence II:
Da Vin VCin
ĩ˙ Lb = − (1 − D0 + ∆D) +
Lb Lb
+ −
Lb Lb
ĩ˙ Lf = −

+ + − +
ILb 2∆DILf
ṽ˙ Cin = (1 − D0 + ∆D)

− +
Cin Cin
+ −
Cin Cin
2 V o 2 ṽ o
ṽ˙ Cf =

(ILf − ) + (ĩLf − )
Cf R Cf R
• sequence III:
Da Vin VCin
ĩ˙ Lb = − (1 − D0 + ∆D) +
Lb Lb
+ −
Lb Lb
ĩ˙ Lf = −

+ + − +
ILb 2∆DILf
ṽ˙ Cin = (1 − D0 + ∆D)

− +
Cin Cin
+ −
Cin Cin
2 V o 2 ṽ o
ṽ˙ Cf =

(ILf − ) + (ĩLf − )
Cf R Cf R
• sequence IV :
Da Vin VCin
ĩ˙ Lb = − (1 − D0 − ∆D) +
Lb Lb
Da ṽin + dã Vin (1 − D0 − ∆D)ṽCin + (d˜0 + ∆d)V ˜ Cin
+ −
Lb Lb
ĩ˙ Lf = −

+ − +
I Lb 2∆DI Lf
ṽ˙ Cin = (1 − D0 − ∆D)

+ +
Cin Cin
+ +
Cin Cin
2 V o 2 ṽ o
ṽ˙ Cf =

(ILf − ) + (ĩLf − )
Cf R Cf R
• sequence V :
Da Vin VCin
ĩ˙ Lb = − (1 − Da − 2D0 ) +
Lb Lb
Da ṽin + dã Vin (1 − Da − 2D0 )ṽCin + (dã − 2d˜0 )VCin
+ −
Lb Lb
V 2∆DV ṽ 2∆Dṽ ˜
Cin + 2∆dVCin
ĩ˙ Lf = −
o Cin o
+ − +
I Lb 2∆DI Lf
ṽ˙ Cin = (1 − D0 − ∆D)

+ +
Cin Cin
+ +
Cin Cin
2 V o 2 ṽ o
ṽ˙ Cf =

(ILf − ) + (ĩLf − )
Cf R Cf R
• sequence V I:
Da Vin VCin
ĩ˙ Lb = − (1 − Da + D0 ) +
Lb Lb
Da ṽin + dã Vin (1 − Da + D0 )ṽCin + (dã − 2d˜0 )VCin
+ −
Lb Lb
ĩ˙ Lf = − + − +
ILb 2∆DILf
ṽ˙ Cin = (1 − D0 − ∆D)

+ +
Cin Cin
+ +
Cin Cin
2 V o 2 ṽ o
ṽ˙ Cf =

(ILf − ) + (ĩLf − )
Cf R Cf R
DC-model of the combined Class D audio power amplifier and buck-boost PFC in
asynchronous operation is obtained by equating the DC quantities on both sides of the
perturbed equations (B.61)-(B.66):
• sequence I:
Da Vin
0 = Da Vin − (1 − D0 + ∆D)VCin ⇒ VCin =
1 − D0 + ∆D
2∆DILf (B.67)
0 = (1 − D0 + ∆D)ILb − 2∆DILf ⇒ ILb =
1 − D0 + ∆D
Vo Vo
0 = ILf − R
⇒ ILf = = Io
R
• sequence II:
Da Vin
1 − D0 + ∆D
2∆DILf (B.68)
0 = (1 − D0 + ∆D)ILb − 2∆DILf ⇒ ILb =
1 − D0 + ∆D
Vo Vo
0 = ILf − R
⇒ ILf = = Io
R
• sequence III:
Da Vin
1 − D0 + ∆D
2∆DILf (B.69)
0 = (1 − D0 + ∆D)ILb − 2∆DILf ⇒ ILb =
1 − D0 + ∆D
Vo Vo
0 = ILf − R
⇒ ILf = = Io
R
• sequence IV :
Da Vin
0 = Da Vin − (1 − D0 − ∆D)VCin ⇒ VCin =
1 − D0 − ∆D
2∆DILf (B.70)
0 = (1 − D0 − ∆D)ILb + 2∆DILf ⇒ ILb = −
1 − D0 − ∆D
Vo Vo
0 = ILf − R
⇒ ILf = = Io
R
• sequence V :
Da Vin
0 = Da Vin − (1 − Da − 2D0 )VCin ⇒ VCin =
1 − Da − 2D0
2∆DILf (B.71)
0 = (1 − D0 − ∆D)ILb + 2∆DILf ⇒ ILb = −
1 − D0 − ∆D
Vo Vo
0 = ILf − R
⇒ ILf = = Io
R
• sequence V I:
Da Vin
1 − D0 + ∆D
2∆DILf (B.72)
0 = (1 − D0 − ∆D)ILb + 2∆DILf ⇒ ILb = −
1 − D0 − ∆D
Vo Vo
0 = ILf − R
⇒ = Io
ILf =
R
Small-signal AC-model of the combined Class D audio power amplifier and buck-boost
PFC in asynchronous mode of operation is obtained by equating the AC quantities on
both sides of the perturbed equations (B.61)-(B.66):
• sequence I:
Da ṽin + dã Vin (1 − D0 + ∆D)ṽCin − (d˜0 − ∆d)V
˜ Cin
ĩ˙ Lb = −
Lb Lb
ṽo ˜
ĩ˙ Lf = − +
2Lf 2Lf (B.73)
(1 − D0 + ∆D)ĩLb − (d˜0 − ∆d)I
˜ Lb 2∆DĩLf + 2∆dI ˜ Lf
ṽ˙ Cin = −
Cin Cin
2 ṽ o
ṽ˙ Cf = (ĩLf − )
Cf R
• sequence II:
˜ Cin
ĩ˙ Lb = −
Lb Lb
ṽo ˜
ĩ˙ Lf = − +
2Lf 2Lf (B.74)
(1 − D0 + ∆D)ĩLb − (d˜0 − ∆d)I
ṽ˙ Cin = −
Cin Cin
2 ṽ o
ṽ˙ Cf = (ĩLf − )
Cf R
• sequence III:

˜ Cin
ĩ˙ Lb = −
Lb Lb
ṽo ˜
ĩ˙ Lf = − +
2Lf 2Lf (B.75)
(1 − D0 + ∆D)ĩLb − (d˜0 − ∆d)I
ṽ˙ Cin = −
Cin Cin
2 ṽ o
ṽ˙ Cf = (ĩLf − )
Cf R
• sequence IV :
Da ṽin + dã Vin (1 − D0 − ∆D)ṽCin + (d˜0 + ∆d)V

˜ Cin
ĩ˙ Lb = −
Lb Lb
ṽo ˜
ĩ˙ Lf = +
2Lf 2Lf (B.76)
(1 − D0 − ∆D)ĩLb − (d˜0 + ∆d)I
ṽ˙ Cin = +
Cin Cin
2 ṽ o
ṽ˙ Cf = (ĩLf − )
Cf R
• sequence V :
Da ṽin + dã Vin (1 − Da − 2D0 )ṽCin + (dã − 2d˜0 )VCin

ĩ˙ Lb = −
Lb Lb
ṽo ˜
ĩ˙ Lf = +
2Lf 2Lf (B.77)
(1 − D0 − ∆D)ĩLb − (d˜0 + ∆d)I
ṽ˙ Cin = +
Cin Cin
2 ṽ o
ṽ˙ Cf = (ĩLf − )
Cf R
• sequence V I:
Da ṽin + dã Vin (1 − Da + D0 )ṽCin + (dã − 2d˜0 )VCin

ĩ˙ Lb = −
Lb Lb
ṽo ˜
ĩ˙ Lf = +
2Lf 2Lf (B.78)
(1 − D0 − ∆D)ĩLb − (d˜0 + ∆d)I
ṽ˙ Cin = +
Cin Cin
2 ṽ o
ṽ˙ Cf = (ĩLf − )
Cf R
iin , DC-bus capacitor voltage vCin and output voltage vo , where vCin and vo are readily
available and are equal to the state quantities vCin and vCf , while the DC and AC value
of the input current are:
Iin = Da ILb (B.79)

and
iin = Da iLb + da ILb (B.80)
AC small-signal models (B.73)-(B.78) can be rewritten in the following state-space

forms:
• sequence I:
1 − D0 + ∆D
 
0 0 − 0

 Lb 
 
∆D 1
  
iLb   i Lb
 0 0 − 
d  iLf  
  Lf 2Lf   iLf 
= 
  vCin  +
· 
dt  vCin    1 − D0 + ∆D −
2∆D
0 0 
vCf 
 Cin Cin  vCf

 2 2 
0 0 −
Cf RCf
Da Vin VCin VCin
 
 Lb −
Lb Lb Lb   

 VCin

 vin
 0 0 0   da 
+ Lf ·
  d0 

ILb ILb − 2ILf

 
 0 0 −  ∆d
 Cin Cin 
0 0 0 0
Da 0 0 0
   
  iLb
vCin  =  0 0 1 0 
 ·  vCin  +
 

vo
0 0 0 1 vCf
0 ILb 0 0
   
vin
   da 
 0
+ 0 0 0 
 ·  d0 
 
0 0 0 0 ∆d
(B.81)
So the system matrix AbbI , input matrix BbbI , output matrix CbbI and input-to-
output matrix DbbI are:
1 − D0 + ∆D
 
0 0 − 0

 Lb 

 ∆D 1 
 0 0 − 
 Lf 2Lf 
AbbI = 
 1 − D0 + ∆D

2∆D 
 − 0 0 

 Cin Cin 

 2 2 
0 0 −
Cf RCf
Da Vin VCin VCin
 
 Lb −
Lb Lb Lb 
VCin
 
 
 0 0 0 
BbbI =  L f

(B.82)
 

 0 0 − 
 Cin Cin 
0 0 0 0
Da 0 0 0
 
 
CbbI = 
 0 0 1 0 

0 0 0 1
0 ILb 0 0
 
 
 0
DbbI =  0 0 0 

0 0 0 0
• sequence II:
1 − D0 + ∆D
 
0 0 − 0

 Lb 
 
∆D 1
  
iLb   i Lb
 0 0 − 
d  iLf  
  Lf 2Lf   iLf 
= 
  vCin  +
· 
dt  vCin    1 − D0 + ∆D −
2∆D
0 0 
vCf 
 Cin Cin  vCf

 2 2 
0 0 −
Cf RCf
Da Vin VCin VCin
 
 Lb −

 VCin

 vin
 0 0 0   da 
+ Lf ·
  d0 

ILb ILb − 2ILf

 
 0 0 −  ∆d
 Cin Cin 
0 0 0 0
Da 0 0 0
   
  iLb
vCin  =  0 0 1 0 
 ·  vCin  +
 

vo
0 0 0 1 vCf
0 ILb 0 0
   
vin
   da 
 0
+ 0 0 0 
 ·  d0 
 
0 0 0 0 ∆d
(B.83)
So the system matrix AbbII , input matrix BbbII , output matrix CbbII and input-to-
output matrix DbbII are:
1 − D0 + ∆D
 
0 0 − 0

 Lb 

 ∆D 1 
 0 0 − 
 Lf 2Lf 
AbbII =  
1 − D 0 + ∆D 2∆D 
 − 0 0 

 Cin Cin 

 2 2 
0 0 −
Cf RCf
Da Vin VCin VCin
 
 Lb −
Lb Lb Lb 
VCin
 
 
 0 0 0 
BbbII =  L f

(B.84)
 

 0 0 − 
 Cin Cin 
0 0 0 0
Da 0 0 0
 
 
CbbII =  0 0 1 0 

0 0 0 1
0 ILb 0 0
 
 
 0
DbbII =  0 0 0 

0 0 0 0
• sequence III:
1 − D0 + ∆D
 
0 0 − 0

 Lb 
 
∆D 1
  
iLb   i Lb
 0 0 − 
d  iLf  
  Lf 2Lf   iLf 
= 
  vCin  +
· 
dt  vCin    1 − D0 + ∆D −
2∆D
0 0 
vCf 
 Cin Cin  vCf

 2 2 
0 0 −
Cf RCf
Da Vin VCin VCin
 
 Lb −

 VCin

 vin
 0 0 0   da 
+ Lf ·
  d0 

ILb ILb − 2ILf

 
 0 0 −  ∆d
 Cin Cin 
0 0 0 0
Da 0 0 0
   
  iLb
vCin  =  0 0 1 0 
 ·  vCin  +
 

vo
0 0 0 1 vCf
0 ILb 0 0
   
vin
   da 
 0
+ 0 0 0 
 ·  d0 
 
0 0 0 0 ∆d
(B.85)
So the system matrix AbbIII , input matrix BbbIII , output matrix CbbIII and input-to-
output matrix DbbIII are:
1 − D0 + ∆D
 
0 0 − 0

 Lb 

 ∆D 1 
 0 0 − 
 Lf 2Lf 
AbbIII = 
 
1 − D 0 + ∆D 2∆D 
 − 0 0 

 Cin Cin 

 2 2 
0 0 −
Cf RCf
Da Vin VCin VCin
 
 Lb −
Lb Lb Lb 
VCin
 
 
 0 0 0 
BbbIII =  L f

(B.86)
 

 0 0 − 
 Cin Cin 
0 0 0 0
Da 0 0 0
 
 
CbbIII = 
 0 0 1 0 

0 0 0 1
0 ILb 0 0
 
 
 0
DbbIII =  0 0 0 

0 0 0 0
• sequence IV :
1 − D0 − ∆D
 
0 0 − 0

 Lb 
 
∆D 1
  
iLb   i Lb
 0 0 − − 
d  iLf  
  Lf 2Lf   iLf 
= 
  vCin  +
· 
dt  vCin    1 − D0 − ∆D 2∆D
0 0 
vCf 
 Cin Cin  vCf

 2 2 
0 0 −
Cf RCf
Da Vin VCin VCin
 
 Lb Lb Lb Lb   

 VCin

 vin
 0 0 0 −   da 
+ Lf ·
  d0 

ILb ILb − 2ILf

 
 0 0 − −  ∆d
 Cin Cin 
0 0 0 0
Da 0 0 0
   
  iLb
vCin  =  0 0 1 0 
 ·  vCin  +
 

vo
0 0 0 1 vCf
0 ILb 0 0
   
vin
   da 
 0
+ 0 0 0 
 ·  d0 
 
0 0 0 0 ∆d
(B.87)
So the system matrix AbbIV , input matrix BbbIV , output matrix CbbIV and input-to-
output matrix DbbIV are:
1 − D0 − ∆D
 
0 0 − 0

 Lb 

 ∆D 1 
 0 0 − − 
 Lf 2Lf 
AbbIV =  1 − D0 − ∆D 2∆D


 0 0 

 Cin Cin 

 2 2 
0 0 −
Cf RCf
Da Vin VCin VCin
 
 Lb Lb Lb Lb 
VCin
 
 
 0 0 0 − 
BbbIV =  L f

(B.88)
 

 0 0 − − 
 Cin Cin 
0 0 0 0
Da 0 0 0
 
 
CbbIV =  0 0 1 0 

0 0 0 1
0 ILb 0 0
 
 
 0
DbbIV =  0 0 0 

0 0 0 0
• sequence V :
1 − Da − 2D0
 
0 0 − 0

 Lb 
 
∆D 1
  
iLb   i Lb
 0 0 − − 
d  iLf  
  Lf 2Lf   iLf 
= 
  vCin  +
· 
dt  vCin    1 − D0 − ∆D 2∆D
0 0 
vCf 
 Cin Cin  vCf

 2 2 
0 0 −
Cf RCf
Da Vin − VCin 2VCin
 
 Lb 0
Lb Lb   

 VCin

 vin
 0 0 0 −   da 
+ Lf ·
  d0 

ILb ILb − 2ILf

 
 0 0 − −  ∆d
 Cin Cin 
0 0 0 0
Da 0 0 0
   
  iLb
vCin  =  0 0 1 0 
 ·  vCin  +
 

vo
0 0 0 1 vCf
0 ILb 0 0
   
vin
   da 
 0
+ 0 0 0 
 ·  d0 
 
0 0 0 0 ∆d
(B.89)
So the system matrix AbbV , input matrix BbbV , output matrix CbbV and input-to-
output matrix DbbV are:
1 − Da − 2D0
 
0 0 − 0

 Lb 

 ∆D 1 
 0 0 − − 
 Lf 2Lf 
AbbV =   1 − D0 − ∆D 2∆D


 0 0 

 Cin Cin 

 2 2 
0 0 −
Cf RCf
Da Vin − VCin 2VCin
 
 Lb 0
Lb Lb 
VCin
 
 
 0 0 0 − 
BbbV =  Lf 
(B.90)
ILb ILb − 2ILf
 
 
 0 0 − − 
 Cin Cin 
0 0 0 0
Da 0 0 0
 
 
CbbV =   0 0 1 0 

0 0 0 1
0 ILb 0 0
 
 
 0
DbbV =  0 0 0 

0 0 0 0
• sequence V I:
1 − D0 + ∆D
 
0 0 − 0

 Lb 
 
∆D 1
  
iLb   i Lb
 0 0 − − 
d  iLf  
  Lf 2Lf   iLf 
= 
  vCin  +
· 
dt  vCin    1 − D0 − ∆D 2∆D
0 0 
vCf 
 Cin Cin  vCf

 2 2 
0 0 −
Cf RCf
Da Vin VCin VCin
 
 Lb −

 VCin

 v in
 0 0 0 −   da 
+ Lf ·
  d0 

ILb ILb − 2ILf

 
 0 0 − −  ∆d
 Cin Cin 
0 0 0 0
Da 0 0 0
   
  iLb
vCin  =  0 0 1 0 
 ·  vCin  +
 

vo
0 0 0 1 vCf
0 ILb 0 0
   
vin
   da 
 0
+ 0 0 0 
 ·  d0 
 
0 0 0 0 ∆d
(B.91)
So the system matrix AbbVI , input matrix BbbVI , output matrix CbbVI and input-to-
output matrix DbbVI are:
1 − D0 + ∆D
 
0 0 − 0

 Lb 

 ∆D 1 
 0 0 − − 
 Lf 2Lf 
AbbVI =  1 − D0 − ∆D 2∆D


 0 0 

 Cin Cin 

 2 2 
0 0 −
Cf RCf
Da Vin VCin VCin
 
 Lb −
Lb Lb Lb 
VCin
 
 
 0 0 0 − 
BbbVI =  L f

(B.92)
 

 0 0 − − 
 Cin Cin 
0 0 0 0
Da 0 0 0
 
 
CbbVI =  0 0 1 0 

0 0 0 1
0 ILb 0 0
 
 
 0
DbbVI =  0 0 0 

0 0 0 0
System matrices in (B.82)-(B.92) can be used to develop small-signal transfer functions

for each of the switching sequences:
 
  vin
iin
vCin  = Cbb+ (sI − Abb+ )−1 Bbb+ + Dbb+ ·  da  =
 
 d0 
vo
∆d  
  vin
Giin vin ,bbK (s) Giin da ,bbK (s) Giin d0 ,bbK (s) Giin ∆d,bbK (s)  da 
= GvCin vin ,bbK (s) GvCin da ,bbK (s) GvCin d0 ,bbK (s) GvCin ∆d,bbK (s) · 

 d0 

Gvo vin ,bbK (s) Gvo da ,bbK (s) Gvo d0 ,bbK (s) Gvo ∆d,bbK (s)
∆d
(B.93)
where K represents one of the switching sequences I − V I.

It is interesting to note that switching sequences I, II and III corresponding to positive
output voltages have the same DC and AC models.
C
Analysis of double-boost SICAM for portable
applications
The analysis of the double-boost SICAM operation will be performed on the set of four
different switch connections shown in Fig. C.1. Stepping through the different possible
connections is performed according to the sign of the output voltage, and is shown in
Fig. C.1 with the plus and minus sign.
_
+
d d
+ vo + vo
+ +
vb vb
Cf1 Cf2 Cf1 Cf2
1-d 1-d
+ vo + vo
+ +
vb vb
Cf1 Cf2 Cf1 Cf2
Fig. C.1. Possible connections in the double-boost SICAM (same as Fig. 4.2)

• during interval d:
diLb1
Lb1 = vb
dt
diLb2
Lb2 = vb − vCf 2
dt (C.1)
dvCf 1 vCf 1 − vCf 2
Cf 1 = −io = −
dt R
Cf 2 = io + iLb2 = + iLb2
dt R
i.e.:
296 C Analysis of double-boost SICAM for portable applications
diLb1 1
= vb
dt LLb1
diLb2 1
= (vb − vCf 2 )
dt LLb2
dvCf 1 vCf 1 − vCf 2 (C.2)
=−
dt RCf 1
dvCf 2 vCf 1 − vCf 2 1
= + iLb2
dt RCf 2 Cf 2
• during interval 1 − d:
diLb1
Lb1 = vb − vCf 1
dt
diLb2
Lb2 = vb − vCf 2
dt (C.3)
Cf 1 = −io + iLb1 = − + iLb1
dt R
dt R
i.e.:
diLb1 1
= (vb − vCf 1 )
dt LLb1
diLb2 1
= (vb − vCf 2 )
dt LLb2
dvCf 1 vCf 1 − vCf 2 1 (C.4)
=− + iLb1
dt RCf 1 Cf 1
= + iLb2
dt RCf 2 Cf 2
For negative output voltages:
• during interval d:
diLb1
Lb1 = vb − vCf 1
dt
diLb2
Lb2 = vb
dt (C.5)
Cf 1 = iLb1 − io = iLb1 −
dt R
Cf 2 = io =
dt R
i.e.:
diLb1 1
= (vb − vCf 1 )
dt LLb1
diLb2 1
= vb
dt LLb2
dvCf 1 1 vCf 1 − vCf 2 (C.6)
= iLb1 −
dt Cf 1 RCf 1
=
dt RCf 2
C Analysis of double-boost SICAM for portable applications 297
• during interval 1 − d:
diLb1
Lb1 = vb − vCf 1
dt
diLb2
Lb2 = vb − vCf 2
dt (C.7)
Cf 1 = −io + iLb1 = − + iLb1
dt R
dt R
i.e.:
diLb1 1
= (vb − vCf 1 )
dt LLb1
diLb2 1
= (vb − vCf 2 )
dt LLb2
dvCf 1 vCf 1 − vCf 2 1 (C.8)
=− + iLb1
dt RCf 1 Cf 1
= + iLb2
dt RCf 2 Cf 2
the positive output voltages this corresponds to summing up equations (C.2) and (C.4)
weighted by their respective duty cycles:
vb vCf 1
i̇Lb1 = − (1 − d)
Lb 1 Lb 1
vb − vCf 2
i̇Lb2 =
Lb2
vCf 1 − vCf 2 iLb1 (C.9)
v̇Cf 1 = − + (1 − d)
RCf 1 Cf 1
vCf 1 − vCf 2 iLb2
v̇Cf 2 = +
RCf 2 Cf 2

For the negative output voltages averaging corresponds to summing up equations (C.6)
and (C.8) weighted by their respective duty cycles:
vb − vCf 1
i̇Lb1 =
Lb1
vb vCf 2
i̇Lb2 = − (1 − d)
Lb 2 Lb 2
v̇Cf 1 = − +
RCf 1 Cf 1
v̇Cf 2 = + (1 − d)
RCf 2 Cf 2
Vb (1 − D)VCf 1 ṽb ˜ Cf 1
(1 − D)ṽCf 1 − dV
ĩ˙ Lb1 = − + −
Lb1 Lb1 Lb1 Lb1
V − V ṽ − ṽ
ĩ˙ Lb2 =
b Cf 2 b Cf 2
+
Lb2 Lb2
VCf 1 − VCf 2 (1 − D)ILb1 ṽCf 1 − ṽCf 2 (1 − D)ĩLb1 − dI ˜ Lb1
ṽ˙ Cf 1 = − + + − +
RCf 1 Cf 1 RCf 1 Cf 1
VCf 1 − VCf 2 ILb2 ṽCf 1 − ṽCf 2 ĩLb2
ṽ˙ Cf 2 = + + +
(C.11)

Vb − VCf 1 ṽb − ṽCf 1
ĩ˙ Lb1 = +
Lb1 Lb1
Vb (1 − D)VCf 2 ṽb ˜ Cf 2
(1 − D)ṽCf 2 − dV
ĩ˙ Lb2 =

− + −
Lb2 Lb2 Lb2 Lb2
VCf 1 − VCf 2 ILb1 ṽCf 1 − ṽCf 2 ĩLb1 (C.12)
ṽ˙ Cf 1 = − + + − +
VCf 1 − VCf 2 (1 − D)ILb2 ṽCf 1 − ṽCf 2 (1 − D)ĩLb2 − dI ˜ Lb2
ṽ˙ Cf 2 = + + +
DC-model of the double-boost SICAM is obtained by equating the DC quantities on

both sides of (C.11) for positive output voltages:
Vb
0 = Vb − (1 − D)VCf 1 ⇒ VCf 1 =
1−D
0 = Vb − VCf 2 ⇒ VCf 2 = Vb
VCf 1 − VCf 2 VCf 1 − VCf 2 (C.13)
0=− + (1 − D)ILb1 ⇒ ILb1 =
R (1 − D)R
0= + ILb2 ⇒ ILb2 = −
R R
and (C.11) for negative output voltages:
0 = Vb − VCf 1 ⇒ VCf 1 = Vb
Vb
0 = Vb − (1 − D)VCf 2 ⇒ VCf 2 =
1−D
VCf 1 − VCf 2 VCf 1 − VCf 2 (C.14)
0=− + ILb1 ⇒ ILb1 =
R R
0= + (1 − D)ILb2 ⇒ ILb2 = −
R (1 − D)R
AC-model of the double boost SICAM is obtained by equating the AC quantities on

both sides of (C.11) for positive output voltages:
vb (1 − D)vCf 1 − dVCf 1
i̇Lb1 = −
Lb1 Lb1
vb − vCf 2
i̇Lb2 =
Lb2
(C.15)
vCf 1 − vCf 2 (1 − D)iLb1 − dILb1
v̇Cf 1 = − +
RCf 1 Cf 1
v̇Cf 2 = +
RCf 2 Cf 2

vb − vCf 1
i̇Lb1 =
Lb1
vb (1 − D)vCf 2 − dVCf 2
i̇Lb2 = −
Lb2 Lb2
v̇Cf 1 = − +
RCf 1 Cf 1
vCf 1 − vCf 2 (1 − D)iLb2 − dILb2
v̇Cf 2 = +
RCf 2 Cf 2

AC small-signal model for positive output voltages (C.15) can be rewritten in the
1−D
 
0 0 − 0
 Lb1 
1
     
iLb1   i Lb1
 0 0 0 − 
d 
 iLb2  = 
  Lb2  ·  iLb2  +
 
dt  vCf 1  1 − D 1 1   vCf 1 
0 − 
vCf 2  Cf 1
 RCf 1 RCf 1  vCf 2

 1 1 1 
0 −
Cf 2 RCf 2 RCf 2
1 VCf 1
 
 Lb1 Lb1  (C.17)
 1
 

 0  vb
+ L b2
·
ILb1  d
 

 0 − 
 Cf 1 
0 0
 
" # iLb1

vo
0 0 1 −1  iLb2 

v
= ·
  +0· b
ib 1 1 0 0 vCf 1  d
vCf 2
So the system matrix Adb+ , input matrix Bdb+ , output matrix Cdb+ and input-to-output
matrix Ddb+ are:
1−D
 
0 0 − 0
 Lb1 
1
 
 
 0 0 0 − 
 Lb2 
Adb+ = 
1 − D 1 1



 Cf 1 0 − 
 RCf 1 RCf 1 

 1 1 1 
0 −
Cf 2 RCf 2 RCf 2
1 VCf 1
 
 Lb1 Lb1 
 1
 
 (C.18)
 0 
 Lb2
Bdb+ =  
ILb1

 
 0 − 
 Cf 1 
0 0
" #
0 0 1 −1
Cdb+ =
1 1 0 0
Ddb+ = 0
AC small-signal model for negative output voltages (C.16) can be rewritten in the
1
 
 0 0 −
Lb1
0 
1 − D
     
iLb1   i Lb1
  0 0 0 −
 
d 
 iLb2  =  Lb2   ·  iLb2  +
 
dt vCf 1
   1 1 1   vCf 1 
 0 − 
vCf 2  Cf 1
 RCf 1 RCf 1  vCf 2

 1−D 1 1 
0 −
Cf 2 RCf 2 RCf 2
1
 
0
 Lb1
(C.19)

 1 VCf 2
 

 vb
 
+  Lb2 Lb2 ·

 0 0  d
 
 
 ILb2 
0 −
Cf 2
 
" # i Lb1

vo 0 0 1 −1  iLb2 

v
= ·  +0· b
ib 1 1 0 0 vCf 1  d
vCf 2
So the system matrix Adb− , input matrix Bdb− , output matrix Cdb− and input-to-output
matrix Ddb− are:
1
 
0 0 − 0
 Lb1 
1−D 
 

 0 0 0 − 
 Lb2 
Adb− = 
 1 1 1



 Cf 1 0 − 
 RCf 1 RCf 1 

 1−D 1 1 
0 −
Cf 2 RCf 2 RCf 2
1
 
0
 Lb1 
 1

VCf 2

 (C.20)
 
 Lb2 Lb2
Bdb− = 


 0 0 
 
 
 ILb2 
0 −
Cf 2
" #
0 0 1 −1
Cdb− =
1 1 0 0
Ddb− = 0
System matrices in (C.18) and (C.20) can be used to develop small-signal transfer

vo −1
vb
= Cdb+ (sI − Adb+ ) Bdb+ + Ddb+ · =
ib d
(C.21)
Gvo vb ,db+ (s) Gvo d,db+ (s) vb
= ·
Gib vb ,db+ (s) Gib d,db+ (s) d
and:

vo −1
vb
= Cdb− (sI − Adb− ) Bdb− + Ddb− · =
ib d
(C.22)
Gvo vb ,db− (s) Gvo d,db− (s) v
= · b
Gib vb ,db− (s) Gib d,db− (s) d
D
Analysis of flyback auxiliary converter for SICAM
with active capacitive voltage clamp
D.1 Analysis of CCM flyback auxiliary converter

The state-space analysis of the CCM flyback auxiliary converter will be performed using
the circuit diagram in Fig. D.1.
+ iC + iL nig niR
2
icl vC C vL L + vg/n -R/n
-
Fig. D.1. Buck-boost auxiliary converter (same as Fig. 6.21)
The differential equations for the CCM flyback auxiliary converter are:
• during interval ton i.e. d:
diL
L = vC
dt
dvC (D.1)
C = −iL + icl
dt
nvg
nig = niR = −
R
• during interval tof f i.e. d′ = 1 − d:
diL vg
L =
dt n
dvC (D.2)
C = icl
dt
nvg
nig = iL + niR = iL −
R
switching harmonics present in the waveforms and reveal the low frequency content. This
corresponds to summing up equations (D.1) and (D.2) weighted by their respective duty
cycles:
diL vg
L = dvC + d′
dt n
dvC (D.3)
C = −diL + icl
dt
nvg
nig = niR = d′ iL −
R
304 D Analysis of flyback auxiliary converter for SICAM with active capacitive voltage clamp

neglected without significant adverse impact on the accuracy. It should be noted that the
perturbation on the complementary duty cycle d′ is ∆d′ = −∆d.
The perturbed average model of (D.3) becomes:
dĩL Vg ṽg Vg ˜
L = (DVc + D′ ) + (DṽC + VC d˜ + D′ − d)
dt n n n
dṽC
C = (−DIL + Icl ) + (−DĩL − IL d˜ + ĩcl ) (D.4)
dt
nVg nṽg
n(Ig + ĩg ) = (D′ IL − ) + (D′ ĩL − IL d˜ − )
R R
DC-model of the CCM flyback auxiliary converter is obtained by equating the DC
quantities on both sides of (D.4):
Vg D′
0 = DVc + D′ ⇒ VC = − Vg
n Dn
Icl
0 = −DIL + Icl ⇒ IL = (D.5)
D
nVg D′ Vg
nIg = D′ IL − ⇒ Ig = Icl −
R nD R
AC-model of the CCM flyback auxiliary converter is obtained by equating the AC
quantities on both sides of (D.4):
diL vg Vg
L = DvC + VC d + D′ − d
dt n n
dvC (D.6)
C = −DiL − IL d + icl
dt
nig = D′ iL − IL d − nvRg

The small-signal AC model (D.6) is simply rewritten in the Laplace domain of complex
variable s:
Vg vg (s)
sLiL (s) = DvC (s) + (VC − )d(s) + D′
n n
sCvC (s) = −DiL (s) − IL d(s) + icl (s) (D.7)
nvg (s)
nig (s) = D′ iL (s) − IL d(s) − R
The transfer function Gvcd from the duty cycle d to the capacitor voltage vC is of
utmost interest:

vc
Gvcd = (D.8)
d vg =icl =0
By setting vg = icl = 0, the inductor current iL can be expressed from the second
equation in (D.7):
D.2 Analysis of DCM flyback auxiliary converter 305
sCvc − IL d
iL = − (D.9)
D
By replacing (D.9) in the first equation from (D.7), the following control-to-clamp-
voltage control function for the CCM flyback auxiliary converter is obtained:
snLIcl
Vg 1 − DVg

vc
Gvcd,ccm = = · (D.10)
d vg =icl =0 nD2 1 + s2DLC
2
D.2 Analysis of DCM flyback auxiliary converter

The state-space analysis of the DCM flyback auxiliary converter will be performed using
its averaged switch model [60], shown with the circuit diagram in Fig. D.2. As a result of
the discontinuous conduction mode, there are three different time intervals during each
switching period Ts : on-time of the main switch during which the inductor current ramps
up (d1 = d), off-time of the main switch with decreasing inductor current (d2 ) and off-time
of the main switch with zero inductor current (d3 = 1 − d − d2 ).
Switching cell
i1 i2
+ +
v1 v2 nig niR
+
2
icl vC + vg/n -R/n
+ -
C
vL L
iL
Fig. D.2. Averaged switch model of the DCM flyback auxiliary converter (same as Fig. 6.22)
The voltage equations for the switching cell of the DCM flyback auxiliary converter
are:
• during interval ton i.e. d1 = d:
v1 = 0
vg (D.11)
v2 = vC −
n
• during interval tof f 1 i.e. d2 :
vg
v1 = vC −
n (D.12)
v2 = 0
• during interval tof f 2 i.e. d3 = 1 − d − d2 :
v1 = vC
vg (D.13)
v2 = −
n
306 D Analysis of flyback auxiliary converter for SICAM with active capacitive voltage clamp
switching harmonics present in the voltage waveforms and reveal the low frequency con-
tent. This corresponds to summing up equations (D.11), (D.12) and (D.13) weighted by
their respective duty cycles:
vg
v1 = (1 − d)vC − d2
n (D.14)
vg
v2 = dvc − (1 − d2 )
n
where all voltages are represented by their average values.
The average values of the switch currents i1 and i2 are calculated in the following way:
1 t+Ts q1 dTs d dTs vc d2 Ts

Z
i1 = i1 dτ = = ipk = = vc
Ts t Ts 2Ts 2 L 2L
Z t+Ts (D.15)
1 q2 d2 Ts d2 dTs vc dd2 Ts
i2 = i2 dτ = = ipk = = vc
Ts t Ts 2Ts 2 L 2L
Duty cycle d2 is found by averaging inductor current waveform iL :
1 d(d + d2 )Ts
iL = ipk (d + d2 ) = vc (D.16)
2 2L
and expressing d2 :

2LiL Re iL
d2 = −d= −1 d (D.17)
dTs vC vC
where Re = (2L)/d2 Ts represents the equivalent resistance of the lossless input port, which
transfers the absorbed power to the output port.
Using the expression (D.17) for the duty cycle d2 , voltage v1 and current i2 can be
written as:
vg 2LiL vg
v1 = (1 − d)vC + d − = γ1 (vg , vC , iL , d) = kg vg + kC vC + r1 iL + f1 d
n ndTs vC (D.18)
d2 Ts vc
i2 = iL − = γ2 (vC , iL , d) = gC vC + h2 iL + j2 d
2L
where the coefficients are obtained by differentiating the input voltage v1 and the output
current i2 of the averaged switch network in (D.18) and are given with the following
expressions:

∂γ1 (vg , VC , IL , D) D 2LIL
kg = = −
∂vg
v =V n nDTs VC
g g
∂γ1 (Vg , vC , IL , D) 2LIL Vg
kC = = (1 − D) +
∂vC
vC =VC nDTs VC2

∂γ1 (Vg , VC , iL , D) 2LVg (D.19)
r1 = =−
∂iL
i =I nDTs VC
L L
∂γ1 (Vg , VC , IL , d) Vg 2LIL Vg
f1 = = −VC + +
∂d
d=D n nD2 Ts VC
and:
D.2 Analysis of DCM flyback auxiliary converter 307
D2 Ts

∂γ2 (vC , IL , D)
gC = = −
∂vC
v =V 2L
c C
∂γ2 (VC , iL , D)
h2 = =1 (D.20)
∂iL
iL =IL

∂γ2 (VC , IL , d) DTs VC
j2 = =−
∂d
d=D L
The small-signal equivalent model of the DCM flyback auxiliary converter is depicted
in Fig. D.3.
+ v1 - + v2 -
+
+
-
-
i1 gCvC i2
kgvg kCvC r1iL f1d
+ iC h2iL nig niR
iL +
2
icl vC C + j2d - vg/n -R/n
vL L
Fig. D.3. Small-signal AC model of DCM flyback auxiliary converter (same as Fig. 6.23)
In order to calculate the control-to-clamp-voltage transfer function of the DCM flyback

auxiliary transformer Gvcd,dcm , it will be again assumed that vg = icl = 0. From the
equivalent circuit diagram in Fig. 6.23, capacitor voltage vC can be represented as:
vC = kC vC + r1 iL + f1 d + sLiL (D.21)
where the inductor current iL is to be eliminated.

Inductor current from the same diagram can be represented as:
iL = −sCvC + gC vC + h2 iL + j2 d
−sCvC + gC vC + j2 d (D.22)
iL =
1 − h2
After replacing the inductor current iL from (D.22) in (D.21), the following control-to-
clamp-voltage control function for the DCM flyback auxiliary converter is obtained:

vc f1 (1 − h2 ) + j2 (r1 + sL)
Gvcd,dcm = = (D.23)
d vg =icl =0 (1 − kC )(1 − h2 ) − (r1 + sL)(gc − sC)
E
Analysis of control methods for SICAMs
E.1 Frequency spectrum of different PWM waveforms in

isolated SICAMs
Double Fourier Series (DFS) of a periodical signal F (x, y) being a function of two variables
x = ωc t and y = ωm t, where ωc and ωm are the carrier and modulating angular frequency,
can be represented with the following equation [33]:
∞
1 X
F (x, y) = A00 + A0n cos(ny) + B0n sin(ny) +
2 n=1
X∞

+ Am0 cos(mx) + Bm0 sin(mx) + (E.1)
m=1
X∞ X±∞

+ Amn cos(mx + ny) + Bmn sin(mx + ny)
m=1 n=±1
where the Fourier coefficients are given with the expressions:

Z 2π Z 2π
1
A00 = 2 F (x, y)dxdy
2π 0 0
Z 2π Z 2π
1
A0n + iB0n = 2 einy F (x, y)dxdy
2π 0
Z 2π Z0 2π (E.2)
1
Am0 + iBm0 = 2 eimx F (x, y)dxdy
2π 0
Z 2π Z0 2π
1
Amn + iBmn = 2 ei(mx+ny) F (x, y)dxdy
2π 0 0
E.1.1 Double Fourier Series of FNADS,1h
The main building block for developing all other PWM waveforms through time-scale
inversion and phase-shifting is the two-level single-sided PWM waveform FN ADS [33]. In
the case of HF-link converters where the frequency of the triangular carrier fc2 is two
times the HF-link frequency fHF , fc2 = 2fHF , a modification of the same waveform is
required, where each second PWM pulse is skipped FN ADS,1h . It is essentially a three-level
waveform, where just two levels are used in the active intervals, while in the skipped
intervals zero is inserted. Its graphical derivation is depicted in Fig. E.1. The coefficient
k = Tc2 /(4 · THF ) in fact defines the maximum duty cycle Dmax of the PWM waveform
and for the particular case fc2 = 2fHF is k = 0.125.
Fourier coefficient A00 of FN ADS,1h is:
310 E Analysis of control methods for SICAMs
y k
p 2p
x
-1
Fig. E.1. Diagram of FN ADS,1h for developing its DFS
Z 2π Z 2πk+2πkM cos y Z 4πk

1
A00 = 2 dx − dx dy =
2π 0 0 2πk+2πkM cos y
(E.3)
1
= 4πkM cos y = 4kM cos y
π
Fourier coefficients A0n and B0n of FN ADS,1h are:

2π Z 2πk+2πkM cos y 4πk
1
Z Z
iny iny
A0n + iB0n = 2 e dx − e dx dy =
Z 2π (E.4)
1
= 2 4πkM cos yeiny dy = 0
2π 0
Fourier coefficients Am0 and Bm0 of FN ADS,1h are:
1 imx imx
Am0 + iBm0 = 2 e dx − e dx dy =
Z 2π
i i(2πmk+2πmkM cos y) i4πmk
=− 2 2e −1−e dy =
2π m 0
i i(2πmk) 2π i(2πmkM cos y)

i
Z
i4πmk
=− 2 e e dy + 1+e =
π m 0 πm
π π π (E.5)
2ei(2πmk− 2 ) ei 2 ei(4πmk+ 2 )
= J0 (2πmkM ) + + =
mπ mπ mπ

= J0 (2πmkM ) + +
mπ mπ
2 sin(2πmk − π2 ) 1 + sin(4πmk + π2 )

+i J0 (2πmkM ) +
mπ mπ
Fourier coefficients Amn and Bmn of FN ADS,1h are:

E.1 Frequency spectrum of different PWM waveforms in isolated SICAMs 311
1 i(mx+ny) i(mx+ny)
Amn + iBmn = 2 e dx − e dx dy =
Z 2π
i i(2πmk+2πmkM cos y) iny iny i4πmk iny
=− 2 2e e −e −e e dy =
2π m 0
i i(2πmk) 2π i(2πmkM cos y) iny 2 i(2πmk+ (n−1)π )
Z
=− 2 e e e dy = e 2 Jn (2πmkM ) =
π m 0 πm
2 cos(2πmk + (n−1)π )

2
= Jn (2πmkM ) +
mπ
2 sin(2πmk + (n−1)π )

2
+i Jn (2πmkM )
mπ
(E.6)
E.1.2 Double Fourier Series of FNADS,2h
FN ADS,2h essentially represents the same waveform FN ADS,1h shown in Fig. E.1, but is
shifted for π rad. Therefore, the DFS of FN ADS,2h can be calculated by starting from the
DFS of FN ADS,1h and shifting it appropriately in the time domain. It can also be developed
in a thorough mathematical way like already done for FN ADS,1h in the previous section,
and this method will be shown below.
Fourier coefficient A00 of FN ADS,2h is:
1
A00 = 2 dx − dx dy =
2π 0 4πk 6πk+2πkM cos y
(E.7)
1
= 4πkM cos y = 4kM cos y
π
Fourier coefficients A0n and B0n of FN ADS,2h are:

2π Z 6πk+2πkM cos y 8πk
1
Z Z
iny iny
A0n + iB0n = 2 e dx − e dx dy =
Z 2π (E.8)
1
= 2 4πkM cos yeiny dy = 0
2π 0
Fourier coefficients Am0 and Bm0 of FN ADS,2h are:
1 imx imx
Am0 + iBm0 = 2 e dx − e dx dy =
Z 2π
i i(6πmk+2πmkM cos y) i4πmk i8πmk
=− 2 2e −e −e dy =
2π m 0
Z 2π
i i(6πmk) i(2πmkM cos y) i i4πmk i8πmk
=− 2 e e dy + e +e =
π m 0 πm
π π (E.9)
2ei(6πmk− 2 ) ei 2

= J0 (2πmkM ) + ei4πmk + ei8πmk =
mπ mπ
2 cos(6πmk − π2 ) cos(4πmk + π2 ) cos(8πmk + π2 )

= J0 (2πmkM ) + + +
mπ mπ mπ
2 sin(6πmk − π2 ) sin(4πmk + π2 ) + sin(8πmk + π2 )

+i J0 (2πmkM ) +
mπ mπ
Fourier coefficients Amn and Bmn of FN ADS,2h are:

1 i(mx+ny) i(mx+ny)
Amn + iBmn = 2 e dx − e dx dy =
Z 2π
i i(6πmk+2πmkM cos y) iny i4πmk iny i8πmk iny
=− 2 2e e −e e −e e dy =
2π m 0
i i(6πmk) 2π i(2πmkM cos y) iny 2 i(6πmk+ (n−1)π )
Z
=− 2 e e e dy = e 2 Jn (2πmkM ) =
π m 0 πm
2 cos(6πmk + (n−1)π )

2
= Jn (2πmkM ) +
mπ
2 sin(6πmk + (n−1)π )

2
+i Jn (2πmkM )
mπ
(E.10)
E.1.3 Double Fourier Series of FNADD,1h
FN ADD,1h is a two-level double-sided PWM waveform with a value of zero in the even
half-periods. Since the changes in the PWM waveform correspond to the intersections of
the sinusoidal reference signal with a double-sided triangular carrier, FN ADD,1h is actually
constituted from two FN ADS,1h waveforms, where the second one has inverted time scale.
Taking into consideration the coefficients of FN ADS,1h in (E.3)-(E.6), DFS of FN ADD,1h
becomes:
FN ADD,1h (t, ϕ) = FN ADS,1h (t, ϕ) + FN ADS,1h (−t, ϕ) =
= 4kM cos(y + ϕ)+
∞
X
+2 J0 (2πmkM ) + cos(mx)+
m=1
mπ mπ
∞ X ±∞
X 2 cos(2πmk + (n−1)π
2
)
+2 Jn (2πmkM ) cos(mx + ny) cos(nϕ)+
m=1 n=±1
mπ
2 sin(2πmk + (n−1)π )
(E.11)
2
+ Jn (2πmkM ) sin(mx + ny) sin(nϕ) =
mπ
= 4kM cos(y + ϕ)+
∞
X
+2 J0 (2πmkM ) + cos(mx)+
m=1
mπ mπ
∞ X ±∞
2
− nϕ)
+4 Jn (2πmkM ) cos(mx + ny + nϕ)
m=1 n=±1
mπ
E.1.4 Double Fourier Series of FNADD,2h
FN ADD,2h is a two-level double-sided PWM waveform with a value of zero in the odd
half-periods and represents a time-shifted version of FN ADD,1h . Its DFS can be obtained
either by shifting the DFS of FN ADD,1h in (E.11) or by calculating it from the coefficients
of FN ADS,2h in (E.7)-(E.10). The latter approach is shown below:
E.2 Switching frequency of GLIM self-oscillating modulator 313

FN ADD,2h (t, ϕ) = − FN ADS,2h (t, ϕ + π) + FN ADS,2h (−t, ϕ + π) =
= −4kM cos(y + ϕ + π)−
∞
2 cos(6πmk − π2 ) cos(4πmk + π2 ) + cos(8πmk + π2 )
X
−2 J0 (2πmkM ) + cos(mx)−
m=1
mπ mπ
∞ X ±∞
X 2 cos(6πmk + (n−1)π
2
)
−2 Jn (2πmkM ) cos(mx + ny) cos(nϕ + nπ)+
m=1 n=±1
mπ
2 sin(6πmk + (n−1)π )

2
+ Jn (2πmkM ) sin(mx + ny) sin(nϕ + nπ) =
mπ
= 4kM cos(y + ϕ)−
∞
2 cos(6πmk − π2 ) cos(4πmk + π2 ) + cos(8πmk + π2 )
X
−2 J0 (2πmkM ) + cos(mx)−
m=1
mπ mπ
∞ X ±∞
2
− n(ϕ + π))
−4 Jn (2πmkM ) cos(mx + ny + nϕ)
m=1 n=±1
mπ
(E.12)
It should be noted that the minus sign in the first row of (E.12) is result of the fact
that the PWM waveform is inverted during the even half-periods because of the negative
voltage of the HF-link. On the other hand, the phase of the sinusoidal reference signal is
ϕ + π because the input to the PWM modulator during the half-periods with negative
HF-link voltage is inverted, as explained in Section 7.2.2.
E.2 Switching frequency of GLIM self-oscillating modulator

Switching frequency of the GLIM self-oscillating modulator will be calculated using the
waveform in Fig. E.2.
vc Dtd Dtd Dtd
DV2
t
2Vh
DV1
Dt1 Dt2
Fig. E.2. GLIM carrier
Due to the delay td in the modulator loop, carrier voltage vc overshoots the hysteresis
window 2Vh in amount of:
Vs (1 − M )
∆V1 = ∆td
τ ka
(E.13)
Vs (1 + M )
∆V2 = ∆td
τ ka
p
where Vs is the supply voltage, M is the modulation index, τ = 1/(2π Lf Cf ) is the
integration constant found also in the MFB block, ka is the amplifier gain and ∆td is the
modulator loop delay.
Time intervals ∆t1 and ∆t2 corresponding to the rising and falling intervals of the
carrier waveform vc can be determined with the following equations:
(2Vh + ∆V1 + ∆V2 )τ ka

∆t1 =
Vs (1 + M )
(E.14)
(2Vh + ∆V1 + ∆V2 )τ ka
∆t2 =
Vs (1 − M )
Switching frequency of the GLIM modulator is:
1 Vs (1 − M 2 )
fs = = =
∆t1 + ∆t2 2(2Vh + ∆V1 + ∆V2 )τ ka
(E.15)
Vs (1 − M 2 )
=
4 Vh τ ka + Vs ∆td
In order to improve the power supply rejection ratio and make the switching frequency
independent of the supply voltage, the hysteresis window is usually chosen to be linear
function of the supply voltage:
Vh = kh Vs (E.16)
In this case, the switching frequency from (E.15) becomes:
1 (1 − M 2 )
fs = (E.17)
4 τ kh ka + ∆td
F
Prototype schematics
F.1 Schematics of isolated SICAM with master/slave operation

Circuit schematics of the isolated SICAM with master/slave operation are given in
Fig. F.1, Fig. F.2 and Fig. F.3.
F.2 Schematics of isolated SICAM with active capacitive load

voltage clamp
Circuit schematics of the isolated SICAM with active capacitive load voltage clamp are
given in Fig. F.4 and Fig. F.5.
F.3 Schematics of isolated SICAM with optimized PWM

modulator and safe-commutation switching sequence
Circuit schematics of the isolated SICAM with optimized PWM modulator and safe-
commutation switching sequence are given in Fig. F.6 and Fig. F.7.
F.4 Schematics of isolated self-oscillating SICAM with GLIM

modulator
Circuit schematics of the isolated self-oscillating SICAM with GLIM modulator are given
in Fig. F.8 and Fig. F.9.
F.5 Schematics of 4Q flyback SICAM

Circuit schematics of the 4Q flyback SICAM are given in Fig. F.10 and Fig. F.11.
316 F Prototype schematics
Fig. F.1. Power circuit schematic of the isolated SICAM with master/slave operation
F.5 Schematics of 4Q flyback SICAM 317
Fig. F.2. Open-loop control circuit schematic of the isolated SICAM with master/slave operation
Fig. F.3. Closed-loop control circuit schematic of the isolated SICAM with master/slave operation
Fig. F.4. Power circuit schematic of the isolated SICAM with active capacitive load voltage clamp
Fig. F.5. Control circuit schematic of the isolated SICAM with active capacitive load voltage clamp
Fig. F.6. Power circuit schematic of the isolated SICAM with optimized PWM modulator and safe-commutation
switching sequence
Fig. F.7. Control circuit schematic of the isolated SICAM with optimized PWM modulator and safe-commutation
switching sequence
Fig. F.8. Power circuit schematic of the isolated self-oscillating SICAM with GLIM modulator
Fig. F.9. Control circuit schematic of the isolated self-oscillating SICAM with GLIM modulator
Fig. F.10. Power circuit schematic of the 4Q flyback SICAM

Fig. F.11. Control circuit schematic of the 4Q flyback SICAM

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Single Conversion stage AMplifier - SICAM

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SIngle Conversion stage AMplifier

PhD thesis, December 2005

Kongens Lyngby Petar Ljušev

Part I Non-isolated SICAMs

3 AC-mains connected Class D audio power amplifiers as SICAMs . . . . . 71

4 SICAM for portable devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Part II Isolated SICAMs

5 Introduction to isolated SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

6 Topologies for isolated SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

7 Control methods for isolated SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

8 Prototypes of isolated SICAMs with non-modulated transformer

9 4Q flyback SICAM with modulated transformer voltages . . . . . . . . . . . . 229

10 Integrated magnetics for isolated SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

11 General conclusion about SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

A Analysis of matrix SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

B Analysis of combined mains-connected Class D audio power amplifier

C Analysis of double-boost SICAM for portable applications . . . . . . . . . . . 295

D Analysis of flyback auxiliary converter for SICAM with active

E Analysis of control methods for SICAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

F Prototype schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

1.1 I-V characteristics of MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1 M-phase to N-phase matrix converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.18 Distribution of switching patterns’ time intervals through one switching

3.1 Non-isolated DC power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.12 Simulated waveforms of combined Class D audio power amplifier and

4.1 Double boost SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.11 Resultant PWM signal FN ADD · Fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

6.1 Class D resonant converter types: a) series LC, b) parallel LC and

7.1 Modified PWM modulator for SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

8.1 Photograph of the prototype master/slave-operated SICAM . . . . . . . . . . . . . 218

8.10 SICAM operation: 1) HF-link voltage (100V/div), 2) bridge voltage

8.37 Self-oscillating SICAM waveforms at Po = 6 W with 10 kHz reference:

9.1 Two-switch 4Q flyback SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

10.1 Three-winding transformer and its equivalent electrical circuit . . . . . . . . . . . 240

D.1 Buck-boost auxiliary converter (same as Fig. 6.21) . . . . . . . . . . . . . . . . . . . . . 303

E.1 Diagram of FN ADS,1h for developing its DFS . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

2.1 Switching states of a single-phase AC to single-phase AC matrix converter 30

4.1 Switching states of the double-boost SICAM . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.1 Current controlled commutation sequence of the bidirectional bridge in

7.1 Explanation of the parameters in Fig. 7.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

B.1 Switching sequences of the asynchronously-operated combined Class D

By definition, sound represents an acoustical or mechanical longitudinal pressure wave

1.1 Linear audio power amplifiers

Fig. 1.1. I-V characteristics of MOSFET

vGS − VGS(th) < vDS (1.1)

PF ET,con = vDS · iD ≫ 0 (1.2)

A scheme of a MOSFET output stage of a single-ended linear audio power amplifier

1.2 Switching-mode audio power amplifiers

vGS − VGS(th) > vDS > 0 (1.3)

PF ET,con = vDS · iD ≈ 0 (1.4)

A scheme of a MOSFET output stage of a single-ended switching-mode audio power

AC-DC DC-AC AC-DC DC-AC

Fig. 1.7. Block diagram of completely switching-mode audio power amplifier

1.3 SICAM project and problem definition

Fig. 1.10. Comparison of linear amplifiers, switching-mode amplifiers and SICAMs

1.4 Need for energy storage on a single-phase AC-mains