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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

A Multistage Interleaved Synchronous Buck

Converter With Integrated Output
Filter in 0.18 m SiGe Process
Siamak Abedinpour, Member, IEEE, Bertan Bakkaloglu, Member, IEEE, and Sayfe Kiaei, Fellow, IEEE

AbstractThe design and analysis of a fully integrated multistage interleaved synchronous buck dcdc converter with on-chip
filter inductor and capacitor is presented. The dcdc converter
is designed and fabricated in 0.18 m SiGe RFBiCMOS process
technology and generates 1.5 V2.0 V programmable output
voltage supporting a maximum output current of 200 mA. High
switching frequency of 45 MHz, multiphase interleaved operation,
and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art
converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling
and filtering and enables direct battery connection for integrated
applications. This design is the first reported fully integrated
multistage interleaved, zero voltage switching synchronous buck
converter with monolithic output filters. The fully integrated
buck regulator achieves 64% efficiency while providing an output
current of 200 mA.
Index TermsFully integrated switched-mode (SM) dcdc
converter, interleaved synchronous buck converter, zero voltage
switching (ZVS).

I. INTRODUCTION

ITH recent advances in integrated mixed-signal circuits

and an increasing demand for low-power multifunction
system-on-a-chip (SOC) and extended battery runtime, there is
a strong need for the development of efficient on-chip power
regulation and distribution. Current portable multimedia terminals incorporate several features on a single-chip, including
computing along with radio frequency (RF) transceivers, advanced human-machine interface circuits, and digital signal
processing capability. In small form factor portable electronic
devices, efficient power regulation and distribution to each
component on the chip is a critical issue. The power supply
voltage level of individual blocks on the integrated circuit
(IC) are scaled and optimized for minimum total power consumption and maximum performance. State-of-the-art mobile

Manuscript received July 15, 2006; revised January 29, 2007. This paper
was presented in part at the IEEE International Solid-State Circuits Conference
(ISSCC), San Francisco, CA, Feb. 59, 2006 and at the IEEE International Symposium on Circuits and Systems (ISCAS), Island of Kos, Greece, May 2124,
2006. Recommended for publication by Associate Editor P. Luk.
S. Abedinpour is with Freescale Semiconductor, Inc., Tempe, AZ 85284 USA
(e-mail: siamak.abedinpour@freescale.com).
B. Bakkaloglu and S. Kiaei are with the Ira A. Fulton School of Engineering, Arizona State University, Tempe, AZ 85287-08406 USA (e-mail:
bertan.bakkaloglu@asu.edu; sayfe.kiaei@asu.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2007.909288

terminals utilize a stand-alone multioutput centralized power

management IC that powers various sections through multiple
input/output (I/O) pads, bond-wires, package pins, and external
board-level interconnects, as shown in Fig. 1(a). This may introduce significant system noise, delay, and power loss. These
sections have different power supply requirements and include
data converters, memory chips, RF front-end, synthesizers,
digital base-band cores, microcontroller, signal processors, and
RF power amplifiers (PA). Given that various sections have
different requirements in terms of efficiency, power, the power
supply rejection ratio (PSRR), noise, and current consumption,
the battery voltage is converted and regulated to different
voltage levels for various components. This includes the application of linear low-dropout (LDO) [1], switched-mode (SM)
[2], and switched-capacitor (SC) [3] dcdc power converters.
LDOs can be integrated on-chip but can only step down the
battery voltage and have poor efficiency as the load voltage is reduced. They have a superior PSRR and are therefore suitable to
supply the sensitive analog and RF blocks which require high
PSRR and low noise supply voltages [4]. Switched-capacitor
dcdc converters can also be integrated [5] but have a complex
control circuit, a high number of switch count, suffer from parasitic bottom plate capacitance and introduce switching noise.
They convert voltages efficiently but have poor efficiency performance for voltage regulation. Therefore, they are suitable to
supply, for example, the display and white LED drivers in a cell
phone. High efficiency, high bandwidth SM dcdc converters
are the best candidates for supplying the RF PA [6], [7], memory
chips, and digital base-band cores [8]. These sections have the
highest current consumptions in a mobile terminal. Therefore,
an efficient power converter provides the highest increase in the
battery lifetime.
Parasitic inductances on the power delivery path of an SM
dcdc converter, such as bond-wires, package leads, and long
metal lines, convert the transient currents into voltage. The resulting additional voltage increases the amount of charge injected into the silicon substrate through junction capacitances
and impacts several parameters such as clock and data integrity
in digital blocks, signal to noise ratio (SNR) in analog, mixedsignal, and RF blocks. Complete integration of the power converter, including the passive filter components, reduces the parasitic inductances and the power converter switching noise.
This paper proposes a distributed power management approach, as shown in Fig. 1(b). Fully integrated SM dcdc
converters, which can be placed in the proximity of the load
circuits on the same silicon substrate, are presented. There

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Fig. 1. Power management architecture (a) centralized and (b) distributed.

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use of advanced deep submicron fabrication techniques with

low parasitic interconnect impedances improves maximum attainable efficiency. However, there are several challenges in the
development of fully integrated SM dcdc converters. Although
most standard deep submicron CMOS processes lack power
MOSFET devices, techniques to utilize standard MOSFET devices as pass transistors have been reported [9], [10]. Integration
of the filter inductor and capacitor required for energy storage
imposes a challenge in the fabrication of a fully integrated SM
converter. In order to enable full integration of SM dcdc converters, the size of these passive components should be significantly decreased. Ideally, the size of the filter inductor and capacitor decrease with increased switching frequency. However,
switching losses are directly proportional to the switching frequency, and this imposes a limit on the high frequency operation of SM dcdc converters. In order to minimize the switching
losses, most of the standard SM dcdc converters have used
lower switching frequencies, which require large off-chip passive filter components.
In this paper a fully integrated multistage interleaved zero
voltage switching (ZVS) synchronous buck dcdc converter
with a monolithic output filter is presented. The SM dcdc converter is designed and fabricated in 0.18 m SiGe RFBiCMOS
process technology and can achieve a switching frequency of
45 MHz. High switching frequency, multiphase interleaved
topology, and a fast hysteretic controller are implemented in
order to reduce the filter inductor and capacitor sizes by two
orders of magnitude compared to state-of-the-art converters
and enable a fully integrated converter. The paper is organized
as follows: a detailed analysis of the fully integrated dcdc
synchronous buck converters is introduced in Section II. Circuit
level implementation of the proposed multistage interleaved
converter architecture is discussed in Section III. Measurement
results are presented in Section IV. Conclusions and future
work on integrated power converters are discussed in Section V.
II. FULLY INTEGRATED SM DCDC CONVERTERS

Fig. 2. Single-chip distributed power supply architecture.

are several advantages in the development of fully integrated

dcdc converters. Fig. 2 shows a typical application for a fully
integrated distributed power management architecture in an
SOC. By utilizing this monolithic power delivery approach,
the power supply interconnect delay and response time to load
transients can be significantly reduced, and multiple supply
rail distribution buses can be replaced with a single dc power
bus. Integrated dcdc converters can provide required regulated
supplies to various blocks. Dedicated regulated supply rails in
an SOC also isolate supply noise coupling from noisy blocks
such as digital signal processors, frequency dividers, and microcontrollers into sensitive circuit blocks while improving
noise isolation.
In a discrete SM dcdc converter, power is dissipated in the
parasitic impedances of interconnects among the control circuit,
power transistors, filter inductor, and filter capacitor. Therefore,

As mentioned earlier, high efficiency SM dcdc converters

supplying the blocks, which dominate the current consumption
in a mobile terminal, will significantly improve the battery runtime. Since state-of-the-art SM dcdc converters operate at frequencies less than 5 MHz, they require external filter capacitors
larger than 1 F and filter inductor values higher than 1 H. This
impacts the system size and weight, which are critical factors
in the commercial viability of mobile terminals. Furthermore,
these converters are incapable of responding to load variations
without significant delay.
Fig. 3(a) shows the block diagram and transient response of
an off-chip external SM dcdc converter IC supplying a digital and analog load on a different IC via board and package
level interconnects. For the purpose of simulation, a simulation
setup has been utilized for characterizing the impact of interconnect parasitics on the performance of the SM dcdc converter.
In this case a typical bond-wire inductance of 1 nH/mm and a
resistance of 40 m mm are assumed to include the package
I/O pads parasitic effects. As depicted in Fig. 3(a), when the
digital load is enabled at 150 ns, large overshoots appear on
and are connected to the digital and
the dc supply line

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Fig. 3. Power management architecture (a) centralized off-chip, (b) monolithic with off-chip passive components, and (c) fully integrated on-chip.

analog loads as well as on the internal substrate connections. In

comparison, the power switches of the SM dcdc converter are
filter
integrated on-chip but are connected to the external
through I/O pad and bond-wire, as shown in Fig. 3(b). In this
case, the transient voltage drop generated via inductive loading
is still significant given that the passive filter components are
external. The transient overshoots on the supply line appear on
the switching node of the logic gates and are coupled to the substrate via the drain and source capacitance to substrate. As a result, the injected switching noise into the substrate is increased.
However, these transient overshoots can be eliminated, as shown
filter are intein Fig. 3(c), if both power switches and the
grated on-chip next to the loads.
High linearity, high voltage rating on-chip capacitors have
been well-established in CMOS process technology. However,
on-chip inductors have been investigated extensively for RF
circuits, and high quality factor ( ) inductors still introduce
serious challenges for integration [11]. There has been an increasing demand for monolithic inductors for power conversion
applications, which require low dc resistance (DCR). However,
the requirement for smaller dc resistance increases the cross
sectional area of the inductor, resulting in a larger capacitance
and reduced self resonance frequency [12]. As discussed earlier, for monolithic filter implementation, the size of the passive
filter components should be significantly decreased. This may
be accomplished by increasing the switching frequency, as
shown in Fig. 4. The plot shows the variation of passive filter
component sizes as a function of frequency for a buck converter

Fig. 4. Variation of L and C as a function of frequency.

operating at a duty cycle of 50% and providing 1.8 V for a

0.2 A resistive load. However, in conventional hard-switched
PWM SM dcdc converters, the power semiconductor switches
are subjected to high switching stresses and high switching
power loss that increase linearly with the switching frequency.
Soft switching techniques are often utilized at high switching
frequencies to minimize switching losses. In these techniques
the power semiconductor switch changes its status during the
switching transient when the voltage across it is zero, i.e. zero
voltage switching (ZVS), or the current through it is zero, i.e.

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Fig. 5. ZVS synchronous buck dcdc converter (a) circuit and (b) waveforms.

zero current switching (ZCS). For a power MOSFET, ZVS operation also eliminates the switching loss associated with reverse
recovery of the non-optimum body diode and improves the reliability of the converter. Fig. 5(a) shows a zero voltage switching
(ZVS) synchronous buck converter where the voltage across the
power device terminal is zero during the switching transient,
ideally eliminating switching losses. For ZVS operation it is
desirable to achieve a peak-to-peak current ripple equivalent to
twice the full load current. This ensures that the inductor current
reaches a negative value under all load conditions, as shown in
Fig. 5(b). The inductor value that guarantees this peak-to-peak
current ripple is given by
(1)
is the steady state duty cycle,
is the switching
where
frequency, and is the nominal output current. By introducing
between conduction of
and
a dead-time
the energy stored in the inductor can discharge their output
capacitances and cause their body diode to conduct prior to
and
can turn on
their channel conduction. Therefore,
under ZVS conditions [13], [14]. As a result, the Miller effect
in both switches is eliminated and the gate drive and the turn-on
switching loss are significantly reduced. The output capacitance
and
keeps the voltage across them close to zero
of
while they turn off, keeping the turn-off switching loss small.
Although a smaller filter inductor value results in a faster transient response and provides suitable conditions for ZVS operation, the resulting larger current ripple causes higher conduction
loss in the switches, inductor, and parasitic resistances. The resulting larger current ripple requires a larger filter capacitor to
decrease the output voltage ripple. In order to maintain a low,
steady-state output voltage ripple and fast transient response, ,
similar stages of synchronous buck converters can be operated
in parallel with a common output filter capacitance, as shown in
phase difference between the
Fig. 6(a). By applying a 360
triggering pulses of the adjacent power stages, the output current
ripple can be cancelled out while maintaining the fast transient
response characteristics of a single stage [15]. Fig. 6(a) shows
the timing diagram of the triggering pulses associated with the
interleaved power stages. As a result, the effective output frequency is increased and a smaller capacitance is required at the

Fig. 6. Multistage interleaved synchronous buck dcdc converters (a) circuit,

control waveforms and (b) output current ripple cancellation as a function of
duty cycle.

output. The output inductors of the individual converters are in

parallel during the transients, which further reduces the effective
output inductance and improves the transient response of the
converter. Another advantage of interleaved converter topologies is better thermal management and reliability. This is a result of the current distribution between parallel power MOSFET
and filter inductor stages.
The output current ripple cancellation depends on and
and improves with more modules in parallel. The relationship
, , and is given by
between the output current ripple,
[16]
(2)
The first term in (2) is the inductor current ripple, and the second
and
on ripple cancellation.
term represents the effect of
, which is norEquation (3) gives the output current ripple,
malized to the inductor current ripple at
0 as a function of
and
(3)

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Fig. 6(b) plots

for different values of . For a two-stage
0.5. For a
interleaved converter the ripple is cancelled when
four-stage interleaved converter the ripple is cancelled for
0.25, 0.5, 0.75 and is reduced at other values of . For small
values of , the output current ripple reduction is not significant. Assuming that all of the ripple components of the output
and its average
current flows through the filter capacitor
component flows through the load resistor, the peak-to-peak
can be written as
output voltage ripple

(4)
Fig. 7(a) shows the circuit of the two-stage interleaved ZVS
synchronous buck converter topology that has been fabricated.
and
The waveforms in Fig. 7(b) show the gate pulses of
, the current through the filter inductors
and
, the
output current , the filter capacitor current , and the output
load current .
III. CIRCUIT DESIGN
This section presents the circuit design of the fully integrated
SM dcdc converters implemented in a distributed power management architecture. Fully integrated dcdc converters are adjacent to the digital and analog blocks of a mixed-signal IC.
Fig. 2 shows the monolithic distributed power management architecture fabricated in 0.18 m SiGe RFBiCMOS process technology [9]. With high speed, low noise figure, high linearity,
and less dependence of speed on high field strength and supply
voltage SiGe RFBiCMOS process technology is well suited to
portable wireless applications. Table I summarizes the characteristics of this process. A modular platform-based approach is
utilized to develop this process. It is based upon a low power
0.18 m CMOS technology that provides both 35 A standard
devices for 1.8 V operation as well as 50 A (or 70 A) devices for 2.7 V (3.3 V) I/O circuits. Up to five layers of Cu metallization are available. The RFBiCMOS technology adds the
CMOS,
following elements to the CMOS technology: low
isolated NMOS, Analog NPN BJT, SiGe NPN HBT, MIM Cap,
and a high inductor. A high resistivity -substrate is utilized
for optimal passive element and signal isolation characteristics.
High quality passive components and the above mentioned features make the 0.18 m SiGe RFBiCMOS process technology
the best choice for fabricating fully integrated SM dcdc converters for portable wireless applications.
The IC consists of four monolithic dc-dc converters connected to the battery. Implemented topologies are synchronous
buck, two-stage interleaved synchronous buck, ZVS synchronous buck, and a two-stage interleaved ZVS synchronous
buck converter. Fig. 7(a) can be used to describe the structure
of both the monolithic synchronous buck converter and the
ZVS synchronous buck converter portion of the distributed
power supply architecture. The only difference between the
two converters is in their controller block. The converter shown
enclosed in the box is self contained and only requires

Fig. 7. Two-stage interleaved ZVS synchronous buck dcdc converter (a) circuit and (b) waveforms.

TABLE I
0.18 m SiGe RFBiCMOS PROCESS TECHNOLOGY

and
inputs for operation. The following circuits are implemented in the fully integrated converters.

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Fig. 8. Current comparator circuit.

A. Comparator
The comparator compares the converter output voltage,
,
and generates the
signal at
with the reference signal
its output. Current-mode comparators have higher speed, larger
bandwidth, and lower supply voltage requirements compared to
their conventional voltage-mode counterparts [17]. Fig. 8 shows
the circuit schematic of the designed current comparator block.
The circuit consists of a -to- converter, a current subtractor,
three cascaded current source inverting amplifiers, and an inand
verter at the output stage. The difference between
inputs of the comparator is converted into
,
is then applied to
at the output of the subtractor stage.
the first current source inverting amplifier, which uses a resistive feedback to reduce its input and output resistance
1 gm . These small resistances reduce the voltage
swing at nodes and , which causes faster transient response
time in the following inverting amplifiers.
In the single stage converters, the resulting PWM waveform
at the output of the comparator is applied directly to the controller block. In the two-stage interleaved converters, the PWM
signal is first applied to a phase-shift block to generate the required PWM signals for each stage of the converter. Fig. 9 shows
the circuit diagram of the phase shift block and its various waveforms. The phase shift block generates the PWM and PWM
signals, which have a 180 phase difference. The PWM and
PWM signals are then applied to the controller blocks to gento control the switching of the
erate the gate pulses
MOSFETs
and generate the required output voltage
.
specified by

B. Controller
The controller block of the synchronous buck converter circuits consists of the gate drive circuits for transistors
,
. The CMOS gate drive circuit is a cascade of
and
inverters, which generates gate pulses
and
to drive the large input capacitance of
and
. Fig. 10
. The width of
shows the gate drive circuit for transistors
each MOSFET in the inverter chain is larger than the previous
one by a scaling factor of , determined by (5), where
is the input capacitance of
and
is the input capacitance of the minimum size inverter
(5)

Fig. 9. Phase shift block (a) circuit diagram and (b) waveforms.

Fig. 10. CMOS gate-drive circuit.

An optimum number of inverter stages need to be utilized in

order to minimize total propagation delay. The optimum number
of inverter stages, , is calculated by

(6)
Since the delay is not very sensitive to changes in the scaling
5 is chosen as a compromise between delay and the
factor,
transisadditional complexity of extra inverter stages. For
tors
5, and for
transistors
4.
Fig. 11(a) shows the block diagram of the controller block
for the ZVS converter, which consists of two separate gate drive
circuits for the PMOS and NMOS power switches and a logic
circuit to ensure precise non-overlap time between two pulses.
Fig. 11(b) shows various simulated waveforms of the ZVS controller. The PWM signal is applied to the logic circuit, which
and
pulses from the output of the gate drive ciruses the
cuits as feedback signals to introduce a dead-time between the
PWM and PWM pulses. These signals are then applied to the
and
pulses to be applied
gate drive blocks and generate
to the converter power train. This ensures ZVS operation over
the entire load range. The body diode conduction of both power
MOSFETs prior to their channel conduction is evident from the

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Fig. 11. ZVS controller (a) block diagram and (b) simulation results.

(a)

(b)

Fig. 12. Variation of MOSFET power losses as a function of device width for (a) NMOS and (b) PMOS.

waveform of the switching node

of Fig. 5(a), as shown in
Fig. 11(b). This causes ZVS turn-on of both power MOSFETs.
C. Power Train
The power train of the converters consists of power MOSFETs
, filter inductors and filter capacitors. Power
are implemented by use of 3.3 V MOSMOSFETs
FETs with 70 A gate oxide thickness. Although implementation of NMOS devices is advantageous for high side power
switches, their complex gate drive makes them less attractive
for monolithic implementation. Therefore, PMOS devices are
and the synchronous rectifiers
are impleused for
are obmented as NMOS. The optimum device widths
tained after equating the conduction losses and switching losses
of the switches to minimize their total power loss, as shown in

Fig. 12. Equation (7) gives the optimum

total device losses

that optimizes the

(7)

Power MOSFETs
are formed by parallel connection of an array of unit size cells. The unit size cells have a width
20 m and multiple gate fingers with a minimum gate
of
0.5 m. Equation (8) is used to choose the required
length
width of the unit size cells, , in order to reduce the RC delay
contributed by the gate structures, which affects the switch transitions
(8)

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Fig. 13. Cross section of synchronous buck converter power train: (a) nonisolated and (b) hybrid isolation.

In this equation
is the resistance of a poly-silicon gate,
m , width of
m , and sheet resistance
with a length of
of
.
is the total capacitance of the
is the gate oxide capoly-silicon gate, where
. Gate finpacitance per unit area with an oxide thickness of
gers are contacted at both ends, which reduce the resistance of
the poly-silicon gate fingers that are connected in parallel with
metal interconnect. The number of fingers in each unit cell determines the size of the cell and is chosen to ensure optimum
isolation.
D. Substrate Noise Isolation
Fig. 13(a) shows the cross section of the power MOSFETs
of the single-stage monolithic synchronous buck converter of
, has
Fig. 5(a). As shown in Fig. 11(b), the switching node
large switching voltage transients. Switching noise is coupled
to the substrate through the drain-substrate capacitance of the
power MOSFETs. The resulting current passes through the
impedance in the path to ground and generates a voltage. As a
result, the noise floor of the substrate common to other circuit
blocks on the chip is increased, which reduces their performance. The noise level depends on the converter load current,
switching frequency, drain-substrate capacitance, and the parasitic impedance of the substrate to ground. For a significant
portion of each switching cycle, large transient currents flow
through the channel of the synchronous rectifier and degrade
the performance of the adjacent circuit blocks. Furthermore,
for a small portion of each switching cycle the body diode of
each power MOSFET conducts prior to its channel conduction
to ensure ZVS turn-on
Fig. 14(a) shows the simplified schematic used to model the
switching noise. A heavily doped substrate behaving as a single

node is assumed in order to simplify the analysis [18]. In the

substrate
guard rings may be placed very
real case of
close to the individual IC blocks to effectively isolate them from
a single substrate node. The diffusion and interconnect capacitance that couples the switching noise from the switching node
to the substrate is modeled by the capacitor
and depends
on the process technology. The substrate impedance consists of
,
, and
. The
resistor models the spreading
resistance through the epi layer and depends on the number of
inductance represents the
substrate contact diffusions. The
bond-wire parasitic inductance. The switching noise coupled
into the substrate is determined by

(9)
Fig. 14(b) shows the magnitude of the frequency response of
for five different values of
. The results show that
the amplitude of the substrate noise is minimized by reducing
.
the inductance
In order to increase the level of isolation in the design of the
monolithic power converters, a hybrid isolation strategy is implemented, as shown in Fig. 13(b). An -buried layer is added
together with an -well ring to create an isolated p-well and
completely isolate the body of the NMOS device from the substrate. In order to further minimize the substrate injection, a
guard ring is also placed, completely enclosing the -well
ring. The width of the guard ring is chosen to maximize the
amount of isolation provided by this double ring configuration.
The number of gate fingers, which determines the size of the

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Fig. 15. (a) Power loss contribution of single-stage synchronous buck dcdc
converter and (b) variation of inductance ACR/DCR versus frequency.
Fig. 14. (a) Simplified schematic used to model the switching noise and (b)
magnitude of the frequency response of v (S ).

power MOSFET unit cell, is chosen such that effective isolation is achieved by reducing the resistance of the substrate and
-well ring contacts.
E. Integrated Filters
6 nF is an array of parThe integrated filter capacitor
allel connection of 1 pF unit size cells. The gate capacitor in
this process provides a specific capacitance of 8 fF m . Five
layers of Cu metallization are available in this process. In order
to obtain high performance inductors, a patterned electroplated
copper layer is utilized. This optional mask layer is located after
the fifth layer of Cu metallization and lies above the passivation
layer. Formed with an extra 10 m thick electroplated copper
11 nH, provides
layer, the high performance inductor,
20 at 2 GHz [9]. But the inductor conduction loss still
dominates the other power loss components of the converter.
Fig. 15(a) shows the power loss contribution of various components of the single-stage synchronous buck converter. Fig. 15(b)
shows the variation of the inductor ac resistance normalized to
its DCR as a function of frequency. The plot shows that for
switching frequencies up to 200 MHz, the use of inductor DCR
is accurate for calculating the inductor conduction losses.
IV. MEASUREMENT RESULTS
Fully integrated dcdc converters are fabricated in 0.18 m
SiGe RFBiCMOS process technology. Each single-stage
2.2 mm, and
converter occupies a silicon area of 1.5 mm

each two-stage interleaved converter occupies a silicon area

of 1.5 mm
4.5 mm. Fig. 16 shows the IC micrograph,
which consists of a monolithic synchronous buck, a two-stage
interleaved synchronous buck, a ZVS synchronous buck, and a
two-stage interleaved ZVS synchronous buck dcdc converter.
Fig. 17(a) shows the packaged part. A quad flat pack-no lead
(QFN) package is used. Multiple pads are utilized for high
current terminals in order to reduce the effect of bond-wire
resistance and inductance. Fig. 17(b) shows the evaluation
board.
Fig. 18(a) shows the measured output waveform of the
two-stage interleaved ZVS synchronous buck converter portion
1.8 V,
2.8 V, and
of the test chip at
22 . Fully integrated filter components are designed for a
nominal switching frequency of 100 MHz. As the gate drive
parasitics and propagation delays in the feedback loop increase,
the converter switching frequency is reduced. As a result,
the output voltage ripple is increased due to fixed internal
filter components. The inductor current ripple also increases,
which increases the conduction loss and reduces the converter
efficiency. Table II shows a comparison of previously reported
on-chip SM dcdc converters [19][26] with this converter
[27]. None of the reported converters have monolithic output
filters. The fully integrated converter has been designed for an
output current rating of about 200 mA and is comparable to
reported converters. Reference [28] reports a low power buck
converter, which uses an in-plane inductor built using a custom
MEMS based technique. A fully integrated boost converter has
been reported in [29].

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Fig. 16. Test chip micrograph.

Fig 18. (a) Measured output waveform of the two-stage interleaved ZVS synchronous buck converter for V = 2.8 V, V
= 1.8 V, with a resistive load of
22
. and (b) Efficiency versus load current for single-stage synchronous buck
and ZVS synchronous buck converters, for V = 2.8 V and V
= 1.8 V.
(a)

(b)

Fig. 17. Photograph of the (a) packaged prototype and (b) evaluation PCB.

TABLE II
PERFORMANCE AND ARCHITECTURE COMPARISON
OF THIS DESIGN WITH REPORTED WORK

Fig. 18(b) shows the efficiency variation of synchronous buck

and ZVS synchronous buck converters as a function of load cur1.8 V,
2.8 V. Fig. 19(a) shows similar
rent at
plots for the two-stage interleaved converters. Fig. 19(b) shows
the transient response of the two-stage interleaved ZVS syn2.8 V
chronous buck converter to a step load of 50 mA at
1.9 V. The load regulation is 3%.
and
V. CONCLUSION
This paper demonstrated a fully integrated multistage interleaved synchronous buck dcdc converter with on-chip filter inductor and capacitor in 0.18 m SiGe RFBiCMOS process technology, occupying 1.5 mm 4.5 mm. This design utilizes several innovative design approaches to increase nominal switching
frequency up to 45 MHz. High switching frequency, multiphase
interleaved operation, and fast hysteretic controller reduce the
filter inductor and capacitor sizes by two orders of magnitude
compared to state-of-the-art converters and enable a fully integrated converter. This design is the first reported fully integrated
multistage interleaved zero voltage switching synchronous buck
converter. Implementing these fully integrated converters in a

monolithic distributed power delivery approach will reduce the

interconnect delay and power loss, reduce the response time to
load transients, replace multiple supply rail distribution buses
with a single dc power bus, and isolate the supply noise coupling

2174

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

Fig. 19. (a) Efficiency vs. load current for two-stage interleaved and two-stage
interleaved ZVS synchronous buck converters, for V
2.8 V and V
1.8 V and (b) transient response of the two-stage interleaved ZVS synchronous
2.8 V and V
1.9 V.
buck converter to a step load of 50 mA at V

from noisy blocks into sensitive circuit blocks. The converter

efficiency is strongly affected by the inductor series resistance.
The use of micro-magnetic materials for the filter inductor will
increase the inductance per area, reduce the silicon area, and improve the inductor . Since the output voltage ripple is inversely
proportional to the product of the filter inductance and capacitance, increased capacitance per unit area will also reduce the
silicon die size for the fully integrated dcdc converters. Advances in process technology will improve the converter efficiency and battery run-time, and reduce the required Silicon die
area. These will complement the present advantages of the fully
integrated converters mentioned earlier, and will make them the
optimum choice for SOC or system-in-a-package (SIP) applications.
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ABEDINPOUR et al.: MULTISTAGE INTERLEAVED SYNCHRONOUS BUCK CONVERTER

Siamak Abedinpour (M99) received the B.S. and

M.S. degrees from the Iran University of Science and
Technology, Tehran and the Ph.D. degree from Arizona State University, Tempe, in 2004, all in electrical engineering.
He is currently a Senior Member of Technical
Staff with the Wireless and Mobile Systems Group,
Freescale Semiconductor, Inc., Tempe, where he is
responsible for designing highly integrated power
management ICs. In 1999, he was a summer intern
with the Power Systems Department, Lucent Technologies, Mesquite, TX, where he developed a small signal model for analysis
of a new asymmetrical half-bridge dcdc converter. In 2001, he was a summer
intern with VIROTEK L.L.C., Buffalo Grove, IL, where he designed and
implemented a circuit for blood glucose level measurements. In 2002, he was
a summer intern with the Semiconductor Product Sector of Motorola, Tempe,
where he designed and implemented a wide bandwidth dcdc converter IC
for envelope tracking of an RF PA. He is an author of 25 technical papers in
refereed international journals and conference proceedings, is an author of a
chapter in the Power Electronics Handbook (New York: Academic, 2001), and
holds two patents. His research interests include integrated high frequency
switched-mode and linear dcdc converters for RF ICs and power amplifiers
(PA).
Dr. Abedinpour has been a Session Organizer and Chair in several international conferences, including: IEEE APEC, RFIC, and ISCAS.

Bertan Bakkaloglu (M94) received the Ph.D.

degree from Oregon State University, Corvallis, in
1995.
He then joined the Mixed Signal Wireless Design
Group, Texas Instruments Incorporated, Dallas,
where he was involved with analog, RF, and
mixed-signal front-ends for wireless and wireline
communication integrated circuits. He was a Design
Leader involved with system-on-chip designs with
integrated battery management and RF, analog
baseband functionality. In 2001, he joined the
Broadband Communications Group, where he was involved with cable modem
analog front-end designs and gigabit Ethernet front-ends. In 2004, he joined
the Electrical Engineering Department, Arizona State University, Tempe, as
an Associate Professor. He holds three patents. His research interests include
RF and power amplifier (PA) supply regulators, RF synthesizers, high-speed
RF data converters, and RF built-in self-diagnostic circuits for communication
integrated circuits and antennas.
Dr. Bakkaloglu has been a Technical Program Chair for the International
Symposium on Circuits and Systems (ISCAS) and the IEEE Microwave Theory
and Techniques (MTT)/RF Integrated Circuit (RFIC) Conferences.

2175

Sayfe Kiaei (M87F07) received the Ph.D. degree

in electrical engineering from Washington State University, Pullman, in 1987.
He is currently a Professor and the Director of
the Connection One Center (NSF I/UCRC Center)
and WINTech Programs in the Ira A. Fulton School
of Engineering. From 1993 to 2001, he was a
Senior Member of Technical Staff with the Wireless
Technology Center and Broadband Operations at
Motorola where he was responsible for the development of Wireless Transceiver ICs and Digital
Subscriber Lines (DSL) transceivers. Before joining Motorola, he was an
Associate Professor at Oregon State University from 19871993 where he
taught courses and performed research in digital communications, VLSI system
design, advanced CMOS IC design, and wireless systems. He assisted in the
establishment of the Industry-University Center for the Design of Analog/Digital ICs (CDADIC) and served as a Co-Director of CDADIC for 10 years. He
has published more than 75 journal and conference papers and holds several
patents. His research interests are in wireless transceiver design, and RF and
Mixed-Signal ICs in CMOS and SiGe.
Dr. Kiaei has been an organizer on the technical program committee, and/or
chair of many conferences, including: RFIC, MTT, ISCAS, and other international conferences.