Esd - Day 2
Esd - Day 2
Esd - Day 2
www.pantechsolutions.net
About me
My Primary Expertise
Microcontroller Architecture: 8051,PIC,AVR,ARM,MSP430,PSOC3
DSP Architecture: Blackfin,C2000,C6000,21065L Sharc
FPGA: Spartan,Virtex,Cyclone
Image Processing Algorithms: Image/Scene Recognition, Machine Learning, Computer Vision, Deep Learning,
Pattern Recognition, Object Classification ,Image Retrieval, Image enhancement and denoising.
Neural Networks : SVM,RBF,BPN
Cryptography :RSA,DES,3DES,Ellipti curve,Blowfish,Diffe Hellman
Compilers: Keil,Visual DSP++,CCS, Xilinx Platform studio,ISE, Matlab, Open CV
https://www.linkedin.com/in/jeevarajan/ www.pantechsolutions.net
Announcement
● Attendance Link at End of the Session
● Minimum attendance required for an E-Certificate is 27
Days. Attendance link will be valid for 1 hrs. after the
event.
● For Internship Candidates no attendance required ,it will
be accessed from the LMS Portal.
(learn.pantechsolutions.net)
● Recorded Video Streaming for LAB classes to improve
Learning Experience
● Videos will be removed from Youtube after 3-5 Days
Day 2
Choosing the Right Processor for
Embedded System Design
Mindset Lesson for the Day
Strangest Secret in the World –Earl Nightingale
https://www.youtube.com/watch?v=uxS3txeXT7s
https://www.youtube.com/watch?v=uxS3txeXT7s
www.pantechsolutions.net
For learning hub visit learn.pantechsolutions.net
Types of Processors and
Controllers
Dallas,philips
Texas,analog
DSP
devices,Motorolla,
Renesas,freescale,
Texas,Microchip
Microprocessors/
Microcontrollers (8/16/32) SOC
QUALCOMM
ASIC BROADCOMM
GENERAL PURPOSE
CPLD/FPGA PROCESSORS INTEL
(CPU Vs GPU)
Xilinx,Altera
Lattice,Actel Intel,AMD,Nvidia
GPU TPU
Microprocessor Basic
CONTROL
ADDRESS Keyboard
BOOT Screen
CPU ROM Instruction Data UART
(program) RAM Transducers
Used at ROM Parallel
startup interface
etc
CPU
Basic Features of DSPs
○ Large memory.
➢ Precision
➢ Cost saving.
➢ Smaller size.
✓Logic blocks
✓ I/O blocks
✓Clock routing
✓Routing matrix
FPGA Architecture
✓Logic blocks
✓I/O blocks
✓Clock routing
✓Routing matrix
✓Memory
✓Multipliers /DSP blocks
✓Processor core
FPGA Technologies
DSP Vs FPGA
When to use DSP in
FPGA
✓ Higher Performance
Parallel algorithm implementation
✓ Customizable Design
Optimize for speed and cost
✓ System Integration
Less board real estate
Less chips could mean less system cost
Traditional embedded system
design using DSP
Power Supply
Ethernet Audio CLK
CLK
MAC Codec
GP I/O Interrupt
Controller
Timer
Address
Decode
Unit CPU UART L
(uP / DSP) Co-
Memory custom C
CLK Proc.
Controller IF-logic
Power Supply
Ethernet Audio CLK
CLK
MAC FPGA Codec
GP I/O Interrupt
Controller
Timer
Address
Decode
Unit CPU UART L
(uP / DSP) Co-
Memory custom C
CLK Proc.
Controller IF-logic
Power Supply
L
C
Symmetric Multiprocessing
✓ Number of Identical Processors
Asymmetric Multiprocessing
✓ Different Processors, Instruction Sets
Cost
Performance
Selection of packages
SOLDERING
IRON
DIP QFP SOIC
SOLDERING
STATION
BGA
PLCC
OVEN
Processor selection Criteria
✓ Development tools
✓ Number of I/O’s
✓ Performance
✓ Cost
✓ Operating systems
✓ Hardware tools
✓ Peripherals
✓ Power consumption
✓ Supplier reputation
Hardware Design Flow
Emulation
Cabinet design
Components Assembly
Integration
Testing
Difference between YouTube & Internship
999 Rs
Embedded System Design & IOT
Master Class(30 Days)
1. ✅ 8051 Architecture (5 Days)
2. ✅ PIC Architecture(5 Days)
3. ✅ARM7-LPC2148(5 Days)
4. ✅LPC4088 CortexM4(5 Days)
5. ✅NodeMCU / ESP32(5 Days)
999 Rs
IOT Master Class(30 Days)
999 Rs
Master class on
Embedded C Programming(30 DAYS)
999 Rs
PCB DESIGN MASTER CLASS(10 DAYS)
499 Rs
Launch offer ( 4 Courses ->100 Hrs
of Learning (I hr Per Day)
4495 Rs999 Rs
This is what you Get @ 999 Rs
130 Days of Learning
Life time Community access (Coaching in Mindset ,Technical and soft skills)
(hub.warriorsway.in)
Entrepreneurs Coaching on Warriorsway Hub
VIP Telegram Group for -30 Days Challenge – Will be active Only for 30 Days Challenge for
www.pantechsolutions.net
For learning hub visit learn.pantechsolutions.net
Q&A
Thank You