An Examination of Power Converter Architectures For Utility-Scale Hybrid Solar Photovoltaic and Battery Energy Storage Systems

©SHUTTERSTOCK.
COM/DOROTHY CHIRON
An Examination of Power
Converter Architectures for
Utility-Scale Hybrid Solar
Photovoltaic and Battery Energy
Storage Systems
THE FEATURES OF SEVERAL POWER CONVERSION ARCHITECTURES
By Mahima Gupta RECENTLY, THE FALLING COSTS OF PHOTOVOLTAIC (PV)

and battery storage (BS) technologies have raised interest in
the creation of hybrid PV+BS power plants. Together with
Digital Object Identifier 10.1109/MIAS.2022.3214016
increasing energy storage capacity by storing clipped ener-
Date of current version: 14 December 2022 gy, hybrid plants broaden a power plant’s grid services
12 IEEE Industry Applications Magazine MARCH/APRIL 2023 1077-2618/22©2022IEEE
Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE SANTA CATARINA. Downloaded on February 09,2023 at 16:22:52 UTC from IEEE Xplore. Restrictions apply.
by featuring fast dispatch flexibility [13]. Moreover, power architectures
and voltage-ampere reactive support. are expected to evolve over time
Although many proposed PV plants A utility-scale PV based on future trends.
are being developed with colocated Currently, hybrid PV+BS power
batteries, the dominant architecture power plant can plants can be broadly classified as
of utility-scale PV+BS power plants is comprise several PV either ac grid- or converter-coupled
uncertain. Moreover, power architec- systems based on their point of com-
tures are expected to evolve over time modules that connect mon coupling. These systems do not
based on future trends. The primary share any components and the stor-
goal of this article is to critically exam- in series and/or in age systems can act independent of
ine and compare several dc–dc and parallel to form PV the PV system. From the perspective
dc–ac power converter architectures of power converter architectures, ac
that are suitable candidates for hybrid strings or PV arrays. grid-coupled systems are expected to
PV+BS power plants. In particular, the have similar characteristics to inde-
article presents characteristics of sev- pendently operated PV and BS plants
eral power conversion architectures [13]. On the other hand, in converter-
from the point of view of power semiconductor require- coupled systems, PVs and BSs share the dc–ac grid-con-
ments, efficiency, reactive component requirements, modu- nected inverter. This article focuses on converter-coupled
larity, control complexity, and so forth. Detailed analytical configurations for utility-scale hybrid PV+BS power plants
models are utilized, along with a benchmark design exam- because of their distinct characteristics and expected
ple to present a comparative evaluation of the alternatives advantages. Further, the design of converter-coupled
for performing engineering tradeoff studies. configurations are more complex and integrated due to
the sharing of electronic and control systems and hence
Introduction requires detailed studies.
The increasing share of intermittent sources of energy Although the growth of hybrid plants is driven by
such as solar and wind intensifies the need for energy significant declines in project costs due to cost savings by
storage technologies such as batteries and pumped- sharing equipment, cutting interconnection, and permit-
storage hydropower. Although pumped-storage facili- ting costs and leveraging federal tax credits [14], there are
ties account for nearly 92% of the U.S. energy storage several other technical advantages as well. First, convert-
capacity [1], battery energy storage systems are growing er-coupled systems permit the energy storage of other-
quickly [2], [3]. This is due to their high energy densi- wise clipped energy that occurs when the inverter loading
ties and smaller size and weight, which leads to added ratio (ILR) exceeds one. Typically, the ILR varies between
flexibility and ease of installation [4], [5]. More recently, one and two and is assumed to be 1.3 in this study, which
the falling costs of PV and BS technologies have raised is equal to the average value for utility-scale PV systems
interest in the creation of hybrid PV+BS power plants. [13]. Further, as the batteries are directly charged from the
These technologies are enabled by the development of PV system, converter-coupled systems have higher charg-
advanced power electronics with unprecedented func- ing efficiency due to a lower number of power electronic
tionality, efficiency, reliability, and power density critical stages. Finally, independent of the point of coupling,
for an electrified world economy. According to some hybridization of the PV power plants with BSs broaden
estimates, 80% of all U.S. electricity could pass through the plant’s grid services, including fast dispatch flexibility,
power electronics devices by 2030 [6]. Further, continu- frequency regulation, and voltage-ampere reactive sup-
ous advancements in control architectures are critical to port. In summary, PV+BS power plants have the potential
support electrified systems that present different and to offer 1) energy savings by capturing clipped energy
challenging characteristics as compared to conventional from PV panels, 2) higher round-trip efficiency during
electrical generators [7], [8], [9]. battery charging times, and 3) improved dispatch flex-
Most of the utility-scale battery energy storage systems ibility, making them more attractive for grid operations. It
that are expected to come online in the United States must be noted that converter-coupled systems also suffer
from 2021 to 2023 are to be colocated with PV power from challenges compared to ac grid-coupled systems.
plants, a change in trends from recent years [10], [11]. Due to the highly integrated structure in converter-cou-
Further, considering the interconnection queues in the pled systems, they are expected to have a higher struc-
United States, 34% of the proposed PV plants are being tural balance of systems due to distributed and smaller
developed with colocated batteries [11]. It may, however, battery packs, in comparison to a larger centralized bat-
be noted that the dominant architecture for the proposed tery pack in colocated ac systems [13].
and future utility-scale PV+BS power plants is highly The primary goal of this article is to critically exam-
uncertain. Most of the interconnection queue data do not ine and compare several dc–dc and dc–ac power con-
include information about the inverter characteristics [12], verter architectures and their control strategies that can
M ARCH/AP RI L 2023 IEEE Industry Applications Magazine 13

enable converter-coupled hybrid PV+BS power plants. ●● The hybrid power-transfer capability of the PV+BS
The results from this article are geared toward support- plant to the ac grid is Pinv . Hence, the dc–ac conversion
ing the current and future planned studies of hybrid PV system is rated for Pinv, which is also noted in Figure 1.
and battery storage power plants from the point of view Here, Pinv refers to the power rating of the inverter.
of converter designs. The structure of the article is as ●● The ILR is assumed to be 1.3, which is equal to the
follows: The “Block Diagram of PV+BS Power Plants” average value for utility-scale PV systems. Hence,
section presents simplified block diagrams of the con- the PV power plant’s rated power is Ppv = 1.3 # Pinv .
figurations of hybrid PV+BS systems; the “DC-Stacked The BS-rated power is assumed to be Pbatt. Typically,
Architectures” and “Cascaded Bridge Architectures” Pbatt . 0.5 # Pinv in today’s hybrid power plants [13]. In
sections examine dc-stacked and modular power con- summary, the PV and the battery converter are rated
verter architectures in terms of power semiconductor for Ppv and Pbatt, respectively.
switch and energy storage element ratings, respectively; As hybrid PV+BS power plants become common, the
the “Control Strategies for Hybrid PV+BS Plants” sec- average ILR is expected to increase [13] as more clipped
tion discusses the control architectures suitable for the energy can be stored in the BS. Analytical results from
topologies under consideration; the “Double-Star Config- the article will still hold true for many purposes, and the
uration” section briefly discusses double-star design con- tools provided in the article can be used for extended
figurations for hybrid power configurations; the “Results designs. In the remainder of the article, the following
and Discussion” section presents detailed comparative notations are commonly used across all the considered
results for a design example; and finally, the “Conclu- power converter architectures: fS represents the switching
sion” section summarizes the article. frequency; TS = 1/fS represents the switching cycle; Vac,
I ac represent the root-mean-square (RMS) values of the ac
Block Diagram of PV+BS Power Plants grid-phase voltages and currents; Vt ac, Itac represent peak
Figure 1 illustrates the simplified block diagram of a values of the ac grid voltages and currents, respectively;
converter-coupled hybrid PV+BS power plant. The PV and fac, Tac represent the ac grid frequency and time period,
BS power plants share a common dc–ac grid-connected respectively; VA represents the voltage × current ratings
inverter that connects the two dc systems (i.e., the PV and of the semiconductor switches; and subscript p and b indi-
the BS) to the ac grid. The two dc systems interface to cate variables for PV and BS, respectively.
each other, either at the dc or ac node. Figure 1(a) and (b)
illustrates block diagrams for dc- and ac-coupled systems, DC-Stacked Architectures
respectively. Based on the coupling-node configuration,
galvanic isolation between the dc sources and the ac grid Topology and Operation
may be at the ac grid or at the converter level, which is Three-phase two-level voltage source converters (VSCs)
discussed later. have traditionally been ubiquitous and are the workhorse
The following assumptions about hybrid power plant topology in many applications such as traction inverters,
systems have been made while examining several power industrial motor drive systems, uninterruptible power
converter architectures. supplies, and so on [15], [16]. In fact, two-level VSCs have
PV System PV System
(ILR × Pinv) (ILR × Pinv)
dc–dc dc–ac
(ILR × Pinv) (ILR × Pinv)
dc–dc dc–ac
BS (Pbatt) BS (Pbatt)
(Pbatt) (Pbatt)
dc–ac ac–ac
ac Grid (Pinv) ac Grid
(Pinv)
(a) (b)
FIGURE 1. A block diagram of converter-coupled PV and BS power plants with (a) a dc-coupled configuration and (b) an ac-coupled
configuration. ILR: inverter loading ratio.
14 IEEE Industry Applications Magazine MARCH/APRIL 2023
dominated industrial-scale grid-con- of the following: 1) a multistring, 2)
nected energy storage projects [17], string, or 3) module distribution. In
[18]. Further, VSCs offer an architec- To provide galvanic the case of large utility-scale installa-
tural solution for hybrid utility-scale tions (beyond 100 kW), the prospect
power plants. The connection of isolation, the of a per-module power converter is
low-voltage battery and PV systems cascaded bridge limited [21], [23]. Large-scale installa-
to the medium-voltage utility grid is tions feature improved module-level
enabled by 1) series connection of architecture can uniformity, in contrast to residential
several low-voltage systems and 2) or commercial rooftop installations.
utilization of a low-frequency step-up feature a low- Further, the additional part count,
transformer, which may be a solid- frequency transformer monitoring and installation time,
state-based transformer for increased and cost-effectiveness are disadvan-
efficiency and power density. at the ac grid or tages to per-module power electron-
Figure 2 illustrates the circuit ics in large installations. Hence, this
schematic for the solution. Although module level. article assumes the distribution of
dc batteries may be directly con- dc–dc converters at the string level
nected to the dc link, PV systems for PV systems.
are typically cascaded via dc–dc Several strings interface to the dc
converters featuring distributed maximum power point link using dc–dc converters while implementing MPPT
tracking (MPPT) algorithms. In the case of hybrid algorithms to maximize energy yield. String-level dc–dc
PV+BS systems, dc–dc converters that interface each of converter systems, which integrate into the utility-scale
the dc systems with each other and the ac grid play a grid, can feature a boost or buck-boost converter configu-
distinct role in the control of power flow. As the com- ration [22], [24]. Similarly, based on the voltage class of
mon point of coupling between the PV, BS, and the ac the battery energy storage, dc–dc converters can feature
grid converters is dc, this topology is a dc-coupled con- either a boost or buck-boost configuration, as detailed
figuration in Figure 1(a). next. Due to the presence of a low-frequency transformer
between the ac converter and ac grid, an isolated dc–dc
Decentralized Converter Architecture Approach converter configuration may not be necessary. On the
DC energy sources such as PV panels and batteries other hand, ac-coupled PV+BS systems will typically
are all series and/or parallel connections of a basic feature transformer-coupled converters, as discussed in
cell. These cells operate at a low voltage, ranging from the “Cascaded Bridge Architectures” section. This article
less than 1 to 4 V [19], [20]. These low-voltage systems considers nonisolated dc–dc converters for dc-stacked
do not interface well with higher-voltage systems and architectures.
hence, several PV or battery cells are connected in The remaining sections discuss voltage × current (VA)
series to form a PV module or a BS. ratings of the semiconductor components and the energy
Considering PV module technologies, PV modules storage ratings of the inductors and capacitors that togeth-
can be categorized into three categories: 1) high-voltage er play a key role in determining the efficiency, power
(. 240 V) amorphous silicon modules, 2) medium- density, cost, and reliability of the architectures.
voltage (. 60 V) amorphous silicon modules, and 3) low-
voltage multicrystalline silicon modules (. 30 V) [21]. VA Ratings of Semiconductor Components
A utility-scale PV power plant can comprise several PV The VA ratings that are imposed by the converter design
modules that connect in series and/or in parallel to form and operation assist in the selection of power semicon-
PV strings or PV arrays. Traditional PV power plants ductor devices for the converter design. Here, the VA rat-
feature a central dc–dc converter that cascades to a grid- ing calculation incorporates the peak voltage stresses and
connected dc–ac inverter for power transport. The dc–dc RMS current values on the devices.
converter implements the MPPT algorithm to maximize
energy yield. In contrast to central dc–dc converters,
distributed dc–dc converters are growing quickly due to +
several advantages, including energy-yield improvements SA+ SB+ SC+
during shading, module mismatch, elimination of single- LVAc MVAc
Vdc
point failure, and added monitoring and diagnostics.
PV BS 1:t
Literature studies indicate that an energy-yield gain of SA– SB– SC–
4–12% can be obtained for distributed systems over cen- –
tral inverter systems [21], [22], [23]. The distribution of
dc–dc converters, along with the MPPT controllers asso- FIGURE 2. The converter topology of a three-phase two-level VSC with
ciated with them for dc-stacked architectures can be one cascaded BSs, and cascaded PV systems connected to the dc link.

DC–ac Grid Inverter energy storage elements (which is discussed next). Note
DC-link voltage utilization is determined by modulation that the effect of the transformer turns ratio does not
strategies [15]. Hence, selection of the modulation strategy feature explicitly in the final VA calculation output as the
plays a role in determining the final VA ratings of semi- transformer operation is considered lossless.
conductor switches. The effect of the modulation strategy
is characterized in the article using a duty-ratio factor d m, DC–DC Converter
where subscript m refers to the term modulation. The set In theory, any unidirectional and bidirectional dc–dc
of equations (1) characterize the VA rating of the solid- converter can be used for integration of the PV systems
state switches S k+ and S k-, where k = A, B, C. and the BSs, respectively. However, as the two dc sys-
tems interface with the utility-scale ac grid, only boost
V 1 - SW = Vdc = 1 Vac or buck-boost configurations are considered in the
t dm article. Availability of the boost mode of operation helps
I 1 - SW = t # I ac reduce the number of series-connected PV modules or
2
n=6 BSs, thus potentially extending life expectancy and mis-
2 Pinv match issues [25], [26].
VA = (1)
dm Several power conversion topologies are proposed in
the literature. This article examines the following configu-
where V 1 - SW and I 1 - SW represent the peak voltage and rations for a detailed analysis: 1) a simple-boost converter,
RMS current ratings, respectively, imposed on a single 2) buck-boost converter, 3) single-ended primary-inductor
switch; n represents the total number of switches; Pinv converter (SEPIC), and 4) Ćuk converter. Figure 3 illus-
represents the total power throughput from dc to the trates circuit schematics of the boost and SEPIC topolo-
three-phase ac system (and is equal to the dc–ac inverter gies. Equation (3) characterizes the ratio of the input
rating in Figure 1); and t represents the low-frequency to the output dc voltage ^V p/b /Vdch in terms of the duty
transformer turns ratio. Based on the modulation strategy, ratios, where V p/b refers to the PV/BS voltage, and VDC
the factor d m can be determined. Equation set (2) docu- refers to the dc-link voltage.
ments the advantage of using space-vector modulation
D l , Boost
= * D l , Buck boost, SEPIC, Cl uk(3)
(SVM) over sine-pulsewidth modulation (PWM) in reduc- V p/b

ing the VA ratings of the switches. Vdc D
Z
] # 1 , Sine - PWM and D refers to the duty ratio of the switches, as anno-
V ] 2 2
d m = 1 ac =[ 1 , SVM .(2) tated in Figure 3, and D l = 1 - D refers to the comple-
t Vdc ]] #
6 mentary duty ratio. Using the duty-ratio expressions,
\ the per-unitized VA ratings of the power semiconductor
The utilization of SVM results in higher link voltage switches can be derived for the four dc–dc converters,
utilization, which also results in optimizing the size of which are also summarized in (4).
Z
] D + D l , Boost
] Dl
VA per unit (p.u.) = [ D + D l .
]
] , Buck boost, SEPIC, l
Cuk
DD l
D′ \
D′ (4)
Vdc Vdc It may be noted that the VA rating is a function of

PV Vp D PV Vp D the operating point of the converter and may vary sig-
nificantly as a function of the voltage-transfer ratio
^V p/b /Vdc h. Figure 4 plots the per-unitized VA rating of
the switching devices as a function of the voltage-transfer
ratio ^V p/b /Vdch for the simple-boost converter and the
three-buck/boost topologies under discussion.
Although a simple-boost converter features the lowest
B Vb B Vb VA rating for the power semiconductor devices, it will not
offer the buck mode of operation. In contrast, the other
(a) (b) converters offer the buck mode of operation with a device
VA rating as a tradeoff. Hence, unless required by the PV,
FIGURE 3. Common dc–dc converter topologies used to control the battery, or dc-link specifications, boost configuration may
power flow between PV modules, batteries, and the dc–ac grid-tied be an ideal choice as buck-boost configurations suffer
inverter. (a) A boost configuration and (b) buck-boost configuration. from additional device stresses.
Battery/PV Energy Storage Ratings Efficiency Calculations
The article presents analytical models to quantify and
DC–AC Grid Inverter compare efficiency of the power electronic architectures
To filter the switching action of the six semiconductor under discussion by characterizing the RMS and aver-
switches, the topology typically features a dc-link capaci- age current calculations in the semiconductor switching
tor and an input inductor to smoothen the dc-link voltage devices, transformers, and the filtering and energy stor-
and input current, respectively. Equation (5) character- age elements. Table 2 summarizes the current expres-
izes the capacitor size, which is a function of the current sions for loss calculations for the dc–dc conversion stage
magnitude, modulation strategy, and the allowed ripple in terms of the duty ratios. For switching-loss calcula-
voltage at the dc link ^rVdch. tions, the switching energies provided by the data sheets
for the reference operating conditions are employed
Itac # dt 0 - dc TS
C link . (5) (characterized by k SW in the equations and defined in
rVdc
“Loss Calculations”). The switching-loss equation per
where dt 0 - dc represents the maximum value of the dc- switch for dc–dc converters is given by (7).
side zero-state duty ratio when only the peak ac current
^ Itac h flows into the capacitor. Due to the buck mode of Psw = '
k sw Vdc I p/b, Boost
.(7)
k sw V p/b + dc I p/b + dc, Buck boost, SEPIC, Cl uk
operation from the dc to the ac side, ac-side currents
will be of higher magnitude. Hence, the capacitor ripple
calculation features the peak value of the ac current
during the freewheeling duration of the dc current 15
when the net capacitor current is not offset by the dc
current. Note that the dc- and ac-side switches may be
12
operating at a different switching frequency and may
not be synchronized.
Similarly, (6) characterizes the net size of the filter 9
VA (p.u.)
inductance to limit the ripple in the dc current ^rI dch.

6
rVdc # dt 0 - ac TS
L Batt = (6)
4rI dc
3
where dt 0 - ac represents the maximum value of the ac- Boost
side zero-state duty ratio when only the peak dc current Buck/Boost
flows into the capacitor. In summary, it can be observed 0
0 0.5 1 1.5 2 2.5
that in the case of dc-stacked topologies, energy storage
Vp/b
elements are sized to filter-switching harmonics, which Voltage Transfer Ratio
Vdc
is in contrast to some power architectures that require
low-frequency filtering, as discussed later. These energy
storage elements may be incorporated within the dc–dc FIGURE 4. A plot of the per-unitized VA rating of the total power
semiconductor devices as a function of the voltage-transfer ratio.
converter stage. The “Results and Discussion” section
demonstrates the performance of such dc-stacked topol-
ogies using a design example.
Table 1. The sizing of filtering elements
DC–dc Converter in dc–dc converters
Table 1 tabulates filter-sizing equations in terms of the
duty ratios (D or D l = 1 - D), switching frequency ( fS), Topology PV/BS DC Link Intermediate
per-unit ripple (r), and the PV/BS or the dc-side imped-
Boost DZ p/b C= D —
ance (Z x = Vx /I x where x = p, b, or dc). Note that the L= rfS Z dc
rfS
subscript p/b in the table refers to the dc–dc converter
Buck boost C = Dl C= D DV p/b
variables for the PV and the BS system and subscript rfS Z p/b rfS Z dc L=
rfS I p/b + dc
dc refers to the dc current at the Vdc terminals. Unlike
SEPIC DZ p/b C= D DI dc
the other buck/boost converters, the output voltage L= C=
rfS rfS Z dc rfS V p/b
polarity of the input and output sides remain the same
L = D Z dc
l
in an SEPIC converter. On the other hand, a Ćuk con- rfS
verter has nonpulsating currents, both at the input
Ćuk DI dc
DZ p/b L = D Z dc
l
and output. Together with minimal VA ratings, a boost L= C=
rfS rfS rfS V p/b + dc
converter features the lowest energy storage and filter-
where V p/b + DC = V p/b + Vdc and I p/b + DC = I p/b + I dc
ing requirements.

The ac inverter conduction losses are given by (8) and (9) illustrates the circuit topology featuring p PV systems and
for uniformly distributed zero vectors. b BSs. For simplicity, p = b. The several dc systems con-
nect to the ac grid via several nonisolated dc–dc and dc–
Itac 8 1 + M cos zB, transistor
I avg = *
2r 8 ac converters and enable voltage compatibility via series
(8)
Itac 8 1 - M cos zB, diode connection of smaller converters. Although the ac grid
2r 8 transformer may provide a step-up function, the primary
Z
]] Itac 1 + M cos z , transistor purpose is to provide galvanic isolation between the dc
8 3r
I RMS = [ 1 - M cos z , diode (9) sources and the ac grid. As the common point of cou-
t
] I ac
\ 8 3 r pling between the PV, BS, and ac grid converters is dc,
Psw = $ k sw Vdc 2 Itac, per inverter leg(10) this topology is a dc-coupled configuration in Figure 1(a).
r
The next few sections characterize the ratings of the
where M represents the modulation index, and z repre- semiconductor components and energy storage elements
sents the phase angle. The equations hold for sine-PWM within this modular CBC.
and SVM with reasonable approximations [27]. Finally,
the switching-loss equation per one leg for dc–ac con- VA Ratings of Semiconductor Components
verters is given by (10), where the dc output-equivalent The dc–dc converter topologies discussed in the “DC–dc
current is the average of one-half sine wave. Converter” section can be utilized to interface the PV and
the BS systems to the dc point of coupling. The following
Cascaded Bridge Architectures analysis assumes a full-bridge (FB) converter for dc–ac
In contrast to dc-stacked topologies wherein the dc sourc- conversion to the grid and is the main focus of this sec-
es/loads are connected in series and interfaced to the ac tion. Similar to a dc-stacked topology, the total VA rating
grid using a single inverter, modular topologies feature is a function of the modulation strategy. However, in con-
smaller inverters that interface the several dc sources/ trast, the VA ratings of a single switch is scaled based on
loads to the ac grid. Several converters cascade in series the level of modularity represented by p for PV systems
to interface low-voltage dc sources to the ac grid. To and b for BSs. The set of equations (11) that characterize
provide galvanic isolation, the cascaded bridge architec- per-switch and total VA ratings for the topology are
ture can feature a low-frequency transformer at the ac
Z Vac
grid or module level. The “Cascaded Bridge Topology ]] , PV
1 - SW 2 # p # dm
With a Low-Frequency Grid Transformer,” “Triple-Active V =[
] Vac
Bridge With a Three-Winding High-Frequency Transform- , BS
\ 2 # b # dm
er Topology,” and “TAB With a Five-Winding High-Fre- 1 - SW I ac
I =
quency Transformer Topology” sections present detailed 2
examinations of the two approaches. n SW = 4 # 3
2 Pinv
VA SW = (11)
dm
Cascaded Bridge Topology With a Low-Frequency
Grid Transformer where the modulation factor d m is defined similar to the
This section benchmarks the cascaded bridge converter dc-stacked topologies discussed in (2) in the “DC–dc
(CBC) topology suitable for hybrid power plants. Figure 5 Converter” section, and the factor of two represents the
Table 2. RMS and average current expressions for dc–dc converters useful for loss calculations
I RMS Iavg
Filtering Energy Storage
Topology Switch 1 Switch 2 L C L C Switch 1 Switch 2
Boost D I p/b Dl I p/b I p/b D Dl I p/b — — DI p/b DlI p/b
Buck boost D I p/b + dc Dl I p/b + dc — Dl I p/b + dc — DI p/b + dc DlI p/b + dc
I p/b
D
SEPIC D I p/b + dc Dl I p/b + dc I p/b Dl IDC Dl DI p/b + dc DlI p/b + dc
I p/b I p/b
D D
Ćuk D I p/b + dc Dl I p/b + dc I p/b, IDC — — Dl DI p/b + dc DlI p/b + dc

I p/b
D
Loss Calculations
The transistor and diode conduction losses can be calculated where E onT , E offT , and E rr represent the energy loss during
using an approximation with a series connection of the dc transistor turn on, transistor turn off, and diode reverse-
voltage drop representing the on-state voltage drop (v on) recovery event, respectively. The switching energy loss values
and the on-state resistance (ron), as illustrated in (S1). are provided in the manufacturer’s data sheet at reference
current (I R) and voltage (VR) operating conditions. Hence,
Pc = v on I avg + ron I 2rms(S1) the switching energies are normalized at VR, I R to derive the
switching losses under the operating conditions imposed by
where v on is the on-state collector-emitter voltage (v ce),
the circuit operation Vop, I op.
drain-source voltage (v ds), or forward voltage (v f ), in the
case of IGBTs, MOSFETs, or diodes, respectively. The switching Converter Parameter Details for
loss is characterized by the switching-loss energy associated Efficiency Calculations
Table S1 lists the converter parameters along with
with each switching event and is typically assumed to be
selected device parameters for the design example under
proportional to the blocking voltage and the conducting
consideration, with a power level of Ppv = 1.3 per unit (p.u.),
current at the instant of switching event. Equation (S2)
P batt = 0.3 p.u., and Pac = 1p.u., as discussed in the “Results
characterizes the switching loss associated with one half
and Discussion” section. The results obtained from the
bridge during a switching cycle.
simulations and the analytical equations are listed. Due to
(E + E offT + E rrD) the similarity between three-winding triple-active bridge
Psw = fSW onT Vop I op(S2) (3-W TAB) and five-winding (5-W) TAB designs, the 5-W TAB
14444442V44444
R IR
43
k sw is excluded from the table.
Table S1. Converter design details for efficiency calculations

Simulation Analytical Loss Simulation Analytical Loss
Results results Parameters Results results Parameters
DC–ac Converter Quantity: Six
DC-Stacked With Boost dc–dc (Per Converter)
[T:] vce = 0.6 V,
Photovoltaic (PV) dc–dc Converter Quantity: One rdson = 0.31 mΩ;
vce = 0.6 V, Eon = 0.65 J,
rms(IT ) 1.56 kA 1.57 kA
rdson = 0.22 mΩ; Eoff = 0.8 J at
avg(IT ) 0.9 kA 0.9 kA
rms(IT ) 3.07 kA 3.08 kA Eon = 0.9 J, VR = 600 V,
peak(IT ) 3.45 kA 3.34 kA
avg(IT ) 1.94 kA 1.95 kA Eoff =1.5 J at IR = 3.2 kA [D:]
rms(ID ) 0.58 kA 0.58 kA
peak(IT ) 4.9 kA 4.88 kA VR = 600 V, vf = 0.7 V,
avg(ID ) 0.16 kA 0.16 kA
IR = 4.8 kA [52] rdon = 0.26 mΩ;
peak(ID ) 3.45 kA 3.34 kA
Err = 0.21 J at
1.5 in vf =1.32 V, VR = 600 V,
rdon = 0.268 mΩ; IR = 3.2 kA [55]
rms(ID ) 3.76 kA 3.78 kA Err = 0.1 J at
avg(ID ) 2.91 kA 2.92 kA VR = 400 V,
peak(ID ) 4.9 kA 4.88 kA IR = 1.5 kA, Cascaded Bridge With Boost dc–dc and Full-Bridge
di/dt = 100 dc–ac (Per Module)
A/μs [53] PV dc–dc Converter Quantity: Three
Battery dc–dc Converter Quantity: One vce = 0.7 V,
[T:] vce = 0.6 V, rdson = 2.2 mΩ;
rms(IT ) 0.58 kA 0.59 kA
rdson = 0.41 mΩ; Eon = 35 mJ,
avg(IT ) 0.37 kA 0.37 kA
Eon = 0.33 J, Eoff = 80 mJ at
rms(IT ) 0.84 kA 0.84 kA peak(IT ) 0.94 kA 0.93 kA
Eoff = 0.4 J at VR = 600 V,
avg(IT ) 0.68 kA 0.68 kA IR = 0.8 kA [56]
VR = 600 V,
IR = 1.8 kA [D:] vf = 1.53 V,
rms(ID ) 0.61 kA 0.61 kA
vf = 0.6 V, rdon = 0.55 mΩ;
avg(ID ) 0.36 kA 0.36 kA rms(ID ) 0.71 kA 0.72 kA
rdon = 0.3 mΩ; Err = 80 mJ at
peak(ID ) 1.07 kA 1.07 kA avg(ID ) 0.55 kA 0.56 kA
Err = 0.15 J at VR = 400 V,
peak(ID ) 0.94 kA 0.93 kA IR = 1 kA, di/dt =
VR = 600 V,
IR = 1.8 kA [54] 100 A/μs [57]
(Continued )

Table S1. Converter design details for efficiency calculations (Continued )
Simulation Analytical Loss Simulation Analytical Loss
Results results Parameters Results results Parameters
Battery dc–dc Converter Quantity: Three Battery dc–dc Converter Quantity: 12
[T:] vce = 0.6 V,
rdson = 4.7 mΩ; rms(IT ) 11 A 13 A
Eon = 25 mJ, [T:] vce = 0.6 V,
rms(IT ) 0.16 kA 0.16 kA avg(IT ) 0.9 A 1.2 A
Eoff =15 mJ at rdson = 4.7 mΩ;
avg(IT ) 0.13 kA 0.13 kA peak(IT ) 0.2 kA 0.2 kA
VR = 600 V, [D:] vf = 0.7 V,
peak(IT ) 0.21 kA 0.2 kA rms(ID ) 0.14 kA 0.14 kA
IR = 0.3 kA [D:] rdon = 2.2 mΩ;
rms(ID ) 0.12 kA 0.12 kA avg(ID ) 99 A 97 A
vf = 0.7 V, [58]
avg(ID ) 69 A 69 A peak(ID ) 0.2 kA 0.2 kA
rdon = 2.2 mΩ;
peak(ID ) 0.21 kA 0.2 kA
Err =15 mJ at
VR = 600 V, AC–dc Converter (Bridge 2) Quantity: 12
IR = 0.3 kA [58]
rms(IT ) 52 A 59 A
DC–ac Converter Quantity: 12 avg(IT ) 8A 9A [T:] vce = 0.5 V,
peak(IT ) 0.51 kA 0.53 kA rdson =1.2 mΩ;
[T:] vce = 0.5 V,
rms(ID ) 0.33 kA 0.34 kA [D:] vf = 0.85 V,
rdson =1.2 mΩ;
avg(ID ) 0.22 kA 0.23 kA rdon =1 mΩ; [59]
Eon = 50 mJ,
rms(IT ) 0.49 kA 0.49 kA peak(ID ) 0.51 kA 0.53 kA
Eoff = 90 mJ at
avg(IT ) 0.26 kA 0.28 kA
VR = 600 V,
IR = 0.6 kA [D:] DC–ac Converter (Bridge 3) Quantity: 12
rms(ID ) 0.21 kA 0.21 kA
vf = 0.85 V,
avg(ID ) 62 A 63 kA
rdon =1 mΩ;
peak(ID ) 1.1 kA 1.1 kA [T:] vce = 0.5 V,
Err = 52 mJ at
VR = 600 V, rdson =1.2 mΩ;
IR = 0.6 kA [59] Eon = 50 mJ,
rms(IT ) 0.49 kA 0.49 kA Eoff = 90 mJ at
3-W TAB (Per Module) avg(IT ) 0.28 kA 0.28 kA VR = 600 V,
peak(IT ) 1.1 kA 1.1 kA IR = 0.6 kA [D:]
PV dc–dc Converter Quantity: 12 rms(ID ) 0.21 kA 0.21 kA vf = 0.85 V,
avg(ID ) 63 A 63 A rdon =1 mΩ;
rms(IT ) 0.75 kA 0.74 kA Err = 52 mJ at
[T:] vce = 0.7 V,
avg(IT ) 0.49 kA 0.49 kA VR = 600 V,
rdson = 2.2 mΩ;
peak(IT ) 1.3 kA 1.2 kA IR = 0.6 kA [59]
[D:] vf =1.53 V,
rms(ID ) 0.14 kA 0.14 kA
rdon = 0.55 mΩ;
avg(ID ) 27 A 27 A
[56] rms: root mean square; avg: average; 3-W TAB: three-winding triple-active
peak(ID ) 1.3 kA 1.2 kA bridge.
FB configuration. It is noted that the voltage scaling at rent value, power cycle frequency, and allowed ripple at
the PV or BSs considers the assumptions discussed in the the dc link ^rVdch.
“Block Diagram of PV+BS Power Plants” section. The PV
and the BSs can interface to the modular dc–ac convert- C link = 2 I dc Tac 1 (12)
r 4 rVdc
ers by employing any of the nonisolated dc–dc topologies
discussed in the “DC–dc Converter” section. The “Results where the factor of four in the denominator accounts for a
and Discussion” section presents a design example that second-harmonic ripple from the FB dc–ac converter, and
compares the dc-stacked architectures with the cascaded (2/r) I dc represents the average value of the mean current
bridge architecture. flowing into the dc–ac converter. In the case of a cas-
caded boost converter at the dc link, I dc = (2/r) I dc (1 - D).
Battery/PV Energy Storage Ratings The switching frequency is considered high in compari-
It may be observed that the modular dc–ac converters in son to the ac power frequency, and hence, the ripple due
Figure 5 have to be sized to filter single-phase ac power to the switching action is ignored. Similarly, (13) charac-
requirements. This is in contrast to dc-stacked topologies, terizes the net size of a series filter inductance to limit the
which only need to filter high switching-frequency com- ripple current from the dc source ^rI dch.
ponents. Equation (12) characterizes the capacitor size at
L s = 2 rVdc Tac 1 (13)
the module level, which is now a function of the ac cur- r 4 rI dc
where the factor of 2/r accounts for the average value VA ratings for the cascaded 3-W TAB topology in a step-
of the ripple voltage across the inductor. In summary, by-step manner, as detailed further. Figure 7 illustrates a
energy storage elements will be bulkier in the case of the single 3-W TAB module fed from a PV system and a BS.
cascaded bridge architecture as compared to dc-stacked Here, the two dc systems are integrated into a single-phase
topologies due to the design archi-
tecture. Together with the dc-link MVAc MVAc
capacitor, the filtering elements at
the dc source will be sized to limit
the single-phase ac ripple from the
dc–ac inverter, as illustrated in (13). PV1A PV1B PVC
1
B1A B1B B1C

Efficiency Calculations
The analytical equations presented
PVpA PVpB PVpC
in the “Efficiency Calculations” sec-
tion can be extended and utilized for
BbA BbB BbC
loss calculations in the dc–dc and
dc–ac converters for CBCs (7)–(10).
The “Results and Discussion” section FIGURE 5. The converter topology of a three-phase cascaded half- (or full-) bridge converter
presents comparative results for the with both BSs and PV systems connected to modular dc–ac converters.
design example under discussion.
MVAc
Triple-Active Bridge With a
Three-Winding High-Frequency
Transformer Topology PV1A PV1B PVC1
This section examines a modular
triple-active bridge (TAB) converter B1A B1B B1C
that connects the dc sources to the
ac grid via a dc–ac–ac converter and
PVpA PVpB PVpC
a high-frequency transformer, as
illustrated in Figure 6. Several TABs BbA BbB BbC
connect in series to form a modular
converter capable of connecting sev-
eral dc systems to the utility-scale ac FIGURE 6. The converter topology of a three-phase cascaded TAB converter with both BSs and
PV systems connected to modular dc–ac–ac converters via a 3-W transformer.
grid. The PV systems and the BSs
interface to the converter via a high-
frequency transformer [28], [29].
IP0
In contrast to dc-stacked topologies IL-pv
or a CBC, a three-winding (3-W) TAB IP 1
features a high-frequency transformer Idc-pv IL-pv –IP0 –IP 1
as part of the design architecture and
Vp t 0 tϕ
provides galvanic isolation between PV Lp
the PV systems, BSs, and the utility- CPV
scale ac grid at the module level.
np : n : 1
As the common point of coupling
between the PV, BS, and the ac grid IL
Bridge 1
converters is ac, this topology is an ac- Vdc
ac
coupled configuration in Figure 1(b).
Idc-batt Cdc
The next few sections characterize the IL-batt
ratings of the semiconductor compo- V
nents and energy storage elements B
within the modular TAB converters. Cbatt Bridge 2 Bridge 3
VA Ratings of Semiconductor
Components
This section presents a systematic FIGURE 7. Circuit schematic of a single module of TAB converter with both BSs and PV systems
approach for the derivation of the connected to modular dc–ac–ac converters via a 3-W transformer.

ac output via a 3-W high-frequency transformer, with a ^ x = pv, batt, inv h. It may be observed that in comparison
turns ratio of n p : n b : 1 where n p and n b represent the to dc-stacked topologies and a nonisolated CBC, a 3-W
turns ratio of the PV and battery converters, respectively. TAB is expected to have a higher switch VA rating. The
To minimize the reactive power between the dc and ac “Results and Discussion” section presents a design exam-
sides, the input voltage must be approximately equal to ple that compares the several architectures.
the output voltage after accounting for the turns ratio of
the transformer. In other words, V p /n p . Vb /n b . Vdc [30]. Battery/PV/Intermediate Energy Storage Ratings
Equation set (14) characterizes the per-switch VA rating Similar to a cascaded bridge modular converter, the dc–ac
for bridge 1, as annotated in Figure 7. converters of the 3-W TAB modular converter have to be
sized to filter single-phase ac power. Although the same
V 1 - SW = '
V p = n p # Vdc, PV
equations remain valid [reiterated in (18) and (19)], the
Vb = n b # Vdc, BS
Z I L - pv capacitance can be distributed between the dc input and
] = I L , PV ac output for filtering.
1 - SW
] 2 2 np
I =[
Bridge 1: ]] I L - batt = I L , BS (14) C dc
\ 2 2 nb C batt
= 2 I dc Tac 1 (18)
n SW = 4 # 3 # p = 12p C PV r 4 rVdc
VA SW = )
2 2 Ppv # rpv, PV L batt rVbatt/PV # Tac
= (19)
2 2 Pbatt # r batt, BS L PV 2rrI batt/PV
where p = b represents the number of TAB modules, and where the definition of the variables remain the same.
I L represents the RMS value of the net inductor current on
the secondary side, which is shared between the two dc Efficiency Calculations
systems during the power-transfer process, and the ratio Table 3 derives the current expressions critical for loss
of I L - x/I DC - x = rx . 1.1 - 1.3 results in an optimized calculations in a 3-W TAB. The notations I x0, I x1 represent
design with minimized VA requirements ^ x = pv, batt h. the current values when the transformer leakage induc-
The analysis assumes a phase shift of up to 0.2 per unit tance is referred to the PV, battery, and ac side bridge
(p.u.) to minimize reactive power flow [30], [31]. Similarly, where x = P, B, ac (I P0, I P1 are annotated in Figure 7).
equation sets (15) and (16) characterize the per-switch VA Duty ratios d 0, d z represent the duty ratios of the diode
rating for bridges 2 and 3, as annotated in the figure. conduction interval referred to the primary side and the
phase shift, respectively. Here, the distribution of currents
V 1 - SW = Vdc between the transistors and the diodes for the RMS and
I 1 - SW = I L average calculations assumes that the power is transferred
Bridge 2: 2 (15)
n SW = 4 # 3 # p = 12p from the PV panel to the battery and the ac grid, where
VA SW = 2 2 Pinv # rinv fb, fac represent the fraction of PV power transfer to the
battery and the ac grid, respectively. Similar expressions
where again the ratio of I L /I dc = rinv . 1.1 - 1.3 results in can be derived for other power-transfer cases. For the
an optimized design with minimized VA requirements. power loss calculations in the output ac bridge (referred
to as bridge 3), the loss expressions (8)–(10) discussed
V 1 - SW = Vdc = 1 Vac in the “Efficiency Calculations” section hold true. The
p 2d m “Results and Discussion” section presents comparative
1 - SW I ac
I = results for a design example under discussion.
Bridge 3: 2 (16)
n SW = 4 # 3 # p = 12p
2 Pinv TAB With a Five-Winding High-Frequency
VA SW = Transformer Topology
dm
To overcome the disadvantage of processing single-phase
It may be observed that the ratio between the mod- ac power processing requirements in modular topologies
ule’s dc-link voltage and the ac grid voltage features the such as CBC and TAB converter, the three ac legs can
number of modules p = b and the ac-modulation strategy be integrated using a high-frequency transformer [31].
factor d m. The total VA rating of the overall converter is The circuit schematic of the converter is illustrated in
characterized in (17). Figure 8. The high-frequency transformer interfaces the
PV and the BSs with the three-ac phases to eliminate the
VA SW = 2 Pinv 82r # (ILR + 0.5 + 1) + 1 B(17)

need for low-frequency power processing. Similar to 3-W

dm TAB converter, this topology is an ac-coupled configura-
tion in Figure 1(b).
where the ratio of I L - x/I dc - x = rx . 1.2 results in an The five-winding (5-W) TAB converter is expected
optimized design with minimized VA requirements to be more power dense in contrast to the 3-W TAB
c onverter, with control complexity as a tradeoff. The next
MVAc
few sections detail quantitative and qualitative results.
ILA
VA Ratings of Semiconductor Components
VA ratings of the 5-W TAB converter are expected CA
to be comparable to the 3-W TAB converter of the PV1 ILB
“Triple-Active Bridge With a Three-Winding High-
CB
Frequency Transformer Topology” section. Equation
ILC
sets (20)–(22) characterize net VA ratings for the three B1
bridges wherein the current magnitudes will include CC
three-phase power calculations.
V 1 - SW = '
V p = n p # Vdc, PV
Vb = n b # Vdc, BS
Z I L - pv
] , PV
] 2 PVp
I 1 - SW = [
Bridge 1: ]] I L - batt , BS (20)
\ 2
n SW = 4 # p Bb
VA SW = )
2 2 Ppv # rpv, PV
2 2 Pbatt # rbatt, BS
V 1 - SW = Vdc
I 1 - SW = I L FIGURE 8. The converter topology of a three-phase cascaded TAB
Bridge 2: 2 (21) converter with both BSs and PV systems connected to modular
n SW = 4 # 3 # p = 12p dc–ac–ac converters via a 5-W transformer. Note that the three ac
VA SW = 2 2 Pinv # rinv phases are integrated together with the same dc systems.
Table 3. RMS and average current expressions for TAB converters useful for loss calculations
Component IRMS Iavg
2 2
PV Transistors (I + I + I P 0 I P1)
P0 P1 I2 I P0 (0.25 - 0.5d z) + I P1 (0.25 - 0.5d 0)
(0.5 - d z) + P1 (d z - d 0)
3 3
Diodes d0 0.5I P0 d 0
I P0
3
Inductor LP (I 2P0 + I P21 + I P0 I P1) (I 2 + I 2 - I I ) -
(1- 2d z) + P0 P1 P0 P1 2d z
3 3
where, d 0 = I P0 L S fS , d = z , I = 2zVdc n p - r (Vdc n p - V p) and I = 2zV p + r (Vdc n p - V p)

2r P0 P1
c V p + dc m
z
V 4rfS L p 4rfS L p
np
Battery Diodes (I 2B0 + I B2 1 + I B0 I B1) I2 I B0 (0.25 + 0.5d 0 - 0.5d z) +

(0.5 - d z) + B1 (d z - d 0)
3 3 I B1 (0.25 - 0.5d z)
Transistors dz - d0 0.5I B0 (d z - d 0)
I B0
3
- rc - Vb m 2zVb + r c - Vb m
2zV p n b Vp n b Vp n b
L p n 2b np np np
where L b = , I B0 = fb and I B1 = fb
n 2p 4rfS L b 4rfS L b
AC Diodes (I 2ac0 + I 2ac1 + I ac0 I ac1) I2 I ac0 (0.25 + 0.5d 0 - 0.5d z) +

(0.5 - d z) + ac1 (d z - d 0)
3 3 I ac1 (0.25 - 0.5d z)
Transistors dz - d0 0.5I ac0 (d z - d 0)
I ac0
3
- rc - Vdc m 2zVdc + r c - Vdc m

2zV p Vp Vp
Lp np np np
where L ac = 2 , I ac0 = fac and I ac1 = fac
np 4rfS L ac 4rfS L ac

V 1 - SW = Vdc = 1 Vac filter any low-frequency ripples that are imposed due to
p dm practical challenges in implementing the control approach.
I 1 - SW = I ac
Bridge 3: 2 .(22) Efficiency Calculations
n SW = 2 # 3 # p = 6p
Although the analytical equations presented in the “Effi-
2 Pinv
VA SW = ciency Calculations” section can be utilized for loss calcu-
dm
lations in the 5-W TAB, it may be noted that the PV and
It may be noted that although expressions (20)–(22) battery bridges are integrated for the three ac phases. The
are comparable to those of the 3-W TAB modules, “Results and Discussion” section presents comparative
the dc–ac converters for the PV and BS process three- results for the design example under discussion.
phase ac power. In other words, in contrast to the 3-W
TAB, the 5-W TAB features a single dc–ac converter Control Strategies for Hybrid PV+BS Plants
per dc source. Modular power electronic converters feature a hierarchi-
Further, considering the ac–dc–ac converter, i.e., cal control strategy. Figure 9 illustrates a simplified block
bridges 2 and 3 in the figure, each of the three cascad- diagram for a hybrid PV+BS power plant, which consists
ed converters process single-phase ac power directly of a central controller at the grid level and local control-
to the output, resulting in minimal capacitance val- lers for module-level controls. The central controller
ues at the intermediate link (C A, C B, and C C ). Hence, receives power dispatch commands from the grid-side
the net converter currents (I LA, I LB, and I LB) feature a system operator, which includes reference active power
second-harmonic ripple, resulting in higher RMS cur- ^ P ref
g h and reference reactive power ^ Q g h, if reactive
ref
rent values. This can be identified in the net VA rating power control is permitted. The central controller con-
calculations of (23). sists of a phase-locked loop (PLL) unit, maintains the
power dispatched from the hybrid plant, and provides
VA SW = 2 2 P 8r # (ILR + z) + r inv p + 1 B(23)
2~
energy balancing between several converters/modules.
dm
Further, the central controller determines the reference
where the ratio of I L - x/I DC - x = rx . 1.2 for the PV and power commands for the modular PV and BS, P kref, pv
2~
battery converters. Note that the factor r inv p will be much and P kref, batt, respectively, where k refers to the kth mod-
higher than a 3-W TAB because the current waveforms ule. The remaining section discusses the several control
will feature a second-harmonic ripple. The “Results and approaches within the central controller and for the local
Discussion” section demonstrates the performance of this controllers suitable for hybrid PV+BS plants. Note that
architecture using a design example. superscript m refers to the measured quantities in the
following discussion.
Battery/PV Energy Storage Ratings
In contrast to a 3-W TAB converter, the energy storage Central Controller
elements of the 5-W TAB converter process only high- The ac grid-side voltages ^v m g h are typically processed by
frequency current and voltage ripples. The sizing equations a PLL to determine the peak value of the grid voltage ^Vt g h
for the capacitive and inductive energy storage that reduce and the frequency (f). Consequently, Vt g and f are utilized
the impact of the switching action at the dc and ac side are to determine the reference active ^ P acref
h and reactive ^ Q ref
ac h
characterized in (24) and (25), and (26), respectively. power values, respectively, typically using synchronverters
or virtual synchronous generators (VSGs) [32], [33].
C Batt - PV = I dc # TS 1 (24) The VSG control concept exploits the idea of operating
4 rVdc
an inverter to mimic a synchronous generator to emulate
rVdc TS 1
L Batt - PV = (25) its inertial characteristics. Typical VSG methods include
4 4 rI dc
voltage and frequency filtering, which are obtained from
It + I dc # dt T
c ac m 0 S the PLL using a deadband and a proportional controller.
3
C dc = (26) The deadband reduces noisy voltage or frequency-support
rVdc
needs to prevent false VSG activation. The proportional
where dt 0 represents the maximum value of the zero state controller is designed based on the megawatt/hertz capa-
of ac bridge 3 when the peak value of the ac phase current bility of the plant. As these methods include deriva-
and rectified inductor current flows into the capacitor. Simi- tive terms and their measurement through PLLs, their
lar to dc-stacked topologies, the size of the energy storage implementation uses slower controllers. Recent advanced
elements is a function of the modulation strategy because VSG schemes illustrate improvements in performance
the dominant ripple is due to the switching action. It may in hybrid plants by eliminating PLL and derivative terms
be noted that while under ideal scenarios although the [34]. Alternatively, although VSGs inherit the advantages
energy storage elements will be sized to filter high-frequen- of droop-control methods and provide inertia support,
cy switching ripples, energy storage elements will need to droop-control methods can be considered where no
inertia emulation and a fast response [43]. Nevertheless, all of these invert-
is required [35], [36]. er control architectures are suitable
The VSG control for the four power electronic archi-
Local Controllers tectures under consideration as they
Based on grid demand, the power concept exploits the are designed for the dc–ac inverter
availability in PV systems ^ Pk, pv h, and idea of operating an connected to the grid.
the state of charge (SOC) of the BS
^ Pk, batth, the central controller cre- inverter to mimic DC-Stacked and CBC Architectures
ates the reference power dispatch Figure 9 also illustrates the control
commands for local controllers of a synchronous structure of a local PV controller
the PV, BS, and inverter systems. generator to suitable for dc-stacked and CBC
The local controllers are responsible architectures. The MPPT algorithm
for PV/MPPT, BS/SOC, and invert- emulate its inertial identifies the maximum power that
er dc voltage control. Although the can be generated by the PV and
control variable for dc-stacked and characteristics. controls the voltage at the termi-
CBC architectures are duty-ratio nals of the PV module v k, p. Based
variables, the 3-W and 5-W TAB on the PV power reference received
architectures require phase-shift from the central controller P kref, pv, a
modulation. The following sections discuss control voltage controller based on PI control creates a current
methods for several cases. reference I ref
k, pv command. Consequently, the PI current
controller generates the duty ratio for the PV dc–dc
Inverter dq Current Controls and Their Alternatives converter [33]. In a BS, the local SOC controller deter-
Synchronous reference frame control, also called dq con- mines the SOC of the batteries and controls the power
trol, transforms grid currents and voltages into a reference of the battery module. Based on the BS power reference
frame that rotates synchronously with the grid voltage, received from the central controller P kref, batt, a power con-
e.g., abc " dq, using PLL techniques. Consequently, as troller based on PI control creates a current reference
the control variables become dc values, control and fil- I ref
k, batt command. Consequently, the PI current controller
tering is simplified. As illustrated in the figure, the grid- generates the duty ratio for the PV dc–dc converter [33].
side converter control strategy typically consists of two
hierarchical loops. The inner-current loop regulates the 3-W and 5-W TAB Architectures
grid current, while the outer-voltage loop regulates the The voltage-transfer ratio between the input and output in
dc voltage based on power demand. Hence, the loops are TAB topologies is a critical design factor that has a direct
designed for power quality and power flow, respectively. effect on the reactive power flow within the topology.
These control loops typically feature proportional–integral In other words, if V p /n p ! Vb /n b ! Vdc, high circulating
(PI) controllers as they have a satisfactory behavior when currents can have a significant effect on converter perfor-
regulating dc variables [37]. Advanced controllers feature mance [30], [44]. Consequently, the complexities in control
cross coupling or voltage feedforward terms to improve strategies for these topologies are higher than traditional
the performance of PI controllers [38], [39]. dc-stacked and CBC topologies.
Due to poor compensation of low-order harmonics With the control architecture in Figure 9, the inverter
with PI control techniques, advanced techniques such as dc voltage is regulated by the central controller refer-
proportional–resonance (PR) controllers, hysteresis and ences and is fixed. Consequently, the reference active
deadbeat controllers are gaining popularity. The imple- power command ^ P kref, pv h and the PV module voltage
mentation of PR controllers is simpler in a stationary ^ v k, p h obtained from the central controller and the MPPT
reference frame, e.g., abc " ab, or a natural frame of algorithm is utilized using a PI controller to gener-
reference and phase-angle information are not necessities ate the phase shift for the output ac bridge. A similar
[40]. A hysteresis controller introduces variable switching- control strategy can be implemented on the BSs. As
frequency operation, which is not suitable for grid-tied V p /n p . Vb /n b . Vdc may not hold true, the converter
applications. Several methods have been proposed in the would not operate at the optimized efficiency operating
literature, employing an adaptive band to obtain a fixed condition. The “Results and Discussion” section quanti-
switching frequency. Complexity of the hysteresis control- fies this using a case scenario based on specifications
ler is high for current regulation [9], [41]. Alternatively, of the design example under consideration. In [45], the
deadbeat controllers are simpler and attempt to mitigate authors suggest regulating the PV panel voltage to main-
errors in the control variables within one sample delay. To tain converter performance. Alternatively, current-fed
compensate for this delay, an observer can be introduced dual-active bridge dc–dc converters are gaining popular-
into the structure of the controller, with the aim to modify ity, where the duty ratio and the phase shift are regulated
the current reference to compensate for the delay [42], to maintain a high efficiency operation [44]. An alternate

strategy to Figure 9, which is more suitable for TAB power at the regulated voltage. The battery bridge phase
architectures to maintain converter performance, is based shift is regulated based on the PV/dc voltages and refer-
on regulating the dc inverter voltage by the PV system ence power commands. Although converter efficiency
[31], [46], [47], [48]. One such implementation is illustrated can be optimized with this approach by minimizing the
in Figure 10, where the MPPT controller is employed to circulating currents, the total per-unit ratings of the con-
regulate the PV output voltage, which provides a constant verter could be higher than both the dc-stacked and CBC
dc voltage to the inverter. Further, the inverter follows converter topologies to support the grid voltage when the
the dc voltage and grid references to provide the desired PV operating voltage is low. As noted in the “TAB With
Central Controller
Pk,pv Pk,batt Pgref Qgref f θ
m
I inv m
Vk,dc
at the ac Grid
ref
Pk,inv
"
Vg
Vdc Voltage Control ref
Vk,inv dk,inv
vgm PQ Inverter PWM
PLL f ref
Qk,inv and
Calculation Modulator
dq Current Control
θ ref
Pk,pv ref
Pk,batt k th dc–ac Inverter Module
ref m ref
Pk,pv Ik,p Pk,batt m
Ik,b
ref
Vk,p ref
I k,p dk,p P k,batt I k,b d k,b
PI Voltage PI Current PI Power PI Current
MPPT Controller Controller SOC Controller Controller
Pk,pv
k th dc–dc PV Module k th dc–dc Battery Module
FIGURE 9. A block diagram of the hierarchical control approach for a hybrid PV+BS plant. PLL: phase-locked loop; SOC: state of charge;
PI: proportional integral.
Central Controller Pk,pv Pk,batt Pgref Qgref m

vk,p m
Vk,dc f θ m
Vk,dc
at the ac Grid
ref
Pk,inv
"
Vg ref ref
I k,inv Vk,inv dk,inv
vgm PQ VDC Voltage dq Current Inverter PWM
PLL f ref
Qk,inv
Calculation PI Control Control Modulator
ref ref
θ Pk,pv Pk,batt
k th dc–ac Inverter Module
m ref m
ref
Pk,pv vk,p Pk,batt vk,dc
Bridge 2 Batt.
Vk,p φk,b vk,b φk,b
PI Voltage Phase-Shift dc/dc PI Voltage Phase-Shift dc–dc
MPPT Controller SOC Controller Modulator
Modulator
φ ref P k,batt φ ref

Pk,pv k th dc–dc Battery Module
k th dc–dc PV Module
FIGURE 10. A block diagram of the hierarchical control approach for a hybrid PV+BS plant suitable for TAB topologies. Batt.: battery.
a Five-Winding High-Frequency Transformer Topology” converter configurations feature a higher per-unitized rat-
section, a 5-W TAB topology necessitates a per-phase ing for the power semiconductor devices in comparison to
phase shift on the ac side to minimize the dc–ac convert- the dc-stacked and cascaded bridge topologies. Further,
er capacitor value and reaps the benefits of a three-phase as noted previously, the 5-W TAB has a slightly higher
integrated transformer-winding configuration [31]. VA rating in comparison to the 3-W TAB architecture due
to the second-harmonic current ripple in the ac/dc/ac
Double-Star Configuration bridges. However, in contrast to other modular topologies,
Cascaded bridge architectures may be viewed as single- the 5-W TAB features a low energy storage requirement
star configurations, which comprise three arms for each due to three-phase transformer integration at the module
of the three ac phases. Although this article focuses on level. It may also be noted that the higher RMS current
cascaded bridge architectures for modular power conver- ratings in TAB converters also result in higher per-unit-
sion, the modular multilevel converter (MMC) configu- ized ratings for high-frequency transformers.
ration provides an alternative for integration of hybrid Using the efficiency calculation analytical models
PV+BS systems to the grid. In contrast to cascaded bridge detailed in the “DC-Stacked Architectures” and “Cas-
architectures, the MMC architecture is a double-star caded Bridge Architectures” sections, and the time-
configuration featuring six arms. The neutral points of domain simulations, Figures 11–15 present and compare
the two-star networks formed by the three arms provide the performance of the four converter approaches in
an accessible dc port output. Hence, MMC architectures terms of efficiency and loss distribution. Figure 11 com-
enable bulk-transmission renewable power by utilizing pares the efficiency of the various topologies as a func-
high-voltage dc (HVdc) transmission infrastructure, along tion of the switching frequency with a power level of
with other grid-support functions [18], [33], [49]. Ppv = 1.3 p.u., Pbatt = 0.3 p.u., and Pac = 1 p.u. The details
The module designs examined in the “Cascaded of the part numbers and the loss parameter values
Bridge Architectures” section, including FB modules, employed for efficiency calculations are summarized in
3-W, and 5-W transformer TAB modules can be connect-
ed in series to form six arms for an MMC configuration.
These architectures will be suitable for HVdc transmis- Table 4. Parameter design values for the design
sion from hybrid PV+BS power plants. The analytical example under consideration
results discussed in the article can be extended for such
double-star configurations. Parameter Value
Power 18 MVA
Results and Discussion
This section presents quantified and qualitative results of Frequency 60 Hz
the power converter architectures in terms of VA ratings, AC source voltage 13.8-kV RMS
energy storage requirements, efficiency estimations, and PV:battery:inverter power ratio 1.3:0.5:1
control complexity for a design example. Table 4 details
DC battery voltage 400–650V
specifications of the parameter design values suitable for
a utility-scale hybrid PV and battery energy storage power PV panel voltage 200–600V
plant. As noted in the “Block Diagram of PV+BS Power
Plants” section, the ILR and the battery plant power rat-
ings are assumed to be 1.3 and 0.5 p.u., respectively, Table 5. Specifications of the selected configurations
which are typical in today’s plants. for the several power converter architectures
Table 5 lists specifications of the selected benchmark
configurations. With a safety margin of 1.2 and a FB DC Cascaded 3-W 5-W
converter approach, both the dc-stacked and modular Topology Stacked Bridge TAB TAB
converter architectures feature eight converters and 14 IGBT voltage 1.2 kV (nominal)
modules, respectively. As the net theoretical per-unitized
Safety factor 1.2
VA and energy storage ratings will not be affected by the
transformer turns ratio, for simplicity, it is assumed to be DC voltage 1,000 V (nominal)
one-for-all configurations. In practical industrial solutions, Converters 8 — — —
other turns ratios could be used for optimization purposes. Modules — 14 14 14
Table 6 details ratings of the power semiconductor
LF-TF 13.8/0.55 1:1 — —
switches and the energy storage elements for the bench- turns-ratio
mark cases under consideration. The circuit architectures
HF-TF — — 1:1:1 1:1:1:1:1
have been developed in the piecewise linear electrical turns-ratio
circuit simulation environment to verify analytical calcu-
LF-TF: low-frequency transformer; HF-TF: high-frequency transformer.
lations. As noted in the analytical models, TAB modular

The solid, stacked bars and
Table 6. Ratings of the power semiconductor devices and the energy storage dashed, stacked bars indicate
elements for the design example under consideration the per-unitized conduction and
switching losses, respectively. As
Cascaded evident in Table 6, 3-W and 5-W
Parameters DC Stacked Bridge 3-W TAB 5-W TAB TAB topologies have a higher
PV converter Switch VA 3.05 p.u. 3.05 p.u. 4.28 p.u. 4.4 p.u. switch VA rating (the addition-
al FB is designed as bridge 2
Filtering ES 15.6 m p.u. 0.05 p.u. 0.05 p.u. 2 m p.u.
or B2 in the discussion). Con-
Battery Switch VA 1.08 p.u. 1.08 p.u. 1.65 p.u. 1.7 p.u. sequently, the net conduction
converter
losses in these topologies are
Filtering ES 5.25 m p.u. 0.02 p.u. 0.02 p.u. 1 m p.u. higher than in dc-stacked and
Grid inverter Switch VA 4.8 p.u. 4.8 p.u. 8.29 p.u. 10.7p.u. CBC topologies. In contrast,
Filtering ES 17.8 m p.u. 1.63 p.u. 1.59 p.u. 0.15 p.u. due to zero-voltage switching
(ZVS) operation, TAB topologies
Low-frequency transformer 1 p.u. 1 p.u. — —
have net lower switching losses.
High-frequency transformer — — 1.2 p.u. 1.5 p.u. Moreover, CBC topologies have
Total VA (p.u.) 8.93 p.u. 8.93 p.u. 14.21 p.u. 16.8 p.u. lower switching losses compared
Total ES (p.u.) 0.04 p.u. 1.7 p.u. 1.67 p.u. 0.15 p.u. to a dc-stacked topology due to
a lack of modularity and loss
Base power = 18 MVA; base frequency = 60 Hz; base energy = 0.3 MJ; ES: energy storage.
parameters of the commercially
available devices for higher volt-
Table S1 in “Loss Calculations.” The validity of the analyt- age and current requirements. When comparing 3-W
ical models is verified using simulations, where accuracy and 5-W TAB converters, due to three-phase integrated
in the current calculations is reported to be 1 1%. The PV and battery converter systems, higher current-rated
efficiency calculations include transformer losses. The low- devices are selected, which can be designed with lower
frequency line transformer for dc-stacked and CBC topologies on-state resistance. Hence, a 5-W TAB design fairs slightly
and high-frequency module transformers for TAB topolo- better than a 3-W TAB one. With the design specifications
gies are assumed to be 99.2 and 99.5%, respectively, and design selections, a CBC is clearly the most efficient
[18], [50], [51]. As the PV, battery, and one of the ac-side with lower switching-frequency designs, while a 5-W TAB
bridges can be designed to operate under zero-voltage
switching, 3-W and 5-W TAB converters feature weaker
dependence on the switching frequency in comparison to Switching Frequency = 2 kHz
dc-stacked and CBC topologies at the rated power. ·10−2
Figures 12 and 13 illustrate loss distribution with 3
a switching frequency of 2 and 20 kHz, respectively.
PPV = 1.3 p.u., PBatt = 0.3 p.u., Pac = 1 p.u. 2

Loss (p.u.)
1
0.99 dc Stacked
CBC
0.98
3-W TAB
0.97 5-W TAB 1
Efficiency (p.u.)
0.96
0.95
0.94
0.93 dc CBC 3-W TAB 5-W TAB
Stacked
0.92
0.91 PV Conduction PV Switching Batt. Conduction
0.9 Batt. Switching B2 Conduction B2 Switching
2 4 6 8 10 12 14 16 18 20
Switching Frequency (kHz) ac Conduction ac Switching Transformer
FIGURE 11. Efficiency of the compared topologies as a FIGURE 12. Loss distribution with a switching frequency of 2 kHz
function of the switching frequency with a power level of with a power level of Ppv = 1.3 p.u., Pbatt = 0.3 p.u., and
Ppv = 1.3 p.u., Pbatt = 0.3 p.u., and Pac = 1p.u. Pac = 1p.u. Batt.: battery.
is the most efficient in high switching-frequency designs. operation ^n p = 0.6 h, during low power output from the
Switching losses at the dc–ac inverter dominate, with a PV panel, the PV panel voltage is operating at 525 V. In
switching frequency of 20 kHz in all of the topologies. the case of dc bus voltage regulation at the ac inverter
Figures 14 and 15 quantify the effect of difference in control loop, the dc voltage is maintained at 1 kV. On the
control methods for TAB topologies. Here, with a power other hand, if the dc inverter’s voltage is regulated by the
level of Ppv = 0.5 p.u., Pbatt = 0 p.u., and Pac = 0.5 p.u., a PV panel voltage, the dc voltage is regulated to 875 V to
low-PV power output scenario is considered. Although minimize circulating currents. Figure 14 illustrates the
the high-frequency transformer turns ratio is optimized current waveform at the PV side of the high-frequency
for a 600-V PV operation and a 1-kV dc inverter voltage transformer. It is noted that the RMS value of the cur-
rent increases by 5% in the case of Vdc = 1 kV. Figure 15
shows the loss distribution, where the net losses are
increased by 10.2 and 9.8% in the case of 3-W and 5-W
Switching Frequency = 20 kHz TABs, respectively. Hence, the tradeoff in adding control
·10−2
10 complexity with efficiency in the case of TAB topologies
is readily observed.
Table 7 provides a summary of the qualitative char-
8
acteristics of the candidate topologies under discussion.
Loss (p.u.)
Ppv = 0.5 p.u., Pbatt = 0 p.u. and Pac = 0.5 p.u.

4
·10−2 ·10−2
6
2
4
Loss (p.u.)
0
dc CBC 3-W TAB 5-W TAB
2
Stacked
PV Conduction PV Switching Batt. Conduction

0
Batt. Switching B2 Conduction B2 Switching 3-W TAB 5-W TAB 3-W TAB 5-W TAB
ac Conduction ac Switching Transformer Vdc : 875 V Vdc : 1,000 V
PV Conduction PV Switching Batt. Conduction

FIGURE 13. Loss distribution with a switching frequency of 20 kHz Batt. Switching B2 Conduction B2 Switching
with a power level of Ppv = 1.3 p.u., Pbatt = 0.3 p.u., and
ac Conduction ac Switching Transformer
Pac = 1p.u. Batt.: battery.
FIGURE 15. Loss distribution with a switching frequency of 20

Primary-Side Current (p.u.)
kHz with a power level of Ppv = 0.5 p.u., Pbatt = 0 p.u., and
Pac = 0.5 p.u. for Vdc = 875 V and Vdc = 1 kV.
1.5
1
0.5 Table 7. Summary of converter qualitative
0 characteristics for the candidate topologies
–0.5
–1 DC Cascaded 3-W 5-W
Topology Stacked Bridge TAB TAB
–1.5
Efficiency Second First Third Third
0 50 100 150 200
Time (ms) Power Third Second Second First
Density
Vdc = 875 V Vdc = 1,000 V
Control First First Second Third
Complexity
FIGURE 14. Current waveforms on the primary-side high- Modularity Second First First First
frequency transformer in a 3-W TAB with a power level of
Ppv = 0.5 p.u., Pbatt = 0 p.u., and Pac = 0.5 p.u.; a PV voltage Maturity First Second Third Third
of 525 V; and dc voltages of 875 V (green line) and 1 kV (red line). Level

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An Examination of Power Converter Architectures For Utility-Scale Hybrid Solar Photovoltaic and Battery Energy Storage Systems

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©SHUTTERSTOCK.

By Mahima Gupta RECENTLY, THE FALLING COSTS OF PHOTOVOLTAIC (PV)

12 IEEE Industry Applications Magazine  MARCH/APRIL 2023 1077-2618/22©2022IEEE

M ARCH/AP RI L 2023  IEEE Industry Applications Magazine 13

14 IEEE Industry Applications Magazine  MARCH/APRIL 2023

M ARCH/AP RI L 2023  IEEE Industry Applications Magazine 15

Vdc Vdc It may be noted that the VA rating is a function of

16 IEEE Industry Applications Magazine  MARCH/APRIL 2023

inductance to limit the ripple in the dc current ^rI dch.

M ARCH/AP RI L 2023  IEEE Industry Applications Magazine 17

Ćuk D I p/b + dc Dl I p/b + dc I p/b, IDC — — Dl DI p/b + dc DlI p/b + dc

18 IEEE Industry Applications Magazine  MARCH/APRIL 2023

Table S1. Converter design details for efficiency calculations

M ARCH/AP RI L 2023  IEEE Industry Applications Magazine 19

20 IEEE Industry Applications Magazine  MARCH/APRIL 2023

B1A B1B B1C

M ARCH/AP RI L 2023  IEEE Industry Applications Magazine 21

VA SW = 2 Pinv 82r # (ILR + 0.5 + 1) + 1 B(17)

22 IEEE Industry Applications Magazine  MARCH/APRIL 2023

where, d 0 = I P0 L S fS , d = z , I = 2zVdc n p - r (Vdc n p - V p) and I = 2zV p + r (Vdc n p - V p)

Battery Diodes (I 2B0 + I B2 1 + I B0 I B1) I2 I B0 (0.25 + 0.5d 0 - 0.5d z) +

AC Diodes (I 2ac0 + I 2ac1 + I ac0 I ac1) I2 I ac0 (0.25 + 0.5d 0 - 0.5d z) +

- rc - Vdc m 2zVdc + r c - Vdc m

M ARCH/AP RI L 2023  IEEE Industry Applications Magazine 23

24 IEEE Industry Applications Magazine  MARCH/APRIL 2023

M ARCH/AP RI L 2023  IEEE Industry Applications Magazine 25

Central Controller Pk,pv Pk,batt Pgref Qgref m

φ ref P k,batt φ ref

26 IEEE Industry Applications Magazine  MARCH/APRIL 2023

M ARCH/AP RI L 2023  IEEE Industry Applications Magazine 27

PPV = 1.3 p.u., PBatt = 0.3 p.u., Pac = 1 p.u. 2

28 IEEE Industry Applications Magazine  MARCH/APRIL 2023

Ppv = 0.5 p.u., Pbatt = 0 p.u. and Pac = 0.5 p.u.

PV Conduction PV Switching Batt. Conduction

PV Conduction PV Switching Batt. Conduction

FIGURE 15. Loss distribution with a switching frequency of 20

M ARCH/AP RI L 2023  IEEE Industry Applications Magazine 29

30 IEEE Industry Applications Magazine  MARCH/APRIL 2023

M ARCH/AP RI L 2023  IEEE Industry Applications Magazine 31

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