Sahyadri College of Engineering and Management

Mangaluru
(Affiliated to Visvesvaraya Technological University, Belagavi)

COMPUTER ORGANIZATION
(17CS34)

Prepared By:

Ganaraj K
Assistant Professor
Dept of ISE
Sahyadri College of Engineering and Management
Mangaluru
 COMPUTER ORGANIZATION
[As per Choice Based Credit System (CBCS) scheme]
(Effective from the academic year 2015 -2016)
SEMESTER - III
Subject Code 15CS34 IA Marks 20

Number of Lecture Hours/Week 04 Exam Marks 80

Total Number of Lecture Hours 50 Exam Hours 03

CREDITS – 04

Course objectives:
This course will enable students to

• Understand the basics of computer organization: structure and operation of computers and their
peripherals.
• Understand the concepts of programs as sequences or machine instructions.
• Expose different ways of communicating with I/O devices and standard I/O interfaces.
• Describe hierarchical memory systems including cache memories and virtual memory.
• Describe arithmetic and logical operations with integer and floating-point operands.
• Understand basic processing unit and organization of simple processor, concept of pipelining and
other large computing systems.
Module -1 Teaching
Hours

Basic Structure of Computers: Basic Operational Concepts, Bus Structures, Performance

– Processor Clock, Basic Performance Equation, Clock Rate, Performance Measurement.
10Hours
Machine Instructions and Programs: Memory Location and Addresses, Memory
Operations, Instructions and Instruction Sequencing, Addressing Modes, Assembly
Language, Basic Input and Output Operations, Stacks and Queues, Subroutines, Additional
Instructions, Encoding of Machine Instructions
Textbook 1: Ch 1: 1.3, 1.4, 1.6.1, 1.6.2, 1.6.4, 1.6.7. Ch 2: 2.2 to 2.10, 2.12
Module -2

Input/Output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware,

Enabling and Disabling Interrupts, Handling Multiple Devices, Controlling Device
10 Hours
Requests, Exceptions, Direct Memory Access, Buses, Interface Circuits, Standard I/O
Interfaces – PCI Bus, SCSI Bus, USB.
Textbook 1: Ch 4: 4.1, 4.2: 4.2.1 to 4.2.5, 4.4 to 4.7.
Module – 3

Memory System: Basic Concepts, Semiconductor RAM Memories, Read Only Memories,
Speed, Size, and Cost, Cache Memories – Mapping Functions, Replacement Algorithms,
10 Hours
Performance Considerations, Virtual Memories, Secondary Storage.
Textbook 1: Ch 5: 5.1 to 5.4, 5.5.1, 5.5.2, 5.6, 5.7, 5.9
Module-4

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Arithmetic: Numbers, Arithmetic Operations and Characters, Addition and Subtraction of
Signed Numbers, Design of Fast Adders, Multiplication of Positive Numbers, Signed
10 Hours
Operand Multiplication, Fast Multiplication, Integer Division, Floating-point Numbers and
Operations.
Textbook 1: Ch 2: 2.1, Ch 6: 6.1 to 6.7
Module-5

Basic Processing Unit: Some Fundamental Concepts, Execution of a Complete

Instruction, Multiple Bus Organization, Hard-wired Control, Micro programmed Control.
10 Hours
Embedded Systems and Large Computer Systems: Examples of Embedded Systems,
Processor chips for embedded applications, Simple Microcontroller. The structure of
General-Purpose Multiprocessors.
Textbook 1: Ch 7: 7.1 to 7.5, Ch 9:9.1 to 9.3, Ch 12:12.3
Course outcomes:
After studying this course, students will be able to:
• Acquire knowledge of
- The basic structure of computers & machine instructions and programs, Addressing Modes,
Assembly Language, Stacks, Queues and Subroutines.
- Input/output Organization such as accessing I/O Devices, Interrupts.
- Memory system basic Concepts, Semiconductor RAM Memories, Static memories,
Asynchronous DRAMS, Read Only Memories, Cache Memories and Virtual Memories.
- Some Fundamental Concepts of Basic Processing Unit, Execution of a Complete Instruction,
Multiple Bus Organization, Hardwired Control and Micro programmed Control.
- Pipelining, embedded and large computing system architecture.
• Analyse and design arithmetic and logical units.
• Apply the knowledge gained in the design of Computer.
• Design and evaluate performance of memory systems
• Understand the importance of life-long learning
Graduate Attributes (as per NBA)
1. Engineering Knowledge
2. Problem Analysis
3. Life-Long Learning
Question paper pattern:
The question paper will have ten questions.
There will be 2 questions from each module.
Each question will have questions covering all the topics under a module.
The students will have to answer 5 full questions, selecting one full question from each module.

Text Books:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky: Computer Organization, 5th Edition, Tata McGraw Hill,
2002.

Reference Books:
1. William Stallings: Computer Organization & Architecture, 9th Edition, Pearson, 2015.

8|Page
 Module 1: BASIC STRUCTURE OF COMPUTERS

TYPES OF COMPUTERS
Desktop Computers
• These are most commonly used computers in home, schools and offices.
• This has
→ processing- & storage-units
→ video & audio output-units
→ Keyboard & mouse input-units.
Notebook Computers (Laptops)
• This is a compact version of a personal-computer (PC) made as a portable-unit.
Workstations
• These have more computational-power than PC.
Enterprise Systems (Mainframes)
• These are used for business data-processing.
• These have large computational-power and larger storage-capacity than workstations.
• These are referred to as
→ server at low-end and
→ Super-computers at high end.
Servers
• These have large database storage-units and can also execute requests from other
computers.
• These are used in banks & educational institutions.
Super Computers
• These are used for very complex numerical-calculations.
• These are used in weather forecasting, aircraft design and military applications.

FUNCTIONAL UNITS
• A computer consists of 5 functionally independent main parts: 1)input,
2)memory,3)arithmetic & logic, 4)output and 5)control units.
Input Unit
• The computer accepts the information in the form of program & data through an input-
device.
Eg: keyboard
• Whenever a key is pressed, the corresponding letter/digit is automatically translated into its
corresponding binary-code and transmitted over a cable to either the memory or the
processor.
Memory Unit
• This unit is used to store programs & data.
• There are 2 classes of storage:
1) Primary-storage is a fast-memory that operates at electronic-speed. Programs must
be stored in the memory while they are being executed.
2) Secondary-storage is used when large amounts of data & many programs have to
be stored. Eg: magnetic disks and optical disks(CD-ROMs).
• The memory contains a large number of semiconductor storage cells(i.e. flip-flops), each
capable of storing one bit of information.
• The memory is organized so that the contents of one word can be stored or retrieved in one
basic operation.

COMPUTER ORGANISATION Page 1

• Memory in which any location can be reached in a short and fixed amount of time after
specifying its address is called RAM (Random Access Memory).
ALU (Arithmetic & Logic Unit)
• This unit is used for performing arithmetic & logical operations.
• Any arithmetic operation is initiated by bringing the required operand into the processor
(i.e. registers), where the operation is performed by the ALU.

Output Unit
• This unit is used to send processed-results to the outside world.
Eg: printer, graphic displays etc.
Control Unit
• This unit is used for controlling the activities of the other units (such as memory, I/O
device).
• This unit sends control-signals (read/write) to other units and senses their states.
• Data transfers between processor and memory are also controlled by the control-unit
through timing-signals.
• Timing-signals are signals that determine when a given action is to take place.

COMPUTER ORGANISATION Page 2

BASIC OPERATIONAL CONCEPTS
• The processor contains ALU, control-circuitry and many registers.
• The instruction-register(IR) holds the instruction that is currently being executed.
• The instruction is then passed to the control-unit, which generates the timing-signals that
determine when a given action is to take place
• The PC(Program Counter) contains the memory-address of the next-instruction to be
fetched & executed.
• During the execution of an instruction, the contents of PC are updated to point to next
instruction.
• The processor also contains „n‟ general-purpose registers R0 through Rn-1.
• The MAR (Memory Address Register) holds the address of the memory-location to be
accessed.
• The MDR (Memory Data Register) contains the data to be written into or read out of the
addressed location.
Following are the steps that take place to execute an instruction
• The address of first instruction(to be executed) gets loaded into PC.
• The contents of PC(i.e. address) are transferred to the MAR & control-unit issues Read
signal to memory.
• After certain amount of elapsed time, the first instruction is read out of memory and placed
into MDR.
• Next, the contents of MDR are transferred to IR. At this point, the instruction can be
decoded & executed.
• To fetch an operand, it's address is placed into MAR & control-unit issues Read signal. As
a result, the operand is transferred from memory into MDR, and then it is transferred from
MDR to ALU.
• Likewise required number of operands is fetched into processor.
• Finally, ALU performs the desired operation.
• If the result of this operation is to be stored in the memory, then the result is sent to the
MDR.
• The address of the location where the result is to be stored is sent to the MAR and a Write
cycle is initiated.
• At some point during execution, contents of PC are incremented to point to next instruction
in the program. [The instruction is a combination of opcode and operand].

COMPUTER ORGANISATION Page 3

BUS STRUCTURE
• A bus is a group of lines that serves as a connecting path for several devices.
• Bus must have lines for data transfer, address & control purposes.
• Because the bus can be used for only one transfer at a time, only 2 units can actively use
the bus at any given time.
• Bus control lines are used to arbitrate multiple requests for use of the bus.
• Main advantage of single bus: Low cost and flexibility for attaching peripheral devices.
• Systems that contain multiple buses achieve more concurrency in operations by allowing 2
or more transfers to be carried out at the same time. Advantage: better performance.
Disadvantage: increased cost.
• The devices connected to a bus vary widely in their speed of operation. To synchronize
their operational speed, the approach is to include buffer registers with the devices to hold the
information during transfers.
Buffer registers prevent a high-speed processor from being locked to a slow I/O device
during a sequence of data transfers.

PROCESSOR CLOCK
• Processor circuits are controlled by a timing signal called a clock.
• The clock defines regular time intervals called clock cycles.
• To execute a machine instruction, the processor divides the action to be performed into a
sequence of basic steps such that each step can be completed in one clock cycle.
• Let P=length of one clock cycle R=clock rate. Relation between P and R is given by R=1/P
which is measured in cycles per second.
• Cycles per second is also called hertz(Hz)

BASIC PERFORMANCE EQUATION

• Let T=processor time required to
execute a program
N=actual number of instruction
executions
S=average number of basic steps needed to execute one
machine instruction R=clock rate in cycles per second
• The program execution time is given by

-----(1)

• Equ1 is referred to as the basic performance equation.

• To achieve high performance, the computer designer must reduce the value of T, which
means reducing N and S, and increasing R.
→ The value of N is reduced if source program is compiled into fewer machine
instructions.
→ The value of S is reduced if instructions have a smaller number of basic steps to
perform.
→ The value of R can be increased by using a higher frequency clock.

COMPUTER ORGANISATION Page 4

• Care has to be taken while modifying the values since changes in one parameter may affect
the other.

PIPELINING & SUPERSCALAR OPERATION

• Normally, the computer executes the instruction in sequence one by one. An
improvement in performance can be achieved by overlapping the execution of
successive instructions using a technique called pipelining.
• Consider the instruction
Add R1,R2,R3;instruction 1
Move R4,R5 ;instruction 2
Let us assume that both operations take 3 clock cycles each for completion.

As shown in above figure, 6 clock cycles are required to complete two operations.

• As shown in above figure, if we use pipelining & prefetching, only 4 cycles are required to
complete same two operations.
• While executing the Add instruction, the processor can read the Move instruction from
memory.
• In the ideal case, if all instructions are overlapped to the maximum degree possible,
execution proceeds at the rate of one instruction completed in each clock cycle.
• A higher degree of concurrency can be achieved if multiple instruction pipelines are
implemented in the processor i.e. multiple functional units can be used to execute different
instructions parallely. This mode of operation is known as superscalar execution.
• With Superscalar arrangement, it is possible to complete the execution of more than one
instruction in every clock cycle.

COMPUTER ORGANISATION Page 5

 PERFORMANCE MEASUREMENT
• SPEC(System Performance Evaluation Corporation) selects & publishes the standard
programs along with their test results for different application domains
The SPEC rating is computed as follows

• If SPEC rating=50 means that the computer under test is 50times as fast as reference
computer.
• The test is repeated for all the programs in the SPEC suite, and the geometric mean of the
results is computed.
Let SPECi be the rating for program i in the suite. The overall SPEC rating for the computer
is given by

where n=number of programs in the suite

INSTRUCTION SET: CISC AND RISC

Architectural CISC RISC
characteristics
instructions with fixed format
Instruction formats instructions with variable formats and
most are register based instruction
addressing modes 12-24 limited to 3-5
8-24 GPRs. Mostly with a unified large number of GPRs with
General purpose register cache mostly
and cache design for instruction and data split data cache and instruction
cache
33-50 Mhz with CPI between 2 and 50-150Mhz with 1 clock cycle
Clock rate & CPI 15 for
almost all instruction and an
average
CPI<15
CPU control mostly microcoded using control mostly hardwired without control
memory memory

COMPUTER ORGANISATION Page 6

 Module 1(CONT.): MACHINE INSTRUCTIONS &
PROGRAMS

MEMORY LOCATIONS & ADDRESSES

• The memory consists of many millions of storage cells (flip-flops), each of which can store
a bit of information having the value 0 or 1 (Figure 2.5).
• Each group of n bits is referred to as a word of information, and n is called the word length.
• The word length can vary from 8 to 64bits.
• A unit of 8 bits is called a byte.
• Accessing the memory to store or retrieve a single item of information (either a word or a
byte) requires distinct addresses for each item location. (It is customary to use numbers from
0 through 2k-1 as the addresses of successive locations in the memory).
• If 2k=number of addressable locations, then 2k addresses constitute the address space of the
computer. For example, a 24-bit address generates an address space of 224 locations (16MB).

COMPUTER ORGANISATION Page 7

• Characters can be letters of the alphabet, decimal digits, punctuation marks and so on.
• Characters are represented by codes that are usually 8 bits long. E.g. ASCII code
• The three basic information quantities are: bit, byte and word.
• A byte is always 8 bits, but the word length typically ranges from 1 to 64 bits.
• It is impractical to assign distinct addresses to individual bit locations in the memory.

BYTE ADDRESSABILITY
• In byte addressable memory, successive addresses refer to successive byte locations in the
memory.
• Byte locations have addresses 0, 1, 2. . . . .
• If the word length is 32 bits, successive words are located at addresses 0, 4, 8. .with each
word having 4 bytes.

BIG-ENDIAN AND LITTLE-ENDIAN ASSIGNMENTS

• There are two ways in which byte addresses are arranged.
1) Big-endian assignment: lower byte addresses are used for the more
significant bytes of the word (Figure 2.7).
2) Little-endian: lower byte addresses are used for the less significant bytes of the
word
• In both cases, byte addresses 0, 4, 8. . . . . are taken as the addresses of successive words in
the memory.

WORD ALIGNMENT
• Words are said to be aligned in memory if they begin at a byte address that is a multiple of
the number of bytes in a word.
• For example, if the word length is 16(2 bytes), aligned words begin at byte addresses 0, 2, 4
. . . . . And for a word length of 64, aligned words begin at byte addresses 0, 8, 16. . . . . . .
• Words are said to have unaligned addresses, if they begin at an arbitrary byte address.

ACCESSING NUMBERS, CHARACTERS & CHARACTERS STRINGS

• A number usually occupies one word. It can be accessed in the memory by specifying its
word address. Similarly, individual characters can be accessed by their byte address.
• There are two ways to indicate the length of the string

COMPUTER ORGANISATION Page 8

 → a special control character with the meaning "end of string" can be used as the last
character in the string, or
→ a separate memory word location or processor register can contain a number
indicating the length of the string in bytes.

MEMORY OPERATIONS
• Two basic operations involving the memory are: Load(Read/Fetch) and Store(Write).
• The Load operation transfers a copy of the contents of a specific memory location to the
processor. The memory contents remain unchanged.
• The steps for Load operation:
1) Processor sends the address of the desired location to the memory
2) Processor issues „read‟ signal to memory to fetch the data
3) Memory reads the data stored at that address
4) Memory sends the read data to the processor
• The Store operation transfers the information from the processor register to the specified
memory location. This will destroy the original contents of that memory location.
• The steps for Store operation are:
1) Processor sends the address of the memory location where it wants to store data
2) Processor issues „write‟ signal to memory to store the data
3) Content of register(MDR) is written into the specified memory location.
INSTRUCTIONS & INSTRUCTION SEQUENCING
• A computer must have instructions capable of performing 4 types of operations:
1) Data transfers between the memory and the processor registers (MOV, PUSH,
POP, XCHG),
2) Arithmetic and logic operations on data (ADD, SUB, MUL, DIV, AND, OR,
NOT),
3) Program sequencing and control (CALL.RET, LOOP, INT),
4) I/0 transfers (IN, OUT)
REGISTER TRANSFER NOTATION (RTN)
• We identify a memory location by a symbolic name (in uppercase alphabets).
For example, LOC, PLACE, NUM etc indicate
memory locations.R0, R5 etc indicate processor
register. DATAIN, OUTSTATUS etc indicate I/O
registers.
• For example,
R<-[LOC] means that the contents of memory location LOC are transferred into
processor register R1 (The contents of a location are denoted by placing square
brackets around the name of the location). R3<-[R1]+[R2] indicates the operation
that adds the contents of registers R1 and R2 ,and then places their sum into register
R3.
• This type of notation is known as RTN(Register Transfer Notation).

ASSEMBLY LANGUAGE NOTATION

• To represent machine instructions and programs, assembly language format can be used.
• For example,
Move LOC, R1; This instruction transfers data from memory-location LOC to
processor-register R1. The contents of LOC are unchanged by the execution of this
instruction, but the old contents of register R1 are overwritten.
Add R1, R2, R3; This instruction adds 2 numbers contained in processor-registers R1
and R2, and places their sum in R3.

COMPUTER ORGANISATION Page 9

• A computer performs its task according to the program stored in memory. A program is a
collection of instructions which tell the processor to perform a basic operation like addition,
reading from keyboard etc.
• Possible locations that may be involved in data transfers are memory locations, processor
registers or registers in the I/O subsystem.

BASIC INSTRUCTION TYPES

• C=A+B; This statement is a command to the computer to add the current values of the two
variables A and B, and to assign the sum to a third variable C.
• When the program is compiled, each variable is assigned a distinct address in memory.
• The contents of these locations represent the values of the three variables
• The statement C<-[A]+[B] indicates that the contents of memory locations A and B are
fetched from memory, transferred to the processor, sum is computed and then result is stored
in memory location C.
Three-Address Instruction
• The instruction has general format
Operation Source1, Source2, Destination
• For example, Add A, B, C; operands A and B are called the source operands, C is called the
destination operand, and Add is the operation to be performed.
Two-Address Instruction
• The instruction has general format
Operation Source, Destination
• For example, Add A, B; performs the operation B<-[A]+[B].
• When the sum is calculated, the result is sent to the memory and stored in location B,
replacing the original contents of this location. This means that operand B is both a source
and a destination.
• The operation C<-[A]+[B] can be performed by the two-instruction sequence
Move B, C
Add A, C
One-Address Instruction
• The instruction has general format
Operation Source/Destination
• For example, Add A ; Add the contents of memory location A to the contents of the
accumulator register and place the sum back into the accumulator.
• Load A; This instruction copies the contents of memory location A into the accumulator and
Store A; This instruction copies the contents of the accumulator into memory location
A.
The operation C<-[A]+[B] can be performed by executing the sequence of instructions
Load A
Add B
Store C
• The operand may be a source or a destination depending on the instruction. In the Load
instruction, address A specifies the source operand, and the destination location, the
accumulator, is implied. On the other hand, C denotes the destination location in the Store
instruction, whereas the source, the accumulator, is implied.
Zero-Address Instruction
• The locations of all operands are defined implicitly. The operands are stored in a structure
called pushdown stack. In this case, the instructions are called zero-address instructions.
• Access to data in the registers is much faster than to data stored in memory locations
because the registers are inside the processor.

COMPUTER ORGANISATION Page 10

• Let Ri represent a general-purpose register. The instructions
Load A,Ri
Store Ri,A
Add A,Ri
are generalizations of the Load, Store and Add Instructions for the single-accumulator case,
in which register Ri performs the function of the accumulator.
• In processors where arithmetic operations as allowed only on operands that are in processor
registers, the C=A+B task can be performed by the instruction sequence

INSTRUCTION EXECUTION & STRAIGHT LINE SEQUENCING

• The program is executed as follows:
1) Initially, the address of the first instruction is loaded into PC (Program counter is a register
which holds the address of the next instruction to be executed)
2)Then, the processor control circuits use the information in the PC to fetch and execute
instructions, one at a time, in the order of increasing addresses. This is called straight-line
sequencing (Figure 2.8)
3) During the execution of each instruction, the PC is incremented by 4 to point to the next
instruction.
4) Executing given instruction is a two-phase procedure.
i) In fetch phase, the instruction is fetched from the memory location (whose address
is in the PC) and placed in the IR of the processor
ii) In execute phase, the contents of IR is examined to determine which operation is to
be performed. The specified operation is then performed by the processor.

COMPUTER ORGANISATION Page 11

BRANCHING
• Consider the task of adding a list of n numbers (Figure 2.10).
• The loop is a straight line sequence of instructions executed as many times as needed. It
starts at location LOOP and ends at the instruction Branch>0.
• During each pass through this loop, the address of the next list entry is determined, and that
entry is fetched and added to R0.
• Register R1 is used as a counter to determine the number of times the loop is executed.
Hence, the contents of location N are loaded into register R1 at the beginning of the program.
• Within the body of the loop, the instruction Decrement R1 reduces the contents of R1 by 1
each time through the loop.
• Then Branch instruction loads a new value into the program counter. As a result, the
processor fetches and executes the instruction at this new address called the branch target.
• A conditional branch instruction causes a branch only if a specified condition is satisfied. If
the condition is not satisfied, the PC is incremented in the normal way, and the next
instruction in sequential address order is fetched and executed.

CONDITION CODES
• The processor keeps track of information about the results of various operations. This is
accomplished by recording the required information in individual bits, called condition code
flags.
• These flags are grouped together in a special processor-register called the condition code
register (or statue register).

COMPUTER ORGANISATION Page 12

• Four commonly used flags are
→ N (negative) set to 1 if the result is negative, otherwise cleared to 0
→ Z (zero) set to 1 if the result is 0; otherwise, cleared to 0
→ V (overflow) set to 1 if arithmetic overflow occurs; otherwise, cleared to 0
→ C (carry) set to 1 if a carry-out results from the operation; otherwise cleared to 0.

ADDRESSING MODES
• The different ways in which the location of an operand is specified in an instruction are
referred to as addressing modes (Table 2.1).

IMPLEMENTATION OF VARIABLE AND CONSTANTS

• Variables & constants are the simplest data-types and are found in almost every computer
program.
• In assembly language, a variable is represented by allocating a register (or memory-
location) to hold its value. Thus, the value can be changed as needed using appropriate
instructions.
Register Mode
• The operand is the contents of a register.
• The name (or address) of the register is given in the instruction.
• Registers are used as temporary storage locations where the data in a register are accessed.
• For example, the instruction,
Move R1, R2 ;Copy content of register R1 into register R2
Absolute (Direct) Mode
• The operand is in a memory-location.
• The address of memory-location is given explicitly in the instruction.
• For example, the instruction,
Move LOC, R2 ;Copy content of memory-location LOC into register R2

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Immediate Mode
• The operand is given explicitly in the instruction.
• For example, the instruction,
Move #200, R0 ;Place the value 200 in register R0

• Clearly, the immediate mode is only used to specify the value of a source-operand.
INDIRECTION AND POINTERS
• In this case, the instruction does not give the operand or its address explicitly; instead, it
provides information from which the memory-address of the operand can be determined. We
refer to this address as the effective address(EA) of the operand.
Indirect Mode
• The EA of the operand is the contents of a register(or memory-location) whose address
appears in the instruction.
• The register (or memory-location) that contains the address of an operand is called a
pointer. {The indirection is denoted by ( ) sign around the register or memory-location}.
E.g: Add (R1),R0;The operand is in memory. Register R1 gives the effective-
address(B) of the operand. The data is read from location B and added to
contents of register R0
* To execute the Add instruction in fig (a), the processor uses the value which is in register
R1, as the EA of the operand.
* It requests a read operation from the memory to read the contents of location B. The value
read is the desired operand, which the processor adds to the contents of register R0.
* Indirect addressing through a memory location is also possible as shown in fig (b). In this
case, the processor first reads the contents of memory location A, then requests a second read
operation using the value B as an address to obtain the operand

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• In above program, Register R2 is used as a pointer to the numbers in the list, and the
operands are accessed indirectly through R2.
• The initialization-section of the program loads the counter-value n from memory-location
N into R1 and uses the immediate addressing-mode to place the address value NUM1, which
is the address of the first number in the list, into R2. Then it clears R0 to 0.
• The first two instructions in the loop implement the unspecified instruction block starting at
LOOP.
• The first time through the loop, the instruction Add (R2), R0 fetches the operand at location
NUM1 and adds it to R0.
• The second Add instruction adds 4 to the contents of the pointer R2, so that it will contain
the address value NUM2 when the above instruction is executed in the second pass through
the loop.

INDEXING AND ARRAYS

• A different kind of flexibility for accessing operands is useful in dealing with lists and
arrays.
Index mode
• The operation is indicated as X(Ri)
where X=the constant value contained
in the instruction Ri=the name
of the index register
• The effective-address of the operand is given by EA=X+[Ri]
• The contents of the index-register are not changed in the process of generating the effective-
address.
• In an assembly language program, the constant X may be given either
→ as an explicit number or
→ as a symbolic-name representing a numerical value.
* Fig(a) illustrates two ways of using the Index mode. In fig(a), the index register, R1,
contains the address of a memory location, and the value X defines an offset(also called a
displacement) from this address to the location where the operand is found.
* An alternative use is illustrated in fig(b). Here, the constant X corresponds to a memory
address, and the contents of the index register define the offset to the operand. In either case,
the effective address is the sum of two values; one is given explicitly in the instruction, and
the other is stored in a register.

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Base with Index Mode
• Another version of the Index mode uses 2 registers
which can be denoted as (Ri, Rj)
• Here, a second register may be used to contain the offset X.
• The second register is usually called the base register.
• The effective-address of the operand is given by EA=[Ri]+[Rj]
• This form of indexed addressing provides more flexibility in
accessing operands, because both components of the effective
address can be changed.

Base with Index & Offset Mode

• Another version of the Index mode uses 2 registers plus a constant,
which can be denoted as X(Ri, Rj)
• The effective-address of the operand is given by EA=X+[Ri]+[Rj]
• This added flexibility is useful in accessing multiple components inside each item in a
record, where the beginning of an item is specified by the (Ri, Rj) part of the addressing-
mode. In other words, this mode implements a 3-dimensional array.

RELATIVE MODE
• This is similar to index-mode with an exception: The effective address is determined using
the PC in place of the general purpose register Ri.
• The operation is indicated as X(PC).

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• X(PC) denotes an effective-address of the operand which is X locations above or below the
current contents of PC.
• Since the addressed-location is identified "relative" to the PC, the name Relative mode is
associated with this type of addressing.
• This mode is used commonly in conditional branch instructions.
• An instruction such as
Branch > 0 LOOP ;Causes program execution to go to the branch
target location identified by name LOOP if
branch condition is satisfied.
ADDITIONAL ADDRESSING MODES
• The following 2 modes are useful for accessing data items in successive locations in the
memory.
Auto-increment Mode
• The effective-address of operand is the contents of a register specified in the instruction
(Fig: 2.16).
• After accessing the operand, the contents of this register are automatically incremented to
point to the next item in a list.
• Implicitly, the increment amount is 1.
• This mode is denoted as
(Ri)+ ;where Ri=pointer register
Auto-decrement Mode
• The contents of a register specified in the instruction are first automatically decremented
and are then used as the effective address of the operand.
• This mode is denoted as
-(Ri) ;where Ri=pointer register
• These 2 modes can be used together to implement an important data structure called a stack.

ASSEMBLY LANGUAGE
• A complete set of symbolic names and rules for their use constitute an assembly language.
• The set of rules for using the mnemonics in the specification of complete instructions and
programs is called the syntax of the language.
• Programs written in an assembly language can be automatically translated into a sequence
of machine instructions by a program called an assembler.
• The user program in its original alphanumeric text formal is called a source program, and
the assembled machine language program is called an object program.
• Move instruction is written is
MOVE R0,SUM ;The mnemonic MOVE represents the binary
pattern, or OP code, for the operation performed by
the instruction.
• The instruction
ADD #5,R3 ;Adds the number 5 to the contents of register R3 and puts
the result back into register R3.

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ASSEMBLER DIRECTIVES
• EQU informs the assembler about the value of an identifier (Figure: 2.18).
Ex: SUM EQU 200 ; This statement informs the assembler that the
name SUM should be replaced by the value 200
wherever it appears in the program.
• ORIGIN tells the assembler about the starting-address of memory-area to place the data
block.
• DATAWORD directive tells the assembler to load a value (say 100) into
the location (say 204). Ex: N DATAWORD 100
• RESERVE directive declares that a memory-block of 400 bytes is to be reserved for data
and that the name NUM1 is to be associated with address 208.
Ex: NUM1 RESERVE 400
• END directive tells the assembler that this is the end of the source-program text.
• RETURN directive identifies the point at which execution of the program should be
terminated.
• Any statement that makes instructions or data being placed in a memory-location may be
given a label.
• The label(say N or NUM1) is assigned a value equal to the address of that location.

GENERAL FORMAT OF A STATEMENT

• Most assembly languages require statements in a source program to be written in the form:
Label Operation Operands Comment
→ Label is an optional name associated with the memory-
address where the machine language instruction produced
from the statement will be loaded.
→ The Operation field contains the OP-code mnemonic of the desired instruction
or assembler → The
Operand field contains addressing information for accessing
one or more operands, depending on the type of instruction.

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ASSEMBLY AND EXECUTION OF PRGRAMS
• Programs written in an assembly language are automatically translated into a sequence of
machine instructions by the assembler.
• Assembler program
→ replaces all symbols denoting operations & addressing-modes
with binary-codes used in machine instructions.
→ replaces all names and labels with their actual values.
→ assigns addresses to instructions & data blocks, starting at the
address given in the ORIGIN directive.
→ inserts constants that may be given in DATAWORD directives.
→ reserves memory-space as requested by RESERVE directives.
• As the assembler scans through a source-program, it keeps track of all names of numerical-
values that correspond to them in a symbol-table. Thus, when a name appears a second time,
it is replaced with its value from the table. Hence, such an assembler is called a two-pass
assembler.
• The assembler stores the object-program on a magnetic-disk. The object-program must be
loaded into the memory of the computer before it is executed. For this, a loader program is
used.
• Debugger program is used to help the user find the programming errors.
• Debugger program enables the user
→ to stop execution of the object-program at some points of
interest and
→ to examine the contents of various processor registers and
memory-location

→ The Comment field is used for documentation purposes to make

the program easier to understand.

BASIC INPUT/OUTPUT OPERATIONS

• Consider the problem of moving a character-code from the
keyboard to the processor. For this transfer, buffer-
register(DATAIN) & a status control flags(SIN) are used.
• Striking a key stores the corresponding character-code in an 8-bit buffer-register(DATAIN)
associated with the keyboard (Figure: 2.19).
• To inform the processor that a valid character is in DATAIN, a SIN is set to 1.
• A program monitors SIN, and when SIN is set to 1, the processor reads the contents of
DATAIN.
• When the character is transferred to the processor, SIN is automatically cleared to 0.
• If a second character is entered at the keyboard, SIN is again set to 1 and the process
repeats.
• An analogous process takes place when characters are transferred from the processor to the
display. A buffer-register, DATAOUT, and a status control flag, SOUT are used for this
transfer.
• When SOUT=1, the display is ready to receive a character.
• The transfer of a character to DATAOUT clears SOUT to 0.
• The buffer registers DATAIN and DATAOUT and the status flags SIN and SOUT are part
of circuitry commonly known as a device interface.

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• Following is a program to read a line of characters and display it

MEMORY-MAPPED I/O
• Some address values are used to refer to peripheral device buffer-registers such as DATAIN
and DATAOUT.
• No special instructions are needed to access the contents of the registers; data can be
transferred between these registers and the processor using instructions such as Move, Load
or Store.
• For example, contents of the keyboard character buffer DATAIN can be
transferred to register R1 in the processor by the instruction
MoveByte DATAIN,R1
• The MoveByte operation code signifies that the operand size is a byte.
• The Testbit instruction tests the state of one bit in the destination, where the bit
position to be tested is indicated by the first operand.

STACKS
• A stack is a list of data elements with the accessing restriction that elements can be added
or removed at one end of the list only. This end is called the top of the stack, and the other
end is called the bottom (Figure: 2.21).
• The terms push and pop are used to describe placing a new item on the stack and removing
the top item from the stack, respectively.
• A processor-register is used to keep track of the address of the element of the stack that is
at the top at any given time. This register is called the SP (Stack Pointer).

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• If we assume a byte-addressable memory with a 32-bit word length,
→The push operation can be implemented as
Subtract #4,SR
Move NEWITEM,(SP)
→ The pop operation can be implemented as
Move (SP),ITEM
Add #4,SP
• Routine for a safe pop and push operation as follows

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QUEUE
• Data are stored in and retrieved from a queue on a FIFO basis.
• Difference between stack and queue?
1) One end of the stack is fixed while the other end rises and falls as data are pushed
and popped.
2) A single pointer is needed to point to the top of the stack at any given time.
On the other hand, both does of a queue move to higher addresses
as data are added at the back and removed from the front. So, two
pointers are needed to keep track of the two does of the queue.
3) Without further control, a queue would continuously move through the memory of
a computer in the direction of higher addresses. One way to limit the queue to a fixed
region in memory is to use a circular buffer.

SUBROUTINES
• A subtask consisting of a set of instructions which is executed many times is called a
subroutine.
• The program branches to a subroutine with a Call instruction (Figure: 2.24).
• Once the subroutine is executed, the calling-program must resume execution starting from
the instruction immediately following the Call instructions i.e. control is to be transferred
back to the calling-program. This is done by executing a Return instruction at the end of the
subroutine.
• The way in which a computer makes it possible to call and return from subroutines is
referred to as its subroutine linkage method.
• The simplest subroutine linkage method is to save the return-address in a specific location,
which may be a register dedicated to this function. Such a register is called the link register.
• When the subroutine completes its task, the Return instruction returns to the calling-
program by branching indirectly through the link-register.
• The Call instruction is a special branch instruction that performs the following operations:
→ Store the contents of PC into link-register.
→ Branch to the target-address specified by the instruction.
• The Return instruction is a special branch instruction that performs the operation:
→ Branch to the address contained in the link-register.

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SUBROUTINE NESTING AND THE PROCESSOR STACK
• Subroutine nesting means one subroutine calls another subroutine.
• In this case, the return-address of the second call is also stored in the link-register,
destroying its previous contents.
• Hence, it is essential to save the contents of the link-register in some other location before
calling another subroutine. Otherwise, the return-address of the first subroutine will be lost.
• Subroutine nesting can be carried out to any depth. Eventually, the last subroutine called
completes its computations and returns to the subroutine that called it.
• The return-address needed for this first return is the last one generated in the nested call
sequence. That is, return-addresses are generated and used in a LIFO order.
• This suggests that the return-addresses associated with subroutine calls should be pushed
onto a stack. A particular register is designated as the SP(Stack Pointer) to be used in this
operation.
• SP is used to point to the processor-stack.
• Call instruction pushes the contents of the PC onto the processor-stack.
Return instruction pops the return-address from the processor-stack into the PC.
PARAMETER PASSING
• The exchange of information between a calling-program and a subroutine is referred to as
parameter passing (Figure: 2.25).
• The parameters may be placed in registers or in memory-location, where they can be
accessed by the subroutine.
• Alternatively, parameters may be placed on the processor-stack used for saving the return-
address • Following is a program for adding a list of numbers using subroutine with the
parameters passed through registers.

STACK FRAME
• Stack frame refers to locations that constitute a private work-space for the subroutine
(Figure:2.26).
• The work-space is
→ created at the time the subroutine is entered &
→ freed up when the subroutine returns control to the calling-program.
• Following is a program for adding a list of numbers using subroutine with the parameters
passed to stack

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• Fig: 2.27 show an example of a commonly used layout for information in a stack-frame.
• Frame pointer(FP) is used to access the parameters passed
→ to the subroutine &

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 → to the local memory-variables
• The contents of FP remains fixed throughout the execution of the subroutine, unlike stack-
pointer SP, which must always point to the current top element in the stack.
Operation on Stack Frame
• Initially SP is pointing to the address of old TOS.
• The calling-program saves 4 parameters on the stack (Figure 2.27).
• The Call instruction is now executed, pushing the return-address onto the stack.
• Now, SP points to this return-address, and the first instruction of the subroutine is executed.
• Now, FP is to be initialized and its old contents have to be stored. Hence, the first 2
instructions in the subroutine are:
Move FP,-(SP)
Move SP,FP
• The FP is initialized to the value of SP i.e. both FP and SP point to the saved FP address.
• The 3 local variables may now be pushed onto the stack. Space for local variables is
allocated by executing the instruction
Subtract #12,SP
• Finally, the contents of processor-registers R0 and R1 are saved in the stack. At this point,
the stack-frame has been set up as shown in the fig 2.27.
• The subroutine now executes its task. When the task is completed, the subroutine pops the
saved values of R1 and R0 back into those registers, removes the local variables from the
stack frame by executing the instruction.
Add #12,SP
• And subroutine pops saved old value of FP back into FP. At this point, SP points to return-
address, so the Return instruction can be executed, transferring control back to the calling-
program.

STACK FRAMES FOR NESTED SUBROUTINES

• Stack is very useful data structure for holding return-addresses when subroutines are nested.
• When nested subroutines are used; the stack-frames are built up in the processor-stack.
• Consider the following program to illustrate stack frames for nested subroutines (refer fig
no. 2.28 from text book).
The Flow of Execution is as follows:
• Main program pushes the 2 parameters param2 and param1 onto the stack and then calls
SUB1.
• SUB1 has to perform an operation & send result to the main-program on the stack
(Fig:2.28& 29).
• During the process, SUB1 calls the second subroutine SUB2 (in order to perform some
subtask).
• After SUB2 executes its Return instruction; the result is stored in register R2 by SUB1.
• SUB1 then continues its computations & eventually passes required answer back to main-
program on the stack.
• When SUB1 executes return statement, the main-program stores this answers in memory-
location RESULT and continues its execution.

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LOGIC INSTRUCTIONS
• Logic operations such as AND, OR, and NOT applied to individual bits.
• These are the basic building blocks of digital-circuits.
• This is also useful to be able to perform logic operations is software, which is done using
instructions that apply these operations to all bits of a word or byte independently and in
parallel.
• For example, the instruction
Not dst

SHIFT AND ROTATE INSTRUCTIONS

• There are many applications that require the bits of an operand to be shifted right or left
some specified number of bit positions.
• The details of how the shifts are performed depend on whether the operand is a signed
number or some more general binary-coded information.
• For general operands, we use a logical shift.
For a number, we use an arithmetic shift, which preserves the sign of the number.
LOGICAL SHIFTS
• Two logical shift instructions are needed, one for shifting left(LShiftL) and another for
shifting right(LShiftR).
• These instructions shift an operand over a number of bit positions specified in a count
operand contained in the instruction.

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ROTATE OPERATIONS
• In shift operations, the bits shifted out of the operand are lost, except for the last bit shifted
out which is retained in the Carry-flag C.
• To preserve all bits, a set of rotate instructions can be used.
• They move the bits that are shifted out of one end of the operand back into the other end.
• Two versions of both the left and right rotate instructions are usually provided.
In one version, the bits of the operand are simply rotated.
In the other version, the rotation includes the C flag.

Multiplication And Division:

Multiply Ri,Rj
Rj= [Ri]*[Rj]

Division Ri,Rj
Rj=[Ri]/[Rj]

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ENCODING OF MACHINE INSTRUCTIONS
• To be executed in a processor, an instruction must be encoded in a binary-pattern. Such
encoded instructions are referred to as machine instructions.
• The instructions that use symbolic names and acronyms are called assembly language
instructions.
• We have seen instructions that perform operations such as add, subtract, move, shift, rotate,
and branch. These instructions may use operands of different sizes, such as 32-bit and 8-bit
numbers.
• Let us examine some typical cases.
The instruction
Add R1, R2 ;Has to specify the registers R1 and R2, in addition to the OP code. If the
processor has 16 registers, then four bits are needed to identify each
register. Additional bits are needed to indicate that the Register
addressing-mode is used for each operand.
The instruction
Move 24(R0), R5 ;Requires 16 bits to denote the OP code and the
two registers, and some bits to express that the
source operand uses the Index addressing
mode and that the index value is 24.
• In all these examples, the instructions can be encoded in a 32-bit word (Fig 2.39).
• The OP code for given instruction refers to type of operation that is to be performed.
• Source and destination field refers to source and destination operand respectively.
• The "Other info" field allows us to specify the additional information that may be needed
such as an index value or an immediate operand.
• Using multiple words, we can implement complex instructions, closely resembling
operations in high-level programming languages. The term complex instruction set computers
(CISC) refers to processors that use
• CISC approach results in instructions of variable length, dependent on the number of
operands and the type of addressing modes used.
• In RISC (reduced instruction set computers), any instruction occupies only one word.
• The RISC approach introduced other restrictions such as that all manipulation of data must
be done on operands that are already in processor registers.
Ex: Add R1,R2,R3
• In RISC type machine, the memory references are limited to only Load/Store operations.

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