Pcie Debug Details

I NV E N TI V E CONFIDENTIAL
PCI Express Purespec

Debug introduction
BEST DEBUG PRACTICES
2
PureSpec Debug solution - Overview
• Dump debug information with minimum effect on

performance.
• Allow different granularity of debug info.
• Debug aids for Purespec is constructed in layered
approach.
• Debug control and enablement is done via .denalirc
mechanism.
3
Overview (Cont.)
The big picture
• Performance report
System • Helps system integrators to better utilize the PCIe.
• Packet Tracker
Link • High level overview of traffic on the link. Can be customized
• Trace\History file
• A cycle accurate log file that keeps everything (Purespec wise) that happened
Protocol in the simulation.
• README file entry for each test.

Test • XML description of most of the tests, describing each step
4
Overview (Cont.)
.denalirc semantics
• All available parameters are specified in section 5.3.3 in

the user guide.
• Has an additive nature.
• Does not check for typos!
• Can be viewed from the simulation trace file.
5
Performance Monitor • Packet Tracker

• High level overview of traffic on the link. Can be customized
Link
• A cycle accurate log file that keeps everything (Purespec wise) that
Protocol happened in the simulation.

• Gives hints on usage of the link

• Helps system integrators to better utilize the PCIe link.
• Measure for all instances from the .denalirc :
perfLogOn 1
• Alternatively start the measurement on port and time
r1
basis by writing 1 to register bit
PCIE_REG_DEN_PERF_CTRL[0] (enable)
• Can query the performance data during simulation.
• The report will be printed to the simulation log at the end
of the simulation
6
Slide 6
r1 is it most?
ronenb, 10/23/2013
r2
Performance Monitor (Cont.)

Measurement time
Time spent in each

“State”
Only Mem data Pkts transmission

Inbounbd = RX in each Layer
Outbound = TX
Only DLL generated

DLLPs
7
Slide 7
r2 latency - explain how measured

need to explain # of records
consider give more detailed reports including TX and stress report with testcase that is more representive
recommend which kind of tesrs should be used for perf monitoring

ronenb, 10/24/2013
Packet Tracker • Packet Tracker

Link

• Shows TLPs, DLLPs and OSs.

• Controlled from the .denalirc :
PcieTransLogFile PciePackets.log
Those are the
PcieTransLogTypes tlp dllp os valid options
8
Packet Tracker (Cont.)
OS packets
SKIP , TS1..
IDLE etc
9
r19
Completer id
Packet Tracker (Cont.)
CPL status Poisoned

or transaction
message
Only for For DLLP 16b
Each line for different
FC DLLP For TLP 32b
TLP pkt type:
Mem
Message
CFG (register number) MR-IOV
CPL r6 info
obff
10
Slide 10
r6 what is message
ronenb, 10/23/2013
r19 what link | lane | nfts | drate.. means

ronenb, 10/24/2013
History File • Packet Tracker

Link


HistoryFile pcie.his
Add History file info
HistoryDebug On to denali.trc file
• Very detailed protocol information with timestamps.
11
History File (Cont.)
State transition
Source (DUT/VIP)
Payload
Time
12
Trace File

TraceFile pcie.trc
or
Tracefile -gzip pcie.trc.gz
• Has all the information from pin level, State machines,
packets, lanes, registers, callbacks etc.
• Serves as the main platform for support.
• After gaining confidence should be the main tool for
debug
13
Debugging With Trace File
Trace Debug information
Debug: .denalirc Settings
• Captures all .denalirc settings used during the simulation
• grep “ V “ denali.trc
:
V PcieTLBypassInit 0
V PciePhyScrambleData 1
V PcieTransLogFile denali.log
V TraceFile denali.trc
:
:
Debug: SOMA File
• For each Denali model, captures:
o SOMA file used
o All the contents of the SOMA file
o grep “ f “ denali.trc
M f /projects/ep_rc_x1/B0/tb_top/soma/pcie_rc_mon_pipe.spc
“M” – Device Instance-id (e.g. testbench.i0)

“f” – Represents soma file instantiation followed by file name
14
Introduction
• Very useful to debug and reproduce issues offsite
• Stores sufficient information to create a test-case for a particular
issue
Trace File Header

• Contains HDL simulator, operating system and PureSpec version
information used for simulation.
#-trace-
Denali Purespec, MMAV Version 3.2.057
Copyright (c) Denali Software, Inc., 1996 - 2008
# THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL AND
# PROPRIETARY INFORMATION OF DENALI SOFTWARE, INC. UNAUTHORIZED USE,
# VIEWING, DISCLOSURE, OR DISTRIBUTION IS STRICTLY PROHIBITED.
# Library: PLI
# Simulator: ncsim 06.20-p001
# System: Linux lc-sj1-1101 2.6.9-42.0.3.ELsmp #1 SMP Mon Sep 25 17:24:31 EDT 2006 x86_64
# RH Release:Red Hat Enterprise Linux WS release 4 (Nahant Update 4)
# BuildData: c441374dde594ec0a2b7100dbc5b26d3 2008/09/08 23:53:35
15
Debug: PCIe instance mapping
• Captures all .denalirc settings used during the simulation
• Grep –i “ i “ denali.trc
i – model instance id
I – denali memory instance id
0 i tb.DUT
1 I tb.DUT(cfg_0_0) @[tb.DUT]
2 I tb.DUT(mem_0_0_0) @[tb.DUT]
3 I tb.DUT(mem_0_0_6) @[tb.DUT]
4 I tb.DUT(vmem_0_0_0) @[tb.DUT]
5 I tb.DUT(vmem_0_0_2) @[tb.DUT]
6 i tb.ep_monitor
7 I tb.ep_monitor(cfg_0_0) @[tb.denali_monitor]
8 I tb.ep_monitor(mem_0_0_0) @[tb.denali_monitor]
9 I tb.ep_monitor(mem_0_0_6) @[tb.denali_monitor]
A I tb.ep_monitor(vmem_0_0_0) @[tb.denali_monitor]
B I tb.ep_monitor(vmem_0_0_2) @[tb.denali_monitor]
C i tb.rc
D I tb.rc(cfg_0_0) @[tb.denali_model]
E I tb.rc(mem_0_0_0) @[tb.denali_model]
F I tb.rc(mem_RCMEM)
G I tb.rc(p_0.cfg_0_0) @[tb.denali_model]
H I tb.rc(mem_msi_64) @[tb.denali_model]
I I tb.rc(mem_RCMEM_0) @[tb.denali_model]
J I tb.rc(mem_RCMEM_1) @[tb.denali_model]
K I tb.rc(mem_RCMEM)
16
:
Trace File (Cont.)
LTSSM
H mean change
info appear at History file
6 H Detected[cfg_1_0] [] PL_LTSSM_STATE [PCISIG]. [port_1] LTSSM state

Rx_L0s.FTS/Tx_L0 => L0
C H Detected[cfg_0_0] [] TL_WRREG_SAME [PCISIG]. cfg_0_0 WrReg: [Express Device
Status] addr[5](transPend):0x05a value:0x1
C H Debug: Cycle 23661 RxData[0:3] { 00 00 00 00 }
C H Debug: Cycle 23661 RxData[0:3] { 00 00 00 00 } Reg. value
F E PCLK 1 change
F H Debug: Cycle 23661 RxData[0:3] { 00 00 00 00 }
F H Debug: Cycle 23661 RxData[0:3] { 00 00 00 00 }
I E PCLK 1
Pin value
I H Debug: Cycle 23660
change RxData[0:3] { 00 00 00 00 }
I H Debug: Cycle 23660 RxData[0:3] { 00 00 00 00 }
Instance
Payload
17
grep / egrep reminder
() needed because .* that precede
^ - start with
egrep "^0.*DLLP.*(ACK|NAK)" denali.trc

.* - any character in between | - match any of the alternative
Disclaimer
Most of the grep result examples at this presentation were trunked to fit the slide size
Please try those grep and see the full results!
18
PCIE HIERARCHY AND
INITIALIZATION PROCESS
19
Hierarchy of PCIe Topology
The hier[cfg] message shows whether

grep hier denali.his a given port in a device is a downstream
port or upstream port function. Unclaimed RCMEM
tb.ep_monitor 96 ns Debug: hier[mem]: cfg_0_0.bar_0[0x00000000] [23b_Mem32]
can be disabled in SOMA
tb.ep_monitor 96 ns Debug: hier[mem]: cfg_0_0.bar_ERom[0x00000000] [20b_ERom] [not_enabled]
tb.ep_monitor 96 ns Debug: hier[mem]: cfg_0_0.vbar_0[0x00000000_00000000] [12b_Mem64] [not_enabled]
tb.ep_monitor 96 ns Debug: hier[mem]: cfg_0_0.vbar_2[0x00000000_00000000] [12b_Mem64] [not_enabled]
tb.ep_monitor 96 ns Debug: hier[cfg]: cfg_0_0 [reqid:0x0000 ExpressEP_UpPort]
tb.rc 4492 ns Debug: hier[mem]: cfg_0_0.bar_0[0x01000000] [20b_Mem32]
tb.rc 4492 ns Debug: hier[mem]: cfg_0_0.bar_RCMEM[0x00000000_00000000] [1b_PfMem64]
tb.rc 4492 ns Debug: hier[mem]: [0x0000000000100000, 0x00000000007fffff] ==> [0x0000000000000000, 0x00000000006fffff]
tb.rc 4492 ns Debug: hier[mem]: [0x0000000001100040, 0xffffffffffffffff] ==> [0x0000000000700000, 0xffffffffff5fffbf]
tb.rc 4492 ns Debug: hier[mem]: cfg_0_0.bar_MSI64[0x00000000_01100000] [6b_MSI64]
tb.rc 4492 ns Debug: hier[mem]: Mem32[0x00000000, 0x00ffffff]
tb.rc 4492 ns Debug: hier[mem]: p_0.cfg_0_0.bar_0[0x00800000] [23b_Mem32] The hier[cfg] message shows also the
tb.rc 4492 ns Debug: hier[mem]: p_0.cfg_0_0.bar_ERom[0x00000000] [20b_ERom] reqid associated with this
tb.rc 5016 ns Debug: hier[cfg]: p_0.cfg_0_0 [reqid:0x0100 ExpressEP_UpPort]
tb.rc 5016 ns Debug: hier[cfg]: cfg_0_0 [reqid:0x0000 Root_DownPort]
device/port/function
tb.rc 5016 ns Debug: hier[br]: cfg_0_0 [bus_0(1 : 1)]
tb.ep_monitor 50219800 ps Debug: hier[mem]: cfg_0_0.bar_0[0x00800000] [23b_Mem32]
tb.ep_monitor 50219800 ps Debug: hier[mem]: cfg_0_0.bar_ERom[0x00000000] [20b_ERom]
tb.ep_monitor 50219800 ps Debug: hier[mem]: cfg_0_0.vbar_0[0x00000000_00000000] [12b_Mem64] [not_enabled]
tb.ep_monitor 50219800 ps Debug: hier[mem]: cfg_0_0.vbar_2[0x00000000_00000000] [12b_Mem64] [not_enabled]
The hier[mem] message shows the

Finalized EP mapping memory resource defined by BAR, MSI,
and Expansion Rom BAR in the design.
20
r7
Hierarchy of PCIe Topology
[port=0, function=0] Requester ID(bus,device,func)

• Configuration Instance:
• tb.ep 3876 ns Debug: hier[cfg]: cfg_0_0 [reqid:0x0018
ExpressEP_UpPort]
EP UpstreamPort
[port=0, function=1] BAR 0 BAR Start Addr
• BAR Instance:
• tb.ep 8 ns Debug: hier[mem]: cfg_0_1.bar_0[0x00400000]
[10b_Mem32]
10 bit size; 32b addr Memory Non-prefechable
32b addr Memory Used addr range

• Memory Instance:
• tb.rc 3900 ns Debug: hier[mem]: Mem32[0x00000000,
0x010fffff]
21
Slide 21
r7 add RC shadow space example

maybe explain in prev slide
ronenb, 10/23/2013
r5
BAR Registers Access and Timings
grep “BAR_0” denali.his

tb.ep_monitor 0 ns Detected[cfg_0_0] [] TL_WRREG_SAME [PCISIG]. cfg_0_0 WrReg: [BAR_0] addr:0x010
value:0x00000000
tb.ep_monitor 231800 ps Detected[cfg_0_0] [] TL_WRREG_SAME [PCISIG]. cfg_0_0 WrReg: [BAR_0] addr:0x010
value:0xff800000
tb.rc 260 ns Detected[cfg_0_0] [] TL_WRREG_DIFF [PCISIG]. p_0.cfg_0_0 WrReg: [BAR_0] addr:0x010 value:0xffffffff
[written:0x00000000]
tb.rc 616 ns Detected[cfg_0_0] [] TL_WRREG_SAME [PCISIG]. p_0.cfg_0_0 WrReg: [BAR_0] addr:0x010 value:0xff800000
tb.rc 4492 ns Detected[cfg_0_0] [] TL_WRREG_SAME [PCISIG]. p_0.cfg_0_0 WrReg: [BAR_0] addr:0x010 value:0x00800000
value:0x00800000
value:0x00800000
value:0x00800000
TL_WRREG_DIFF: Certain registers may not be written with the exact value specified by
the write command due to access types of one or more bits
TL_WRREG_SAME: The exact value was written
grep for “Denali BAR” will get denali internal bar registers. Check at the User manual
what can be done with this register!
22
Slide 22
r5 grep BAR
why each write appear so many times

how can see final bar configuration?
mention that denali BAR is an internal register
does it appear in backdoor access to registers?
what does cfg_0_0 mean ? in the rc line
need to add kind of story explnations on those writes, explain the shadow cfg etc , explain the _DIFF
ronenb, 10/24/2013
Register Writes (WrReg)
• grep WRRREG denali.his

• shows the details of all register writes. The message shows the Register
Name, the PCI-Express specified address of the register, and the value to
be written.
• Include also DENALI model internal registers
• Appear for CfgWr/Rd access , user backdoor acess , model internal
access.
Register name Configuration space
tb.ep_monitor 4547800 ps Detected[cfg_0_0] [] TL_WRREG_SAME [PCISIG].
cfg_0_0 WrReg: [BAR_0] addr:0x010 value:0x00800000
Written value
tb.ep_monitor(cfg_0_0) 4547800 ps SIM WRITE

40f+0 00800000
• grep SIM WRITE denali.his
• SIM WRITE is the actual write to PureSpec memory resources. It shows both the
address and the data value written to memory location. Since the address is for
PureSpec memory, the address value for registers may not correspond to the exact
23
PCI-Express address. The address mapping can be found in denaliPcieTypes.v for
verilog use or api_pcie.h for use with the DDVAPI.
Register Writes (WrReg)
User backdoor access
• User writes to different registers
Long name as appear in the
• grep mmwriteword denali.trc REG description
C mmwriteword 7 REG_DEN_LN_SKEW laneNum=1,op=1,param=0,value=0

6 H Detected[cfg_0_0] [] TL_WRREG_SAME [PCISIG]. cfg_0_0 WrReg: [Denali Lane Skew]
addr[31:9](value):0x1cac value:0x000000
Same name as appear at reg enum

without leading PCIE keyword
24
Capabilities query
r12
• Keyword “capability”
tb.ep 0 ns Detected[cfg_0_0] [] TL_CFG_NEWCAP [PCISIG]. [cfg_0_0] capability:
Type0 Header [0x00,0x3f] next=>0x40
Power Management [0x40,0x47] next=>0x48
PCI Express [0x48,0x5b] next=>0x00
tb.rc 0 ns Detected[cfg_0_0] [] TL_CFG_NEWCAP [PCISIG]. [cfg_0_0] capability:
Type1 Header [0x00,0x3f] next=>0x40
Power Management [0x40,0x47] next=>0x48
PCI Express [0x48,0x6b] next=>0x00
tb.rc 0 ns Detected[cfg_0_0] [] TL_CFG_NEWCAP [PCISIG]. [p_0.cfg_0_0]
capability: Type0 Header [0x00,0x3f] next=>0x40
tb.rc 0 ns Detected[cfg_0_0] [] TL_CFG_NEWCAP [PCISIG]. [p_0.cfg_0_0]
capability: Power Management [0x40,0x47] next=>0x48
25
Slide 25
r12 why i get all this in time 0

try to run without any bypass
ronenb, 10/23/2013
Initialization process
Device active
The only that count
is the RC !!!
r14
• grep "Device state : ACTIVE" denali.his
tb.ep_monitor 96 ns Debug: ExpressEP Device state :
ACTIVE
tb.rc 5016 ns Debug: RootComplex Device state : ACTIVE
• This is the starting point when you see there is no traffic transmitted
between PCIe components.
• Later need to check the below in descending order : Check where stuck
– egrep "Port Function state" denali.his at enumeration
need to reach END
– egrep “TL state” denali.his
Make sure reach
– egrep "DLCMSM state" denali.his to Normal
– egrep "LTSSM state" denali.his
Make sure
reach to
Active
Make sure
reach to
26 L0
Slide 26
r14 add somthing about electrical idle

ronenb, 10/23/2013
Enumration state Can combine together
egrep "Port Function state" denali.his with BAR_ and
tb.rc 92 ns Debug: cfg_0_0[0_0_0]: Port Function state BEGIN => POLL_DEVICE capability grep
tb.rc 208 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state BEGIN => HEADER_TYPE
tb.rc 208 ns Debug: cfg_0_0[0_0_0]: Port Function state POLL_DEVICE => SET_BARS_BEGIN
tb.rc 208 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state HEADER_TYPE => WR_1S_BARS
tb.rc 460 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state WR_1S_BARS => COMMON_HEADER
tb.rc 1196 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state COMMON_HEADER => CAP_BEGIN
tb.rc 1252 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state CAP_BEGIN => CAP_END
tb.rc 1308 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state CAP_END => CAP_BEGIN
r18
tb.rc 3660 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state CAP_BEGIN => VC_BEGIN
tb.rc 3820 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state VC_BEGIN => VC_ARB
tb.rc 3980 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state VC_ARB => VC_PORT_ARB
tb.rc 3984 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state VC_PORT_ARB => CAP_END
tb.rc 4492 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state CAP_END => SET_BARS_BEGIN
tb.rc 4492 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state SET_BARS_BEGIN => ASSIGN_BARS
tb.rc 4492 ns Debug: cfg_0_0[0_0_0]: Port Function state SET_BARS_BEGIN => ASSIGN_BARS
tb.rc 4492 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state ASSIGN_BARS => SET_BARS_END
tb.rc 4492 ns Debug: cfg_0_0[0_0_0]: Port Function state ASSIGN_BARS => SET_BARS_END
tb.rc 4496 ns Debug: cfg_0_0[0_0_0]: Port Function state SET_BARS_END => FLUSHQ
tb.rc 5012 ns Debug: cfg_0_0[0_0_0]: Port Function state FLUSHQ => END
tb.rc 5012 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state SET_BARS_END => FLUSHQ
tb.rc 5016 ns Debug: p_0.cfg_0_0[1_0_0]: Port Function state FLUSHQ => END
27
Slide 27
r18 explain about differen cfg_space of rc

ronenb, 10/24/2013
TL state
grep “TL state” denali.his
tb.ep_monitor 0 ns Debug: TL state[UpPort_0] <undefined> => Idle

tb.ep_monitor 0 ns Debug: TL state[UpPort_0] Idle => DL_Down
tb.ep_monitor 0 ns Debug: TL state[UpPort_0] DL_Down => Idle
tb.rc 0 ns Debug: TL state[DownPort_0] <undefined> => Idle
tb.rc 0 ns Debug: TL state[DownPort_0] Idle => DL_Down
tb.rc 0 ns Debug: TL state[DownPort_0] DL_Down => Idle
tb.rc 92 ns Debug: TL state[DownPort_0] Idle => DL_Up
tb.rc 92 ns Debug: TL state[DownPort_0] DL_Up => Normal
tb.ep_monitor 95800 ps Debug: TL state[UpPort_0] Idle => DL_Up
tb.ep_monitor 95800 ps Debug: TL state[UpPort_0] DL_Up => Normal
tb.rc 5016 ns Debug: TL state[RootPort_0] => Normal
28
DL state
• grep "DL.*state" denali.his
tb.ep_monitor 0 ns Debug: DL[port_0] : DLCMSM state : <Undefined> =>
Inactive
tb.ep_monitor 0 ns Debug: DL[port_0] : state unknown => DL_Down
tb.ep_monitor 0 ns Debug: DL[port_0] : DLCMSM state : Inactive => Init
tb.rc 0 ns Debug: DL[port_0] : DLCMSM state : <Undefined> => Inactive
tb.rc 0 ns Debug: DL[port_0] : state unknown => DL_Down
tb.rc 30 ns Debug: DL[port_0] : DLCMSM state : Inactive => Init
tb.ep_monitor 75800 ps Debug: DL[port_0] : state DL_Down => DL_Up
tb.rc 80 ns Debug: DL[port_0] : state DL_Down => DL_Up
tb.rc 92 ns Debug: DL[port_0] : DLCMSM state : Init => Active
tb.ep_monitor 95800 ps Debug: DL[port_0] : DLCMSM state : Init => Active
29
LTSSM state The first L0
is important
• grep “LTSSM state” denali.his

(presented only for RC)
tb.rc 0 ns Detected[cfg_0_0] [] PL_LTSSM_STATE [PCISIG]. [port_0] LTSSM state =>
Detect.Entry
tb.rc 30 ns Detected[cfg_0_0] [] PL_LTSSM_STATE [PCISIG]. [port_0] LTSSM state
Detect.Entry => Detect.Quiet
Detect.Quiet => L0
tb.rc 12304 ns Detected[cfg_0_0] [] PL_LTSSM_STATE [PCISIG]. [port_0] LTSSM state L0 =>
Rx_L0s.Entry/Tx_L0
tb.rc 12316 ns Detected[cfg_0_0] [] PL_LTSSM_STATE [PCISIG]. Toggle
[port_0] LTSSM state between
Rx_L0s.Entry/Tx_L0 => Rx_L0s.Idle/Tx_L0 IDLE and L0
tb.rc 12360 ns Detected[cfg_0_0] [] PL_LTSSM_STATE [PCISIG]. [port_0] LTSSM state which is OK
Rx_L0s.Idle/Tx_L0 => Rx_L0s.Idle/Tx_L0s.Entry
Rx_L0s.Idle/Tx_L0s.Entry => Rx_L0s.Idle/Tx_L0s.Idle
Rx_L0s.Idle/Tx_L0s.Idle => Rx_L0s.Idle/Tx_L0s.FTS
Rx_L0s.Idle/Tx_L0s.FTS => Rx_L0s.FTS/Tx_L0s.FTS
Rx_L0s.FTS/Tx_L0s.FTS => Rx_L0s.FTS/Tx_L0
Rx_L0s.FTS/Tx_L0 => L0
30
Full LTSSM grep
grep LTSSM denali.his

will give more info like state change reason TS1 ,TS2 order set
counters etc
tb.rcModel 11630403350 fs Debug: [port_0] LTSSM reason [all lanes RX 8 matching TS1/TS2 with
speed_change bit equals directed_speed_change] => Recovery.RcvrCfg
tb.rcModel 11906631250 fs Detected[cfg_0_0] [] PL_LTSSM_TS2_RX [PCISIG]. [port_0] received

TS2 (17 of 8) in Recovery.RcvrCfg
tb.rcModel 11906631250 fs Detected[cfg_0_0] [] PL_LTSSM_TS2_TX [PCISIG]. [port_0]

transmitted TS2 (16 of 16) in Recovery.RcvrCfg
tb.rcModel 65429849050 fs Debug: [port_0] LTSSM reason [RX-IDL] => Rx_L0s.Entry/Tx_L0s.Idle
31
Power Management (PM)
• grep “PM” denali.his

tb.ep 0 ns Debug: PM:Dstate(cfg_0_0) UNKNOWN ==>
D0uninit
tb.ep 3636 ns Debug: PM: Changing current state to L0
tb.ep 3880 ns Debug: PM:Dstate(cfg_0_0) D0uninit ==>
D0active
tb.ep 3880 ns Detected[cfg_0_0] [] TL_WRREG_SAME
[PCISIG]. cfg_0_0 WrReg: [Denali PM Status and Control]
addr[7:4](deviceState):0x1504 value:0x2
32
PACKETS FLOW
33
Requests and Completions
CMPL 2
CMPL 1
CMPL
REQ
REQ
TL TL
DLL DLL
PL PL
TX RX TX RX
34 8/17/2009 Cadence Confidential: Cadence Internal Use Only

Recap – Good TLP/DLLP
TLP
REQ
TL TL
TLP ACK
DLL DLL
Seq CRC
PL PL
Frm
Frm
TX RX TX RX
35 8/17/2009 Cadence Confidential: Cadence Internal Use Only

TLP – DLLP – recap – cont’
Does any TLP REQ answered No, only non - posted TLPs like:
with CMPL pkt? Cfg , Mrd , IO
Does DLLP layer send No, one DLLP packet can target
ACK\NAK for each TLP pkt? multiple TLPs
Does DLLP layer send Yes! CMPL protected by

ACK\NAK for TLP– CMPL pkts? DLLP like any other TLP
How can I Bind between REQ-CMPL: using req_id + Tag

REQ and CMPL? TLP-ACK\NAK : seq_num
TLP and ACK\NAK?
36
Debugging Packet Flow
• start with the Packet Tracker

r15
• Can grep using the same callback names see next
slide as reminder for available callbacks.
See 11.1.1 Data Packet Callback Reasons at the
user manual
• All callbacks are recorded regard less the
setCallback status
• User add pkts (using transAdd) will firstly shown at
TL_user_queue_exit and not
TL_user_queue_enter!
• User initiated pkts will have “User” keyword along
near the callback name (in all TX callbacks)
• While grep don’t forget to trunk the PCIE_CB from
the callback name
37
Slide 37
r15 why discarded
how connect pkts in the several layers etc and completion retry buffer etc maybe pointer to the manual
explain about User indication at the RC etc

ronenb, 10/24/2013
Debugging Packet Flow – continue
• grep Discard denali.his

r22
• Find discarded pkts.
• grep “Error:” denali.his
• Look for pkts with errors which are not going to
be transmitted
• Use completion status to understand if pkt delivered
correctly (SC)
38
Slide 38
r22 why discarded
how connect pkts in the several layers etc and completion retry buffer etc maybe pointer to the manual
explain about User indication at the RC etc

ronenb, 10/24/2013
TLPs in Transaction log
RC sent Mwr TLP follow by MRd TLP

both with req_id = 0x0000 ,
seq id =0x63 , 0x64
EP sent CPld for the MRd TLP

req_id match and status SC
this TLP sent wit seq_id = 0x63
EP sent one ACK for both MWr , MRd TLPs
RC sent ACK for the CPLd TLP
39
Packet Callback Diagram
TL_user_queue_enter
TX Side RX side
TL process
User Queue
TL_user_queue_exit
TL_user_queue_exit TL_Rx_packet
TL_transmit_queue_enter
TL_api_queue_exit
TL_transmit_queue_enter
TL process
Transmit Queue API Queue
TL_TX_completion_queue_enter TL_api_queue_enter
Ordering checks
TL_transmit_queue_exit TL_RX_completion_queue_enter
TL_receive_queue_exit
Completion Queue
Completion Queue
TL Receive Queue
TL_ Tx
TL_TX_packet
_packet TL_to_DL
TL_to_DL TL_TX_completion_queue_exit, TL_Rx_packet
TL_TX_completion_queue_exit,
TL_RX_completion_queue_exit TL_receive_queue_enter
TL_RX_completion_queue_exit
DL_to_TL DL_to_TL
DL_ Tx _retry_buffer_enter
DL_TX_retry_buffer_enter
DL_ Tx _queue_enter
DL_Rx_queue_enter
DL_ Tx _retry_buffer_exit
DL_TX_retry_buffer_exit DL_Rx_queue_exit
DL Tx Queue Retry
RetryBuffer
Buffer Queue DL Rx Queue
DL DL_ Tx _queue_exit DL_Rx_queue_exit

DL_Rx_queue_enter
DL_to_PL DL_ Tx
DL_TX_retry_buffer_purge
_retry_buffer_purge
DL_to_PL
PL_to_DL
PL process PL process
PL
PL_TX_start_packet PL_RX_start_packet
40
TX/TX_ PL_TX_end_packet PL_RX_end_packet RX/RX_
Packet Callback information
example
grep "MRd.*User" denali.his
tb.rc 50176 ns Debug: [port_0] TL_user_queue_exit TLP [MRd_32] User [addr:0x00d534e4
reqId:0x0000 tag:-- len:28 fbe:1000 lbe:0011 tc:0 td:0 ep:0 attr:0] [Qsize:0]
At this point both User and model gen
tb.rc 50176 ns Debug: [port_0] TL_transmit_queue_enter TLP [MRd_32] User [addr:0x00d534e4 Pkts will appear
reqId:0x0000 tag:0] [Qsize:2 PLsize:7 tc0.Qsize:2] Add valid Tag for non-posted pkts
tb.rc 50192 ns Debug: [port_0] TL_TX_completion_queue_enter TLP [MRd_32] User
[addr:0x00d534e4 reqId:0x0000 tag:0] [Qsize:1]
tb.rc 50192 ns Debug: [port_0] TL_transmit_queue_exit TLP [MRd_32] User [addr:0x00d534e4
reqId:0x0000 tag:0] [Qsize:0 PLsize:0 tc0.Qsize:0] A TLP passed the Flow Control gating
tb.rc 50192 ns Debug: [port_0] TL_TX_packet TLP [MRd_32] User [addr:0x00d534e4 functions and TLP ordering rules,
reqId:0x0000 tag:0 len:28 fbe:1000 lbe:0011 tc:0 td:0 ep:0 attr:0] ready to be transmitted through DL.
tb.rc 50192 ns Debug: [port_0] TL_to_DL TLP [MRd_32] User [addr:0x00d534e4 reqId:0x0000
tag:0 len:28 fbe:1000 lbe:0011 tc:0 td:0 ep:0 attr:0] If the __error field does not have an error ID,
this indicates that the TLP has been
tb.rc 50192 ns Debug: [port_0] DL_TX_retry_buffer_enter DLP[seq:100 crc:0x60a95b53]
successfully processed by the TL
[MRd_32] User [addr:0x00d534e4 reqId:0x0000 tag:0]
tb.rc 50192 ns Debug: [port_0] DL_TX_queue_enter DLP[seq:100 crc:0x60a95b53] [MRd_32]
User [addr:0x00d534e4 reqId:0x0000 tag:0 len:28 fbe:1000 lbe:0011 tc:0 td:0 ep:0 attr:0]
tb.rc 50216 ns Debug: [port_0] DL_TX_queue_exit DLP[seq:100 crc:0x60a95b53] [MRd_32] User
[addr:0x00d534e4 reqId:0x0000 tag:0]
A TLP has a valid TLP sequence number
tb.rc 50216 ns Debug: [port_0] DL_to_PL DLP[seq:100 crc:0x60a95b53] [MRd_32] User A DLLP has the
and CRC assigned.
[addr:0x00d534e4 reqId:0x0000 tag:0 len:28 fbe:1000 lbe:0011 tc:0 td:0 ep:0 attr:0]
correct LCRC assigned.
tb.rc 50216 ns Debug: [port_0] PL_TX_start_packet PLP[seq:100 crc:0x60a95b53] [MRd_32] User
[addr:0x00d534e4 reqId:0x0000 tag:0]
tb.rc 50224 ns Debug: [port_0] PL_TX_end_packet PLP[seq:100 crc:0x60a95b53] A packet has[MRd_32] User
been transmitted
[addr:0x00d534e4 reqId:0x0000 tag:0 len:28 fbe:1000 lbe:0011 tc:0 td:0 ep:0 attr:0]the Link.
through
Packet Callback information
example - receive view
tb.ep_monitor 50231800 ps Debug: [port_0] DL_to_TL TLP [MRd_32] [addr:0x00d534e4

reqId:0x0000 tag:0 len:28 fbe:1000 lbe:0011 tc:0 td:0 ep:0 attr:0]
tb.ep_monitor 50231800 ps Debug: [port_0] TL_receive_queue_enter TLP [MRd_32] At this point recognize it’s TLP MRd
Before[beforeQsize:0]
[addr:0x00d534e4 reqId:0x0000 tag:0 len:28 fbe:1000 lbe:0011 tc:0 td:0 ep:0 attr:0] we will have all PL-DL callbacks
tb.ep_monitor 50231800 ps Debug: [port_0] TL_receive_queue_exit TLP [MRd_32]
[addr:0x00d534e4 reqId:0x0000 tag:0 len:28 fbe:1000 lbe:0011 tc:0 td:0 ep:0 attr:0] [beforeQsize:1]
tb.ep_monitor 50231800 ps Debug: [port_0] TL_api_queue_enter TLP [MRd_32] [addr:0x00d534e4
reqId:0x0000 tag:0 len:28 fbe:1000 lbe:0011 tc:0 td:0 ep:0 attr:0] [beforeQsize:0]
tb.ep_monitor 50231800 ps Debug: [port_0] TL_RX_packet TLP [MRd_32] [addr:0x00d534e4
reqId:0x0000 tag:0 len:28 fbe:1000 lbe:0011 tc:0 td:0 ep:0 attr:0]
tb.ep_monitor 50231800 ps Debug: [port_0] TL_RX_completion_queue_enter TLP [MRd_32]
tb.ep_monitor 50231800 ps Debug: [port_0] TL_api_queue_exit TLP [MRd_32] [addr:0x00d534e4
reqId:0x0000 tag:0 len:28 fbe:1000 lbe:0011 tc:0 td:0 ep:0 attr:0] [beforeQsize:1]
tb.ep_monitor 50475800 ps Debug: [port_0](accPL:112) TL_RX_completion_queue_exit TLP
[MRd_32] [addr:0x00d534e4 reqId:0x0000 tag:0] [Qsize:0]
tb.rc 50480 ns Debug: [port_0](accPL:112) TL_TX_completion_queue_exit TLP [MRd_32] User
tb.rc 50660 ns Debug: [port_0](accPL:112) DL_TX_retry_buffer_purge PLP[seq:100
crc:0x60a95b53] [MRd_32] User [addr:0x00d534e4 reqId:0x0000 tag:0]
Since ACK was received the pkt purged
From the retry buffer , otherwise it would
Have “exit”
42
User Packet Flow
where is my packet?
• grep "TL_user.*_exit.* User" denali.his

tb.denali_model 50004 ns Debug: [port_0] TL_user_queue_exit TLP [MWr_32] User [addr:0x00a4cbec reqId:0x0000
len:32 fbe:1000 lbe:0111 tc:0 td:0 ep:0 attr:0 pl:0xb40888b4 ...] [Qsize:2]
• If doesn’t exist:
• Validate that there were actually transAdd , check ipg
grep "dentransset.*DENALI_ARG_PCIE__pkt_type" denali.trc
C dentransset 527 DENALI_ARG_PCIE__pkt_type 1 DENALI_ARG_PCIE__error_control_count 0
DENALI_ARG_PCIE__ipg 2533130092 DENALI_ARG_PCIE__user_data 0 DENALI_ARG_PCIE__pkt_bytecnt 0
DENALI_ARG_PCIE__delay 3233835158 DENALI_ARG_PCIE__block_info 0
• If do exit user queue:

grep “Error:” denali.his
tb.denali_model 50004 ns Error: Detected[cfg_0_0] (TX) [NONFATAL-
UnsupportedRequest] TL_TLP_ADNON_1 [PCISIG]. Request MWr_32 with address
[0x3b23ff44] refers to a non-existing or out-of-range Memory/IO device, reject the
request.
43
User Packet Flow
DL Retry Buffer
• grep “retry_buffer” denali.his
DL_TX_retry_buffer_exit CB - a retry TLP will be

transmitted
DL_TX_retry_buffer_purge CB - clearing the RB on receipt
of Ack/Nak
44
User Packet Flow
DL ACK/NAK
• Ack/Nak being transmitted/received :
egrep "DLLP.*(ACK|NAK)" denali.his
• Check the sequence #
tb.rc 3476 ns DL[port_0] : RX DLLP (type:ACK, seq:64) from physical layer
tb.ep_monitor 3851800 ps DL[port_0] : RX DLLP (type:ACK, seq:71) from physical layer
tb.rc 3908 ns DL[port_0] : RX DLLP (type:ACK, seq:73) from physical layer
tb.ep_monitor 4227800 ps DL[port_0] : RX DLLP (type:ACK, seq:78) from physical layer
• Ack/Nak Timers:
grep "DL.*Timer" denali.his
tb.epMon 8859800 ps DL[port_0] : Ack/Nak Latency Timer Limit = 162993480 fs
tb.epMon 8859800 ps DL[port_0] : Ack/Nak Latency Timer Limit With L0s Adjustment =
406983720 fs
tb.epMon 8859800 ps DL[port_0] : Replay Timer Limit = 488980440 fs
tb.epMon 8859800 ps DL[port_0] : Replay Timer Limit With L0s Adjustment = 8678652840
fs
tb.epMon 19398219370 fs Debug: DL[port_0] : The Max Payload Size modification will now
cause the Ack/Nak and Replay Timer values to be recalculated
45
FLOW CONTROL
46
FC credits – Spec recap
In which resolution FC credits For each VC in each

are managed? link direction
6 FC types –
How many FC credits
PH , PD , NPH ,
types do we have?
NPD , CPLH , CPLD
What are the measurement unit 4 DW(32bit) for data

for FC credits ? depended - for header
Last note: FC credits always count up until they wrap around
47
Debugging Flow Control
Flow Control Pkts
• grep “INIT” denali.his
tb_top.bfm 19882 ns DL[port_0] : TX DLLP (type:INIT_FC1_P vc:0 hdr:112
data:35)
tb_top.bfm 19886 ns DL[port_0] : TX DLLP (type:INIT_FC1_NP vc:0 hdr:4
data:1099)
tb_top.bfm 19918 ns DL[port_0] : TX DLLP (type:INIT_FC1_CPL vc:0 hdr:0
data:0)
tb_top.bfm 20002 ns DL[port_0] : RX DLLP (type:INIT_FC1_P vc:0 hdr:4
data:64)
tb_top.bfm 20034 ns DL[port_0] : RX DLLP (type:INIT_FC1_NP vc:0 hdr:4
data:0)
• grep “UPDATE” denali.his

tb_top.bfm 118162 ns DL[port_0] : RX DLLP (type:UPDATE_FC_P
vc:0 hdr:34 data:280)
tb_top.bfm 126274 ns DL[port_0] : TX DLLP (type:UPDATE_FC_P
tb_top.mon 126314 ns DL[port_0] : RX DLLP (type:UPDATE_FC_P
tb_top.bfm 129370 ns DL[port_0] : TX DLLP (type:UPDATE_FC_NP
vc:0 hdr:100 data:1124)
48
flow control credits counters Partial snapshot!
• egrep “ FC credits ” denali.his
tb.DUT 5492 ns Debug: Initializing VC[0] PH RX_ALLOCATED FC credits = 1
tb.DUT 5492 ns Debug: Initializing VC[0] PD RX_ALLOCATED FC credits = 32
tb.DUT 5492 ns Debug: Initializing VC[0] NPH RX_ALLOCATED FC credits = 1
tb.DUT 5492 ns Debug: Initializing VC[0] NPD RX_ALLOCATED FC credits = 1
tb.DUT 5492 ns Debug: Initializing VC[0] CPLH RX_ALLOCATED
• Focus on one VIP instance , one bucket and one direction

grep “ep.* PD RX.* FC cred" denali.his
tb.epMon 5579800 ps Debug: Initializing VC[0] PD RX_ALLOCATED FC credits = 32
tb.epMon 50319495470 fs Debug: Updating VC[0] PD RX_RECEIVED FC credits + 8 = 8
tb.epMon 50643469550 fs Debug: Updating VC[0] PD RX_ALLOCATED FC credits = 40
Credit name Update kind
• Focus on one VIP instance , one bucket and one direction
grep "rc.* PD TX.* FC cred" denali.his
tb.rcModel 5584 ns Debug: Initializing VC[0] PD TX_LIMIT FC credits = 32
tb.rcModel 50253563250 fs Debug: Updating VC[0] PD TX_CONSUMED FC credits + 8 = 8
tb.rcModel 50644531970 fs Debug: Updating VC[0] PD TX_LIMIT FC credits = 40
49
flow control timer
grep “FC timer” denali.his
tb.rcModel 58070187870 fs Debug: PM:(Port_0) reset FC timer

tb.epMon 58199115050 fs Debug: Port 0: start default FC timer [vc:0] for PH at 58199115050 fs
[endTime:103199115050 fs]
tb.epMon 58199115050 fs Debug: Port 0: start default FC timer [vc:0] for PD at 58199115050 fs
[endTime:103199115050 fs]
50
EQUALIZATION
51
Equalization Sequence
52
Equalization Debug
Useful facilities
Equalization state:
grep “EQ phase” denali.his
tb.rcModel 9680559350 fs Debug: PL enter EQ phase 1 (entry)
tb.epMon 9729242950 fs Debug: PL enter EQ phase 0 (entry)
tb.epMon 10232952650 fs Debug: PL enter EQ phase 1 (Rx-2xTS1(EC==1))
tb.rcModel 10265512550 fs Debug: PL enter EQ phase 2 (timeout)
tb.epMon 10882900650 fs Debug: PL enter EQ phase 3 (timeout)
tb.rcModel 10899211850 fs Debug: PL enter EQ phase 3 (Rx-2xTS1(EC=3))
All Equalization info (review registers:PCIE_REG_DEN_EQ_CTRL_ST, PCIE_REG_DEN_EQ_RX_(0-31),
PCIE_REG_DEN_EQ_TX_(0-31)
egrep "Equalization|accept|reject|preC|phase" denali.his
Together with LTSSM state machine

egrep “Equalization|accept|reject|preC|phase |LTSSM state" denali.his
tb.rcModel 10899211850 fs Debug: PL enter EQ phase 3 (Rx-2xTS1(EC=3))
tb.rcModel 11402921550 fs Detected[cfg_0_0] [] PL_LTSSM_STATE [PCISIG]. [port_0] LTSSM state
Recovery.Equalization => Recovery.RcvrLock
Together with OrderSet info

53
egrep “Equalization|accept|reject|preC|phase |LTSSM state|PL_.X_end.*Block" denali.his
Equalization Debug
egrep results example
Only partial copy!
tb.epMon 8857400 ps Detected[cfg_0_0] [] TL_WRREG_SAME [PCISIG]. cfg_0_0 WrReg: [Denali
Transmitter Equalization Setting in lane 0] addr[27:24](preset):0x1f30 value:0x1
tb.epMon 8857400 ps Detected[cfg_0_0] [] TL_WRREG_SAME [PCISIG]. cfg_0_0 WrReg:
[Denali Transmitter Equalization Setting in lane 0] addr[23:18](LF):0x1f30 value:0x01
[Denali Transmitter Equalization Setting in lane 0] addr[5:0](preC):0x1f30 value:0x0b
[Denali Transmitter Equalization Setting in lane 0] addr[11:6](C):0x1f30 value:0x34
tb.epMon 11516599950 fs Detected[cfg_0_0] [] TL_WRREG_SAME [PCISIG]. cfg_0_0 WrReg: [Denali
Transmitter Equalization Setting in lane 0] addr[27:24](preset):0x1f30 value:0x1
tb.rcModel 10395502150 fs Debug: Port_0: EQ (phase_2), accept change in lanes 0xff on preset(ffh).
54
Debug: Simulation Time
Simulation time stampZ
Zfollowed by all the activities at that time
tgrep script is available for giving time for each grep results
- 16295 ns -
R E TxDataK 01
R E TxData 0000000010111100
R H Debug: [port_0].TxData state Polling => Training
R H Debug: [port_0].RxData state Polling => Training
Debug: Event on Pin
• Events occuring on a particular pin
• First character always represents instance-id
– 2 E RX 00000000
– 2 – instance-id (testbench.i0)
– E – symbol for event followed by value (0000000 – Represents data on
different lanes.)
– RX – Pin name
55
Debug: Scheduled Event on Pin
• Events scheduled on a particular pin
– 2 S TX 00001100 10 ns T
– 2 – Instance-id
– S – Symbol to represent event scheduling followed by value
– 10 ns – after 10 ns of current simulation time.
– TX – TX pin name
56
r20
XML description • Packet Tracker

Link
PureSuite / 3check debug • Trace\History file


• Available for ~80% of the tests.

• Step-by-step explanation of the Puresuite ‘black-box’
tests.
• Sheds light about the design intent of the various tests.
57
Slide 57
r20 where can be reached?

ronenb, 10/31/2013
XML description (Cont.)
TXN.02.21#06.UR.CfgWr0 : Completion Status[2:0] -- must be encoded to

<test desc="Completion Status[2:0] -- must be encoded to indicate the status for a Completion (see Base
Specification, Table 2-20)" indicate the status for a Completion (see Base
Specification, Table 2-20)
fullname="TXN.02.21#06.UR.CfgWr0"
sig-item="TXN.02.21#06">
<isTestable ref="TL.Configured"/>
Requirements :
<isTestable ref="TL.DUT.EP"/>
<isTestable ref="TL.IC.DEV_ACTIVE"/>
1. TL must be configured (model)
<seq name="TXN.02.21#06.UR.CfgWr0">
2. DUT must be number="1"
<step an EP (monitor)
ref="TL.Wait500Cycles"/>
<step number="2" desc="Send DUT a poisoned CfgWr0">
<action_func>
Initial Conditions : name="pciePsTlSendTlp">
<func
Start from device <const
activename="argNames" type="string" value="tlpType length errorPoisoning"/>
<enum name="tlpType" type="pcieTlpTypeT" value="DENALI_PCIE_TL_CfgWr0"/>
<const name="length" type="unsigned" value="4"/>
Scenario : <const name="errorPoisoning" type="unsigned" value="1"/>
</func>
1. Wait for 500 cycles
</action_func>
2. Send DUT a poisoned CfgWr0
</step>
3. Wait for<step
DUTnumber="3"
to receivedesc="Wait
CfgWr0for DUT to receive CfgWr0">
<action_ewait inst="monitor" event="TL_RX_packet">
4. Wait for BFM to<watchreceive Cpl with UR value="Tlp"/>
field="_pkt_type" status
<watch field="TL__type" value="CfgWr0"/>
</action_ewait>
</step>
<step number="4" name="TL.BFM.RX.UR.CPL" desc="Wait for BFM to receive Cpl with UR status">
<action_ewait inst="model" event="TL_RX_packet">
58
Support Resources
• The following is the only available option for creating and updating the
verification IP (VIP) service requests in the Cadence Support System:
– Submitting a new service request: Use site: http://support.cadence.com
• Choose Service requests -> Create service request
• Set "Product" to:
– "Memory Model" for memory model (MMAV/MMPT) issues
– "Verification IP" for other non-memory protocols like PCIe, USB, SATA, Ethernet, PLB,
MIPI, AMBA etc.
• Select related "Product Feature" in the next page.
• Use the following ftp instructions for uploading files:
– unix> ftp ftp.cadence.com
– ftp> user: cdn_vip_c
– ftp> password: DEnCus10
– ftp> put <file name>
– Updates to existing service requests can be done:
• by replay to an email given from the support with "Update <Case#>" in the subject line.
– For example:
Update 45493616 [Ethernet] ENET how can Z. [ref:_00Dd0c1Z9._500d08HMQR:ref]
• by updating the SR using Cadence Online Support website.
59
Appendix A. (Cont.)
Useful grep commands
General PL
“^. i “ – Get all instances. .(trc file) link speed – Changed link speed
“^. I “ – Get all memorinstances. .(trc file) Cycle.*TX – Tx buffer, before scrambling.
“^. f “ – Get soma files of instances. .(trc file) Cycle.*RX – Rx buffer, after descrambling
“ V “ - .denalirc settings (trc file) LTSSM state – LTSSM state change.
discard – See if a packet was discard at receiver or
reason
transmitter.
E PERST – Value of the wire.
"hier\[mem\]" – Memory picture
:: Detected – Errors\Warnings\info Link state
mmwriteword – register backdoor access by user Pipe state
WRRREG – all register acess EQ phase
Hierarchy and capabilities “Equalization|accept|reject|preC|phase” – all EQ details
“hier” – all PCIe topology
BAR_ - BAR register access Error Handling
capability FatErr(Det|En) – Fatal\Non Fatal Error detected\enabled
Initialization process corErr(Det|En) – correctable error detected\enabled
UR(det|en) – UR detected\enabled
“port Function state”
correctable error (status|mask|severity)
TL state
DLCMSM state
“LTSSM state|LTSSM reason” - – reason for LTSSM state
change (not always).
60
Appendix A.
Useful grep commands
DLL
"DLLP.*(ACK|NAK)" - Ack/Nak being transmitted/received
DL.*Timer – ACK/NAK timers
DLCMSM state – DLCMSM state change.
FC credits – flow control credits couners
NPH TX.*FC – same , only for NPH TX
FC timer – flow control tmer
TL
“TL_user_queue_exit.*User”
“TL_TX.*MRd_32 TL_RX.*CplD” - Tx\Rx a TLP.
dentransset.*DENALI_ARG_PCIE__pkt_type" (trc file) – transadd pkt
“retry_buffer_exit” - TL pkt will be re-transmitted
PureSuite
Can_Run – Which tests can run un this sim.
Step – Puresuite step.
PS : - Puresuite message.
Error: - Puresuite error message.
"# Tes" - Test pass\fail message
61

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I NV E N TI V E CONFIDENTIAL

PCI Express Purespec

• Dump debug information with minimum effect on

• README file entry for each test.

• All available parameters are specified in section 5.3.3 in

Performance Monitor • Packet Tracker

• README file entry for each test.

• Gives hints on usage of the link

Performance Monitor (Cont.)

Time spent in each

Only Mem data Pkts transmission

Only DLL generated

r2 latency - explain how measured

recommend which kind of tesrs should be used for perf monitoring

Packet Tracker • Packet Tracker

• README file entry for each test.

• Shows TLPs, DLLPs and OSs.

CPL status Poisoned

r19 what link | lane | nfts | drate.. means

History File • Packet Tracker

• README file entry for each test.

• Controlled from the .denalirc :

• Very detailed protocol information with timestamps.

• Controlled from the .denalirc :

“M” – Device Instance-id (e.g. testbench.i0)

Trace File Header

6 H Detected[cfg_1_0] [] PL_LTSSM_STATE [PCISIG]. [port_1] LTSSM state

egrep "^0.*DLLP.*(ACK|NAK)" denali.trc

Please try those grep and see the full results!

The hier[cfg] message shows whether

The hier[mem] message shows the

[port=0, function=0] Requester ID(bus,device,func)

10 bit size; 32b addr Memory Non-prefechable

32b addr Memory Used addr range

r7 add RC shadow space example

grep “BAR_0” denali.his

why each write appear so many times

mention that denali BAR is an internal register

does it appear in backdoor access to registers?

what does cfg_0_0 mean ? in the rc line

• grep WRRREG denali.his

tb.ep_monitor(cfg_0_0) 4547800 ps SIM WRITE

C mmwriteword 7 REG_DEN_LN_SKEW laneNum=1,op=1,param=0,value=0

Same name as appear at reg enum

r12 why i get all this in time 0

r14 add somthing about electrical idle

r18 explain about differen cfg_space of rc

grep “TL state” denali.his

tb.ep_monitor 0 ns Debug: TL state[UpPort_0] <undefined> => Idle

• grep “LTSSM state” denali.his

grep LTSSM denali.his

tb.rcModel 11906631250 fs Detected[cfg_0_0] [] PL_LTSSM_TS2_RX [PCISIG]. [port_0] received

tb.rcModel 11906631250 fs Detected[cfg_0_0] [] PL_LTSSM_TS2_TX [PCISIG]. [port_0]

tb.rcModel 65429849050 fs Debug: [port_0] LTSSM reason [RX-IDL] => Rx_L0s.Entry/Tx_L0s.Idle

• grep “PM” denali.his

34 8/17/2009 Cadence Confidential: Cadence Internal Use Only

35 8/17/2009 Cadence Confidential: Cadence Internal Use Only

egrep "^0.DLLP.(ACK|NAK)" denali.trc

• grep "TL_user._exit. User" denali.his