The 8253

THE 8253
PROGRAMMABLE COUNTER/
INTERVAL TIMER
MPMC
Features
• The Intel 8253 is a programmable counter/
timer chip designed for use as an Intel
microcomputer peripheral.
• It is packaged in a 24-pin plastic DIP.
• Six programmable timer modes allow the
8253 to be used as an event counter, elapsed
time indicator, programmable one-shot, and
in many other applications e.g., to create
different intervals.
• It has 3 identical 16-bit counters
– Counters 0, 1, 2
Cont…
• To operate a counter, a 16-bit count is loaded in its
register and, on command (Gate), it begins to decrement
the count until it reaches 0.
• At the end of the count, it generates a pulse that can be
used to interrupt the CPU. The counter can count either
in binary or BCD.
• In addition, a count can be read by the CPU while the
counter is decrementing.
• Compatible with all Intel and most other
microprocessors
• 8254 (8-10MHz) and 8253 (2MHz)
Pin Diagram
Pin Diagram of 8253/ 54

Block Diagram of 8253
Each counter has 3
lines connected to it.
Two of these lines,
clock and gate, are
inputs. The third,
labelled OUT is an
output.
•The function of these
lines changes and
depends on how the
device is initialized or
programmed.
Data Bus Buffer
• This tri-state, bi-directional, 8-bit buffer is
used to interface the 8253/54 to the system
data bus. The Data bus buffer has three basic
functions.
• 1. Programming the modes of 8253/54.
• 2. Loading the count registers.
• 3. Reading the count values.
Read/Write Logic
• The Read/Write logic has five signals : RD’, WR’,
CS’ and the address lines A0 and A1.
• In the peripheral I/O mode, the RD’ and WR’
signals are connected to IOR’ and IOW’,
respectively.
• In memory-mapped I/O, these are connected to
MEMR’ and MEMW’.
• Address lines A0 and A1 of the CPU are usually
connected to lines A0 and A1 of the 8253/54,
and CS’ is tied to a decoded address.
• The control word register and counters are
selected according to the signals on lines A0 and
A1.
Cont..
Control Word Register and Counters
• This Control word register is accessed when lines A0 and A1
are both at logic 1.
• It is used to write a command word which specifies the counter
to be used (binary or BCD), its mode, and either a read or write
operation.
• The three Counters functional blocks are identical in operation.
• Each counter consists of a single, 16 bit, pre-settable, down
counter.
• The counter can operate in either binary or BCD and its input,
gate and output are configured by the selection of modes
stored in the control word register.
• The programmer can read the contents of any of the three
counters without disturbing the actual count in process.
Control Word Register Format
Programming the 8253/54
• Each counter of the 8253/54 is individually
programmed by writing a control word into
the control word register (A0 - A1 = 11).
• Bits SC1 and SC0 select the counter, bits RW1
and RW0 select the read, write or latch
command, bits M2, M1 and M0 select the
mode of operation and bit BCD decides
whether it is a BCD counter or binary counter.
WRITE Operation
• Write a control word into control register.
• Load the low-order byte of a count in the
counter register.
• Load the high-order byte of count in the
counter register.
READ Operation
• In some applications, especially in event counters, it is
necessary to read the value of the count in process. This
can be done by three possible methods:
• 1. Simple Read : It involves reading a count after inhibiting
the counter by controlling the gate input or the clock input
of the selected counter, and two I/O read operations are
performed by the CPU. The first I/O operation reads the
low-order byte, and the second I/O operation reads the
high order byte.
• 2. Counter Latch Command : In the second method, an
appropriate control word is written into the control
register to latch a count in the output latch, and two I/O
read operations are performed by the CPU. The first I/O
operation reads the low-order byte, and the second I/O
operation reads the high order byte.
• 3. Read Back 8284
Modes of Operation
• There are 6 modes of operation of 8253
• Mode 0 (000): Interrupt on terminal count.
• Mode 1 (001): Programmable one shot.
• Mode 2 (X10): Rate generator.
• Mode 3 (X11): square wave generator.
• Mode 4 (100): Software Triggered Strobe.
• Mode 5 (101): Hardware Triggered Strobe.
Mode 0: Interrupt on Terminal Count
• The output will start off zero. The count is loaded
and the timer will start to count down. When the
count has reached zero the output will be set high,
and remain high until the next count has been
reloaded. Gate must be high to enable counting and
0 to disable counting.
Mode 1: Programmable One-Shot.
• The output will go low following the rising
edge of the gate input. The counter will count
and the output will go high once the counter
has reached zero.
Mode 2: Rate Generator.
• This mode is called either rate generator. In this
mode, if N is loaded as the count value, then,
after N pulses, the output becomes low only for
one clock cycle. The count N is reloaded and
again the output becomes high and remains high
for N clock pulses. Count=1 is illegal.
Mode 3: Square Wave Generator
• This mode is similar to Mode 2 except the
output remains low for half of the timer
period and high for the other half of the
period.
Mode 4: Software Triggered Pulse
• After the mode is set, the output goes high.
When a count is loaded, counting down
starts. On terminal count, the output goes
low for one clock cycle, and then it again
goes high. This low pulse can be used as a
strobe, while interfacing the microprocessor
with other peripherals. The count is
inhibited and the count value is latched,
when the GATE signal goes low.
Cont..
Mode 5: Hardware Triggered Pulse.
• The counter will start counting once the gate input
goes high, when the counter reaches zero the
output will pulse low and then go high again.
Example
Write a program to initialize
counter 2 in mode 0 with a count
of C030H.
Assume address for

control register = 0BH, 00001011
counter 0 = 08H, 00001000
counter 1 = 09H; 00001001
and counter 2 = 0AH; 00001010
CW= 1 0 1 1 0 0 0 0 =B0h
Assume address for
control register = 0BH,
Solution counter 0 = 08H,

counter 1 = 09H
and counter 2 = 0AH.
MVI A, B0; Move CW in ACC

OUT 0B; Move to CWR
MVI A, 30; Move LSB of count in ACC
OUT 0A; Load it in buffer reg of Counter 2
MVI A, C0; Move LSB of count in ACC
OUT 0A; Load it in buffer reg of Counter 2
HLT; Stop
Example
To generate a pulse every 100 usec using Counter 0
in mode 2.
Solution
Control Word: 0 0 0 1 0 1 0 0 = 14H
Count Value=100usec/ 0.5usec=200D= C8H
MVI A, 14
OUT 83
MVI A, C8
OUT 80
HLT
Address Map
Chip Select
Interfacing
END OF SLIDES

The 8253

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THE 8253

Pin Diagram of 8253/ 54

Assume address for

Solution counter 0 = 08H,

MVI A, B0; Move CW in ACC

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