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  • Coa Ese Q (2022)

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    Aayush Kumar Dubey
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    This document provides details of an end semester examination for a Computer Architecture and Organization course. It includes 5 questions related to topics like cache memory design, virtual memory, pipelining, and RISC vs CISC architectures. The exam is for semester 3 students across all branches, has a duration of 3 hours and maximum marks of 100. It tests comprehension of concepts from different units of the course through questions involving explanations, diagrams and calculations.

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    COA_ESE_Q(2022)

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    This document provides details of an end semester examination for a Computer Architecture and Organization course. It includes 5 questions related to topics like cache memory design, virtual memory, pipelining, and RISC vs CISC architectures. The exam is for semester 3 students across all branches, has a duration of 3 hours and maximum marks of 100. It tests comprehension of concepts from different units of the course through questions involving explanations, diagrams and calculations.

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    © All Rights Reserved
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    15 views2 pages

    Coa Ese Q (2022)

    Uploaded by

    Aayush Kumar Dubey
    This document provides details of an end semester examination for a Computer Architecture and Organization course. It includes 5 questions related to topics like cache memory design, virtual memory, pipelining, and RISC vs CISC architectures. The exam is for semester 3 students across all branches, has a duration of 3 hours and maximum marks of 100. It tests comprehension of concepts from different units of the course through questions involving explanations, diagrams and calculations.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    of 2

    Sardar Patel Institute of Technology

    Bhavan’s Campus, Munshi Nagar, Andheri (W), Mumbai: 400058, India

    (Autonomous College of Affiliated to University of Mumbai)

    End Semester Examination


    December 2022
    Maxi Marks: 100 Duration: 3 hours
    Class: SE Semester: III
    Course code: CS203/AI203/EC201/DS203 Branch: All Branches
    Name of the course: Computer Architecture & Organization

    QNo Max CO
    Marks
    Q.l A Direct Mapped Cache Subsystem needs to be designed having the 12 CO 4
    (a) following specifications:
    a) Main Memory Size of 1GB
    b) Block Size of 16 Bytes
    c) Cache Memory Size of 64 KB
    d) Line Size of 16 Bytes
    Answer the following:
    1) Address Interpretation by Main Memory
    2) Address Interpretation by Cache Memory
    3) Design of Line Entry
    Draw a neat Conceptual Diagram of the System showing all the blocks.

    OR

    A Two Way Set Associative Cache Subsystem needs to be designed


    having the following specifications:
    a) Main Memory Size of 1GB
    b) Block Size of 16 Bytes
    c) Cache Memory'' Size of 64 KB
    d) Line Size of 16 Bytes
    Answer the following:
    1) Address Interpretation by Main Memory
    2) Address Interpretation by Cache Memory'
    3) Design of Line Entry
    Draw a neat Conceptual Diagram of the System showing all the blocks.

    Q.l Devise the mechanism to implement Virtual Memory Segmentation 8 CO 4


    (b) technique that translates the Virtual Address to its equivalent Physical
    Address. Your answer must have the supporting diagram of the
    mechanism._______________________________________________
    0.2 Consider the following page reference string: 10 CO 4
    (a) 1,2,3,4,2,1,5,6,2,1,2,3,7,6,3,2,1,2,3, 6
    How many page faults would occur for the following replacement
    algorithms, assuming three-page frames?
    1. FIFO
    2. LRU
    Q.2 Explain the basic organization of the microprogrammed control unit with 10 CO 3
    (b) neat diagram. Write a control store (microprogram) for
    (i) ADDR1.R2
    (ii) Branch LOCN
    OR
    Generate the control signals by using Hardwired control unit design for
    WMFC signal and MARin signal. Use the following instructions:
    (i) ADDR1,R2
    (ii) ADDR1,LOCA;
    (iii) BRANCH LABEL

    Q.3 What are the largest and smallest positive, finite, normalized numbers 10 CO2
    (a) that can be represented as IEEE single precision float? Represent 231.56
    in IEEE Single Precision Format

    OR

    Prove how Modified Booths (Bit-Pair Recoding) speed-up the


    multiplication process as compared to Booths Algorithm by Multiplying
    the Multiplicand (-17) with the Multiplier (21).___________ _______
    Q.3 A benchmark program is run first on 200 Mhz and then on 300 Mhz 10 CO 1
    (b) processor. The executed program consists of 1 million instruction
    execution, with the following instruction mix and clock cycle count:

    Instruction Type Instruction Count Cycles per


    Instruction
    Integer Arithmetic 4,00,000 1
    Data Transfer 3,50,000 2
    Floating Point 2,00,000 3
    Control Transfer 50,000 2
    Determine the effective CPI, MIPS rate and Execution Time. Also
    compare the performance. ____________ __________________
    Q.4 What is the major functionality of I/O Module? Describe the process 10 CO6
    (a) involved when the user provides input through the keyboard till it is
    displayed on the monitor._________________________________
    Q.4 Compare different Allocation policy and Release Policy for Bus 10 CO6
    (b) Arbitration.
    Q.5 Compare Instruction level and Processor level parallelism. Discuss in 10 COS
    (a) detail data and control pipeline hazards.

    Q.5 RISC uses Harvard Model and CISC uses Von-Neumann Model”, Justify 10 COB
    (b) the statement. Explain the important design rules of RISC philosophy.

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