GUJARAT TECHNOLOGICAL UNIVERSITY

Bachelor of Engineering
Subject Code: 3140707
Semester – IV
Subject Name: Computer Organization & Architecture

Syllabus:
Sr. Content
No.
1 Computer Data Representation
Basic computer data types, Complements, Fixed point representation,
Register Transfer and Micro-operations:
Floating point representation, Register Transfer language, Register Transfer, Bus and
Memory Transfers (Tree-State Bus Buffers, Memory Transfer), Arithmetic Micro-
Operations, Logic Micro-Operations, Shift Micro-Operations, Arithmetic logical shift unit
2 Basic Computer Organization and Design
Instruction codes, Computer registers, computer instructions, Timing and Control,
Instruction cycle, Memory-Reference Instructions, Input-output and interrupt, Complete
computer description, Design of Basic computer, Design of Accumulator Unit.
3 Assembly Language Programming
Introduction, Machine Language, Assembly Language Programming: Arithmetic and
logic operations, looping constructs, Subroutines, I-O Programming.
4 Micro programmed Control Organization:
Control Memory, Address sequencing, Micro program example, Design of Control Unit
5 Central Processing Unit
Introduction, General Register Organization, Stack Organization, Instruction format,
Addressing Modes, Data transfer and manipulation, Program control, Reduced Instruction
Set Computer (RISC) & Complex Instruction Set Computer (CISC)
6 Pipeline And Vector Processing
Flynn's taxonomy, Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction,
Pipeline, RISC Pipeline, Vector Processing, Array Processors
7 Computer Arithmetic
Introduction, Addition and subtraction, Multiplication Algorithms (Booth Multiplication
Algorithm), Division Algorithms, Floating Point Arithmetic operations, Decimal
Arithmetic Unit.
8 Input-Output Organization
Input-Output Interface, Asynchronous Data Transfer, Modes Of Transfer, Priority
Interrupt, DMA, Input-Output Processor (IOP), CPUIOP Communication, Serial
communication.
9 Memory Organization
Memory Hierarchy, Main Memory, Auxiliary Memory, Associative Memory, Cache
Memory, Virtual Memory.
10 Multiprocessors
Characteristics of Multiprocessors, Interconnection Structures, Inter-processor
Arbitration, Inter-processor Communication and Synchronization, Cache Coherence,
Shared Memory Multiprocessors.

Page 1 of 1
w.e.f. AY 2018-19
 Paper 1
MARKS
Q.1 (a) Draw the block diagram of 4-bit combinational circuit shifter. 03
(b) Construct diagram of common bus system of four 4-bits registers with 04
diagram.
(c) What is the role of sequence counter(SC) in control unit? Interpret its 07
concept with the help of its three inputs using diagram.

Q.2 (a) List out names of eight main registers of basic computer with their 03
symbolic name and purpose.
(b) Summarize following addressing modes with example. 04
1) Implied mode 2) Register mode
(c) Which are the different phases of Instruction Cycle? Describe Register 07
transfer for fetch phase with its diagram.
OR
(c) Define: microinstruction; Identify different types of 16 bits instruction 07
formats for basic computer using figure.

Q.3 (a) Use BSA and BUN instruction with example and diagram. 03
(b) Criticize Three-Address Instructions and Zero address instruction with 04
common example.
(c) Describe how control unit determine instruction type after the 07
decoding using flowchart for instruction cycle.
OR
Q.3 (a) Prepare flowchart of CPU-IOP communication. 03
(b) Differentiate RISC and CISC architecture. 04
(c) What is cache memory? Interpret direct addressing mapping with 07
diagram.

Q.4 (a) Draw and criticize memory hierarchy in a computer system. 03

(b) Write an Assembly level program for addition of 50 numbers. 04
(c) Draw the flowchart of first pass of the assembler and explain working 07
of the same.
OR
Q.4 (a) Interpret the following instructions: INP, ISZ and LDA 03
(b) Write an Assembly level program to move one block of data to another 04
location.
(c) List out modes of transfer. Formulate direct memory access technique 07
in detail.

Q.5 (a) Summarize major hazards in pipelined execution. 03

1
 (b) What is a data dependency conflict in instruction pipeline? 04
Recommend solutions for data dependency conflicts.
(c) Demonstrate four-segment instruction pipeline in detail 07
OR
Q.5 (a) Sketch Microinstruction code format. Quote BR and CD field in brief. 03
(b) Compare following terms: 04
1. Write through-cache and Write back cache.
2. Spatial locality and Temporal locality
(c) Elaborate flynn’s classification scheme with proper diagram. 07

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2
 Paper 2

Marks
Q.1 (a) Write the name of basic computer registers with their functionalities. 03
(b) Discuss 4-bit binary adder with neat diagram. 04
(c) Enlist various kinds of addressing modes. Explain any five of same and support 07
your answer by taking small example.

Q.2 (a) Write sequence of microoperations to execute the following instructions: 03

- AND
- STA
(b) Write assembly language program to subtract two numbers. 04
(c) Write two address, one address and zero address instructions program for the 07
following arithmetic expression:
X = (A + B) * (C – D / E) + F * G
OR
(c) Assume A = + 6 and B = + 7, apply Booth algorithm for multiplying A and B. 07
Make necessary assumptions if required.

Q.3 (a) Explain Flynn’s classification for computers in brief. 03

(b) Draw the flowchart for first pass of assembler and explain the same in brief. 04
(c) Elaborate CPU-IOP communication. 07
OR
Q.3 (a) Explain pipeline conflicts in brief. 03
(b) Discuss three state bus buffers with neat diagram. 04
(c) Write a detailed note on associative memory. 07
Q.4 (a) Explain DMA in brief. 03
(b) Write a note on SIMD array processor. 04
(c) A computer uses a memory unit with 256K words of 32 bits each. A binary 07
instruction code is stored in one word of memory. The instruction has four
parts: an indirect bit, an operation code, a register code part to specify one of 64
registers, and an address part.
1. How many bits are there in operation code, the register code part and the
address part?
2. Draw the instruction word format and indicate the number of bits in
each part.
3. How many bits are there in the data and address inputs of the memory?
OR

Q.4 (a) Write a brief note on memory hierarchy. 03

(b) In certain scientific computations it is necessary to perform the arithmetic 04
operation (Ai + Bi) * (Ci + Di) with a stream of numbers. Specify pipeline
configuration to carry out this task. List the contents of all registers in the
pipeline for i=1 through 4.
(c) Discuss microprogrammed control organization with neat diagram. 07

Q.5 (a) Perform A – B (subtract) operation for the following numbers using signed 03
magnitude number format. (Write necessary assumptions if required)
A = + 11 and B = - 6
(b) Explain status bit conditions with neat diagram. 04
(c) Discuss cache coherence problem in detail. 07
OR

1
Q.5 (a) Write the difference(s) between arithmetic shift left and logical shift left 03
instruction. Support your answer with proper illustration.
(b) State the differences between RISC and CISC. 04
(c) Explain any two types of mapping procedures when considering the 07
organization of cache memory.

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