Convolution Codes

97.478

1.0 Prologue:
Convolutional codes, why should complicate our lives with them
People use to send voice waveforms in electrical form over a twisted pair of wires. These telephone voice signals had a bandwidth of 4KHz. If the channel polluted the signal with a bit of noise, the only thing that happened was that the conversation got a bit noisier. As technology developed, we digitized the voice signals at 8000 samples per second (twice the highest frequency to prevent aliasing) and transmitted the bits. If noise corrupted a few bits, the corresponding sample value(s) would be slightly wrong or very wrong depending on whether the bad bits were near the most-signicant-bit or least-signicant-bit. The conversation sounded noisier, but were still discernible. Someone saying cat will not be thought to have said dog, and probably would not even be thought to have said caught. When people started to send data les rather than voice, corrupted bits became more important. Even one wrong bit could prevent a program from running properly. Say the noise in a channel was low enough for the probability of a bad bit to be 1x10-9 i.e. the chances of a bit being correct is 0.999999999 (nine 9s). The chances of 1000 bits being all correct is 0.999999 (six 9s) and the chances of 106 bits being all correct is 0.999 (three 9s). A 1 megabyte le (8x106 bits) has almost a 1% chance of being corrupted. The reliability of the channel had to be improved. The probability of error can be reduced by transmitting more bits than needed to represent the information being sent, and convolving each bit with neighbouring bits so that if one transmitted bit got corrupted, enough information is carried by the neighbouring bits to estimate what the corrupted bit was. This approach of transforming a number of information bits into a larger number of transmitted bits is called channel coding, and the particular approach of convolving the bits to distribute the information is referred to as convolution coding. The ratio of information bits to transmitted bits is the code rate (less than 1) and the number of information bits over which the convolution takes place is the constraint length. For example, suppose you channel encoded a message using a convolution code. Suppose you transmitted 2 bits for every information bit (code rate=0.5) and used a constraint length of 3. Then the coder would send out 16 bits for every 8 bits of input, and each output pair would depend on the present and the past 2 input bits (constraint length =3). The output would come out at twice the input speed. Since information about each input bit is spread out over 6 transmitted bits, one can usually reconstruct the correct input even with several transmission errors.
Convolution channel encoder

00101101
a b

11 10 00 01 01 00
a 3 bits in the input stream generate 2 bits

in the output stream.

b Take the most recent of these input bits

plus one new input bit and generate the next 2 output bits. Thus each input bit effects 6 output bits.
FIGURE 1

Authors, Fred Ma, John Knight

January 26, 2001

Convolution Codes

The need for coding is very important in the use of cellular phones. In this case, the channel is the propagation of radio waves between your cell phone and the base station. Just by turning your head while talking on the phone, you could suddenly block out a large portion of the transmitted signal. If you tried to keep your head still, a passing bus could change the pattern of bouncing radio waves arriving at your phone so that they add destructively, again giving a poor signal. In both cases, the SNR suddenly drops deeply and the bit error rate goes up dramatically. So the cellular environment is extremely unreliable. If you didnt have lots of redundancy in the transmitted bits to boost reliability, chances are that digital cell phones would not be the success they are today. As an example, the rst digital cell system, Digital Advance Mobile Phone Service (D-AMPS) used convolution coding of rate 1/2 (i.e. double the information bit rate) and constraint length of 6. Current CDMA-based cell phones use spread-spectrum to combat the unreliably of the air interface, but still use convolution coding of rate 1/2 in the downlink and 1/3 in the uplink (constraint length 9). What CDMA is, is not part of this lab. You can ask the TA if you are curious.

2.0 Example of Convolution Encoding

XOR Output u1
MUX

Shift register Input information bit stream x

The constraint length is 3. The output is effected (constrained) by 3 bits. The present input bit and the two previous bits stored in the shift register. Today bit Yesterdays bit

yesterdays bit

Day before

0 1
clock

Double speed output z

Output u2 XOR
FIGURE 2

This is a convolution encoder of code rate 1/2 This means there are two output bits for each input bit. Here the output bits are transmitted one after another, two per clock cycle. The output u1 = x(n) x(n-1)x(n-2). Here x(n) is the present input bit, x(n-1) was the previous (yesterdays) bit, etc. The output u2= x(n) x(n-2). The input connections to the XORs can be written as binary vectors [1 1 1] and [1 0 1] are known as the generating vectors for the code.

Authors Fred Ma, John Knight

January 26, 2001

Convolution Codes

2.1 The Encoder as a Finite-State Machine

The correlation encoder can be described as a Mealy machine. The state is the two bits in the shift register. Assume shift register was reset to zero and the rst data bit x(n) = 1. Then:State= 00 = A = [x(n-1),x(n-2)] Output z=[u1,u2] u1 = x(n) x(n-1)x(n-2) = 1 0 0 =1 u2 = x(n) x(n-2). = 1 0 =1 z=[u1,u2]= 11 After the clock, state bit x(n-1)=0 will shift right into x(n-2), the input x(n)=1 will shift right into x(n-1), and the next state will be 10 = B.
x=1 z=11 x=0/ z=00

A=00 x=0 z=11

B=10

x=1/ z= x=0/ z=

00

10
C=01

x=1 z=01

x = x(n) state = [x(n-1),x(n-2)]

FIGURE 3

D=11

x=0 z=01

2.2 The Trellis Encoding Diagram

To get the trellis diagram, squash the state diagram so A, B, C and D are in a vertical line. This line represents the possible states at time t=n (now). Make time the horizontal axis. Put another line of states to show the possible states at t=n+1. Then add the transitions to the diagram. Make the them all go from states @ t=n to states @ t=n+1. Thus the self loop at state A in the state graph becomes the horizontal line from A@t=n to A @t=n+1 in the trellis diagram. The complete trellis diagram extends past t=n+1 to as many time steps as are needed. Suppose the encoder is reset to state A=00, and the input is 1,0,1,1,0,0. By following the trellis one sees that the output is 11 10 00 01 01 11. Also it passes through states A, B, C, B, D, C ending in A @ t=n+6.
FIGURE 5

x=1/ z=10

NOTATION

TRELLIS 0/00 1/1 1 A

input/output x/z A 1 input 0 input B

C
FIGURE 4

D t=n

1 0/0 1/10

0/
A

11

0 B 1/0 0/1 0 C

1/

01

D t=n+1

More Complete Trellis Diagram A 0/00 1/1 1 A 0/00 1/1 1 A 0/00 1/1 1 A 0/00 1/1 1 0/00 1/1 1 A

0/00 1/1 1

11

11

11

0/ 1

0/

0/

C D t=n

1 0/0 1/10

D t=n+1

1 0/0 1/10

D t=n+2

1 0/0 1/10

D t=n+3

1 0/0 1/10

D t=n+4

1 0/0 1/10

D t=n+5

1 0/0 1/10

0/

0 B 1/0 0/1 0 C

0 B 1/0 0/1 0 C

0/ 1

0 B 1/0 0/1 0 C

0 B 1/0 0/1 0 C

0/

0 B 1/0 0/1 0 C

11

0 B 1/0 0/1 0 C
D t=n+6

01 1/

Authors Fred Ma, John Knight

1/

1/

0 1/

01 1/

1/

01

01

01

January 26, 2001

Convolution Codes

2.3 First Exercise: A Convolution Encoder.

1. Problem: Encoding a number Take the last 4 digits in your student (the least signicant digits). Convert them to a hexadecimal number (Matlab has a function dec2hex). Convert the hexadecimal number to binary (12 to 16 bits). Use this as data for the encoder below. Feed in the least signicant bit rst. Also reset the shift register to 00 before you start. Calculate the output bits and states when one encodes these bits using a code rate 1/2, constraint length 3 encoder with generating vectors [111] and [101]. Tabulate how the state and output values change with each clock cycle.
Clock cycle input bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

shift reg (state) 00 Output [u1,u2] 2. Problem: Draw the circuit for an encoder which has: a code rate =1/2, constraint length of 4, generating vectors [1111] and [1011], where the 0 means no connection to x(n-1). 3. Problem: Draw the state graph for the above constraint length 4 encoder, and then the rst three time steps of the trellis diagram for the above constraint length 4 encoder.

2.4 First Lab: Design a Convolution Encoder in Verilog

The constraint length 4 encoder circuit is a nite-state machine. It is also a shift register. One can code it following the standard nite-state machine model with three-bit states, or as a shift register. reg [2:0] State; always @(posedge clk) begin State <=State >> 1; // Right shift 1 position end The test bench is not part of the circuit. It supplies the input signals and may compare output signals with those that are expected. Test benches are easier to write and use if they are synchronous. This means they always send out signals slightly after the clock (or at least never at the same time as the clock). It also means a writing style with few #n delay. initial begin ... #11 x=1; #10 x=0; #10 x=1; #20 x=0; #10 x=1; ...
Test Bench module clk reset x u1 u2

ConvEncode module

Poor
FIGURE 6

Authors Fred Ma, John Knight

January 26, 2001

Convolution Codes

2.4.1 A Synchronous Test Bench

In a synchronous test bench, the test signals are timed by @(posedge clk) statements rather than each having its own timing. There are only two delays here, one to set the clock period, and the other to delay the input signal x so its changes are obviously past the clock edge. Note there are things not included here, like reset. module SyncTestBench; reg [1:8] data; //Fill this with the data stream to be encoded. // Note the rst bit is on the left reg x, clk; integer I; initial begin I=1; data=8'b1010_1101; // Underscore has no meaning except // to visually space the bits. clk=0; forever #5 clk=~clk; end // send in a new value of x every clock cycle always @(posedge clk) begin if (I==9) $nish; // The #1 makes x change 1ns after the clock and never on the clock edge. // The nonblocking symbol <= on I ensures that any other clocked module using // I will grab the same I as this procedure, that is before I is updated to I+1. x<= #1 data[I]; I<=I+1; end endmodule For the constraint length 3 system, you must have the test bench automatically compare your answer with the result you obtained from your student number. 1. Write a finite-state machine encoder for the constraint length 3 system.

2. Write a shift-register based encoder for the constraint length 4 system (Sect 2.3 prob 2). 3. Write a synchronous test bench so the other two modules can be simulated. 3a) Compare the result for the data 1 1 0 1 0 0 1 0 1 1 0 0 0 0 Ans: Constraint length 3 encoded data11,01,01,00,10,11,11,10,00,01,01,11,00,00,00,00. Ans: Constraint length 4 encoded data11,01,01,11,01,11,00,10,00,10,01,00,11,00,00,00,00.

2.5 Lab and Problem Rules

The Viterbi decoder design problem will be done by a groups of three persons. The number of exercises is (usually) divisible by three so one person in each group does one-third of the exercises. The three are to be submitted together with the name of the person doing each part attached to the part. All members of the group are responsible for knowing how to do each exercise. Related problems will appear on the examination. Also the TAs will ask other members of the group to explain the submissions they did not submit. This will effect their mark as much as their submission.
Authors Fred Ma, John Knight January 26, 2001 5

Convolution Codes

3.0 Convolution Decoder

The next part of the project will be to design a convolution decoder to retrieve the information bits from the transmitted bits. It should succeed even in the presence of some errors in the transmitted bits. The implementation we will use is called a Viterbi decoder.

3.1 Decoding Using the Trellis Diagram

Consider a decoder that receives the transmitted signal 11 01 01 00 10 11 going from t=n to t=n+6. Assume the trellis was reset to state A (00) at the start. One goes through the trellis as before, only for decoding the numbers are output\input. So the rst input, 11, gives a decoded output of 1 and takes the machine to state B. At t=n+1 in state B, the next input 01 causes a 1 output and a change to state D. Trellis Diagram for Decoding (Receiving) Received 11 input Decoded 1 output 00/0 A 11/ 1 01 1 00/0 11/ 1 01 0 A 00/0 11/ 1 A 00 1 00/0 1/1 1 A 10 0 00/0 11/ 1 A
FIGURE 7

11 0 00/0 11/ 1 A

/0

/0

/0

/0

/0

11

11

11

11
11

B C D t=n

1 B 00/ 10/ 0 C
D t=n+1

1 B 00/ 10/ 0 C
D t=n+2

11

11

1 B 00/ 10/ 0 C
D t=n+3

1 B 00/ 10/ 0 C
D t=n+4

1 B 00/ 10/ 0 C
D t=n+5

0 01/ 10/1

0 01/ 10/1

0 01/ 10/1

0 01/ 10/1

0 01/ 10/1

0 01/ 10/1

/0
1 B 00/ 10/ 0 C
D t=n+6

01

3.1.1 The Hamming Distance

This distance is used to show how far apart two binary numbers are. Compare the bits in the same positions in the two numbers. The number of positions that are different is the Hamming distance (h). Thus 11and 01 are distance 1 apart (h=1), 1001001 and 1001010 are distance 2 apart (h=2). Applying the Hamming Distance to Decoding Suppose the rst four received bits have an error so instead of 11 01, one receives 11 11. On the trellis in Fig. 8, there are two choices leaving state A, one for input 11 0 and the other for input 00 2 . The number in the box is the Hamming distance between the received input and the bits for the transition. It is clear one should make the transition from AB. Received 11 input A 00 2 11 0 A

The next input has an error. Note there are no 11 or 00 paths leaving state B. Both possible paths, 10 or 01, are at Hamming distance 1. At this time either transition looks equally likely, but wait!
Authors Fred Ma, John Knight January 26, 2001 6

01

01

01

01

01

/1

/1

/1

D D t=n+1 t=n+2 Instead of input/output (i.e. 11/1) we now show input Hamming distance D t=n

/1

/1

FIGURE 8

Hamming distance B B

/1

B C

10

01
1

Convolution Codes

Received 11 input A 00 2 11 0 A

error 11

Trellis Diagram 01

FIGURE 9

00 00 0

10 00 1 11 1
1

11

A
1

11

A
0

11

11

B C
Outputs is 0 is 1

11

10

00

1 B

00 10

0 B 1

00 10

1 B 0

10

C D t=n+1

At t=n+2, if one starts from D, then h=0 for the path to state C. However if one starts from C one has h=1 for either the path to A or to B. Thus at t=n+1 the proper path was not obvious, at t=n+2, the choice is clearer. We will chose a path through the trellis based on the cumulative Hamming distance, which is the sum of the Hamming distances as one steps along a path through the trellis. Figure 10 shows how the Hamming distances sum as one goes down various paths through the trellis diagram. At t=n+5, one path has a total distance of 1 from the input data. The others A 00 2
0

01
1

01

01

C D t=n+4 10 0

C D t=n+5

C D t=n+6

0
D t=n+2

10
D t=n+3

01 10 1

A
1

1+ 1+ 0

3 1

FIGURE 10

+1

3 1
4
1

A
Lowest cummultative Hamming distance
7

B C D

B
1

B C D t=n+2

1+ 1+

1 B

C D t=n+1

0 C

0 0+ B 1+ 1+ 1+ 1 C 1+ 1 +1

1 B

C D t=n+5

The sum of the Hamming distances is shown like 1 + 1 + 0 until this gets too messy. Then the sum, and the distance for the current step, are shown in a hexagon and a box like 2 1 have a distance of 3 or 4. Thus the most likely path is ABDCBC with a cumulative distance of 1, and the corresponding output data is 11010 (Recall trellis edges represent a receiver output of 0, and edges represent an output of 1). References: Bernard Sklar, Digital Communications Fundamentals and Applications. B.P.Lathe, Modern Digital and Analog Communication Systems, Holt, Rinehart & Winston, 1989 Prof. Ian Marsland, http://www.sce.carleton.ca/courses/94554/ Click on "Convolutional Codes." You will need Ghostview (gv) to read the Postscript le.

D t=n+3

D t=n+4

3 0

Authors Fred Ma, John Knight

January 26, 2001

Convolution Codes

4.0 The Viterbi Decoder

The decoding example shown above has to follow multiple paths through the trellis, and remember them for future decisions. For larger decoders, such the cell phone ones with constraint lengths (shift-register lengths + 1) of 6 and 9, the number of paths can get quite large. This means a decoding ASIC may take considerable storage, and one may have to use slower, more compact RAM type memory rather than the faster ip-ops. Viterbi developed an algorithm 1n 1967, which allows the many paths to be discarded without tracking them to completion. He noticed that if two paths merge to one state, only the one with the smaller cumulative Hamming distance, H, need be remembered. The other one can never be part of the most likely path. This means that with the constraint length 3 (shift-register length 2) system in the previous examples only have to remember 4 paths. In general a constraint length K system will have to remember 2K-1 paths. In theory, the path length should go for the length of the message in order to get the true maximum likelihood path. However it turns out that path lengths of 4 to 5 times the constraint length can almost always give the best path. The next few gures show how the decoder picks the best path, even when there are errors. Received 11 input A B 00 2 11 0 A B error 0111 00 2 4 A 11 0
2
At t=n Starting at state A, there are two possible paths. The boxes 2 show one step Hamming distance The hexagons 4 show H, the cumulative Hamming distance At t=n+1 There are 4 paths out to t=n+2 Since the input has an error, no path has a zero Hamming distance H.
FIGURE 11

10

B
1
1

C D t=n

C D t=n+1

C D t=n+2

C State
4 Cumulative Hamming distance 2 Hamming distance for this step 00 Recd input to make this transition Output a 0 if this transition is used Output a 1 if this transition is used

Received 11 input A B 00 2 11 0 A B

error 0111

002 4 00 1 5 A A 11 11 1 5 2 0 2

10

01
1

01
Going out to t=n+3 The paths temporarily double to 8 There are two paths to each node. One has a larger cumulative distance. The larger H path can never be the most likely path, hence we will erase it.

B
1
1

C D t=n

C D t=n+1

11 1 2 B 00 10 01 2 6 C
0

01
1

10 2 3 D D t=n+3 t=n+2

01

0 1

2
FIGURE 12

Authors Fred Ma, John Knight

January 26, 2001

Convolution Codes

FIGURE 13

Here just the cumulative Hamming distances are shown so it is easy to see which paths should be erased.

Here the unneeded paths are eliminated. This is all important information up to to t=n+3.

Recd 11 A B
2

error 0111 A B
1
4

01 A
5

11 A
2

error 0111 A B
1

01 A
2

A B

A B

2
6

C D t=n

C
1

C D t=n+2
3

1
2

C D t=n+3 2nd error 0001

C D t=n

C
1

C D t=n+2

1
2

C D t=n+3

D t=n+1

D t=n+1

Recd 11 input A
0

error 0111 A
2

FIGURE 14

01 A
2

00 A 11 1 3 1
3

A
2

Entering t=n+4, Eight paths are created temporarily Again at each node, only the lowest cumulative Hammingdistance path can be part of the most likely path so four of the eight paths will again be eliminated. The second error has made four paths all with equal chances of being the most-likely paths (four paths with 2 ) But see what happens next.

B
1

C D t=n

C
1

C D t=n+2

B B 10 2 11 1 2 2 00 01 4 C 1 C 2
0
2

D t=n+1

D t=n+3

01 10 2

2
4

D t=n+4

Recd 11 input A
0

error 0111 A
2

FIGURE 15

01 A
2

2nd error 0001 A

2

10 00 1 3 111
3
1

A B
1

A
3

B
2

C D t=n

C
1

C D t=n+2

1 C

C
2

11 1 3 B 00 10 01 0 2 C
2

Entering t=n+5 Eight new paths are created, keep the four lowest H ones enter ing each state Since two paths have the same H as they enter B, we have no way of choosing a better path. Pick one randomly; Here we choose the one AB.

D t=n+1

D t=n+3

D t=n+4

01

Note path dies out.

There are two most likely paths (with H=2). Down from four at t=n+4
January 26, 2001

10 0 2

D t=n+5

Authors Fred Ma, John Knight

Convolution Codes

Recd 11 input A B
0

error 0111 A
2

01 A
2

2nd error 0001 A

2

10
3

11 A 100 2 5 10 3 2 B
0

A B
1

B
2

2 B

C D t=n

C
1

C D t=n+2

C
2

C D t=n+5

11 2 4 00 10 01 1 4 C
1

Entering t=n+6 Note how the correlation has A continued to act. We are now down to one most likely B path.

D t=n+1

D t=n+3

D t=n+4

01

1 3

10 1 3

D t=n+6
FIGURE 16 FIGURE 17

Recd 11 input A B
0

error 0111 A
2

01
2

2nd error 0001 A

2

10
3
3

11 A

11 A 100 2 4 10 2 3 2 B A

A B
1

A B
2

3
B
2

B
2

C D t=n

C
1

C D t=n+2

C
2

C
3

0 11 2 5 B 00 0 1 01 1 4 C

3 10 1 4 D D D t=n+7 t=n+6 t=n+5 Entering t=n+7: The one best path is getting fairly clear. The most likely path ends at B and a close second at A. The paths to C and D have H= 4

D t=n+1

D t=n+3

D t=n+4

01

Retrieving the Original Message

Recd 11 input A B
0

error 0111 A B A B

FIGURE 18

01

2nd error 0001 A B A B

10 A B

11 A B

11 A B

10
4

A B

4
2

C
4

Common path D D D D D D D D D t=n+1 t=n+2 t=n+3 t=n+4 t=n t=n+6 t=n+7 t=n+8 t=n+5 Entering t=n+8: One can be fairly sure the best path at t=n+8 ends at state C. Follow the path back from C -> B-> A-> C-> B-> C-> D-> B-> A. Also follow the paths back from A, B and D. No matter what state you start in at t=n+8, all paths come together when you get back to t=n+1. From the solid (for 0)and dashed (for 1) lines along the path one can decode the probable original message as 11010010 (travelling t=n to t=n+8).
Authors Fred Ma, John Knight January 26, 2001 10

Convolution Codes

As illustrated above, the Viterbi decoder can decode a convolution code for a message of N bits in the presence of some errors. If two branches entering a state have equal H, then the code is unable to tell if one path is more likely than another. Pick one path at random.
FIGURE 19

4.1 Exercise 2: A Viterbi Decoder Design

1. Problem: Using the algorithm A typical step in the trellis decoder is shown. The cumulative Hamming distances H at each trellis step are HA, HB, HC, and HD. The Hamming distance for each edge are given subscripts matching the input which makes them 0. Thus the edge from A to A , and C to B both use the symbol h00. If the input is 00, h00=0, If the input is 10 or 01, h00=1, if the input is 11, h00=2. Input = 00 FIGURE 20
HA=4 A

HA A

0/00 h00 1/1 1

HA

11

HB HC

0/ 11

h1

0 0h 0 1/0 /1 0 0h

HB HC

10

HD

1 1h 0 0/0 1/10 h10 D

h00=

A HA= B HB= C HC= D HD= t=n+9

t=n+1 t=n a) For the rst lab partner: Starting at t=n+8 with an input of 00, as in Figure 20, calculate and ll in the values of hij and hence the Hk for t=n+9.

h1

1=

HB=4 B

= h 00 h

b) For the 2nd lab partner: Starting at t=n+9, using the Hk from step a) and input 10, calculate and ll in Figure 21. Input =10
HA= HB= HC= HD=
FIGURE 21

01 1/

h 01
D HD

11 =

10 =

= h 01

HC=2 C HD=4 D

h0

= 1

A B C D

h00=

A HA=5 B HB= C HC=

h10=

t=n+8 Input =11

HA= HB= HC= HD=

FIGURE 22

A B

A HA'= HC + h11 = 2 ' B HB=

h10=

D HD= t=n+10

t=n+9

h1
C

0=

' C HC=

= h 01
D

' D HD= t=n+11

t=n+10

c)For the 3rd partner: Start at t=n+10, with input 11 and use the Hk from step b). Let the new Hk at t=n+11 be written with a prime i.e. HA HB HC and HD Fill in Figure 22 but put ' ' ' '. in an expression, as well as a number, for '. each Hk. This has already been done for HA Only the better path is written here.

Pseudocode This is Verilog in which the syntax is not critical. For example begin, end and semicolons may be omitted if the meaning is clear to the reader. In pseudocode the comments are often more important than the code.
Authors Fred Ma, John Knight January 26, 2001 11

Convolution Codes

2. Problem: In parts a) and b) you will write pseudocode to calculate the Hamming distances for each step. Let the two input bits In[1:0] be y, x. Let the Hamming distances associated with the eight trellis edges for this step be h00, h01, etc. For part b) use reg /*wire*/ [1:0] h00, h01, h10, h11; a) Calculate these distances using a case statement: case ({y, x}) 2'b00 : begin h00=0; ... h11=2; end 2'b01 : ... b) Another partner should use Boolean algebra to calculate them as 2-bit binary numbers. Example: h00[1] = y&x ; h00[0] = y^x; 3. Problem: Pseudocode to update the Hk in going from step t=n to step t=n+1. a) Use if statements to calculate the Hk' to be associated with the four states at t=n+1. Use HAnext instead of HA' since Verilog cannot handle quotes. if (HA+h00 < HC+h11) then HAnext= HA+h00; else ... 4. Problem: The ip-op procedure. Write a procedure to clock the ip-ops and store the necessary data. Combinational logic in parts 2 and 3 calculated the D inputs for the ip-ops. For example:HAnext = ... HA + h00 .... This procedure stores the data i.e it clocks HA <= HAnext. Dont put combinational logic in a ip-op procedure, and dont forget a reset. 5. Problem: When is the output correct? Experience has shown that all backward paths converge into one if one traces them back 4 or 5 times the constraint length. Using the paths in Figure 18, you will show for this example that if one traces back far enough it does not matter which path one follows. a) Take a copy of Figure 18. Start at t=n+8; start at each state in turn and colour backwards until you reach t=n or until you hit previous colouring. At what time (t=n+?) do the paths all converge? b) Look at Figure 14 in which the ending time is t=n+4. Test decoder encoder Using data available at t=n+4 could you say, with Bench condence, what the original data bit was between t=n and t=n+1? Why not? original data bit encoded, 2 bits for 1 c) Take a copy of Figure 17. Start at t=n+7; start at each decoded output, back to 1 bit. state in turn and colour backwards until you reach t=n or until you hit previous colouring. At what time (t=n+?) do the paths all converge? In communications latency is the term for the time difference between the time the input signal was received and the output signal is sent out. d) If a decoder had to wait until all paths converged before it had condence it could send out a correct output, what would the latency be in clock cycles? There are two answers for c): (i) The latency as observed for typical data stream as shown in Figure 18 and 17. (ii) The latency, mentioned earlier, that experience has shown gives the most likely bit for almost all cases. State the latencies for both (i) and (ii).
Authors Fred Ma, John Knight January 26, 2001 12

Convolution Codes

e)

If the decoder delays the signal by 12 to 15 clock cycles, would anyone care assuming: The signal was a digitized phone conversation? The signal was a www page? The signal was a digital TV signal?

6. Problem: How to backtrack. Figure 23 is the same as Figure 18 except the numbers are all removed. It still contains enough information to trace back from t=n+8.
Retrieving the Original Message
FIGURE 23

A B

A B

A B

A B

A B

A B

A B

A B

4 A

4
B
2

C D t=n

C D t=n+1

C D t=n+2

C D t=n+3

C D t=n+4

C D t=n+5

C D t=n+6

C
4

C D t=n+8

D t=n+7

Figure 24 shows a trellis decoder only. It gives no information about the data. Figure 23 shows paths, but when you trace back to the area between t=n+2 and t=n+3 you cannot tell from the gure what the data was. a) Use Figure 24 only. If the decoder was in state C at t=n+3, what was the original data (before encoding) between t=n+2 and t=n+3? (The obvious answer is right.) If it was in state A at t=n+3, what was the original data between t=n+2 and t=n+3? If it was in state B at t=n+3, what was the original data between t=n+2 and t=n+3? If it was in state D at t=n+3, what was the original data between t=n+2 and t=n+3?
orig. data is 0 is 1

Trellis Diagram with no signal knowledge superimposed A A A A A A

FIGURE 24

B C D t=n+2

B ? C D t=n+3

B C D t=n+4

B C D t=n+5

B C D t=n+6

B C D t=n+7

B C D t=n+8

b) Figure 25 is the same as Figure 24 except some little squares have been drawn associated with each state in each time step.

Authors Fred Ma, John Knight

January 26, 2001

13

Convolution Codes

Lab partner one should ll a minimum of information in each square. This information would allow lab partner two to back trace knowing that Hc had the minimum Hamming distance at t=n+8. Thus by looking only at Figure 25 partner two, starting at state C at time t=n+8, should be able to tell what the original bit was between t=n+2 and t=n+3. You may establish some conventions like a 1 in the state C box means .... However they must be independent of the data. Using the same gure (Fill in the boxes at t=n+3 if you have not done so already) partner three should be able to determine the original data bit between t=n+1 and t=n+2. You should hand in the lled in Figure 25 and your list of conventions. Trellis Diagram on which you will superimpose signal knowledge A A A A A A
FIGURE 25

B C D t=n+2

B ? C D t=n+3

B C D t=n+4

B C D t=n+5

B C D t=n+6

B C D t=n+7

B C D t=n+8

c) How many bits per step must be stored to allow for backtracking? d) Describe the Verilog storage declaration for ip ops to hold the backtracking information. One dimension of the array will be the latency.

4.2 Extracting The Original Data.

Consider Figure 26. The path with the lowest cumulative Hamming distance H , starts at state C at t=n+8 with H=2. Backing up would take the path to B at t=n+7. The edge is a solid line which seems to say the original data was 0. Unfortunately we cant be sure of this. Because of the convolution code, this paths H of 2 could increase in the next few cycles and another path might get the lowest H. However if one goes back to t=n+2 and travels ahead in time, only paths that start at D or C make it all the way to t=n+8. The others die out. Only the path from D has H=2 at t=n+8, thus we are fairly sure the edge from D at t=n+2 to C at t=n+3 is on the most likely path and the original data between these two clock edges was 0 (a solid line is 0, a broken line is 1). This illustrates why we want to wait six (or usually more) cycles before sending out the output. If we are at time t=n+8, we can be condent that the 0 data at t=n+2 is the most likely.

Carrying the Data Forward Instead of Tracing the Path Back

Tracing back is a long process and the full trace must be done every data cycle. The back trace could be done as a FSM but this is convenient only if the clock runs several times faster than the data rate. However it turns out one can avoid the back trace, and allow the data rate to equal the clock rate, by sending the data forward through a shift register.

Authors Fred Ma, John Knight

January 26, 2001

14

Convolution Codes

input recd A B C

11
0

error 0111 A B
1
1

FIGURE 26

01
2

2nd error 0001 A

2

10
3
3

11 A B

11 A
2

10 A 100 1 4 11 4 B A B

A B

A B

2
1

B C

2
2

B
4

C C On best path

C
3

1 01 00 2
2
4

2 D 3 D 4 D D D D D D D t=n t=n+1 t=n+2 t=n+3 t=n+4 t=n+5 t=n+6 t=n+7 t=n+8 One may not be sure which data bit is best at t=n+2. However if one traces the paths forward from t=n+2, only two paths survives to t=n+8, and one has a much smaller H.

Figure 27 shows the essence of this circuit drawn to show feeding forward the ones and zeros as perceived from the data at t=n+2. This data is shifted forward through the ip ops and is not changed by later inputs. However the path through the shift register is controlled by these later inputs. At t=n+8, the decoder can supply the data bit originally received at t=n+2. The desired bit is at the end of the shift register, in the ip op corresponding to the state with the lowest H . Note this is a schematic showing connections. However, for the data in the ip-ops and the appropriate mux connections, each column represents a different time.
FIGURE 27

Recd input
A

01
A

01
A

10
A

11
A

11
A

10
4
A

0
B

0
B

0
B

0
B

1
B

1
B

0 1 1 0

1
C

0
C

0
C

0
C

0
C

1
2
4
C

0
D

1
D

0
D

1
D

0
D

0
D

t=n+2 t=n+3 t=n+4 t=n+5 t=n+7 t=n+6 t=n+8 The data bits at t=n+2 are shifted right each clock cycle. Thus the 0 bit here at the lowest H at t=n+8 is the best choice for the data bit at t=n+2. The advantage of the shift register is that one does not have to backtrack to know that the data on this path at t=n+2 was also 0. Figure 28 shows the same thing as Figure 27 except the muxes are not specically shown. It shows how the 4 data bits, inserted in the four best paths at t=n+2, can be shifted from ip-op to ip-op down the paths one clock cycle at a time. They arrive at the output at t=n+8. At each cycle the data bit is shifted right into a state controlled by later input data. These forward paths may disappear, or fork. However the minimum H path never stops, so the 0 injected into it at t=n+2 appears at t=n+8 in state C, which is the minimum H= 2 path.

Authors Fred Ma, John Knight

January 26, 2001

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Convolution Codes

Summary: Compare Figure 28 with Figure 14. Note the path from t=n+2 to t=n+8 is the same. The difference is the data bit 0was shifted through and comes out at t=n+8 without backtracking. FIGURE 28 2nd error Recd 01 0001 10 11 10 11 input A
2

0
B

0
B

0
B

1
B

B C D t=n+2

0 2B 1 1 C 1 10 0 2D
1
t=n+3

00 1 4 A 1 111 4 B

output output best output output

0
C

0
C

0
C

0
C

10
01

1
0 2 C

1
D

0
D

1
D

0
D

0
D

2
4

1
t=n+4

1
t=n+5

t=n+6 t=n+7 t=n+8 At t=n+3, one is probably in state C, but because of errors one might be A, B, or D.

If one is in state C, the decoded data between t=n+2 and t=n+3, would be 0. In state A it would be 0, and in B or D it would be 1. We will shift these data bits forward through the paths of the trellis diagram, storing the data in ip-ops during each clock cycle. Most of the paths die out. At t=n+8, the ip-op beside state C indicates there was a 0 in this path between t=n+2 and n+3. This is the same result one got in Figure 18 by tracing the path backwards.
FIGURE 29: The 0,1,0,1 between t=n+3 and n+4 is carried forward to be used at t=n+9

Recd input A B C D

2nd error 0001 A

10 A

11 A

11 A

10

00
4

0B 1 1C 00 1D 1
t=n+4

0
B

1
B

1
B

1
B C

00 0 4

1
B

4
2
4

0
C

0
C

1
C

1 10 1 0 1

00

1 0 5 C 1
D
5

1
D

1
D

0
D

1 01

1
t=n+5

1
t=n+6

1
t=n+7

t=n+9 t=n+8 The data capture at t=n+3 is carried forward along the paths, if they dont break. Note the selected trellis paths are the same as in the previous gure, but the data stored in the ip-ops is different. Figure 29 shows the next cycle where the 0,1,0,1 data bits between t=n+4 and n+5 are injected into four paths at t=n+5. Although the paths look the same as in Figure 28, the bits travelling down them are different unless they coincide by accident. Later we will see that this data can timeshare ip-ops with the data in the previous gures. Figure 30 shows the bits that would be injected into ip-ops at t=n+5. This bits would travel down the paths and be available for output at t=n+10.

t=n+3

Authors Fred Ma, John Knight

January 26, 2001

16

Convolution Codes

Figure 30 shows another point. Both possible paths coming into each state at t=n+5 are shown even though the Viterbi algorithm will discard one. This shows that no matter which path is discarded states A and C always receive a 0 and states B and D always receive a 1. Thus there is no need to actually use ip-ops to store the data. It can be hard wired. Solid lines are 0 dashed lies are 1 Recd input A 10 A 11 A 11 A 10
4
FIGURE 30

Output will not come until t=n+10

Note that both paths going into state A correspond B to a data bit of 0, thus one can permanently associate state A with 0. C Also state C can be associated with 0 and, B and D with 1. D In other words the rst column of ip-ops is redundant. t=n+4 2nd error 0001
A A

00 B 11 C 00 1D 1
t=n+5 10
A

0
B

1
B

1
4
B

0
C

0
C
2

1
C

1
D

0
4

0
D

1
t=n+6

1
t=n+7

0
t=n+8

FIGURE 31

section 3

Recd input
A

01

11
A

11
A

10
4
A

00
B B C

0
B

0
B

0
B

0
B

0
B

1 C 00 11
t=n+3
D

0
C

0
C

0
C

0
C

0
2
4
C

1
D

0
D

0
D

0
D

0
D

Useless ff t=n+2

1
t=n+4

1
t=n+5

1
t=n+6

1
t=n+7

0
t=n+8

Figure 31 is like Figure 28 except it shows how the forward path is controlled by multiplexers. The state and inputs at t=n+k control the mux which selects what will be clocked into the ipop at t=n+k+1. This will turn out to be the same logic used to select the path with the lowest H . Figure 31 looks like it has 20 MUXs and 24 ip-ops just to forward 4 bits. However: a) There is no need to use ip-ops to store the initial constants which are always 0,1,0,1. b) The four bits injected at t=n+3 need only four ip-ops at any time. If those 4 bits are shifted right the rst ip-ops become available to hold data injected later. The complete circuit can be arranged as an unconventional shift register. See Figure 33. Figure 32 shows data injected at three different time steps travelling down the paths. At any given time only 4 ip-ops are in use for todays input set. However 4 more are used for the previous set, and 4 more for the set before that. To get Figure 33 from Figure 32, note that at say t=n+6 only one set of ip-ops and MUXs is active in each section. Thus at t=n+6 one can overlay the three sections of the gure and ignore
Authors Fred Ma, John Knight January 26, 2001 17

Convolution Codes

components operating at any time except t=n+6. The top of Figure 32 has two more sections which were left out because the gure was too big already. When the ve sections are overlaid, and one extracts all the registers active at t=n+6, one obtains Figure 33
FIGURE 32:

To show three shift registers can be compacted into one Only 4 ip-ops in each section are active at say t=n+6, thus only the shaded ip-ops are in use. The others only show what is going to be stored later or what was stored earlier. This means that at t=n+6 one can erase all but the shaded ip-ops.

The data is collected between t=n+2 and n+3 Note it is always the same.
#A #B#C#D

MUX control wires

4
0 0 1 1

4
1 0 0 1

4
1 1 0 0

Sections 4 and 5 would be up here but are not shown.

0 1 0 1
t=n+3 Data from t=n+3 to n+4

0 0 1 1

0 0 0 1

This shows how the data collected between t=n+2 and t=n+3 goes through the shift register.
To see what is in the shift register at any given time follow a common time down as was done for the shaded MUXs at t=n+6.

t=n+4
0 0 1 1

t=n+5
1 0 1 1

t=n+6
1 1 0 1

t=n+7
1 1 1 1

t=n+8
1 1 1 1

0 1 0 1

section 2

How the data collected during t=n+3 to n+4 goes through the shift register.
The control for the MUXs is represented by the line running through them. This line is a cable and contains 4 wires.

t=n+4 Data from t=n+4 to n+5

t=n+5
0 0 1 1

t=n+6
1 0 0 1

t=n+7
1 1 0 0

t=n+8
1 0 1 1

t=n+9
1 1 0 0

0 1 0 1

section 1

How the data collected during t=n+5 to n+6 goes through the shift register.
Note all MUXs operating at a given time, have the same control lines. The top (state A) MUX in each section all use control wire #A. The bottom MUXs all use wire #D, etc.

t=n+5

t=n+6

t=n+7

t=n+8

t=n+9

t=n+10

In Figure 33, four data bits start through the trellis paths in each clock cycle. The MUXs do not change the bits but only place them in the right path. Since all the columns represent the same time step all the MUXes are set the same way in each column. Here they are set for t=n+6.

Authors Fred Ma, John Knight

January 26, 2001

18

Convolution Codes

FIGURE 33 WARNING: This shows hardware and data at a single time.

#A #B#C#D Control wires

4 4 A 4 A A

0
B

0
B

1
B

0
B

1
B B

1
C

0
C

0
C

0
C

1
C C

0 1
D

1
D

0
D

0
D

1
D D

t=n+6 t=n+6 t=n+6 t=n+6 t=n+6 t=n+6 Column (i) (ii) (iii) (iv) (v) Shift register structure. The ip-ops contain the data for t=n+6. The 4 path edges selected at t=n+6 were made thicker. The rst three columns contain the data that can be taken from Figure 26. Column (I) contains data injected at t=n+2 and one has to go back to Figure 17 to obtain it. Can you calculate the data in column (v)? Hypertext link to solution (Figure 45). All 5 MUXs in a row are controlled by the same input line, i.e wire #A for the top row, #B for the next etc.

4.3 Summary of Circuit Up Through Section 4.4

Test Bench Signal Source Comparison with original signal (loopback) dataIn reset clk Top module Encoder serial_in
Error generator

Encoder

dataOut

serial_in_err Top module serial_in_err Decoder Serial-to Parallel convSig[2:1]

Calc_Came_From_and_Ham_Dist input clk, reset, convSig[2:1]; output dataOut;

Data_Shift_Forward input clk, reset, came_from[4:1]; //maybe input HA,HB,HC,HD; output dataOut;

Authors Fred Ma, John Knight

January 26, 2001

19

Convolution Codes

4.4 Second Lab: Start of Convolution Decoder in Verilog

At this point the lab is starting to switch from a lab to a project. It is now you need to know where you are going. You should be able to recognize each block in the block diagram. The Data_Shift_Forward block has been described in the theory. However it will not be done until Exercise/Lab 3. You should consider these concepts: a) Normally the encoder and decoder are widely separated so they cannot run from a common clock. The decoder will have a clock recovery module. This is beyond 97.478 and we will use a common clock for both.

b) Your design will be a rate=1/2, constraint length=3; [111],[101] decoder. This is to make it easy to check things by hand or from books. c) To save work you will want to parameterize your design. One can do this automatically in Verilog for some parameters. For others it too much trouble. First, design a distinctive comment style like /*|Para|* comment on parameters *|Para|*/ which indicate code where there are parameters nearby which will need attention. In your comments cross-reference all the modules that are effected by the parameters. Second, there are two ways to pass parameters in Verilog. Which one works for synthesis? d) Considerable emphasis will be given to testing. One simple test is a loopback test where the output is sent back to the input and the two compared. Other thing you can do to your circuit to aid testing will be considered later. e) The Error Generator block is necessary if you want to simulate to the error correction properties. First it will be done as a test bench so it is only useful during simulation. Later you might consider making it part of the loopback test so it can be used for testing in the eld.

What to do for the lab 1. Draw a block diagram somewhat like that of Section 4.3 on page 19. 1However make it bigger and show the arguments passed to all modules. If a module will be over a page of code, try to divide it. 2. Write Verilog for the Decoder Top Module and Encoder Top Module (already done?) 3. Design a serial to parallel module. The serial_in signal changes at twice the clock rate. Let the serial_in bits be labelled s, e, r, i, a, l ... Decide how these bits will come out of a transparent-high latch.See the latch_sig below. You will probably use a transparent latch and two ip-ops in the module.
serial_in
or serial_in_err

1D C1
Transparenthigh latch

1D C1

1D C1

clk serial_in s latch_sig ConvSig[1] ConvSig[2]

e s

r s e

a r i

Waveforms for serial to parallel

FIGURE 34

1. We like originality in block diagrams as long as you can give a reason for changes.
Authors Fred Ma, John Knight January 26, 2001 20

Convolution Codes

4. Write the Verilog code for the serial to parallel module. How do you write a latch in Verilog? Hints, see Figure 46. 5. Write the Calculate Next State and Hamming Distance module. (See Exercise 2.) 6. Modify the Test Bench to handle the decoder and the encoder. This should include a loopback test which compares the dataIn (x on the right) with dataOut. You will have a delay (latency) between dataIn and dataOut. At the start dataOut will be the bit corresponding to the present lowest H (cumulative Hamming distance) so the latency will be only that of the serial-to-parallel converter. Later you will want to add a latency of 4 to 5 times the constraint length.
Calc_Nxt_State_and_Ham_Dist

// send in a new x every clock cycle always @(posedge clk) begin if (I==9) $nish; x<= #1 data[I]; if(I>latncy) y<=#1 data[I-latncy]; I<=I+1; end assign err=(y!=dataOut) FIGURE 35

7. Add to the module to generate a four-bit signal called came_from. These signals indicate whether the trellis lines leading back from the next states to the present-time-step states, came from a higher state or a lower state. Thus it would show whether the next state A came from the present A (up) or C (down). Figure 36 shows these bits and their meaning. These will be the MUX control signals to shift the data forward. 8.
3 A

input 11 00 2 5 110
0

FIGURE 36

A came_from[0]=down
2

3 B

2 C

11 0 2 5 0 10 0 3 01
2
5

B came_from[1]=up C came_from[2]=up

2 D

01

t=now

10 1 3 D came_from[3]=down t=next step (now + 1)

Then write a preliminary Data_shift_Forward module stub which has input declarations for these four signals but no code to do anything with them, at least not yet.
FIGURE 37

9. Consider the Error Generator. For the moment treat it like a test bench so you can use nonsynthesizable constructs like $random. This gives a new random integer every time it is called. Try to make it so there is an error every 16 time steps (every 32 serial_in bits) on average. A random 5-bit number will be 01110 (or any single value) one time out of 32 on average. Alternately you might try a pseudorandom generator as used to be done in 97.350. There is a lot about pseudorandom generators in the notes.

reg [4:0] randy; always @(clk) begin //Run at twice clock rate //randy gets the 5 lsb of $random randy <= $random; if (randy = = 4b01110) serial_in_err<= ~serial_in;

Authors Fred Ma, John Knight

January 26, 2001

21

Convolution Codes

4.4.1 Feed Forward, an Alternate Viewpoint

D C B A Input 11
n+0 n+1

11
n+2

01
n+3

01
n+4

10
n+5

11
n+6

11
n+7

10
n+8

00 time

State Inputs 1 0 1 0

1010 1010 1010 1010 1010 1010 1010 1010 1010 1100 1100 1100 1100 1100 1100 1100 1100 0001 0111 0111 1000 1101 1001 0000 0000 1011 0111 1100 1011 0011
space

0000 1111 0011 1001 1111 0000 1111 0110 0011 0000 1111 1100 Output

0
\//\

1
////

1
//\/

Direction of came_from

\\/\

///\

/\\\

/\\\ \//\

\\/\

FIGURE 38 The horizontal axis is time. the vertical axis shows the circuit (space). The table

shows how the state input bits shift through the ip-ops with time. Boxes in the same row show the contents of the same four ip-ops, each box shows a different time. Boxes in the same column show the ip-op contents at a given time. The \ and / symbols at the bottom show the direction the mux inputs came from. In each time step the six muxs in a column have the same control signal.

4.5 Third Exercise: Forward Tracing

1. Problem: Walk-through of the data-shift-forward algorithm Figure 39 through Figure 44 show one step of the trellis on the left, and the circuit to implement the shift forward on the right. You will ll in the data as it exists in the circuit. It is important to note the circuit only shows data at one time, t=now. The trellis diagram shows more than one time. In the circuit you will show the data at the ip-ops D inputs ready to be stored and the likely different data stored inside the ip-op. 2. Problem: Assign a group member to clean up unnished parts from Lab 2. 3. Problem: Write pseudocode for the Data_Shift_Forward module a) The latency will be a parameter which will effect this module and the loopback test. You will want to dene this parameter from the top module (or maybe the testbench) and pass it down. Write down how to do this.

Authors Fred Ma, John Knight

January 26, 2001

22

Convolution Codes

input recd A B C D
t=now

decoded bit between t=now and t=now+1 for state A

FIGURE 39

01 A
2

01 A
2

02 1 0 13
1

B C D

B C D

0 B 2 1 13C 0
2

If you know the present and next trellis states, then you know what the proper decoded output bit is. You can guess the states by choosing the lowest H but often you must wait several steps to be sure.

t=now+1

t=now t=now+1

a) Fill in the blanks showing the candidate decoded bits between t=now and now+1 for each state in these two typical trellis steps. Here we inject the data associated with each path into the initial ip ops of the feed-forward shift register. b) At the D-input to each ip-op, show the bit that will be stored on the next clock after t=now. State C has it written in already.
#1 #2 #3 #4

FIGURE 40 A

input recd A B
1

01
A

A
2

C D t=now
(t=n+2)

02 1 0 13
1

B C

D t=now+1

(t=n+3)

0 0 1 1 0 0 1 1 t=now

X
B

X 0 X
D C

Unknown We havent put anything is in these ip-ops at the start

D input to this ip-op

TRELLIS

CIRCUIT

The clock has advanced one cycle from Figure 38. c) Fill in the data on the D inputs in column (i), and also what was clocked into the column (i) ip-ops (Q). Fill the column (ii) D inputs.These will be shifted from column (i) along the best four paths. The rst row of muxes is shown with dashes because they are redundant.

FIGURE 41

input recd

2nd error 0001 A

2

#1 #2 #3 #4

Control wires

2 A 2 B 1 C 3 D t=now
(t=n+3)

0
B B B

0 2 1 0 1
2

1
C C

3 C

0
D

X
D

D t=now+1
(t=n+4)

1
Q

t=now
D

(i)

(ii)

Authors Fred Ma, John Knight

January 26, 2001

23

Convolution Codes

the up or down position input 10 recd 3 A The rst column 2 A of muxes is 3 slowly being B 2 B removed from the picture. 2

0 1 0

UP #1 #2 #3 #4

Control wires

FIGURE 42 4 #1 A

4 #1

0
B B

B #2 #2

1
C C

3 C 2 D

C
2 D 1t=now+1
(t=n+5)

#4

(t=n+4)

t=now

(i)

(ii)

d) Continue writing in D and Q for the ip-ops. Also write in whether the control wires will switch the muxes to up or down. input recd The 1st column of MUXes has been removed. We dont need them. The shaded ip-ops will be removed in the next gure.
3 A 3 B 2 C 2 D
#1 #2 #3 #4 Control wires

FIGURE 43 4 A 4 A

11
A A

1 3 0 B 03
C

A
B

0
B B B B

1
C C C C C

0
D D D D D

t=now
(t=n+5)

13

D t=now+1
(t=n+6)

1
(i) (ii)
Control wires

e) Continue writing in D and Q for the ip-ops. input recd

2 A 3 B 2 C 2 D t=now
(t=n+6)
#1 #2 #3 #4

(iii) t=now

FIGURE 44 4 A 4 A

11
A A

1 2 0 B 04
C

A
B

0
B B B B

1
C C C C C

0
D D D D D

14

D t=now+1
(t=n+7)

t=now

f) Complete lling in the Q outputs. At now which is also t+6, we know the best path ends on B. g) How do you nd what the data value on that path was between t=n+2 and n+3?

Authors Fred Ma, John Knight

January 26, 2001

#4

t=now

#3

#3 D

0
1

(iii)

(iv)

24

Convolution Codes

b) Develop pseudocode to implement the forward shift registers. A hint as to a possible method follows: Dene four registers in the form of: reg [1:latency-1] Areg, Breg, Creg, Dreg; Then considerif (came_from[A]) AregNxt ={0,Areg}>>1; else AregNxt={0,Creg}>>1; Watch out whether you shift in a 1 or a 0. on the left. The following code may give you some ideas: parameter lat=12; // latency parameter A=0, B=1, C=2, D=3; reg [1:lat] Areg, Breg, Creg, Dreg; //Storage reg [1:lat] Anxt, Bnxt, Cnxt, Dnxt; //Not storage always @(came_from or A reg or Breg or Creg or Dreg) begin if (came_from[A])Anxt={1'b0,Areg}>>1; else Anxt={1'b0,Creg}>>1; if (came_from[B])Bnxt= whatever; if (came_from[C]) Cnxt= ...; if (came_from[D]) Dnxt= ...; end always @(posedge clk or posedge reset) begin Areg<=Anxt; Breg<=Bnxt; Creg ... Dreg ... if (reset) begin Areg<=0; Breg<=0; Creg<=0; Dreg<=0; end end c) Decide a strategy to get the dataOut bit. Do you take the one on the best path? Do you take the majority of the four? Do you take the rst one and assume the others will be the same? Write some pseudocode to implement your strategy to get the dataOut bit.

Authors Fred Ma, John Knight

January 26, 2001

25

Convolution Codes

4.6 Some Hints and Answers

Solution: to Figure 33. (back)
PARTIAL COPY OF FIGURE 17 FIGURE 45

A B

A B
1

A
2

A
2

A B
2

3
3

A
2

A 1 10 2 B
11
0

A
3

3
B
2

B
2

B
4

10 1
C
3

C D t=n

C
1

C D t=n+2
0 0 1 1

C
2

C
3

C D t=n+7
1 1 1 1

D t=n+1

D t=n+3
1 1 1 0

D t=n+4

D t=n+5
1 1 1 1

D t=n+6
1 1 1 1

10 1 4

0 1 0 1
t=n+1

1 1 0 1

1 1 1 1

t=n+2
0 0 1 1

t=n+3

t=n+4

t=n+5
1 1 0 0

t=n+6
0 1 1 0

t=n+7

t=n+8

0 1 0 1
t=n+2

1 1 1 0

1 1 1 0

0 0 1 1

t=n+3

t=n+4

t=n+5

t=n+6

t=n+7

t=n+8

FIGURE 46. How to code a latch

(Back)

Latches have something happen on both edges. Do not use posedge clock. When transparent, latches must follow the data. You need more than @(clock). Put the reset for the latch in the procedure for the latch, not with some stray ip-op. Latches cannot be put in the same procedure as ip-ops. Do not put logic in the same procedure as the latch.

Authors Fred Ma, John Knight

January 26, 2001

26