Compal LA-D101P r0.1

A B C D E
1 1
Compal Confidential
2 2
BIWB6/BIWB7/BIWE7/BIWE8
DIS M/B Schematics Document
Intel Skylake U Processor with DDR3L
AMD EXO Pro / MESO XT
2015-03-17
3 3
LA-D101P
REV：
：0.1
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/24 2012/07/12 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D101P
Date: Wednesday, March 04, 2015 Sheet 1 of 53
A B C D E
A B C D E
For DIS Memory Bus

A-ch DDR3L-SO-DIMM X1
DDR3L 1600MHz (1.35V)
AMD Exo Pro 18W PCIe X4
VRAM 1GB/2GB
DDR3L x4 (Gen2)
Memory Bus
1
AMD Meso XT 25W Reserve
B-ch DDR3L-SO-DIMM X1 1
VRAM 1GB/2GB DDR3L 1600MHz (1.35V)

DDR3L x4
eDP X1 Left USB3.0 x2 Right USB2.0 x1 Int. Camera

(2 Lanes) USB3.0 x3 USB30 Port 1,2 USB20 Port 4 USB20 Port 5
eDP Conn.
DDI X1 USB2.0 x9 Touch Screen Right USB2.0 x1 Finger Printer
CRT Translator (2 Lanes) Reserve For E14
USB20 Port 6
CRT Conn. Realtek USB20 Port 8 USB20 Port 3
RTD2168
USB3.0 X1
Docking USB2.0 X1 Intel SKYLAKE U
For B15 E15 SATA X1 HDD Conn.
USB30 Port 3 DDI X1 15W SATA Port 0
USB20 Port 9 DP Switch (4 Lanes)
2 2
For Docking 1168pin BGA
HDMI Conn. PS8339BQFN56GTR2 SATA X1 ODD Conn.
SATA Port 1
For No Docking
I2C X1 NFC Conn.

PCIe X1 Reserve
LAN (1 Lanes) I2C Port 1
PCIe Port 5
RJ45 Conn. Realtek
RTL8107E/RTL8111H
10/100/GIGA
PCIe X1 Audio Codec

Card Reader HDA Realtek
PCIe Port 9
(1 Lanes) ALC3240
Realtek
RTS5220-GRT
PCIe X1
NGFF Conn. (1 Lanes)
Sub-borad Int. MIC Conn. Int. Speaker Conn. Audio Combo Jacks
WLAN / BT HP & MIC
3
15" USB2.0 X1
3
14" (1 Lanes)
PCIe Port 6
DC-in/B Docking/B
For B15 E15 USB20 Port 7
Option LPC BUS
Power/B Battery/B SPI ROM EC TPM
8MB Nuvoton Reserve
NPCE388N Z32H320TC
IO/B ODD/B
For E14
USB Charge
Thermal Sensor Touch Pad Int. KBD APS

Reserve For E14
Reserve
4 4

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
MB Block Diagram
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E
1 2 3 4 5
Voltage Rails USB Port Table

3 External BOM Structure Table
USB 2.0 Port USB Port Item BOM Structure
+5VS 0 USB Port (Left Side) USB3.0 BIWB6 (14") B14@
UHCI0
+3VS 1 USB Port (Left Side) USB3.0 BIWB7 (15") B15@
power
plane +1.5VS 2 Touch Screen BIWE7 (14") E14@
A UHCI1 A
+V1.05S_VCCP 3 Camera BIWE8 (15") E15@
EHCI1
+5VALW +1.35V +VCC_CORE 4 Docking Option Docking@
UHCI2
+B +VGA_CORE 5 No Docking Option NoDocking@
+3VALW +VCC_GFXCORE_AXG 6 LAN RTL8107E-CG 8107E_LDO@
UHCI3
+1.8VS 7 LAN RTL8111H-CG 8111H_LDO@
State +0.75VS 8 Deep Sleep DS3@
UHCI4
+1.05VS 9 USB Port (Right Side USB-BD) No Deep Sleep NODS3@
10 Mini Card(WLAN) GPU EXO Pro EXO@
EHCI2 UHCI5
11 Card Reader GPU MESO XT MESO@
12 For DIS PX@
UHCI6
13 For PCIE Gen2 PX_G2@
For PCIE Gen3 PX_G3@
S0 O O O O For UMA UMA@
Camera COMS@
Touch Screen TS@
S3
O O O X TPM TPM@
No TPM NOTPM@
S5 S4/AC O O X X EMI pop EMI@
B
EMI Un-pop @EMI@ B
S5 S4/ Battery only
O X X X ESD pop ESD@
ESD Un-pop @ESD@
S5 S4/AC & Battery
X X X X For CMC Debug CMC@
don't exist
For ES Sample ES@
Finger Printer FP@
NFC NFC@
EC SM Bus1 address EC SM Bus2 address EC SM Bus3 address R-Short RS@
UC1 UC1
APS (G-sensor) GS@
Device Address Device Address Device Address No APS (G-sensor) NOGS@
Smart Battery 0001 011x Thermal Sensor 1001 101xb 9Ah APS (G-Sensor) 0001 100X Test Point TP@
CPU1@ CPU2@
USB 3.0 USB3@
CPU CPU VRAM indentify X76@
SA00008M420 SA00008M320
HDMI Royalty 45@
PCH SM Bus address PCH SML1 Bus address ZZZ ZZZ ZZZ ZZZ
Connector ME@
DA6001FI000 PCB_14_DIS@
Device Address Device Address
DDR_JDIMM1 1010 000x A0h AMD thermal sensor 1000 001xb 82h
DA6001FJ000 PCB_14_UMA@
DDR_JDIMM2 1010 010x A4h
DA6001FI100 PCB_15_DIS@
PCB_14_DIS@ PCB_14_UMA@ PCB_15_DIS@ PCB_15_UMA@
PCB PCB PCB PCB
DA6001FJ100 PCB_15_UMA@
DA6001FI000 DA6001FJ000 DA6001FI100 DA6001FJ100
X7654738LB1 JH1G@
SMBUS Control Table
C C
X7654738LB2 JM1G@
UV1 UV1
X7654738LB3 JS1G@
Thermal X7654738LB4 JH2G@
SOURCE VGA BATT KB9012 SODIMM WLAN Sensor PCH
X7654738LB5 JM2G@
SMB_EC_CK1
KB9012
SMB_EC_DA1 +3VALW
X V
+3VALW
X X X X X EXO@
VGA
MESO@
VGA
X7654738LB6
SA00008M420
JS2G@
CPU1@
SMB_EC_CK2
KB9012
SMB_EC_DA2 +3VS +3VGS
V X X X X V
+3VS
V
+3VALW
SA000087T00 SA00008B100
SA00008M320 CPU2@
PCH_SMBCLK
PCH
PCH_SMBDATA +3VALW
X X X V
+3VS
V
+3VS
X X
PCH_SML0CLK
PCH
PCH_SML0DATA +3VALW
X X X X X X X
SML1CLK
SML1DATA
PCH
+3VALW +3VGS
V X V
+3VS X X V
+3VS X
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
D Full ON HIGH HIGH HIGH HIGH ON ON ON ON D
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
Size
Notes List
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Date:
LA-D101P
Wednesday, March 04, 2015 Sheet 3 of 53
1 2 3 4 5
5 4 3 2 1
EXO Pro / MESO XT VRAM STRAP Power-Up/Down Sequence

X76@ X76@ "EXO" has the following requirements with regards to power-supply
Vendor
UV3, UV4, UV5, UV6
ID PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ]
R_pu
RV21
R_pd
RV24 ‧
sequencing to avoid damaging the ASIC:
All the ASIC supplies must reach their respective nominal voltages within 20ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.
‧
Hynix 2048Mbits The maximum slew rate on all rails is 50 mV/µs.
‧
JH1G@ SA00006H400
D 1GBytes 128Mx16 H5TC2G63FFR-11C 0 0 0 0 NC 4.75K It is recommended that the 3.3-V rail ramp up frist. D
It is recommended that the 0.95-V rail reach at least 90% of its nominal value no later
1GBytes
JM1G@
Micron 2048Mbits
SA000067500
128Mx16 MT41J128M16JT-093G 1 0 0 1 8.45K 2K ‧ than 2ms from the start of VDDC ramping up.
The power rails that are shared with other components on the system should be gated for
the dGPU so that when dGPU is powered down (for example AMD PowerXpressTM idle state),
1GBytes
JS1G@
Samsung 2048Mbits
SA000068U00
128Mx16 K4W2G1646E-BC1A 2 0 1 0 4.53K 2K
‧
all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as 50mV/us)
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
≦
2GBytes
JH2G@
Hynix 4096Mbits
SA00008DN00
256MX16 H5TC4G63CFR-N0C 4 1 0 0 4.53K 4.99K
‧ should reach 90% before VDD_CT starts to ramp up (or vice versa).
For power down, reversing the ramp-up sequence is recommended.
Micron 4096Mbits
JM2G@ SA000077K00
2GBytes 256Mx16 MT41J256M16HA-093G 5 1 0 1 3.24K 5.62K
Samsung 4096Mbits
JS2G@ SA000076P80
2GBytes 256MX16 K4W4G1646E-BC1A 6 1 1 0 3.4K 10K
ZZZ ZZZ ZZZ VDDR3(+3VGS)
C
PCIE_VDDC(+0.95VGS) C
JH2G@ JM2G@ JS2G@

2G HYNIX 2G MICRON 2G SAMSUNG
X7654738LB1 X7654738LB2 X7654738LB3
VDD_CT(+1.8VGS)
ZZZ ZZZ ZZZ
VDDR1(+1.35VGS)
JH1G@ JM1G@ JS1G@ VDDC/VDDCI(+VGA_CORE)

1G HYNIX 1G MICRON 1G SAMSUNG
X7654738LB4 X7654738LB5 X7654738LB6
DGPU_PWROK
PERSTb
REFCLK
Straps Reset
B B
Straps Valid
Global ASIC Reset
A A

VGA Notes List
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5 4 3 2 1
A B C D E
1 1
SOC_DP1_CTRL_DATA(Internal Pull Down):

UC1A SKL-U
Display Port B Detected Rev_1.0
E55 C47
[28] CPU_DP1_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 [26]
0 = Port B is not detected. [28] CPU_DP1_P0
E58 DDI1_TXP[0] EDP_TXP[0] D46
EDP_TXP0 [26]
<DP to VGA> [28] CPU_DP1_N1 DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 [26]
F58 C45
[28] CPU_DP1_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 [26]
1 = Port B is detected. ==> Default DDI1_TXN[2] EDP_TXN[2]
G53 B45 <eDP>
F56 DDI1_TXP[2] EDP_TXP[2] A47
G56 DDI1_TXN[3] EDP_TXN[3] B47
DDI1_TXP[3] EDP_TXP[3]
+3VS CPU_DP2_N0 C50 E45
[36] CPU_DP2_N0 DDI2_TXN[0] DDI EDP_AUXN EDP_AUXN [26]
CPU_DP2_P0 D50 EDP F45
[36] CPU_DP2_P0 DDI2_TXP[0] EDP_AUXP EDP_AUXP [26]
CPU_DP2_N1 C52
[36] CPU_DP2_N1 DDI2_TXN[1]
CPU_DP2_P1 D52 B52
1 2 [36] CPU_DP2_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL
SOC_DP1_CTRL_DATA <HDMI> CPU_DP2_N2
[36] CPU_DP2_N2 B50 DDI2_TXN[2] G50
RC1 2.2K_0402_5% CPU_DP2_P2
[36] CPU_DP2_P2 DDI2_TXP[2] DDI1_AUXN DDI1_AUX_DN [28]
CPU_DP2_N3 D51 F50 DP Aux (Port B for VGA)
[36] CPU_DP2_N3 DDI2_TXN[3] DDI1_AUXP DDI1_AUX_DP [28]
1 2 SOC_DP1_CTRL_CLK CPU_DP2_P3 C51 E48
[36] CPU_DP2_P3 DDI2_TXP[3] DDI2_AUXN DDI2_AUX_DN [36]
RC2 2.2K_0402_5% F48 DP Aux (Port C for Docking)
DDI2_AUXP DDI2_AUX_DP [36]
G46
DISPLAY SIDEBANDS RSVD F46
SOC_DP1_CTRL_CLK L13 RSVD
SOC_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9 From VGA Trans.
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 DDI1_HPD [28]
L7 TMDS_B_HPD [27,36]
From HDMI
N7 GPP_E14/DDPC_HPD1 L6
[27,36] HDMICLK_NB GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2
HDMI DDC (Port C) N8 N9
[27,36] HDMIDAT_NB GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 EC_SCI# [34,9]
L10 From eDP
< Compensation PU For eDP > N11 GPP_E17/EDP_HPD EDP_HPD [26]
Docking_PRSNT# N12 GPP_E22 R12
2 +1.0VS_VCCIO [35,36] Docking_PRSNT# GPP_E23 EDP_BKLTEN ENBKL [26,34] 2
R11
EDP_BKLTCTL INVPWM [26]
EDP_COMP E52 1 OF 20 U13
EDP_RCOMP EDP_VDDEN PCH_ENVDD [26]
RC3 1 2 EDP_COMP SKL-U_BGA1356
24.9_0402_1% @
Trace width=20 mils, Spacing=25mil, Max length=100mils
+3V_PCH
1 2 Docking_PRSNT#
RC98 10K_0402_5% +1.0VS_VCCIO
1
RC4 UC1D SKL-U

+1.0V_VCCST 1K_0402_5% Rev_1.0
T99 TP@ SOC_CATERR# D63 < PU/PD for CMC Debug >
H_PECI A54 CATERR# +1.0VS_VCCIO
[34] H_PECI
2
1 2 H_THERMTRIP# 1 2 H_PROCHOT#_R C65 PECI

[34] H_PROCHOT# PROCHOT# JTAG
RC5 1K_0402_5% RC6 499_0402_1% H_THERMTRIP# C63
SOC_OCC# A65 THERMTRIP# SOC_XDP_TMS RC11 1 @ 2 51_0402_5%
T100 TP@ SKTOCC#
CPU MISC B61 CPU_XDP_TCK0
XDP_BPM#0 C55 PROC_TCK D60 SOC_XDP_TDI SOC_XDP_TDI RC12 1 @ 2 51_0402_5%
T103 TP@ BPM#[0] PROC_TDI
T105 TP@ XDP_BPM#1 D55 A61 SOC_XDP_TDO
XDP_BPM#2 B54 BPM#[1] PROC_TDO C60 SOC_XDP_TMS SOC_XDP_TDO RC13 1 @ 2 51_0402_5%
T107 TP@ BPM#[2] PROC_TMS
XDP_BPM#3 C56 B59 SOC_XDP_TRST#
T109 TP@ BPM#[3] PROC_TRST#
T111 TP@ SOC_GPIOE3 A6 B56 PCH_JTAG_TCK1
follow CRB A7 GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 SOC_XDP_TDI CPU_XDP_TCK0 RC14 1 @ 2 51_0402_5%
[26] TS_INT# GPP_E7/CPU_GP1 PCH_JTAG_TDI
BA5 A56 SOC_XDP_TDO
[26] TS_Detect GPP_B3/CPU_GP2 PCH_JTAG_TDO
SOC_GPIOB4 AY5 C59 SOC_XDP_TMS PCH_JTAG_TCK1 RC15 1 @ 2 51_0402_5%
T115 TP@ GPP_B4/CPU_GP3 PCH_JTAG_TMS C61 PCH_XDP_TRST# T116 TP@
3 RC7 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 PCH_TRST# A59 CPU_XDP_TCK0 3
RC8 2 1 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP JTAGX
RC9 2 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP SOC_XDP_TRST# RC23 1 2 51_0402_5%
RC10 2 1 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
4 OF 20
SKL-U_BGA1356
@
4 4

SKL-U(1/12)DDI,EDP,MISC,CMC
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
A B C D E
5 4 3 2 1
Interleaved Memory
D D
SKL-U
UC1C
UC1B SKL-U Rev_1.0
Rev_1.0
[17] DDR_A_D[0..15] [18] DDR_B_D[0..15] Interleave / Non-Interleaved
DDR_A_D0 AL71 AU53 DDR_A_CLK#0 DDR_A_CLK#0 [17] DDR_B_D0 AF65 AN45 DDR_B_CLK#0 DDR_B_CLK#0 [18]
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKN[0] AT53 DDR_A_CLK0 DDR_B_D1 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1
DDR0_DQ[1] DDR0_CKP[0] DDR_A_CLK0 [17] DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK#1 [18]
DDR_A_D2 AN68 AU55 DDR_A_CLK#1 DDR_A_CLK#1 [17] DDR_B_D2 AK65 AP45 DDR_B_CLK0 DDR_B_CLK0 [18]
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_B_D3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1
DDR0_DQ[3] DDR0_CKP[1] DDR_A_CLK1 [17] DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 [18]
DDR_A_D4 AL70 DDR_B_D4 AF66
DDR_A_D5 AL69 DDR0_DQ[4] BA56 DDR_A_CKE0 DDR_B_D5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR0_DQ[5] DDR0_CKE[0] DDR_A_CKE0 [17] DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE0 [18]
DDR_A_D6 AN70 BB56 DDR_A_CKE1 DDR_A_CKE1 [17] DDR_B_D6 AK67 AP55 DDR_B_CKE1 DDR_B_CKE1 [18]
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[1] AW56 DDR_B_D7 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55
DDR0_DQ[7] DDR0_CKE[2] TP@ T119 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] TP@ T120
DDR_A_D8 AR70 AY56 DDR_B_D8 AF70 AP53
DDR0_DQ[8] DDR0_CKE[3] TP@ T118 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] TP@ T121
DDR_A_D9 AR68 DDR_B_D9 AF68
DDR_A_D10 AU71 DDR0_DQ[9] AU45 DDR_A_CS#0 DDR_B_D10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
DDR0_DQ[10] DDR0_CS#[0] DDR_A_CS#0 [17] DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDR_B_CS#0 [18]
DDR_A_D11 AU68 AU43 DDR_A_CS#1 DDR_A_CS#1 [17] DDR_B_D11 AH68 AY42 DDR_B_CS#1 DDR_B_CS#1 [18]
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_B_D12 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0
DDR0_DQ[12] DDR0_ODT[0] DDR_A_ODT0 [17] DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDR_B_ODT0 [18]
DDR_A_D13 AR69 AT43 DDR_A_ODT1 DDR_B_D13 AF69 AW42 DDR_B_ODT1
DDR0_DQ[13] DDR0_ODT[1] DDR_A_ODT1 [17] DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 [18]
DDR_A_D14 AU70 DDR_B_D14 AH70
DDR_A_D15 AU69 DDR0_DQ[14] DDR_B_D15 AH69 DDR1_DQ[14]/DDR0_DQ[30]
DDR0_DQ[15] DDR3L / LPDDR3 / DDR4 [18] DDR_B_D[16..31] DDR1_DQ[15]/DDR0_DQ[31] DDR3L / LPDDR3 / DDR4
BA51 DDR_A_MA5 DDR_A_MA5 [17] DDR_B_D16 AT66 AY48 DDR_B_MA5 DDR_B_MA5 [18]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 DDR_B_D17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA9
[17] DDR_A_D[16..31] Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA9 [17] DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR_B_MA9 [18]
DDR_A_D16 BB65 BA52 DDR_A_MA6 DDR_B_D18 AP65 BA48 DDR_B_MA6
DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR_A_MA6 [17] DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR_B_MA6 [18]
DDR_A_D17 AW65 AY52 DDR_A_MA8 DDR_B_D19 AN65 BB48 DDR_B_MA8
DDR_A_D18 AW63 AW52 DDR_A_MA7 DDR_A_MA7 [17] DDR_B_D20 AN66 AP48 DDR_B_MA7 DDR_B_MA7 [18]
DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BS2 DDR_B_D21 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_BS2
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_BS2 [17] DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_BS2 [18]
DDR_A_D20 BA65 AW54 DDR_A_MA12 DDR_A_MA12 [17] DDR_B_D22 AT65 AN50 DDR_B_MA12 DDR_B_MA12 [18]
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 DDR_B_D23 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11
DDR_A_D22 BA63 BA55 DDR_A_MA15 DDR_B_D24 AT61 AN53 DDR_B_MA15
DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_A_MA15 [17] DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_MA15 [18]
DDR_A_D23 BB63 AY54 DDR_A_MA14 DDR_A_MA14 [17] DDR_B_D25 AU61 AN52 DDR_B_MA14 DDR_B_MA14 [18]
C DDR_A_D24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AU46 DDR_A_MA13 DDR_B_D26 AP60 DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] BA43 DDR_B_MA13 C
DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_A_MA13 [17] DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR_B_MA13 [18]
DDR_A_D25 AW61 AU48 DDR_A_CAS# DDR_A_CAS# [17] DDR_B_D27 AN60 AY43 DDR_B_CAS# DDR_B_CAS# [18]
DDR_A_D26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_WE# DDR_B_D28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_WE#
DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_WE# [17] DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_WE# [18]
DDR_A_D27 AW59 AU50 DDR_A_RAS# DDR_B_D29 AP61 AW44 DDR_B_RAS#
DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_RAS# [17] DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_RAS# [18]
DDR_A_D28 BB61 AU52 DDR_A_BS0 DDR_A_BS0 [17] DDR_B_D30 AT60 BB44 DDR_B_BS0 DDR_B_BS0 [18]
DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 DDR_B_D31 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_MA2
DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_MA2 [17] [18] DDR_B_D[32..47] DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR_B_MA2 [18]
DDR_A_D30 BA59 AT48 DDR_A_BS1 DDR_A_BS1 [17] DDR_B_D32 AU40 BA44 DDR_B_BS1 DDR_B_BS1 [18]
DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 DDR_B_D33 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_MA10
[17] DDR_A_D[32..47] DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA10 [17] DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR_B_MA10 [18]
DDR_A_D32 AY39 BB50 DDR_A_MA1 DDR_B_D34 AT37 AY46 DDR_B_MA1
DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR_A_MA1 [17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR_B_MA1 [18]
DDR_A_D33 AW39 AY50 DDR_A_MA0 DDR_A_MA0 [17] DDR_B_D35 AU37 BA46 DDR_B_MA0 DDR_B_MA0 [18]
DDR_A_D34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_B_D36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] BA50 DDR_A_MA3 DDR_B_D37 AP40 DDR1_DQ[36]/DDR1_DQ[20] BB46 DDR_B_MA3
DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA3 [17] DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3] DDR_B_MA3 [18]
DDR_A_D36 BB39 BB52 DDR_A_MA4 DDR_B_D38 AP37 BA47 DDR_B_MA4
DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_A_MA4 [17] DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4] DDR_B_MA4 [18]
DDR_A_D37 BA39 AM70 DDR_A_DQS#0 DDR_B_D39 AR37
DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQSN[0] DDR_A_DQS#0 [17] DDR1_DQ[39]/DDR1_DQ[23]
DDR_A_D38 BA37 AM69 DDR_A_DQS0 DDR_A_DQS0 [17] DDR_B_D40 AT33
DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSP[0] DDR1_DQ[40]/DDR1_DQ[24] Interleave / Non-Interleaved
DDR_A_D39 BB37 AT69 DDR_A_DQS#1 DDR_A_DQS#1 [17] DDR_B_D41 AU33 AH66 DDR_B_DQS#0 DDR_B_DQS#0 [18]
DDR_A_D40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_B_D42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_B_DQS0
DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSP[1] DDR_A_DQS1 [17] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_B_DQS0 [18]
DDR_A_D41 AW35 DDR_B_D43 AT30 AG69 DDR_B_DQS#1
DDR0_DQ[41]/DDR1_DQ[9] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_B_DQS#1 [18]
DDR_A_D42 AY33 DDR_B_D44 AR33 AG70 DDR_B_DQS1
DDR0_DQ[42]/DDR1_DQ[10] Interleave / Non-Interleaved DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3] DDR_B_DQS1 [18]
DDR_A_D43 AW33 BA64 DDR_A_DQS#2 DDR_A_DQS#2 [17] DDR_B_D45 AP33 AR66 DDR_B_DQS#2 DDR_B_DQS#2 [18]
DDR_A_D44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2 DDR_B_D46 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_B_DQS2
DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS2 [17] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[2]/DDR0_DQSP[6] DDR_B_DQS2 [18]
DDR_A_D45 BA35 AY60 DDR_A_DQS#3 DDR_A_DQS#3 [17] DDR_B_D47 AP30 AR61 DDR_B_DQS#3 DDR_B_DQS#3 [18]
DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_B_DQS3
DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS3 [17] [18] DDR_B_D[48..63] DDR1_DQSP[3]/DDR0_DQSP[7] DDR_B_DQS3 [18]
DDR_A_D47 BB33 BA38 DDR_A_DQS#4 DDR_B_D48 AU27 AT38 DDR_B_DQS#4
[17] DDR_A_D[48..63] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0] DDR_A_DQS#4 [17] DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2] DDR_B_DQS#4 [18]
DDR_A_D48 AY31 AY38 DDR_A_DQS4 DDR_A_DQS4 [17] DDR_B_D49 AT27 AR38 DDR_B_DQS4 DDR_B_DQS4 [18]
DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5 DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#5
DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_A_DQS#5 [17] DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS#5 [18]
DDR_A_D50 AY29 BA34 DDR_A_DQS5 DDR_A_DQS5 [17] DDR_B_D51 AU25 AR32 DDR_B_DQS5 DDR_B_DQS5 [18]
DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6 DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_A_DQS#6 [17] DDR1_DQ[52]
DDR_A_D52 BB31 AY30 DDR_A_DQS6 DDR_B_D53 AN27 AR25 DDR_B_DQS#6
DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4] DDR_A_DQS6 [17] DDR1_DQ[53] DDR1_DQSN[6] DDR_B_DQS#6 [18]
DDR_A_D53 BA31 AY26 DDR_A_DQS#7 DDR_A_DQS#7 [17] DDR_B_D54 AN25 AR27 DDR_B_DQS6 DDR_B_DQS6 [18]
DDR_A_D54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_A_DQS7 DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[6] AR22 DDR_B_DQS#7
DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_A_DQS7 [17] DDR1_DQ[55] DDR1_DQSN[7] DDR_B_DQS#7 [18]
DDR_A_D55 BB29 DDR_B_D56 AT22 AR21 DDR_B_DQS7 DDR_B_DQS7 [18]
DDR_A_D56 AY27 DDR0_DQ[55]/DDR1_DQ[39] AW50 DDR_B_D57 AU22 DDR1_DQ[56] DDR1_DQSP[7] AN43
DDR_A_D57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# AT52 DDR_B_D58 AU21 DDR1_DQ[57] DDR1_ALERT# AP43
DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR TP@ T122 DDR1_DQ[58] DDR1_PAR TP@ T123
DDR_A_D58 AY25 DDR_B_D59 AT21 AT13 DDR_DRAMRST# DDR_DRAMRST# [17,18]
B DDR_A_D59 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR CH - A AY67 +0.675V_VREFCA DDR_B_D60 AN22 DDR1_DQ[59] DDR CH - B DRAM_RESET# AR18 B
DDR0_DQ[59]/DDR1_DQ[43] DDR_VREF_CA +0.675V_VREFCA DDR1_DQ[60] DDR_RCOMP[0]
DDR_A_D60 BB27 AY68 +0.675V_A_VREFDQ DDR_B_D61 AP22 AT18
DDR_A_D61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ BA67 +0.675V_B_VREFDQ
+0.675V_A_VREFDQ Trace width/Spacing >= 20mils DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[1] AU18 SM_RCOMP0 RC16 1 2 121_0402_1%
DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ +0.675V_B_VREFDQ DDR1_DQ[62] DDR_RCOMP[2]
DDR_A_D62 BA25 DDR_B_D63 AN21 3 OF 20 SM_RCOMP1 RC17 1 2 80.6_0402_1%
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] 2 OF 20 AW67 DDR_PG_CTRL DDR1_DQ[63] SM_RCOMP2 RC18 1 2 100_0402_1%
DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL SKL-U_BGA1356
SKL-U_BGA1356 @
@
+1.35V
< For ODT & VTT Power Control >
1
+3VALW +1.35V RC20
470_0402_5%
1
CC1 1 2 0.1U_0201_10V6K
RC19
2
100K_0402_5% UC2
5 1 DDR_DRAMRST#
VCC NC
2
2 DDR_PG_CTRL
A
1
4
[45] DDR_VTT_PG_CTRL Y 3 @ESD@ CC96
GND
100P_0402_50V8J
2
74AUP1G07GW_TSSOP5
Close to CPU
A A

SKL-U(2/12)DDR3L
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C851P
5 4 3 2 1
5 4 3 2 1
SML0ALERT# (Internal Pull Down):
eSPI or LPC
0 = LPC is selected for EC ==> Default
1 = eSPI is selected for EC

D UC1E SKL-U D
+3V_PCH Rev_1.0
SPI - FLASH
SMBUS, SMLINK
SOC_SPI_CLK AV2 R7 SOC_SMBCLK SMB
SPI0_CLK GPP_C0/SMBCLK SOC_SMBCLK [17,18]
SOC_SPI_SO AW3 R8 SOC_SMBDATA
SPI0_MISO GPP_C1/SMBDATA SOC_SMBDATA [17,18] (Link to DDR)
SOC_SPI_SI AV3 R10 SOC_SMBALERT# TP@ T124
RC21 1 2 1K_0402_5% SOC_SPI_IO2 SOC_SPI_IO2 AW2 SPI0_MOSI GPP_C2/SMBALERT#
SOC_SPI_IO3 AU4 SPI0_IO2 R9 SOC_SML0CLK
SOC_SPI_CS#0 AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SOC_SML0DATA
RC22 1 @ 2 1K_0402_5% SOC_SPI_IO3 AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SOC_SML0ALERT# TP@ T125
AU1 SPI0_CS1# GPP_C5/SML0ALERT#
SPI0_CS2# W3 EC_SMB_CK2
RC24 1 ES@ 2 1K_0402_5% GPP_C6/SML1CLK V3 EC_SMB_DA2
EC_SMB_CK2 [20,28,31,34] SML1
SPI - TOUCH GPP_C7/SML1DATA EC_SMB_DA2 [20,28,31,34]
AM7 SOC_SML1ALERT# TP@ T126 (Link to EC,DGPU)
M2 GPP_B23/SML1ALERT#/PCHHOT#
M3 GPP_D1/SPI1_CLK
From WW36 MOW for SKL-U ES sample J4 GPP_D2/SPI1_MISO
V1 GPP_D3/SPI1_MOSI
V2 GPP_D21/SPI1_IO2 AY13 LPC_AD0
GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 LPC_AD0 [31,34]
+1.8VS_3VS_PGPPA M1 LPC BA13 LPC_AD1
GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 LPC_AD1 [31,34]
BB13 LPC_AD2
GPP_A3/LAD2/ESPI_IO2 LPC_AD2 [31,34]
AY12 LPC_AD3
C LINK GPP_A4/LAD3/ESPI_IO3 LPC_AD3 [31,34]
RC25 1 2 8.2K_0402_5% SERIRQ BA12 LPC_FRAME#
GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# [31,34]
G3 BA11 NFC_DW L_REQ [30]
G2 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET#
G1 CL_DATA
CL_RST# AW9 LPC_CLK0 RC26 1 EMI@ 2 22_0402_5%
GPP_A9/CLKOUT_LPC0/ESPI_CLK CK_LPC_KBC [34]
AY9 LPC_CLK1 RC27 1 2 22_0402_5%
GPP_A10/CLKOUT_LPC1 CK_LPC_TPM [31]
[34] KB_RST# AW13 AW11 PM_CLKRUN# TPM@
C GPP_A0/RCIN# GPP_A8/CLKRUN# C
[31,34] SERIRQ SERIRQ AY11

GPP_A6/SERIRQ 5 OF 20
SKL-U_BGA1356
@
+3VS +3VS +3V_PCH
1
RC108 RC78
0_0402_5% @ 0_0402_5%
2
RPC1, RPC3 and RC30 are close to UC3 SOC_SML1ALERT# RC54 2 1 150K_0402_5%
< SPI ROM - 8M >
RPC1 +3V_PCH SOC_SML0CLK RC28 1 2 499_0402_1%
SOC_SPI_SO 1 8 SOC_SPI_SO_0_R @
SOC_SPI_IO2 2 7 SOC_SPI_IO2_0_R UC3 CC2 1 2 0.1U_0201_10V6K SOC_SML0DATA RC29 1 2 499_0402_1%
SOC_SPI_SI 3 6 SOC_SPI_SI_0_R SOC_SPI_CS#0 1 8
SOC_SPI_IO3 4 5 SOC_SPI_IO3_0_R SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R
SOC_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_0_R RPC2
From SOC 33_0804_8P4R_5% 4 /WP(IO2) CLK 5 SOC_SPI_SI_0_R SOC_SMBCLK 1 8
EMI@ GND DI(IO0) SOC_SMBDATA 2 7
1
SOC_SPI_CLK 1 2 SOC_SPI_CLK_0_R W 25Q64FVSSIQ_SO8 EC_SMB_CK2 3 6
B RC30 EMI@ 33_0402_5% CC3 EC_SMB_DA2 4 5 B
10P_0402_50V8J
2 @EMI@ 1K_0804_8P4R_5%
RPC3
EC_SPI_CLK 1 8 SOC_SPI_CLK_0_R +1.8VS_3VS_PGPPA
[34] EC_SPI_CLK
EC_SPI_MOSI 2 7 SOC_SPI_SI_0_R
[34] EC_SPI_MOSI
From EC EC_SPI_CS0# 3 6 SOC_SPI_CS#0
[34] EC_SPI_CS0#
EC_SPI_MISO 4 5 SOC_SPI_SO_0_R PM_CLKRUN# 1 @ 2
[34] EC_SPI_MISO
RC31 8.2K_0402_5%
33_0804_8P4R_5%
EMI@
A A

SKL-U(3/12)SPI,SMB,LPC,ESPI
Date: W ednesday, March 04, 2015 Sheet 7 of 53
5 4 3 2 1
5 4 3 2 1
D D
UC1G SKL-U
Rev_1.0
< HD AUDIO >
AUDIO
RPC4
[38] HDA_BITCLK_AUDIO 1 8 HDA_BIT_CLK HDA_SYNC BA22
2 7 HDA_SYNC HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
[38] HDA_SYNC_AUDIO HDA_BLK/I2S0_SCLK
[38] HDA_SDOUT_AUDIO 3 6 HDA_SDOUT HDA_SDOUT BB22 SDIO / SDXC
4 5 BA21 HDA_SDO/I2S0_TXD
[38] HDA_SDIN0 HDA_SDI0/I2S0_RXD
AY21 AB11
33_0804_8P4R_5% AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
EMI@ J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
< To Enable ME Override > AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
[34] ME_EN GPP_A16/SD_1P8_SEL
H5 AB7 RC109 2 @ 1 200_0402_1%
GPP_D19/DMIC_CLK0 SD_RCOMP
2
+1.8V_HDA D7
G
GPP_D20/DMIC_DATA0
RC32 1 2 1K_0402_5% 1 3 HDA_SDOUT D8 AF13
C C8 GPP_D17/DMIC_CLK1 GPP_F23 C
S
GPP_D18/DMIC_DATA1
QC1 [38] HDA_SPKR HDA_SPKR AW5
BSS138W -7-F_SOT323-3 GPP_B14/SPKR
7 OF 20
SKL-U_BGA1356
@
+3VS
1 @ 2 HDA_SPKR
RC33 2.2K_0402_5%
UC1I SKL-U
Rev_1.0
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
SPKR (Internal Pull Down): D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
TOP Swap Override B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
B C31 E13 RC117 2 @ 1 100_0402_1% B
0 = Disable TOP Swap mode. ==> Default D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
1 = Enable TOP Swap Mode. A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1 RC116 2 @ 1 200_0402_1%
EMMC_RCOMP
SKL-U_BGA1356
@
A A

SKL-U(4/12)HDA,EMMC,SDIO,CSI2
5 4 3 2 1
5 4 3 2 1
@
+3VS SOC_XTAL24_IN
RPC5
8 1 CLKREQ_PCIE#4
7 2 SOC_XTAL24_OUT
6 3 CLKREQ_PCIE#5 1 2
5 4 UC1J SKL-U RC34 1M_0402_5%
Rev_1.0
10K_0804_8P4R_5% CLOCK SIGNALS
YC1
D42 24MHZ_12PF_7V24000020
RPC6 [19] CLK_PCIE_GPU# CLKOUT_PCIE_N0
DGPU C42
8 1 [19] CLK_PCIE_GPU AR10 CLKOUT_PCIE_P0 3 1
EC_SCI# EC_SCI# [34,5] [20] GPUCLK_REQ# GPUCLK_REQ#
GPP_B5/SRCCLKREQ0# 3 1
22P_0402_50V8J
22P_0402_50V8J
7 2 WLANCLK_REQ#
6 3 CRCLK_REQ# B42 GND GND
[37] CLK_PCIE_LAN# CLKOUT_PCIE_N1
CC4
CC5
D
5 4 LANCLK_REQ# LAN A42 F43
[37] CLK_PCIE_LAN CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N 4 2 D
[37] LANCLK_REQ# LANCLK_REQ# AT7 E43
10K_0804_8P4R_5% GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
D41 BA17 SUSCLK
[30] CLK_PCIE_WLAN# CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK [30]
NGFF WL+BT(KEY E) C41
[30] CLK_PCIE_WLAN CLKOUT_PCIE_P2
RC61 1 UMA@ 2 10K_0402_5% [30] WLANCLK_REQ# WLANCLK_REQ# AT8 E37 SOC_XTAL24_IN
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 SOC_XTAL24_OUT
1 PX@ 2 GPUCLK_REQ# D40 XTAL24_OUT
[39] CLK_PCIE_CR# CLKOUT_PCIE_N3
RC55 10K_0402_5% Card Reader C40 E42 XCLK_BIASREF
[39] CLK_PCIE_CR CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK5_F24NS
CRCLK_REQ# AT10
(For B14/E14/B15) [39] CRCLK_REQ# GPP_B8/SRCCLKREQ3# AM18 SOC_RTCX1
B40 RTCX1 AM20 SOC_RTCX2 XCLK_BIASREF 1 2
A40 CLKOUT_PCIE_N4 RTCX2 RC35 2.7K_0402_1%
CLKREQ_PCIE#4 AU8 CLKOUT_PCIE_P4 AN18 SOC_SRTCRST# 1 @ 2
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 SOC_RTCRST# RC110 60.4_0402_1%
E40 RTCRST#
E38 CLKOUT_PCIE_N5
CLKREQ_PCIE#5 AU7 CLKOUT_PCIE_P5
+3VL_RTC GPP_B10/SRCCLKREQ5#
Follow 546765_2014WW48_Skylake_MOW_Rev_1_0
10 OF 20
RC36 1 2 20K_0402_5% SOC_SRTCRST# Stuff 2.7k ohm(RC35) PU for Skylake-U
SKL-U_BGA1356
CC6 1 2 1U_0402_6.3V6K @ Stuff 60.4 ohm(RC110) PD for Cannonlake-U
CLRP1 1 2 SHORT PADS CLR ME
RC37 1 2 20K_0402_5% SOC_RTCRST#
2
CC7 1 2 1U_0402_6.3V6K SOC_RTCX2
RC38 < PCH PLTRST Buffer >
CLRP2 1 2 SHORT PADS CLR CMOS 1 @ 0_0402_5%
RC42 1 RS@ 2 0_0402_5%
D SOC_RTCX1
1
RC39 1 2 1M_0402_5% SM_INTRUDER# 2 EC_CLEAR_CMOS [34]
C +3VS 1 2 C
QC2 G
L2N7002LT1G SOT23-3 S RC41 10M_0402_5%
1
3
RC40
5
10K_0402_5% UC4
SOC_PLTRST# 1 YC2
P
B 4 1 2
PCIRST# [19,30,31,34,37,39]
2
2 Y
A
G
32.768KHZ_12.5PF_9H03200042
1
TC7SH08FUF_SSOP5 1
RC44
100K_0402_5%
18P_0402_50V8J
18P_0402_50V8J
@ 1 1
+3VALW
CC8
10P_0402_50V8J
@ESD@
CC9
CC10
2
RPC7
2
2 2
8 1 PCH_PWROK
7 2 EC_RSMRST#
6 3 LAN_WAKE#
5 4 SYS_RESET#
10K_0804_8P4R_5% DS3
DPWROK_EC RC114 1 DS3@ 2 0_0402_5% PCH_DPWROK
ESD [34] DPWROK_EC
UC1K SKL-U
EC_RSMRST# RC115 1 NODS3@2 0_0402_5% Rev_1.0
@ESD@ 1 2 SYS_RESET# SYSTEM POWER MANAGEMENT
CC97 100P_0402_50V8J AT11 PM_SLP_S0#
GPP_B12/SLP_S0# TP@T130
@ESD@ 1 2 EC_RSMRST# AP15 PM_SLP_S3#
GPD4/SLP_S3# PM_SLP_S3# [34]
CC94 100P_0402_50V8J SOC_PLTRST# AN10 BA16 PM_SLP_S4#
GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S4# [34,40]
@ESD@ 1 2 SYS_PWROK SYS_RESET# B5 AY16 PM_SLP_S5# TP@T135
CC95 100P_0402_50V8J EC_RSMRST# AY17 SYS_RESET# GPD10/SLP_S5#
[34] EC_RSMRST# RSMRST# AN15 SLP_SUS#
H_CPUPWRGD A68 SLP_SUS# AW15
SLP_SUS# [34,46] DS3
Only For Power Sequence Debug T132 TP@ PROCPWRGD SLP_LAN#
B EC_VCCST_PG B65 BB17 SLP_WLAN# TP@T133
B
VCCST_PWRGD GPD9/SLP_WLAN# AN16 PM_SLP_A#
GPD6/SLP_A# TP@T134
SYS_PWROK B6
[34] SYS_PWROK SYS_PWROK
PCH_PWROK BA20 BA15 PBTN_OUT#
[34] PCH_PWROK PCH_PWROK GPD3/PWRBTN# PBTN_OUT# [34]
PCH_DPWROK BB20 AY15 AC_PRESENT RC103 1 @ 2 0_0402_5%
+3VALW DSW_PWROK GPD1/ACPRESENT VCIN1_AC_IN [20,32,34,43]
AU13 PM_BATLOW#
RC111 1 DS3@ 2 0_0402_5% SUSWARN#_R AR13 GPD0/BATLOW#
1 2 WAKE#
DS3 [34] SUSWARN#
RC113 1 DS3@ 2 0_0402_5% SUSACK#_R AP11 GPP_A13/SUSWARN#/SUSPWRDNACK +3VALW
[34] SUSACK# GPP_A15/SUSACK#
RC47 1K_0402_5% AU11
WAKE# BB15 GPP_A11/PME# AP16 SM_INTRUDER#
LAN_WAKE# AM15 WAKE# INTRUDER# PM_BATLOW# 1 2
AW17 GPD2/LAN_WAKE# AM10 GS_INT2_R RC46 8.2K_0402_5%
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 SOC_VRALERT# AC_PRESENT 1 @ 2
1 DS3@ 2 PCH_DPWROK GPD7/RSVD 11 OF 20 GPP_B2/VRALERT# RC48 10K_0402_5%
R132 100K_0402_5%
SKL-U_BGA1356
@
+3V_PCH
SOC_VRALERT# 1 @ 2
RC50 10K_0402_5%
+3VS
+1.0V_VCCST
From EC (Open-Drain)
1 2
1
RC82 10K_0402_5%
RC52 GS_INT2_R 1 @ 2 GS_INT2 [35]
1K_0402_5% RC104 0_0402_5%
2
A RC53 1 2 60.4_0402_1% EC_VCCST_PG A

[34,40] VCCST_PWRGD

SKL-U(5/12)CLK,PM,GPIO
Custom 0.1
5 4 3 2 1
5 4 3 2 1
GSPI0_MOSI (Internal Pull Down):
No Reboot
0 = Disable No Reboot mode. ==> Default
1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This function is useful
when running ITP/XDP.
D D
GSPI1_MOSI (Internal Pull Down):
Boot BIOS Strap Bit
0 = SPI Mode ==> Default
1 = LPC Mode
UC1F SKL-U
Rev_1.0
+3VS LPSS ISH
PCH_GPPB15 AN8 P2
1 @ 2 GSPI0_MOSI AP7 GPP_B15/GSPI0_CS# GPP_D9 P3
RC59 2.2K_0402_5% AP8 GPP_B16/GSPI0_CLK GPP_D10 P4
1 @ 2 GSPI1_MOSI GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D11 P1
RC60 2.2K_0402_5% GPP_B18/GSPI0_MOSI GPP_D12
AM5 M4
1 2 I2C_1_SDA AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
RC43 1K_0402_5% AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO N1
1 2 I2C_1_SCL GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
RC45 1K_0402_5% AB1 GPP_D8/ISH_I2C1_SCL
[30] NFC_EN GPP_C8/UART0_RXD
AB2 AD11
1 2 I2C_0_SDA PCH_GPPC10 W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12
RC49 1K_0402_5% WLBT_OFF# AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
[30] WLBT_OFF# GPP_C11/UART0_CTS#
1 2 I2C_0_SCL UART_2_CRXD_DTXD AD1 U1
[30] UART_2_CRXD_DTXD GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
RC51 1K_0402_5% UART_2_CTXD_DRXD AD2 U2
[30] UART_2_CTXD_DRXD GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL +3VS
AD3 U3
C 1 2 UART_2_CRXD_DTXD AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 C
RC66 49.9K_0402_1% GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
AC1 DGPU_PWR_EN WLBT_OFF# 2 1
GPP_C12/UART1_RXD/ISH_UART1_RXD DGPU_PWR_EN [21,34,48]
1 2 UART_2_CTXD_DRXD I2C_0_SDA U7 AC2 DGPU_HOLD_RST# 10K_0402_5% RC130
[30] I2C_0_SDA GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD DGPU_HOLD_RST# [19]
RC67 49.9K_0402_1% NFC I2C_0_SCL U6 AC3 DGPU_PWROK DGPU_PWROK [48] I2C_CTL_EN 2 1
[30] I2C_0_SCL GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 DGPU_PRSNT# 10K_0402_5% RC80
I2C_1_SDA U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
[26] I2C_1_SDA GPP_C18/I2C1_SDA
I2C_1_SCL U9 AY8 ODD_EN RPC8
Touch Screen [26] I2C_1_SCL GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 I2C_CTL_EN
ODD_EN [29]
DGPU_PWR_EN 1 8
GPP_A19/ISH_GP1 I2C_CTL_EN [36]
check with ketpart team AH9 BB7 PCH_GPPA20 DGPU_HOLD_RST# 2 7
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7 DGPU_PWROK 3 6
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7 PCH_GPPA22 ODD_EN 4 5
AH11 GPP_A22/ISH_GP4 AW7 PCH_GPPA23
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13 10K_0804_8P4R_5%
GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6
AF11 DGPU_PRSNT# PD for DIS SKU
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL 6 OF 20
SKL-U_BGA1356
@
BIOS Strap Pin

Function GPPA22 Function GPPB15
NoDocking SKU 1 EXO PRO 1
B
Docking SKU 0 MESO XT 0 B
+3VS +3VS
NoDocking@
RC118 1 2 10K_0402_5% PCH_GPPA22 RC124 1 EXO@ 2 10K_0402_5% PCH_GPPB15
RC119 1 2 10K_0402_5% RC125 1 2 10K_0402_5%
Docking@ MESO@
Function GPPA23 Function GPPA12

Zero ODD 1 UMA 1
No Zero ODD 0 DIS 0
+3VS +3VS
RC120 1 @ 2 10K_0402_5% PCH_GPPA23 RC128 1 UMA@ 2 10K_0402_5% DGPU_PRSNT#

RC121 1 2 10K_0402_5% RC129 1 2 10K_0402_5%
PX@
Function GPPC10 Function GPPA20

TPM 1 No G-Sensor 1
NO TPM 0 G-Sensor 0
+3VS +3VS
A A
RC106 1 TPM@ 2 10K_0402_5% PCH_GPPC10 RC102 1 NOGS@ 2 10K_0402_5% PCH_GPPA20
RC107 1 2 10K_0402_5% RC105 1 2 10K_0402_5%
NOTPM@ GS@

SKL-U(6/12)GPIO,I2C,GSPI
Custom 0.1
5 4 3 2 1
5 4 3 2 1
CC11 CC14 CC15 CC16

PX_G3@ PX_G3@ PX_G3@ PX_G3@ S CER CAP 0.22U 10V K X5R 0402
CC17 CC18 CC101 CC102

PX_G3@ PX_G3@ PX_G3@ PX_G3@
UC1H SKL-U
Rev_1.0
PCIE / USB3 / SATA SSIC / USB3

D H8 USB3_RX_N1 [33] D
USB3_1_RXN G8
USB3_1_RXP USB3_RX_P1 [33]
[19] PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N1 H13 C13 USB2/3 MB(Left)
PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3_TX_N1 [33]
[19] PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P1 G13 D13
PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_TX_P1 [33]
1
CC11 PX_G2@ 2 0.1U_0402_25V6 PCIE_CTX_GRX_N1 B17
[19] PCIE_CTX_C_GRX_N1 PCIE1_TXN/USB3_5_TXN
[19] PCIE_CTX_C_GRX_P1 1
CC14 PX_G2@ 2 0.1U_0402_25V6 PCIE_CTX_GRX_P1 A17 J6 USB3_RX_N2 [33]
PCIE1_TXP/USB3_5_TXP USB3_2_RXN / SSIC_RXN H6
USB3_2_RXP / SSIC_RXP USB3_RX_P2 [33]
PCIE_CRX_GTX_N2 G11 B13 USB2/3 MB(Left)
[19] PCIE_CRX_GTX_N2 PCIE2_RXN/USB3_6_RXN USB3_2_TXN / SSIC_TXN USB3_TX_N2 [33]
PCIE_CRX_GTX_P2 F11 A13
[19] PCIE_CRX_GTX_P2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP / SSIC_TXP USB3_TX_P2 [33]
1
CC15 PX_G2@ 2 0.1U_0402_25V6 PCIE_CTX_GRX_N2 D16
[19] PCIE_CTX_C_GRX_N2 1
CC16 PX_G2@ 2 0.1U_0402_25V6 PCIE_CTX_GRX_P2 C16 PCIE2_TXN/USB3_6_TXN J10
[19] PCIE_CTX_C_GRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN USB3_RX_N3 [35]
H10 USB3_RX_P3 [35]
H16 USB3_3_RXP B15
dGPU [19] PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N3
PCIE3_RXN USB3_3_TXN USB3_TX_N3 [35] Docking (For B15)
PCIE_CRX_GTX_P3 G16 A15
[19] PCIE_CRX_GTX_P3 PCIE3_RXP USB3_3_TXP USB3_TX_P3 [35]
1
CC17 PX_G2@ 2 0.1U_0402_25V6 PCIE_CTX_GRX_N3 D17
[19] PCIE_CTX_C_GRX_N3 PCIE3_TXN
1
CC18 PX_G2@ 2 0.1U_0402_25V6 PCIE_CTX_GRX_P3 C17 E10
[19] PCIE_CTX_C_GRX_P3 PCIE3_TXP USB3_4_RXN F10
PCIE_CRX_GTX_N4 G15 USB3_4_RXP C15
[19] PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 F15 PCIE4_RXN USB3_4_TXN D15
[19] PCIE_CRX_GTX_P4 1
CC101 PX_G2@ 2 0.1U_0402_25V6 PCIE_CTX_GRX_N4 B19 PCIE4_RXP USB3_4_TXP
[19] PCIE_CTX_C_GRX_N4 PCIE4_TXN
1
CC102 PX_G2@ 2 0.1U_0402_25V6 PCIE_CTX_GRX_P4 A19 AB9 USB20_N1
[19] PCIE_CTX_C_GRX_P4 PCIE4_TXP USB2N_1 USB20_N1 [33]
AB10 USB20_P1 USB2/3 MB(Left)
USB2P_1 USB20_P1 [33]
PCIE_CRX_DTX_N5 F16
[37] PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 E16 PCIE5_RXN AD6 USB20_N2
[37] PCIE_CRX_DTX_P5 PCIE5_RXP USB2N_2 USB20_N2 [33]
LAN CC19 1 2 0.1U_0402_25V6 PCIE_CTX_DRX_N5 C19 AD7 USB20_P2 USB2/3 MB(Left)
[37] PCIE_CTX_C_DRX_N5 PCIE5_TXN USB2P_2 USB20_P2 [33]
CC20 1 2 0.1U_0402_25V6 PCIE_CTX_DRX_P5 D19
[37] PCIE_CTX_C_DRX_P5 PCIE5_TXP AH3 USB20_N3
USB2N_3 USB20_N3 [33]
[30] PCIE_CRX_DTX_N6 PCIE_CRX_DTX_N6 G18 AJ3 USB20_P3 Right USB2__I/O Port (For E14)
PCIE6_RXN USB2P_3 USB20_P3 [33]
[30] PCIE_CRX_DTX_P6 PCIE_CRX_DTX_P6 F18
D20 PCIE6_RXP AD9
C NGFF WLAN+BT [30] PCIE_CTX_DRX_N6
PCIE_CTX_DRX_N6
PCIE6_TXN USB2N_4
USB20_N4
USB20_N4 [33]
C
PCIE_CTX_DRX_P6 C20 AD10 USB20_P4 Right USB2__I/O Port
[30] PCIE_CTX_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 [33]
F20 AJ1 USB20_N5
[29] SATA_CRX_DTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_N5 [26]
E20 AJ2 USB20_P5 Camera
[29] SATA_CRX_DTX_P0 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 [26]
HDD B21 USB2
[29] SATA_CTX_DRX_N0 A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6
[29] SATA_CTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_N6 [33]
AF7 USB20_P6 Finger Print (For B14/E14/B15)
USB2P_6 USB20_P6 [33]
G21
[29] SATA_CRX_DTX_N1 F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
[29] SATA_CRX_DTX_P1 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 [30]
ODD D21 AH2 USB20_P7 NGFF WLAN+BT
[29] SATA_CTX_DRX_N1 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 [30]
C21
[29] SATA_CTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8 USB20_N8
USB2N_8 USB20_N8 [26]
PCIE_CRX_DTX_N9 E22 AF9 USB20_P8 Touch Screen
[39] PCIE_CRX_DTX_N9 PCIE9_RXN USB2P_8 USB20_P8 [26]
Card Reader PCIE_CRX_DTX_P9 E23
[39] PCIE_CRX_DTX_P9 CC99 1 2 0.1U_0402_25V6 PCIE_CTX_DRX_N9 B23 PCIE9_RXP AG1 USB20_N9
(For B14/E14/B15) [39] PCIE_CTX_C_DRX_N9 CC100 1 2 0.1U_0402_25V6 PCIE_CTX_DRX_P9 A23 PCIE9_TXN USB2N_9 AG2 USB20_P9
USB20_N9 [35]
[39] PCIE_CTX_C_DRX_P9 PCIE9_TXP USB2P_9 USB20_P9 [35] Docking (For B15)
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
D23 PCIE10_RXP USB2P_10
C23 PCIE10_TXN AB6 USB2_COMP RC70 1 2 113_0402_1%
PCIE10_TXP USB2_COMP AG3 USB2_ID RC62 1 2 1K_0402_5%
RC71 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC63 1 2 1K_0402_5%
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 USB_OC0#
GPP_E9/USB2_OC0# USB_OC0# [33]
T147 TP@ XDP_PRDY# D56 C9 USB_OC1# USB_OC1# [33]
XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9
T148 TP@ PROC_PREQ# GPP_E11/USB2_OC2#
BB11 B9 follow CRB
B GPP_A7/PIRQA# GPP_E12/USB2_OC3# NFC_INT [30] B
E28 J1
E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 follow CRB (ORB is N11)
PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 ODD_DA# [29]
D24 J3
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
E30 PCIE11_TXP/SATA1B_TXP H2
When PCIE8/SATA1A is used PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0
F30 H3 SATA_ODD_PRSNT follow CRB
as SATA Port 1 (ODD), then A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4
SATA_ODD_PRSNT [29]
PCIE11/SATA1B (M.2 SSD) B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
PCIE12_TXP/SATA2_TXP
cannot be used as SATA GPP_E8/SATALED#
H1 PCH_SATALED# PCH_SATALED# [32]
Port 1. 8 OF 20
SKL-U_BGA1356
+3V_PCH
@
USB_OC0# RC72 1 2 10K_0402_5%
USB_OC1# RC73 1 2 10K_0402_5%
+3VS
PCH_SATALED# 1 2
RC112 10K_0402_5%
SATA_ODD_PRSNT 2 1
A
RC77 10K_0402_5% A

SKL-U(7/12)PCIE,USB,SATA
5 4 3 2 1
5 4 3 2 1
+1.35V +1.0VS_VCCIO
UC1N SKL-U
Rev_1.0
+5VALW +1.0VALW CPU POWER 3 OF 4
AU23 AK28
+1.0V_VCCST AU28 VDDQ_AU23 VCCIO AK30
AU35 VDDQ_AU28 VCCIO AL30
VDDQ_AU35 VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
I(Max) : 0.16 A(+1.0V_VCCST) AU42 AL42
+1.0VALW TO +1.0V_VCCST 1 1 VDDQ_AU42 VCCIO
CC21
CC22
RON(Max) : 25 mohm BB23 AM28
BB32 VDDQ_BB23 VCCIO AM30
D V drop : 0.004 V D
VDDQ_BB32 VCCIO +VCCSA
0.1U_0201_10V6K
@ 1 BB41 AM42
2 2 +1.0VS_VCCIO VDDQ_BB41 VCCIO
CC23
BB47
BB51 VDDQ_BB47 AK23
VDDQ_BB51 VCCSA AK25
UC5 2 VCCSA G23
1 14 +1.0V_VCCST AM40 VCCSA G25
2 VIN1 VOUT1 13 VDDQC VCCSA G27
VIN1 VOUT1 A18 VCCSA G28
RC74 1 2 0_0402_5% 3 12 1 2 VCCST VCCSA J22
EN_1.0V_VCCSTU
ON1 CT1
Follow 543977_SKL_PDDG_Rev0_91 VCCSA
[34,40,45] SYSON CC24 A22 J23
CC24 10PF ->22us(Spec:<= 65us) VCCSTG_A22 VCCSA
4 11 10P_0402_50V8J J27
VBIAS GND AL23 VCCSA K23
RC75 1 2 0_0402_5% EN_1.8VS 5 10 1 2 VCCPLL_OC VCCSA K25
[34,40,45] SUSP# ON2 CT2 CC25 K20 VCCSA K27
VCCPLL_K20 VCCSA
0.1U_0402_25V6
0.1U_0402_25V6
6 9 1000P_0402_50V7K K21 K28
1 VIN2 VOUT2 VCCPLL_K21 VCCSA
1
+1.8VALW
CC88
CC89
7 8 K30
@ @ VIN2 VOUT2 +1.8VS VCCSA
15 AM23
2
2
GPAD VCCIO_SENSE AM22
EM5209VF_DFN14_2X3 VSSIO_SENSE
+1.8VALW TO +1.8VS
1U_0402_6.3V6K
0.1U_0201_10V6K
1 1 H21 VSSSA_SENSE
VSSSA_SENSE VSSSA_SENSE [49]
CC26
CC27
H20 VCCSA_SENSE
VCCSA_SENSE VCCSA_SENSE [49]
14 OF 20
@
2 2 Trace Length Match < 25 mils
I(Max) : 0.2 A(+1.8VS) SKL-U_BGA1356
RON(Max) : 25 mohm @
V drop : 0.005 V
C C
+1.0VALW TO +1.0VS_VCCIO
+1.0V_VCCST +1.0VS_VCCIO
+5VALW +1.0VALW I(Max) : 3.04 A(+1.0VS_VCCIO)
RON(Max) : 6.2 mohm PSC Side BSC Side
V drop : 0.019 V
0.1U_0201_10V6K
1U_0402_6.3V6K
1 1
CC30
CC32
UC6
+1.0VS_VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
@ 1 1 1 1
2 2 2 VIN1
VIN2
CC28
CC34
CC35
7 6 +1.0VS_VCCIO_STG RC79 1 RS@ 2 0_0805_5% @
VIN thermal VOUT 2 2 2
3 1
VBIAS
SUSP# RC81 1 2 0_0402_5% 4 5 CC33
ON GND @ 0.1U_0201_10V6K
B 2 B
0.1U_0402_25V6
1
CC90
TPS22961DNYR_W SON8 Close to A18 Close to K20 Close to A22

@
2
+1.0VS_VCCIO +1.35V
BSC Side PSC Side BSC Side PSC Side BSC Side
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC37
CC38
CC49
CC50
CC36
CC39
CC40
CC41
CC42
CC29
CC43
CC44
CC45
CC46
CC47
CC48
@ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Underneath CPU Close to CPU Close to AL23 Close to AM40 Close to CPU Underneath CPU
A A

SKL-U(8/12)Power
5 4 3 2 1
5 4 3 2 1
D +1.0VALW D
+1.0V_APLL +1.0VALW +1.0VALW +1.8VALW
+1.0V_PRIM_CORE UC1O SKL-U
Follow 543016_SKL_U_Y_PDG_1_0 Rev_1.0 +3V_PCH
CPU POWER 4 OF 4
LC1 1 2 CC51 1 2 1U_0402_6.3V6K AB19
VCCPRIM_1P0
22U_0603_6.3V6M
RC83 1 RS@ 2 0_0805_5% AB20 AK15 +3V_1.8V_PGPPA
2.2UH_LQM2MPN2R2NG0L_30% @ P18 VCCPRIM_1P0 VCCPGPPA AG15
1 VCCPRIM_1P0 VCCPGPPB
CC52
Y16
Imax : 2.57A VCCPGPPC
1U_0402_6.3V6K
1 AF18 Y15
+1.0V_PRIM_CORE VCCPRIM_CORE VCCPGPPD
@ AF19 T16
2 VCCPRIM_CORE VCCPGPPE
CC54
V20 AF16 VCCPGPPF support 1.8V only
@ V21 VCCPRIM_CORE VCCPGPPF AD15
2 VCCPRIM_CORE VCCPGPPG
CC55 1 2 1U_0402_6.3V6K DCPDSW AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19
CC56 1 2 1U_0402_6.3V6K K17 T1 +1.0VALW
L1 VCCMPHYAON_1P0 VCCPRIM_1P0_T1
Close to K17 VCCMPHYAON_1P0
+1.0V_AMPHYPLL +1.0V_MPHYGT AA1 CC57 1 2 1U_0402_6.3V6K
N15 VCCATS_1P8
+1.0V_MPHYGT VCCMPHYGT_1P0_N15
Follow 543016_SKL_U_Y_PDG_1_0 N16 AK17
RC84 1 RS@ 2 0_0805_5% N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
LC2 1 2 P15 VCCMPHYGT_1P0_N17 AK19
VCCMPHYGT_1P0_P15 VCCRTC_AK19 +3VL_RTC
22U_0603_6.3V6M
1U_0402_6.3V6K
P16 BB14
Imax : 3.5A VCCMPHYGT_1P0_P16 VCCRTC_BB14
22U_0603_6.3V6M
1U_0402_6.3V6K
2.2UH_LQM2MPN2R2NG0L_30% 1 1 1 1
CC58
CC59
CC60
CC61
+1.0V_AMPHYPLL
K15 BB10 DCPRTC CC62 1 2 0.1U_0201_10V6K
L15 VCCAMPHYPLL_1P0 DCPRTC
@ @ VCCAMPHYPLL_1P0 A14
2 2 2 2 VCCCLK1 +1.0V_CLK6_24TBT
V15
+1.0V_APLL VCCAPLL_1P0
@ K19
AB17 VCCCLK2
Y18 VCCPRIM_1P0_AB17 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_APLL
AD17 N20
+3VALW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4_F100OC
AD18
+1.0V_CLK5_F24NS AJ17 VCCDSW_3P3_AD18 L19
C VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5_F24NS C
Follow 543016_SKL_U_Y_PDG_1_0
+1.8V_HDA
AJ19 A10 +1.0V_CLK6_24TBT
RC85 1 2 0_0603_5% +1.8VALW +1.8V_HDA VCCHDA VCCCLK6
AJ16 AN11
+3V_PCH VCCSPI GPP_B0/CORE_VID0
22U_0603_6.3V6M
AN13
AF20 GPP_B1/CORE_VID1
1 VCCSRAM_1P0
CC63
RC86 1 RS@ 2 0_0402_5% AF21

VCCSRAM_1P0
1U_0402_6.3V6K
T19
@ T20 VCCSRAM_1P0
2 1 VCCSRAM_1P0
CC66
AJ21
@ VCCPRIM_3P3_AJ21
2 AK20
VCCPRIM_1P0_AK20
N18
+3V_PCH +1.0VALW VCCAPLLEBB_1P0 15 OF 20
+1.0V_CLK4_F100OC
Follow 543016_SKL_U_Y_PDG_1_0 +3V_1.8V_PGPPA SKL-U_BGA1356
@
RC87 1 2 0_0603_5% 2 2 2
RC88 1 @ 2 0_0402_5% @ @
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
22U_0603_6.3V6M
CC67
CC65
CC68
1 1 1 1
CC70
+3V_PCH
@ LPC 3.3V
2 RTC Battery
RC89 1 RS@ 2 0_0402_5%
Close to AJ21 Close to AF20 Close to N18
+3VL_RTC +RTCBATT
W=20mils
+1.0V_CLK6_24TBT RC90 1 RS@ 2 0_0402_5%
+1.8VS +1.8VS_3VS_PGPPA
B Follow 543016_SKL_U_Y_PDG_1_0 1 B
CC82
RC91 1 2 0_0603_5% RC92 1 @ 2 0_0402_5% Follow 543016_SKL_U_Y_PDG_1_0 1U_0402_6.3V6K
2
22U_0603_6.3V6M
+3VS +1.0VALW +3VALW +1.8VALW

1U_0402_6.3V6K
1 1 +3V_PCH
CC85
CC84
LPC 3.3V
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
@ @ Safty suggestion remove EE side ,Keep PWR side
2 2 RC93 1 RS@ 2 0_0402_5% 1 1 1 1 1 1
CC71
CC72
CC73
CC74
CC75
CC76
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
1 1 1 1 1
CC80
CC77
CC78
CC81
CC79
@ @ @ @ @ @ @ @ @
2 2 2 2 2 2
2 2 2 2 2
Close to AG15 Close to Y16 Close to T16 Close to AK17
A A

SKL-U(9/12)Power
Custom 0.1
5 4 3 2 1
5 4 3 2 1
+VCCCORE +VCCCORE +VCCGT +VCCGT

UC1M SKL-U
UC1L SKL-U Rev_1.0
Rev_1.0 CPU POWER 2 OF 4
CPU POWER 1 OF 4
N70
A30 G32 A48 VCCGT N71
A34 VCC_A30 VCC_G32 G33 A53 VCCGT VCCGT R63
D D
AK33 VCC_A44 VCC_G37 G38 A66 VCCGT VCCGT R66
AK35 VCC_AK33 VCC_G38 G40 AA63 VCCGT VCCGT R67
AK37 VCC_AK35 VCC_G40 G42 AA64 VCCGT VCCGT R68
AK38 VCC_AK37 VCC_G42 J30 AA66 VCCGT VCCGT R69
AK40 VCC_AK38 VCC_J30 J33 AA67 VCCGT VCCGT R70
AL33 VCC_AK40 VCC_J33 J37 AA69 VCCGT VCCGT R71
AL37 VCC_AL33 VCC_J37 J40 AA70 VCCGT VCCGT T62
AL40 VCC_AL37 VCC_J40 K33 AA71 VCCGT VCCGT U65
AM32 VCC_AL40 VCC_K33 K35 AC64 VCCGT VCCGT U68
AM33 VCC_AM32 VCC_K35 K37 AC65 VCCGT VCCGT U71
AM35 VCC_AM33 VCC_K37 K38 AC66 VCCGT VCCGT W63
G30 VCC_AM38 VCC_K42 K43 AC69 VCCGT VCCGT W66
VCC_G30 VCC_K43
Trace Length Match < 25 mils VCCGT VCCGT
AC70 W67
K32 E32 AC71 VCCGT VCCGT W68
RSVD VCC_SENSE VCCCORE_SENSE [49] VCCGT VCCGT
E33 J43 W69
VSS_SENSE VSSCORE_SENSE [49] VCCGT VCCGT
AK32 J45 W70
RSVD B63 SOC_SVID_ALERT# J46 VCCGT VCCGT W71
AB62 VIDALERT# A63 VR_SVID_CLK J48 VCCGT VCCGT Y62
VCCOPC_AB62 VIDSCK VR_SVID_CLK [49] VCCGT VCCGT
P62 D64 VR_SVID_DATA J50
V62 VCCOPC_P62 VIDSOUT J52 VCCGT
VCCOPC_V62 G20 J53 VCCGT AK42
VCCSTG_G20
ALERT signal must be routed between CLK and DATA signals VCCGT VCCGTX_AK42
H63 J55 AK43
VCC_OPC_1P8_H63 +1.0VS_VCCIO J56 VCCGT VCCGTX_AK43 AK45
G61 J58 VCCGT VCCGTX_AK45 AK46
VCC_OPC_1P8_G61 J60 VCCGT VCCGTX_AK46 AK48
AC63 K48 VCCGT VCCGTX_AK48 AK50
C For GT3 SKU VCCOPC_SENSE VCCGT VCCGTX_AK50
C
AE63 K50 AK52
VSSOPC_SENSE K52 VCCGT VCCGTX_AK52 AK53
AE62 K53 VCCGT VCCGTX_AK53 AK55
AG62 VCCEOPIO K55 VCCGT VCCGTX_AK55 AK56
VCCEOPIO K56 VCCGT VCCGTX_AK56 AK58
AL63 K58 VCCGT VCCGTX_AK58 AK60
AJ62 VCCEOPIO_SENSE K60 VCCGT VCCGTX_AK60 AK70
VSSEOPIO_SENSE 12 OF 20 L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
VCCGT VCCGTX_AL46
For GT3 SKU
SKL-U_BGA1356 L64 AL50
@ VCCGT VCCGTX_AL53
L66 AL56
L68 VCCGT VCCGTX_AL60 AM48
L69 VCCGT VCCGTX_AM48 AM50
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
SVID ALERT N66 VCCGT
VCCGT
VCCGTX_AU58
VCCGTX_AU63
AU63
+1.0V_VCCST N67 BB57
Place the PU VCCGT VCCGTX_BB57
N69 BB66
resistors close to CPU VCCGT VCCGTX_BB66
VCCGT_SENSE J70 AK62 VCCGTX_SENSE T161 TP@
[49] VCCGT_SENSE VCCGT_SENSE VCCGTX_SENSE
1
VSSGT_SENSE J69 AL61 VSSGTX_SENSE T162 TP@

[49] VSSGT_SENSE VSSGT_SENSE
RC94 13 OF 20VSSGTX_SENSE
56_0402_5%
B B
Trace Length Match < 25 mils SKL-U_BGA1356
@
2
SOC_SVID_ALERT# 1 2 (To VR)

VR_ALERT# [49]
RC95 220_0402_5%
+1.0V_VCCST
SVID DATA Place the PU

resistors close to CPU
1
RC96
100_0402_5%
2
VR_SVID_DATA
VR_SVID_DATA [49] (To VR)
A A

SKL-U(10/12)Power,SVID
5 4 3 2 1
5 4 3 2 1
D D
UC1P SKL-U UC1Q SKL-U
Rev_1.0 Rev_1.0 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3 Rev_1.0
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
C AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10 C
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356
AJ20 VSS VSS AR28 B22 VSS VSS E46
VSS VSS VSS VSS @
AJ4 AR35 B30 E50
AK11 VSS VSS AR42 B34 VSS VSS E53
B AK27 VSS VSS AR5 B58 VSS VSS F1 B
AK63 VSS VSS AR50 B62 VSS VSS F13
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL52 VSS VSS AT4 F68 VSS VSS F40
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
@ @
A A

SKL-U(11/12)GND
5 4 3 2 1
5 4 3 2 1
D D
UC1S SKL-U UC1T SKL-U

Rev_1.0 Rev_1.0
RESERVED SIGNALS-1 SPARE
T164 TP@ CFG0 E68 BB68 AW69 F6

CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 AW68 RSVD_AW69 RSVD_F6 E3
T163 TP@ CFG[1] RSVD_TP_BB69 RSVD_AW68 RSVD_E3
T165 TP@ CFG2 D65 AU56 C11
CFG3 D67 CFG[2] AK13 AW48 RSVD_AU56 RSVD_C11 B11
T175 TP@ CFG[3] RSVD_TP_AK13 RSVD_AW48 RSVD_B11
T166 TP@ CFG4 E70 AK12 C7 A11
CFG5 C68 CFG[4] RSVD_TP_AK12 RSVD_U12 U12 RSVD_C7 RSVD_A11 D12
T167 TP@ CFG[5] RSVD_U12 RSVD_D12
T168 TP@ CFG6 D68 BB2 RSVD_U11 U11 C12
CFG7 C67 CFG[6] RSVD_BB2 BA3 H11 RSVD_U11 RSVD_C12 F52
T169 TP@ CFG[7] RSVD_BA3 RSVD_H11 RSVD_F52
T170 TP@ CFG8 F71
CFG9 G69 CFG[8] 20 OF 20
T171 TP@ CFG[9]
T172 TP@ CFG10 F70 AU5
CFG11 G68 CFG[10] TP5 AT5 SKL-U_BGA1356
T173 TP@ CFG[11] TP6
T176 TP@ CFG12 H70 @
CFG13 G71 CFG[12]
T174 TP@ CFG[13]
T177 TP@ CFG14 H69 D5
CFG15 G70 CFG[14] RSVD_D5 D4
T178 TP@ CFG[15] RSVD_D4 B2
CFG16 E63 RSVD_B2 C2
T179 TP@ CFG[16] RSVD_C2
T180 TP@ CFG17 F63 +1.8VALW
CFG[17] B3
CFG18 E66 RSVD_B3 A3
T181 TP@ CFG[18] RSVD_A3
T182 TP@ CFG19 F66
C CFG[19] AW1 RSVD_U12 RC122 1 @ 2 0_0402_5% C
CFG_RCOMP E60 RSVD_AW1
CFG_RCOMP E1 RSVD_U11 RC123 1 @ 2 0_0402_5%
XDP_ITP_PMODE E8 RSVD_E1 E2
T183 TP@ ITP_PMODE RSVD_E2 2
@
AY2 BA4 CC87
AY1 RSVD_AY2 RSVD_BA4 BB4 1U_0402_6.3V6K
RSVD_AY1 RSVD_BB4 1
D1 A4
D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69 RS@
RSVD_AL27 AY3 RC97 1 2 0_0402_5%
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2
J71 AY71
J68 RSVD_J71 VSS_AY71 AR56 LPM_ZVM#
B RSVD_J68 ZVM# T186 TP@ For 2+3e Solution B
F65 AW71 LPM_ZVM#
G65 VSS_F65 RSVD_TP AW70 PM_MSM#
VSS_G65 RSVD_TP
F61 AP56 PM_MSM# T185 TP@
E61 RSVD_F61 MSM# C64 SKL_CNL# +1.0V_VCCST
RSVD_E61 PROC_SELECT#
19 OF 20 1 @ 2
RC99 100K_0402_5%
1 2 CFG_RCOMP SKL-U_BGA1356
RC100 49.9_0402_1% @
Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0
1 2 CFG4
RC101 1K_0402_5% Stuff 100k(RC99) for Cannonlake.
Un-stuff 100k(RC99) for Skylake
Display Port Presence Strap
1 : Disabled; No Physical Display Port

attached to Embedded Display Port
CFG4
0 : Enabled; An external Display Port device is
A connected to the Embedded Display Port A

SKL-U(12/12)CFG,RSVD
5 4 3 2 1
A B C D E
[6] DDR_A_DQS#[0..7]
[6] DDR_A_D[0..63]
+0.675V_DDRA_VREFDQ
10mils JDIMM1
Reverse Type
D/DQ Signals link to CPU 1 2
3 VREF_DQ VSS 4 DDR_A_D0
[6] DDR_A_DQS[0..7] VSS DQ4 2-3A to 1 DIMMs/channel
2.2U_0402_6.3V6M
0.1U_0201_10V6K
DDR_A_D1 5 6 DDR_A_D4
DDR_A_D5 7 DQ0 DQ5 8
1 DQ1 VSS
CD1
CD2
9 10 DDR_A_DQS#0
[6] DDR_A_MA[0..15] 11 VSS DQS0# 12 DDR_A_DQS0
DDR_A_BS0 @ 13 DM0 DQS0 14
[6] DDR_A_BS0
2
DDR_A_BS1 2 DDR_A_D6 15 VSS VSS 16 DDR_A_D3
[6] DDR_A_BS1 DDR_A_BS2 CMD Signals from CPU DDR_A_D2 17 DQ2 DQ6 18 DDR_A_D7
@
[6] DDR_A_BS2 DDR_A_WE# 19 DQ3 DQ7 20
[6] DDR_A_WE# 21 VSS VSS 22
DDR_A_CAS# DDR_A_D12 DDR_A_D9
1 [6] DDR_A_CAS# DDR_A_RAS# DDR_A_D11 23 DQ8 DQ12 24 DDR_A_D8 1
[6] DDR_A_RAS# 25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS VSS 28
DDR_A_CLK0 DDR_A_DQS1 29 DQS1# DM1 30 DDR_DRAMRST#
[6] DDR_A_CLK0 DDR_A_CLK#0 Clock Signals from CPU 31 DQS1 RESET# 32 DDR_DRAMRST# [18,6]
[6] DDR_A_CLK#0 33 VSS VSS 34
DDR_A_CLK1 DDR_A_D13 DDR_A_D10 1
[6] DDR_A_CLK1 DDR_A_CLK#1 DDR_A_D15 35 DQ10 DQ14 36 DDR_A_D14
[6] DDR_A_CLK#1 37 DQ11 DQ15 38 CD3
DDR_A_D16 39 VSS VSS 40 DDR_A_D20 @ESD@
DQ16 DQ20 100P_0402_50V8J
DDR_A_CKE0 DDR_A_D17 41 42 DDR_A_D21 2
[6] DDR_A_CKE0 DDR_A_CKE1 CTL Signals from CPU 43 DQ17 DQ21 44
[6] DDR_A_CKE1 DDR_A_CS#0 DDR_A_DQS#2 45 VSS VSS 46
[6] DDR_A_CS#0 DDR_A_CS#1 DDR_A_DQS2 47 DQS2# DM2 48
[6] DDR_A_CS#1 49 DQS2 VSS 50 DDR_A_D19
DDR_A_D18 51 VSS DQ22 52 DDR_A_D23
SOC_SMBDATA SMBUS Signals link to CPU DDR_A_D22 53 DQ18 DQ23 54
[18,7] SOC_SMBDATA SOC_SMBCLK 55 DQ19 VSS 56 DDR_A_D24
[18,7] SOC_SMBCLK DDR_A_D29
DDR_A_D28
57
59
VSS
DQ24
DQ25
DQ28
DQ29
VSS
58
60
DDR_A_D25 +1.35V
ESD
DDR_A_ODT0 61 62 DDR_A_DQS#3
[6] DDR_A_ODT0 From SOC ODT Signals to CH A 63 VSS DQS3# 64
DDR_A_ODT1 DDR_A_DQS3
[6] DDR_A_ODT1 65 DM3 DQS3 66
DDR_A_D30 67 VSS VSS 68 DDR_A_D26
DQ26 DQ30 1 1 1 1 1
DDR_A_D31 69 70 DDR_A_D27
DQ27 DQ31
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
71 72 CD4 CD5 CD6 CD7 CD8
+1.35V VSS VSS +1.35V @ESD@ @ESD@ @ESD@ @ESD@ @ESD@
2 2 2 2 2
Note:
Layout Note: DDR_A_CKE0 73 74 DDR_A_CKE1
Check voltage tolerance of 75 CKE0 CKE1 76
Place near JDIMM1 VREF_DQ at the DIMM socket 77 VDD VDD 78 DDR_A_MA15
DDR_A_BS2 79 NC A15 80 DDR_A_MA14
81 BA2 A14 82
2 DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11 2
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
+1.35V DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2
A3 A2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_MA1 97 98 DDR_A_MA0
99 A1 A0 100
1 1 1 1 VDD VDD
@ @ DDR_A_CLK0 101
CK0 CK1
102 DDR_A_CLK1
+EC_VCCA
CD9
CD10
CD11
CD12
DDR_A_CLK#0 103 104 DDR_A_CLK#1

105 CK0# CK1# 106
2 2 2 2 DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1
A10/AP BA1
16.5K_0402_1%
DDR_A_BS0 109 110 DDR_A_RAS#
BA0 RAS#
1
111 112
VDD VDD
RD1
DDR_A_WE# 113 114 DDR_A_CS#0
DDR_A_CAS# 115 WE# S0# 116 DDR_A_ODT0
117 CAS# ODT0 118
DDR_A_MA13 119 VDD VDD 120 DDR_A_ODT1
2
DDR_A_CS#1 121 A13 ODT1 122 +0.675V_DDR_VREFCA
+1.35V 123 S1# NC 124
125 VDD VDD 126
10mils [34] DDR_TEMP
127 TEST VREF_CA 128
VSS VSS
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2.2U_0402_6.3V6M
0.1U_0201_10V6K
DDR_A_D37 129 130 DDR_A_D33
DDR_A_D32 131 DQ32 DQ36 132 DDR_A_D36 RHD1
DQ33 DQ37 1
CD22
CD23
@ @ 1 133 134 100K_0402_1%_TSM0B104F4251RZ
VSS VSS
220U_6.3V_M
1 1 1 1 1 1 1 1 @ DDR_A_DQS#4 135 136

DQS4# DM4
CD13
CD14
CD15
CD16
CD17
CD18
CD19
CD20
CD21
+ DDR_A_DQS4 137 138 @
2
139 DQS4 VSS 140 DDR_A_D35 2
2 2 2 2 2 2 2 2 2 DDR_A_D38 143 DQ34 DQ39 144
145 DQ35 VSS 146 DDR_A_D41 ECAGND
3 DDR_A_D45 147 VSS DQ44 148 DDR_A_D40 3
DDR_A_D44 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_A_DQS#5
153 VSS DQS5# 154 DDR_A_DQS5
155 DM5 DQS5 156 +1.35V
DDR_A_D47 159 DQ42 DQ46 160 DDR_A_D43
DQ43 DQ47
1
1.8K_0402_1%
Layout Note: Layout Note: 161 162
VSS VSS
RD2
DDR_A_D48 163 164 DDR_A_D52
Place near JDIMM1.203,204 Place near JDIMM1.199 DDR_A_D53 165 DQ48 DQ52 166 DDR_A_D49
167 DQ49 DQ53 168 +0.675V_DDRA_VREFDQ +0.675V_A_VREFDQ
DDR_A_DQS#6 169 VSS VSS 170
2
DDR_A_DQS6 171 DQS6# DM6 172
173 DQS6 VSS 174 DDR_A_D51 RD3 1 RS@ 2 0_0402_5%
+0.675VS +3V_DA DDR_A_D55 177 DQ50 DQ55 178
179 DQ51 VSS 180 DDR_A_D56
VSS DQ60
1
1.8K_0402_1%
DDR_A_D58 181 182 DDR_A_D57
DQ56 DQ61
RD4
DDR_A_D59 183 184
DQ57 VSS
0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2U_0402_6.3V6M
0.1U_0201_10V6K
185 186 DDR_A_DQS#7

187 VSS DQS7# 188 DDR_A_DQS7
1 1 1 1 1 DM7 DQS7
1
CD25
CD26
CD27
CD28
CD29
CD30
189 190
2
@ @ @ DDR_A_D61 193 DQ58 DQ62 194 DDR_A_D63
2
2 2 2 2 2 +0.675VS +3V_DA 195 DQ59 DQ63 196 +0.675VS

DDR_A_SA0 197 VSS VSS 198
199 SA0 EVENT# 200 SOC_SMBDATA
DDR_A_SA1 201 VDDSPD SDA 202 SOC_SMBCLK
+0.675VS_VTT 203 SA1 SCL 204 +0.675VS_VTT
VTT VTT Place near to SO-DIMM connector
205 206
207 GND1 GND2 208
4 BOSS1 BOSS2 4
Address : 00 FOX_AS0A621-J4RB-7H
ME@
DDR_A_SA0 SP07000J520
DDR_A_SA1
Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
DDR3L_DIMMA
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
A B C D E
A B C D E
[6] DDR_B_DQS#[0..7]
+0.675V_DDRB_VREFDQ Standard Type
10mils JDIMM2
1 2
[6] DDR_B_D[0..63] D/DQ Signals link to CPU 3 VREF_DQ VSS1 4 DDR_B_D10
2-3A to 1 DIMMs/channel
VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0201_10V6K
DDR_B_D14 5 6 DDR_B_D11
[6] DDR_B_DQS[0..7] DDR_B_D15 7 DQ0 DQ5 8
1 DQ1 VSS3
CD31
CD32
9 10 DDR_B_DQS#1
11 VSS4 DQS#0 12 DDR_B_DQS1
[6] DDR_B_MA[0..15] 13 DM0 DQS0 14
@ @
2
DDR_B_BS0 2 DDR_B_D9 15 VSS5 VSS6 16 DDR_B_D13
[6] DDR_B_BS0 DDR_B_BS1 CMD Signals from CPU DDR_B_D8 17 DQ2 DQ6 18 DDR_B_D12
[6] DDR_B_BS1 DDR_B_BS2 19 DQ3 DQ7 20
[6] DDR_B_BS2 21 VSS7 VSS8 22
DDR_B_WE# DDR_B_D5 DDR_B_D4
1 [6] DDR_B_WE# DDR_B_CAS# DDR_B_D1 23 DQ8 DQ12 24 DDR_B_D0 1
[6] DDR_B_CAS# DDR_B_RAS# 25 DQ9 DQ13 26
[6] DDR_B_RAS# DDR_B_DQS#0 27 VSS9 VSS10 28
DDR_B_DQS0 29 DQS#1 DM1 30 DDR_DRAMRST#
DDR_B_CLK0 31 DQS1 RESET# 32 DDR_DRAMRST# [17,6]
[6] DDR_B_CLK0 Clock Signals from CPU 33 VSS11 VSS12 34
DDR_B_CLK#0 DDR_B_D3 DDR_B_D6 1
[6] DDR_B_CLK#0 DDR_B_CLK1 DDR_B_D2 35 DQ10 DQ14 36 DDR_B_D7
[6] DDR_B_CLK1 DDR_B_CLK#1 37 DQ11 DQ15 38 CD33
[6] DDR_B_CLK#1 DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D21 @ESD@
DQ16 DQ20 100P_0402_50V8J
DDR_B_D17 41 42 DDR_B_D20 2
DDR_B_CKE0 43 DQ17 DQ21 44
[6] DDR_B_CKE0 DDR_B_CKE1 CTL Signals from CPU DDR_B_DQS#2 45 VSS15 VSS16 46
[6] DDR_B_CKE1 DDR_B_CS#0 DDR_B_DQS2 47 DQS#2 DM2 48
[6] DDR_B_CS#0 49 DQS2 VSS17 50
DDR_B_CS#1 DDR_B_D19
[6] DDR_B_CS#1 DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D22 53 DQ18 DQ23 54
SOC_SMBDATA SMBUS Signals link to CPU 55 DQ19 VSS19 56 DDR_B_D29
[17,7] SOC_SMBDATA SOC_SMBCLK DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D28
[17,7] SOC_SMBCLK 59 DQ24 DQ29 60 +1.35V
DDR_B_D25
61 DQ25 VSS21 62 DDR_B_DQS#3
DDR_B_ODT0 63 VSS22 DQS#3 64 DDR_B_DQS3
[6] DDR_B_ODT0 DM3 DQS3
1
1.8K_0402_1%
DDR_B_ODT1 From SOC ODT Signals to CH B 65 66
[6] DDR_B_ODT1 VSS23 VSS24
RD6
DDR_B_D27 67 68 DDR_B_D30
DDR_B_D26 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72 +0.675V_DDRB_VREFDQ +0.675V_B_VREFDQ
VSS25 VSS26
Layout Note:
2
+1.35V +1.35V
Place near JDIMM2 RD7 1 RS@ 2 0_0402_5%
DDR_B_CKE0 73 74 DDR_B_CKE1
75 CKE0 CKE1 76
77 VDD1 VDD2 78 DDR_B_MA15
NC1 A15
1
1.8K_0402_1%
DDR_B_BS2 79 80 DDR_B_MA14
BA2 A14
RD8
2 81 82 2
+1.35V DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
2
VDD5 VDD6
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_B_MA8 89 90 DDR_B_MA6
@1 @1 DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
1 1 A5 A4
93 94
VDD7 VDD8
CD35
CD36
CD37
CD38
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
2 2 2 2 99 A1 A0 100
DDR_B_CLK0 101 VDD9 VDD10 102 DDR_B_CLK1
DDR_B_CLK#0 103 CK0 CK1 104 DDR_B_CLK#1 Place near to SO-DIMM connector
105 CK0# CK1# 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS#
111 BA0 RAS# 112 +3V_DA +3V_DB +3V_PCH
DDR_B_WE# 113 VDD13 VDD14 114 DDR_B_CS#0
+1.35V DDR_B_CAS# 115 WE# S0# 116 DDR_B_ODT0 RPC9
117 CAS# ODT0 118 1 8
DDR_B_MA13 119 VDD15 VDD16 120 DDR_B_ODT1 2 7
A13 ODT1 +0.675V_DDR_VREFCA
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_CS#1 121 122 3 6

123 S1# NC2 124 4 5
125 VDD17 VDD18 126
10mils
@1 @1 127 NCTEST VREF_CA 128 0_0804_8P4R_5%
1 1 1 1 1 1 VSS27 VSS28
CD39
CD40
CD41
CD42
CD43
CD44
CD45
CD46
DDR_B_D36 129 130 DDR_B_D32 @

DQ32 DQ36 +3VS
2.2U_0402_6.3V6M
0.1U_0201_10V6K
DDR_B_D37 131 132 DDR_B_D33
133 DQ33 DQ37 134
VSS29 VSS30 1
1
2 2 2 2 2 2 2 2
CD47
CD48
DDR_B_DQS#4 135 136 RPC10
DDR_B_DQS4 137 DQS#4 DM4 138 4 5
139 DQS4 VSS31 140 DDR_B_D39 3 6
2
DDR_B_D35 141 VSS32 DQ38 142 DDR_B_D38 2 DDR_B_SA1 2 7
DDR_B_D34 143 DQ34 DQ39 144 @ 1 8
3 145 DQ35 VSS33 146 DDR_B_D41 3
DDR_B_D45 147 VSS34 DQ44 148 DDR_B_D40 0_0804_8P4R_5%
DDR_B_D44 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
Layout Note: Layout Note: VSS37 VSS38 +1.35V
DDR_B_D43 157 158 DDR_B_D47
Place near JDIMM2.203,204 Place near JDIMM2.199 DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D46
161 DQ43 DQ47 162
VSS39 VSS40
1
1.8K_0402_1%
DDR_B_D49 163 164 DDR_B_D52
DQ48 DQ52
RD10
DDR_B_D48 165 166 DDR_B_D53
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170 +0.675V_DDR_VREFCA +0.675V_VREFCA
+0.675VS +3V_DB DDR_B_DQS6 171 DQS#6 DM6 172
2
173 DQS6 VSS43 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D51 RD11 1 RS@ 2 0_0402_5%
DDR_B_D55 177 DQ50 DQ55 178
DQ51 VSS45
0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2U_0402_6.3V6M
0.1U_0201_10V6K
179 180 DDR_B_D61

DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D60
1 1 1 1 1 DQ56 DQ61
1
1
CD50
CD51
CD52
CD53
CD54
CD55
1.8K_0402_1%
DDR_B_D57 183 184
DQ57 VSS47
RD12
185 186 DDR_B_DQS#7
@ @ @ 187 VSS48 DQS#7 188 DDR_B_DQS7
2
2 2 2 2 2 189 DM7 DQS7 190

DDR_B_D59 191 VSS49 VSS50 192 DDR_B_D62
2
DDR_B_D58 193 DQ58 DQ62 194 DDR_B_D63
+0.675VS +3V_DB 195 DQ59 DQ63 196 +0.675VS
DDR_B_SA0 197 VSS51 VSS52 198
199 SA0 EVENT# 200 SOC_SMBDATA
DDR_B_SA1 201 VDDSPD SDA 202 SOC_SMBCLK
+0.675VS_VTT 203 SA1 SCL 204 +0.675VS_VTT
VTT1 VTT2
205 206
4 G1 G2 Place near to SO-DIMM connector 4
Address : 01 FOX_AS0A621-J4SB-7H
ME@
SP07000P110
DDR_B_SA1
DDR_B_SA0
2014/05/19
Compal Secret Data
2015/12/31 Title
DDR3L_DIMMB
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
A B C D E
1 2 3 4 5
UV1A
A
AC Coupling Capacitor A
PCIe Gen3: Recommended value is 220 nF
PCIe Gen1 and Gen2 only: Recommended value is 100 nF
AF30 AH30 PCIE_CRX_C_GTX_P1 CV1 1 2 PX_G2@ 0.1U_0402_25V6

[11] PCIE_CTX_C_GRX_P1 PCIE_RX0P PCIE_TX0P PCIE_CRX_GTX_P1 [11]
AE31 AG31 PCIE_CRX_C_GTX_N1 CV2 1 2 PX_G2@ 0.1U_0402_25V6
[11] PCIE_CTX_C_GRX_N1 PCIE_RX0N PCIE_TX0N PCIE_CRX_GTX_N1 [11]
AE29 AG29 PCIE_CRX_C_GTX_P2 CV3 1 2 PX_G2@ 0.1U_0402_25V6

AD28 AF28 PCIE_CRX_C_GTX_N2 CV4 1 2 PX_G2@ 0.1U_0402_25V6
AD30 AF27 PCIE_CRX_C_GTX_P3 CV5 1 2 PX_G2@ 0.1U_0402_25V6

AC31 AF26 PCIE_CRX_C_GTX_N3 CV6 1 2 PX_G2@ 0.1U_0402_25V6
AC29 AD27 PCIE_CRX_C_GTX_P4 CV7 1 2 PX_G2@ 0.1U_0402_25V6

AB28 AD26 PCIE_CRX_C_GTX_N4 CV8 1 2 PX_G2@ 0.1U_0402_25V6
AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25 CV1 CV2 CV3 CV4
PCIE_RX4N PCIE_TX4N PX_G3@ PX_G3@ PX_G3@ PX_G3@ S CER CAP 0.22U 10V K X5R 0402
AA29 Y23 CV5 CV6 CV7 CV8

Y28 PCIE_RX5P PCIE_TX5P Y24 PX_G3@ PX_G3@ PX_G3@ PX_G3@
PCIE_RX5N PCIE_TX5N
Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N
W29 Y27
B
V28 PCIE_RX7P PCIE_TX7P Y26 B
PCIE_RX7N PCIE_TX7N
V30 W24
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23
U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26
PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23
No Use GPU Display Port outpud
R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27 UV1F EXO@
+VGA_CORE
P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23 AB11 0_0402_5% 2 MESO@ 1 RV177
VARY_BL AB12 0_0402_5% 2 MESO@ 1 RV176 FOR TOPAS CORE POWER USE
N29 P27 DIGON
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26
M30 P24 AL15

L31 NC#M30 NC#P24 P23 TXCAP_DPA3P AK14
NC#L31 NC#P23 TXCAM_DPA3N
AH16
L29 M27 TX0P_DPA2P AJ15
K30 NC#L29 NC#M27 N26 TX0M_DPA2N
NC#K30 NC#N26 AL17
TX1P_DPA1P AK16
C C
TX1M_DPA1N
CLOCK AH18
CLK_PCIE_GPU AK30 TX2P_DPA0P AJ17
[9] CLK_PCIE_GPU PCIE_REFCLKP TX2M_DPA0N
CLK_PCIE_GPU# AK32
[9] CLK_PCIE_GPU# PCIE_REFCLKN +0.95VGS AL19
+3VGS NC_TXOUT_L3P AK18
CALIBRATION NC_TXOUT_L3N
Y22 RV1 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX TMDP
RV2 1 PX@ 2 1K_0402_5% N10 AA22 RV3 1 PX@ 2 1K_0402_5%
TEST_PG PCIE_CALR_RX
5
UV2 PX@ AH20

PCIRST# 2 TXCBP_DPB3P AJ19
P
[30,31,34,37,39,9] PCIRST# B TXCBM_DPB3N

4 GPU_RST# AL27
DGPU_HOLD_RST# 1 Y PERSTB AL21
[10] DGPU_HOLD_RST# A TX3P_DPB2P
G
AK20
TX3M_DPB2N
1
3
RV4 216-0841018 A0 SUN PRO S3 EXO@ AH22

MC74VHC1G08DFT2G_SC70-5 100K_0402_5% TX4P_DPB1P AJ21
[20] GPU_RST# TX4M_DPB1N
PX@
AL23
2
TX5P_DPB0P AK22
TX5M_DPB0N
AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N
216-0841018 A0 SUN?PRO S3
D D

EXO/MESO(1/5)_PCIE/DP
Custom 0.1
1 2 3 4 5
1 2 3 4 5
+3VGS
RS@
RV375 1 2 0_0402_5%
+1.8VGS
PS_0[3:1]=001 Strap Name :
1
GPU_RST# 1 @ 2 PX@ PX@ UV1B EXO@ U?
[19] GPU_RST#
RV112 0_0402_5% RV157 RV158 PS_0[5:4]=11
1
47K_0402_5% 47K_0402_5% PS_0[1] ROM_CONFIG[0]
2
PX@
AF2 RV12 PS_0[2] ROM_CONFIG[1]
2
6 1 VGA_SMB_DA2 NC#AF2 AF4 8.45K_0402_1%
[28,31,34,7] EC_SMB_DA2 NC#AF4
PS_0[3] ROM_CONFIG[2]
2
PX@ QV9A N9 AG3 PS_0
DBG_DATA16 NC#AG3
5
ME2N7002D1KW-G 2N_SOT363-6 L9 AG5 Resistor Divider Lookup Lable PS_0[4] N/A
DBG_DATA15 NC#AG5
1
AE9 1
0.68U_0402_10V
DPA
3 4 VGA_SMB_CK2 Y11 DBG_DATA14 AH3 PX@
[28,31,34,7] EC_SMB_CK2 AE8 DBG_DATA13 NC#AH3 AH1 CV30 RV7
PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
PX@ QV9B AD9 DBG_DATA12 NC#AH1 R_pu (ohm) R_pd (ohm) Bitd [3:1] 2K_0402_1%
A ME2N7002D1KW-G 2N_SOT363-6 AC10 DBG_DATA11 AK3 @ 2 A
2
AD7 DBG_DATA10 NC#AK3 AK1
AC8 DBG_DATA9 NC#AK1 NC 4.75k 000
DVO
AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3
8.45k 2k 001
AB8 DBG_DATA6 NC#AM3
+3VGS +3VGS +3VGS +1.8VGS AB7 DBG_DATA5 AK6
4.53k 2k 010
AB4 DBG_DATA4 NC#AK6 AM5
AB2 DBG_DATA3 NC#AM5 6.98k 4.99k 011 +1.8VGS
DBG_DATA2 DPB PS_1[3:1]=000 Strap Name :
2
2 2 @ Y8 AJ7 4.53k 4.99k 100

CV195 RV71 RV161 Y7 DBG_DATA1 NC#AJ7 AH6
DBG_DATA0 NC#AH6 PS_1[5:4]=11
1
10K_0402_5% 10K_0402_5% CV182 3.24k 5.62k 101 PS_1[1] STRAP_BIF_GEN3_EN_A
0.1U_0201_10V7K @ @ 0.1U_0201_10V7K AK8 @
@ 1 1 NC#AK8 AL7 RV9
3.4k 10k 110 PS_1[2] TRAP_BIF_CLK_PM_EN
1
@ FOR MESO only NC#AL7 8.45K_0402_1%

UV13 @ 4.75k NC 111 PS_1[3] N/A
2
@ 33_0402_5% 1 8 33_0402_5% +1.8VGS W6 PS_1
GPU_VID3 RV162 1 2GPU_VID3_GPIO_15 2 VCCA VCCB 7 GPU_SVD_R RV131 1 2 GPU_SVD V6 NC#W6
A1 B1 NC#V6 0402 1% resistors are equired PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
1
GPU_VID1 RV81 1 2GPU_VID1_GPIO_20 3 6 GPU_SVC_R RV130 1 2 GPU_SVC V4 1
0.68U_0402_10V
@ 33_0402_5%DIR 5 A2 B2 4 AC6 NC#V4 U5 PX@
DIR GND 33_0402_5% @ AC5 NC#AC5 NC#U5 CV31 RV14
PS_1[5] STRAP_TX_DEEMPH_EN
NC#AC6
2
W3 4.75K_0402_1%
NC#W3
2
SN74LVC2T45DCTR_SM8 AA5 V2 @ 2
Capacitor Divider Lookup Lable
2
RV16 RV11 AA6 NC#AA5 NC#V2
DPC
RV135 RV134 4.7K_0402_5% 4.7K_0402_5% NC#AA6 Y4
10K_0402_5% 10K_0402_5% GPU_VID3 RV182 1 EXO@ 2 2.2K_0402_5% GPU_SVD MESO@ MESO@ NC#Y4 W5 Cap (nF) Bitd [5:4]
1
@ @ GPU_VID1 RV183 1 EXO@ 2 2.2K_0402_5% GPU_SVC NC#W5
1
U1 AA3 PLL_ANALOG_OUT 1 PX@ 2
TP@ 1 FB_VDDCI W1 NC#U1 NC#AA3 Y2 RV17
@
TV23
U3 NC#W1 NC#Y2 16.2K_0402_1%
680nF 00
+3VGS 10K_0402_5% CV180 10U_0603_6.3V6M Y6 NC#U3 J8 +1.8VGS
RV136 2 1 DIR 2 1 TP@ 1 PLL_ANALOG_IN AA1 NC#Y6 NC#J8 82nF 01 PS_2[3:1]=000 Strap Name :
TV18 NC#AA1
10nF 10 PS_2[5:4]=11
1
@ CV196 PS_2[1] N/A
2 1 0.1U_0201_10V7K NC 11 AMD recommend 09/25 @
RV57 PS_2[2] N/A
@ I2C 8.45K_0402_1%
PS_2[3] STRAP_BIOS_ROM_EN
2
B R1 PS_2 B
R3 SCL
SDA PS_2[4] STRAP_BIF_VGA_DIS
1
+3VGS
1
0.68U_0402_10V
+3VGS AM26 @ PX@
REAK CURRENT CONTROL ( MESO only ) +VGA_CORE R AK26 CV32 RV19
PS_2[5] N/A
GENERAL PURPOSE I/O AVSSN#AK26
2
U6 +3VGS 4.75K_0402_1%
GPIO_0
2
RV170 1 MESO@ 2 0_0402_5%

U10 AL25 2
2
RV10 RV174 1 MESO@ 2 0_0402_5%
T10 GPIO_1 G AJ25 @ RV373
GPIO_2 AVSSN#AJ25
2
10K_0402_5% VGA_SMB_DA2 U8 4.7K_0402_5%
VGA_SMB_CK2 U7 SMBDATA AH24 RV371
MESO@
2 1
RV15 MESO@ DV1 1 2 GPU_GPIO5 T9 SMBCLK B AG25
[32,34,43,9] VCIN1_AC_IN 4.7K_0402_5%
1
GPIO_5_AC_BATT AVSSN#AG25
G
1K_0402_5% GPU_GPIO6 T8 @
GPU_GPIO6 1 2 GPU_PROCHOT# RB751V_SOD323 T7 GPIO_6 DAC1 AH26
GPU_PROCHOT# [48]
1
MESO@ P10 GPIO_7_BLON HSYNC AJ27 3 1 GPU_WAKEB 1 TP@
1 GPIO_8_ROMSO VSYNC TV26
1 @ 2 P4 +1.8VGS
D
[43] AC_BATT GPIO_9_ROMSI PS_3[3:1]=000 Strap Name :
2
CV17 RV180 0_0402_5% P2
+VGA_CORE N6 GPIO_10_ROMSCK AD22 RV372 2N7002H_SOT23-3
0.1U_0201_10V7K GPIO_11 RSET PS_3[5:4]=11
1
2 N5 @ QV20
MESO@
N3 GPIO_12 AG24
4.7K_0402_5%
PX@ X76@
PS_3[1] BOARD_CONFIG[0] (Memory ID)
RV172 1 MESO@ 2 0_0402_5% Y9 GPIO_13 AVDD AE22
OBFF OPTION: RV21 PS_3[2] BOARD_CONFIG[1] (Memory ID)
1
GPU_VID3 N1 GPIO_14_HPD2
GPIO_15_PWRCNTL_0
AVSSQ reserved for AMD request 8.45K_0402_1%
M4 AE23 Pull down for none OBFF design
PS_3[3] BOARD_CONFIG[2] (Memory ID)
2
FOR TOPAS CORE POWER USE THM_ALERT# RV194 1 2 RS@ 0_0402_5% THM_ALERT#_R R6 GPIO_16 VDD1DI AD23 PS_3
[31] THM_ALERT# GPIO_17_THERMAL_INT VSS1DI
RV173 1 MESO@ 2 0_0402_5% W10 PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
GPIO_18
1
GPIO19_CTF M2 1
0.68U_0402_10V
GPIO_19_CTF FutureASIC/SEYMOUR/PARK
GPU_VID1 P8 AM12
CV33
X76@ PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
+1.8VGS P7 GPIO_20_PWRCNTL_1 CEC_1 @ RV24
N8 GPIO_21 2K_0402_1%
1 RV13 2 GPIO19_CTF AK10 GPIO_22_ROMCSB AK12 SVI2_SVD RV166 1 MESO@ 2 0_0402_5% GPU_SVD 2
GPU_SVD [48]
2
10K_0402_5% AM10 GPIO_29 RSVD#AK12 AL11 SVI2_SVT RV167 1 MESO@ 2 0_0402_5% GPU_SVT
GPIO_30 RSVD#AL11 GPU_SVT [48]
@ N7 AJ11 SVI2_SVC RV168 1 MESO@ 2 0_0402_5% GPU_SVC GPU_SVC [48]
[9] GPUCLK_REQ# CLKREQB RSVD#AJ11
2
RV22 JTAG_TRSTB L6 FOR MESO

JTAG_TDI L5 JTAG_TRSTB EXO doesn't have native SVI2
10K_0402_5%
JTAG_TCK L3 JTAG_TDI
@ JTAG_TCK
+3VGS 1 @ 2 TP@ JTAG_TMS L1 AL13
1
RV26 5.11K_0402_5% 1 JTAG_TDO K4 JTAG_TMS GENLK_CLK AJ13

TV24 JTAG_TDO GENLK_VSYNC
+3VGS 1 PX@ 2 TESTEN K7
C RV27 1K_0402_5% AF24 TESTEN C
RV18 2 PX@ 1 4.7K_0402_5% THM_ALERT# +VGA_CORE NC#AF24 AG13
SWAPLOCKA AH12
RV169 1 MESO@ 2 0_0402_5% AB13 SWAPLOCKB
W8 GENERICA
RV171 1 MESO@ 2 0_0402_5% W9 GENERICB
W7 GENERICC AC19 PS_0
AD10 GENERICD PS_0
AJ9 GENERICE AD19 PS_1
+3VGS TP@ 1 AL9 NC#AJ9 PS_1
TV22 NC#AL9 AE17 PS_2
RV175 1 MESO@ 2 0_0402_5% AC14 PS_2
TP@ 1 PX_EN AB16 HPD1 AE20 PS_3
TV25 PX_EN PS_3
RV58 1 @ 2 GPU_GPIO5
10K_0402_5%
RV20 1 @ 2 JTAG_TDO AE19
10K_0402_5% AC16 TS_A
DBG_VREFG
VGA_AC_BATT
pull up DDC/AUX
+3VGS AE6
PLL/CLOCK DDC1CLK AE5
DDC1DATA OPTIAN FOR 3.3V tolerance VR,
RPV1 @ AD2 Check with VR vendor
1 8 JTAG_TRSTB AUX1P AD4 +VGA_CORE +1.8VGS +3VGS
2 7 JTAG_TDI AUX1N RV185 RV186
3 6 JTAG_TMS AC11 RV178 1 MESO@ 2 0_0402_5% 1 MESO@ 2 1 EXO@ 2
4 5 JTAG_TCK DDC2CLK AC13 RV179 1 MESO@ 2 0_0402_5% FOR MESO CORE POWER USE 0_0402_5% 0_0402_5%
DDC2DATA
2
10K_8P4R_5% XTALIN AM28 AD13 RV164 RV163
XTALOUT AK28 XTALIN AUX2P AD11 10K_0402_5% PX@ 10K_0402_5%
XTALOUT AUX2N @
RV28 RV29 1 PX@ 2 10K_0402_5% AC22 AD20 FB_GND RV37 1 MESO@ 2 0_0402_5%
1
XTALIN 1M_0402_5% XTALOUT RV31 1 PX@ 2 10K_0402_5% AB22 XO_IN NC#AD20 AC20 FB_VDDC RV51 1 MESO@ 2 0_0402_5% GPU_VDD_RUN_FB_L [48] GPU_SVD
PX@ TO EXTERNAL THERMAL SENSOR XO_IN2 NC#AC20 ONLY AVAILABLE ON TOPAZ, NC BALLS ON JET/SUN GPU_VDD_SEN [48] GPU_SVC
AE16
NC#AE16
2
AD16
D YV1 PX@ NC#AD16 D
4 3 SEYMOUR/FutureASIC AC1 @ PX@
NC OSC REMOTE1+ T4 DDCVGACLK AC3 RV165 RV184
[31] REMOTE1+ DPLUS THERMAL DDCVGADATA
1 2 REMOTE1- T2 GPU_VDD_RUN_FB_L RV30 1 @ 2 0_0402_5% 10K_0402_5% 10K_0402_5%
[31] REMOTE1-
1
OSC NC DMINUS
27MHZ 10PF +-10PPM 7V27000050 +1.8VGS GPU_VDD_SEN RV32 1 @ 2 0_0402_5%
2 2 +VGA_CORE
SJ10000FH00 Enable MLPS RV33 1 EXO@ 2 10K_0402_5% GPIO28 R5
PX@ CV19 PX@ CV20 RS@ AD17 GPIO28_FDO
LV4 1 2 0_0402_5% +TSVDD AC17 TSVDD
10P_0402_50V8J 10P_0402_50V8J
1 1 TSVSS
1
CV21
1U_0402_6.3V6K Security Classification Compal Secret Data Compal Electronics, Inc.
PX@ 2015/01/07 2016/01/07 Title
2 216-0841018 A0 SUN PRO ?S3
EXO/MESO(2/5)_MSIC
Custom 0.1
1 2 3 4 5
1 2 3 4 5
+1.35VS to +1.35VGS UV1E EXO@ U?
+1.35V +1.35VGS
UV14 PX@ AA27 A3
AP4800BGM-HF 1N SO-8 No Use GPU Display Port outpud AB24 GND GND A30
8 1 +1.8VGS AB32 GND GND AA13
7 2 AC24 GND GND AA16
GND GND
2
0.1U_0201_10V7K
6 3 UV1G EXO@ U? AC26 AB10
GND GND
10U_0603_6.3V6M
1U_0402_6.3V6K
1 5 1 1 RV34 AC27 AB15
GND GND
CV25
CV26
CV22
AD25 AB6
CV23
CV24
470_0603_5% DP POWER NC/DP POWER
AD32 GND GND AC9
PX@ 1 1
4
AG15 AE11 AE27 GND GND AD6
A A
3 1
2 PX@ 2 PX@ 2 PX@ AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7
1U_0402_6.3V6K
10U_0603_6.3V6M
2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
DP_VDDR#AG17 NC#AF13 GND GND
PX@
PX@
AG18 AG8 K28 AH10
PX@ 220K_0402_5% 5 DGPU_PWR_EN# AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
1 2 1.35VSG_GATE 1 PX@ 2 AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
B+ DP_VDDR#AF14 GND GND
RV35 1M_0402_5% RV36 QV10B M32 B12
4
GND GND
6
ME2N7002D1KW-G 2N_SOT363-6 N25 B14
PX@ PX@ N27 GND GND B16
P25 GND GND B18
1 GND GND
DGPU_PWR_EN# 2 QV10A PX@ AG20 AF6 P32 B20
ME2N7002D1KW-G 2N_SOT363-6 CV27 AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
0.022U_0402_25V7K +0.95VGS AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
1
2 AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
AD14 DP_VDDC#AG22 NC#AF9 U25 GND GND B6
DP_VDDC#AD14 U27 GND GND B8
V32 GND GND C1
CV28
CV29
W25 GND GND C32
1 1 GND GND
AG14 AE1 W26 E28
AH14 DP_VSSR NC#AE1 AE3 W27 GND GND F10
AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12
1U_0402_6.3V6K
0.1U_0201_10V7K
2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
DP_VSSR NC#AG6 GND GND
PX@
PX@
AM18 AH5 F16
AF23 DP_VSSR NC#AH5 AF10 GND F18
AG23 DP_VSSR NC#AF10 AG9 GND F2
AM20 DP_VSSR NC#AG9 AH8 GND F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
AE14 DP_VSSR NC#AG11 N21 GND GND
GND F8
DP_VSSR P6 GND GND G10
+1.8VALW TO +1.8VGS P9
R12
GND
GND
GND
GND
G27
G31
B +1.0VALW
+1.0VALW TO +0.95VGS AF17
DPAB_CALR NC#AE10
AE10 R15
R17
GND
GND
GND
GND
GND
GND
G8
H14
B
C29 Load switch R20

T13
T16
GND
GND
GND
GND
H17
H2
H20
GND GND
1U_0402_6.3V6K
1 216-0841018 A0 SUN PRO? S3 T18 H6

@ T21 GND GND J27
T6 GND GND J31
+0.95VGS U15 GND GND K11
2 UV1895 U17 GND GND K2
1 14 +0.95VGS_LS RV5 1 RS@ 2 0_0805_5% U20 GND GND K22
PX@ 2 VIN1 VOUT1 13 U9 GND GND K6
R1642 VIN1 VOUT1 V13 GND GND
GND
2
DGPU_PWR_EN 2 1 DGPU_PWR_EN_R 3 12 @ 1 2 PX@ V16
150K_0402_5% ON1 CT1 2200P_0402_50V7K C28 C32 V18 GND
4 11 Y10 GND
VL 0.1U_0201_10V7K
1
VBIAS GND Y15 GND
GND
0.1U_0402_25V6
5 10 @ 1 2 Y17
ON2 CT2 GND
1
+1.8VGS
C1380
2200P_0402_50V7K C27 Y20

PX@ +1.8VALW 6 9 R11 GND A32
7 VIN2 VOUT2 8 +1.8VGS_LS RV6 1 RS@ 2 0_0805_5% T11 GND VSS_MECH AM1
2
VIN2 VOUT2 AA11 GND VSS_MECH AM32

15 M12 GND VSS_MECH
GPAD GND
2
PX@ N11
EM5209VF DFN 14P C31 V11 GND
GND
0.1U_0201_10V7K
1
1 PX@
@ C30
?
216-0841018 A0 SUN PRO S3
SA00007PM00
1U_0402_6.3V6K
C C
+3VALW to +3VGS
+VGA_CORE +1.8VGS +0.95VGS
+3VALW +3VGS
2
PX@
RV39 RV53 RV56
3 1 4.7U_0603_6.3V6K 1U_0402_6.3V6K 470_0603_5% 470_0603_5% 470_0603_5%
PX@ @ @
1
ME2N7002D1KW-G 2N_SOT363-6
ME2N7002D1KW-G 2N_SOT363-6
QV16 1 1 @
1 1
6 1
3 1
LP2301ALT1G_SOT23-3 CV36 CV37 RV40
D
680_0603_5%
2
PX@ @ DGPU_PWR_EN# 2 PX@

2 2 QV11
3VGS_EN#
G
2
+5VALW S 2N7002H_SOT23-3 2 DGPU_PWR_EN# 5 DGPU_PWR_EN#
3
@
1
D QV21A QV21B
4
2 @ @
PX@ QV17 G
RV42 PX@ DGPU_PWR_EN# 1 2 S 2N7002H_SOT23-3
3
RV43 10K_0402_5%
20K_0402_5%
D D
1
RS@ D
1 PX@
R1640 2 1 0_0402_5% DGPU_PWR_EN_3VGS 2 PX@ DGPU_PWR_EN#
[10,34,48] DGPU_PWR_EN CV38
G QV18
0.1U_0201_10V7K
1
S 2N7002H_SOT23-3
3
RV41 2
@
100K_0402_5%
2
EXO/MESO(3/5)_PWR/GND
Custom 0.1
1 2 3 4 5
1 2 3 4 5
A A
+1.35VGS
UV1D EXO@ +1.8VGS
U?
AM30
MEM I/O PCIE_PVDD
PCIE
CV47
CV48
+1.35VGS H13 AB23 1 1
H16 VDDR1 NC#AB23 AC23
H19 VDDR1 NC#AC23 AD24
CV75
CV88
CV74
CV80
CV83
CV87
CV76
CV77
CV78
CV79
CV81
CV82
CV89
CV86
CV85
CV84
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
220U_B2_2.5VM_R35
J10 VDDR1 NC#AD24 AE24
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M
1U_0402_6.3V6K
+ J23 VDDR1 NC#AE24 AE25 2 2
VDDR1 NC#AE25
PX@
PX@
@ J24 AE26
J9 VDDR1 NC#AE26 AF25
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VDDR1 NC#AF25
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
@
K10 AG26
K23 VDDR1 NC#AG26
K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L20 VDDR1 PCIE_VDDC M22 +0.95VGS
L21 VDDR1 PCIE_VDDC N22
L22 VDDR1 PCIE_VDDC N23
VDDR1 PCIE_VDDC N24
PCIE_VDDC R22
PCIE_VDDC T22
CV49
CV50
CV51
CV52
CV53
CV54
+1.8VGS LEVEL PCIE_VDDC U22
TRANSLATION PCIE_VDDC 1 1 1 1 1 1
V22
AA20 PCIE_VDDC
AA21 VDD_CT
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AB20 VDD_CT AA15 2 2 2 2 2 2
CV55
B VDD_CT CORE VDDC B
PX@
PX@
PX@
PX@
PX@
@
1 AB21 N15
VDD_CT VDDC N17
+3VGS VDDC R13
I/O VDDC R16
1U_0402_6.3V6K
2 AA17 VDDC R18
VDDR3 VDDC
PX@
AA18 Y21
AB17 VDDR3 VDDC T12
CV56
AB18 VDDR3 VDDC T15 +VGA_CORE
1 VDDR3 VDDC T17
V12 VDDC T20
Y12 VDDR4 VDDC U13
1U_0402_6.3V6K
2 U12 VDDR4 VDDC U16
VDDR4 VDDC
PX@
U18
VDDC V21 VGA_CORE Caps in power side sheet
VDDC V15
VDDC V17
VDDC V20
VDDC
POWER
Y13
VDDC Y16
VDDC Y18
VDDC AA12
VDDC M11
VDDC N12
VDDC U11
VDDC
+1.8VGS
RS@ PLL
LV1 1 2 0_0603_5% +MPLL_PVDD
+0.95VGS
R21
CV39
CV40
CV41
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
BIF_VDDC U21
1 1 1 BIF_VDDC
L8
+1.8VGS MPLL_PVDD
C C
2 2 2 +VGA_CORE
PX@
PX@
PX@
RS@
CV62
ISOLATED
LV2 1 2 0_0402_5% +SPLL_PVDD CORE I/O 1
M13
H7 VDDCI M15
CV42
CV43
10U_0603_6.3V6M
1U_0402_6.3V6K
SPLL_PVDD VDDCI M16
1 1
1U_0402_6.3V6K
VDDCI M17 2
+0.95VGS VDDCI
@
M18
0_0402_5% VDDCI M20
2 2 VDDCI
PX@
PX@ LV3 1 2 +SPLL_VDDC H8 M21

RS@ SPLL_VDDC VDDCI N20
J7 VDDCI
SPLL_PVSS
CV46
CV90
VGA_CORE Caps in power side sheet
1U_0402_6.3V6K
0.1U_0201_10V7K
1 1
216-0841018 A0 SUN PRO S3?

2 2
PX@
PX@
D D

EXO/MESO(4/5)_PWR
Custom 0.1
1 2 3 4 5
1 2 3 4 5
EXO@
M_DA[63..0] UV1C U?
[24,25] M_DA[63..0]
M_MA[15..0] GDDR5/DDR3 GDDR5/DDR3
[24,25] M_MA[15..0]
A M_DA0 K27 K17 M_MA0 A
M_DQM[7..0] M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M_MA1
[24,25] M_DQM[7..0] DQA0_1 MAA0_1/MAA_1
M_DA2 H30 H23 M_MA2
M_DQS[7..0] M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M_MA3
[24,25] M_DQS[7..0] DQA0_3 MAA0_3/MAA_3
M_DA4 G29 G24 M_MA4
M_DQS#[7..0] M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M_MA5
[24,25] M_DQS#[7..0] DQA0_5 MAA0_5/MAA_5
M_DA6 F32 J19 M_MA6
M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
M_DA11 C28 DQA0_10 J14 M_MA8
M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M_MA9
M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M_MA10
M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M_BA2
DQA0_16 MAA1_5/MAA_BA2 M_BA2 [24,25]
M_DA17 C25 J16 M_BA0
DQA0_17 MAA1_6/MAA_BA0 M_BA0 [24,25]
M_DA18 E25 L15 M_BA1
DQA0_18 MAA1_7/MAA_BA1 M_BA1 [24,25]
M_DA19 D24 G14 M_MA14
M_DA20 E23 DQA0_19 MAA1_8/MAA_14 L16
MEMORY INTERFACE
M_DA21 F23 DQA0_20 MAA1_9/RSVD
M_DA22 D22 DQA0_21 E32 M_DQM0
+1.35VGS M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1
M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2
M_DA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 M_DQM3
M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_DQM4
DQA0_26 WCKA1_0/DQMA1_0
1
M_DA27 A19 D12 M_DQM5

PX@ M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_DQM6
RV44 M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7
40.2_0402_1% M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3
M_DA31 C17 DQA0_30 H28 M_DQS0
2
M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_DQS1

M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_DQS3
B
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_DQS4 B
DQA1_3 EDCA1_0/QSA1_0
1
1 M_DA36 D14 D10 M_DQS5

PX@ PX@ M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_DQS6
RV46 CV65 M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7
100_0402_1% 1U_0402_6.3V6K M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3
2 M_DA40 E11 DQA1_7 H27 M_DQS#0
2
M_DA41 A11 DQA1_8 DDBIA0_0/QSA0_0B A27 M_DQS#1

M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DQS#2
M_DA43 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 M_DQS#3
M_DA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 M_DQS#4
M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DQS#5
M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DQS#6
M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DQS#7
+1.35VGS M_DA48 E7 DQA1_15 DDBIA1_3/QSA1_3B
M_DA49 A7 DQA1_16 L18 VRAM_ODT0
DQA1_17 ADBIA0/ODTA0 VRAM_ODT0 [24]
M_DA50 C7 K16 VRAM_ODT1
DQA1_18 ADBIA1/ODTA1 VRAM_ODT1 [25]
M_DA51 F7
DQA1_19
1
M_DA52 A5 H26 M_CLK0

DQA1_20 CLKA0 M_CLK0 [24]
PX@ M_DA53 E5 H25 M_CLK#0
DQA1_21 CLKA0B M_CLK#0 [24]
RV45 M_DA54 C3
40.2_0402_1% M_DA55 E1 DQA1_22 G9 M_CLK1
DQA1_23 CLKA1 M_CLK1 [25]
M_DA56 G7 H9 M_CLK#1
M_CLK#1 [25]
2
M_DA57 G6 DQA1_24 CLKA1B

M_DA58 G1 DQA1_25 G22 M_RAS#0
DQA1_26 RASA0B M_RAS#0 [24]
M_DA59 G3 G17 M_RAS#1
DQA1_27 RASA1B M_RAS#1 [25]
M_DA60 J6
DQA1_28
1
1 M_DA61 J1 G19 M_CAS#0

DQA1_29 CASA0B M_CAS#0 [24]
PX@ PX@ M_DA62 J3 G16 M_CAS#1
DQA1_30 CASA1B M_CAS#1 [25]
RV47 CV66 M_DA63 J5
100_0402_1% 1U_0402_6.3V6K DQA1_31 H22 M_CS0B#0
2 CSA0B_0 M_CS0B#0 [24]
+MVREFDA K26 J22
2
+MVREFSA J26 MVREFDA CSA0B_1

MVREFSA G13 M_CS1B#0
CSA1B_0 M_CS1B#0 [25]
J25 K13
RV52 1 PX@ 2 120_0402_1% K25 NC#J25 CSA1B_1
C C
MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE0 [24]
PX@ PX@ J17 M_CKE1
CKEA1 M_CKE1 [25]
RV48 RV49
49.9_0402_1% 10_0402_1% G25 M_WE#0
WEA0B M_WE#0 [24]
1 2 2 1 DRST L10 H10 M_WE#1
[24,25] DRAM_RST DRAM_RST WEA1B M_WE#1 [25]
1 RV54 @ 1 2 51.1_0402_1% CV69 @1 2 0.1U_0201_10V7K K8

CLKTESTA
1
1 @ RV55 @ 1 2 51.1_0402_1% CV70 @1 2 L7

PX@ PX@ CV67 0.1U_0201_10V7K CLKTESTB
CV68 RV50 68P_0402_50V8J
120P_0402_50V8J 5.1K_0402_1% 2 Route 50ohms single-ended/100ohm diff and keep short
216-0841018 A0 SUN PRO S3
2 debug only, for clock observation,if not need, DNI. ?
2
Place close to GPU (within 25mm)

and place componment close to each other
D D

EXO/MESO(5/5)_MEM
Custom 0.1
1 2 3 4 5
1 2 3 4 5
DDR3L Memory Channel Rank 0:A0

M_DA[63..0]
[23,25] M_DA[63..0]
M_MA[15..0]
[23,25] M_MA[15..0]
M_DQM[7..0] +1.35VGS +1.35VGS
[23,25] M_DQM[7..0]
M_DQS[7..0]
[23,25] M_DQS[7..0]
1
A M_DQS#[7..0] PX@ PX@ A
[23,25] M_DQS#[7..0]
RV63 RV62
4.99K_0402_1% UV5 4.99K_0402_1% UV6
2
+FBA_VREF0 M8 E3 M_DA8 +FBA_VREF1 M8 E3 M_DA18
H1 VREFCA DQL0 F7 M_DA14 H1 VREFCA DQL0 F7 M_DA19
VREFDQ DQL1 F2 M_DA10 VREFDQ DQL1 F2 M_DA16
DQL2 DQL2
1
PX@
1
PX@
M_MA0
M_MA1
N3
P7 A0 DQL3
F8
H3
M_DA13
M_DA9 PX@
1
PX@
M_MA0
M_MA1
N3
P7 A0 DQL3
F8
H3
M_DA20
M_DA21
+EC_VCCA
RV75 CV72 M_MA2 P3 A1 DQL4 H8 M_DA12 RV66 CV71 M_MA2 P3 A1 DQL4 H8 M_DA23
4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA11 4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA17
2 M_MA4 P8 A3 DQL6 H7 M_DA15 2 M_MA4 P8 A3 DQL6 H7 M_DA22
2
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
16.5K_0402_1%
A5 A5
1
M_MA6 R8 M_MA6 R8
M_MA7 R2 A6 D7 M_DA5 M_MA7 R2 A6 D7 M_DA31
RV374
M_MA8 T8 A7 DQU0 C3 M_DA3 M_MA8 T8 A7 DQU0 C3 M_DA27 PX@
M_MA9 R3 A8 DQU1 C8 M_DA6 M_MA9 R3 A8 DQU1 C8 M_DA30
M_MA10 L7 A9 DQU2 C2 M_DA2 M_MA10 L7 A9 DQU2 C2 M_DA24
2
M_MA11 R7 A10/AP DQU3 A7 M_DA4 M_MA11 R7 A10/AP DQU3 A7 M_DA28
M_MA12 N7 A11 DQU4 A2 M_DA1 M_MA12 N7 A11 DQU4 A2 M_DA25 [34] VRAM_TEMP
M_MA13 T3 A12 DQU5 B8 M_DA7 M_MA13 T3 A12 DQU5 B8 M_DA29
M_MA14 T7 A13 DQU6 A3 M_DA0 M_MA14 T7 A13 DQU6 A3 M_DA26
A14 DQU7 A14 DQU7
1
M_MA15 M7 M_MA15 M7
A15/BA3 +1.35VGS A15/BA3 +1.35VGS PHV1
PX@ 100K_0402_1%_TSM0B104F4251RZ
M_BA0 M2 B2 M_BA0 M2 B2
[23,25] M_BA0 BA0 VDD BA0 VDD
M_BA1 N8 D9 M_BA1 N8 D9
[23,25] M_BA1
2
M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7
K2 K2
VDD K8 VDD K8
VDD N1 VDD N1
M_CLK0 M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9
[23] M_CLK0 CK VDD CK VDD
M_CLK#0 M_CLK#0 K7 R1 M_CLK#0 K7 R1
[23] M_CLK#0 CK VDD CK VDD
M_CKE0 K9 R9 M_CKE0 K9 R9
[23] M_CKE0 CKE/CKE0 VDD +1.35VGS CKE/CKE0 VDD +1.35VGS
1
B B
PX@ PX@ ECAGND
RV102 RV103 VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1
[23] VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
40.2_0402_1% 40.2_0402_1% M_CS0B#0 L2 A8 M_CS0B#0 L2 A8
[23] M_CS0B#0 CS/CS0 VDDQ CS/CS0 VDDQ
M_RAS#0 J3 C1 M_RAS#0 J3 C1
[23] M_RAS#0 RAS VDDQ RAS VDDQ
M_CAS#0 K3 C9 M_CAS#0 K3 C9
[23] M_CAS#0
2
M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2

[23] M_WE#0 WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
M_DQS1 F3 VDDQ H2 M_DQS2 F3 VDDQ H2
1 DQSL VDDQ DQSL VDDQ
PX@ M_DQS0 C7 H9 M_DQS3 C7 H9
CV73 DQSU VDDQ DQSU VDDQ
0.01U_0402_16V7K
2 M_DQM1 E7 A9 M_DQM2 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
M_DQS#1 G3 VSS J2 M_DQS#2 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#3 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
[23,25] DRAM_RST RESET VSS RESET VSS
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1
PX@ L1 NC/ODT1 VSSQ B9 PX@ L1 NC/ODT1 VSSQ B9
RV111 J9 NC/CS1 VSSQ D1 RV110 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
SINGLE RANK:RV102,RV103 install 40.2 ohms
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
C C
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
X76@ X76@
+1.35VGS +1.35VGS +1.35VGS

10U_0603_6.3V6M
CV105
1U_0402_6.3V6K
CV106
1U_0402_6.3V6K
CV107
1U_0402_6.3V6K
CV108
1U_0402_6.3V6K
CV109
1U_0402_6.3V6K
CV112
1U_0402_6.3V6K
CV113
0.1U_0201_10V7K
CV125
10U_0603_6.3V6M
CV115
10U_0603_6.3V6M
CV116
1U_0402_6.3V6K
CV117
1U_0402_6.3V6K
CV120
1U_0402_6.3V6K
CV121
1U_0402_6.3V6K
CV126
1U_0402_6.3V6K
CV123
1U_0402_6.3V6K
CV122
1U_0402_6.3V6K
CV124
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
D D

EXO/MESO_DDR3L_A1 Rank 0
Custom 0.1
1 2 3 4 5
1 2 3 4 5
DDR3L Memory Channel Rank 0:A1

+1.35VGS
+1.35VGS
1
1
PX@
PX@ RV119
RV118 4.99K_0402_1% UV4
4.99K_0402_1% UV3
2
A M_DA[63..0] +FBA_VREF3 M8 E3 M_DA34 A
[23,24] M_DA[63..0]
2
+FBA_VREF2 M8 E3 M_DA58 H1 VREFCA DQL0 F7 M_DA38
M_MA[15..0] H1 VREFCA DQL0 F7 M_DA61 VREFDQ DQL1 F2 M_DA35
[23,24] M_MA[15..0] VREFDQ DQL1 DQL2
1
F2 M_DA59 1 M_MA0 N3 F8 M_DA39
DQL2 A0 DQL3
1
M_DQM[7..0] 1 M_MA0 N3 F8 M_DA62 PX@ PX@ M_MA1 P7 H3 M_DA32
[23,24] M_DQM[7..0] A0 DQL3 A1 DQL4
PX@ PX@ M_MA1 P7 H3 M_DA56 RV127 CV118 M_MA2 P3 H8 M_DA37
M_DQS[7..0] RV126 CV119 M_MA2 P3 A1 DQL4 H8 M_DA63 4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA33
[23,24] M_DQS[7..0] A2 DQL5 2 A3 DQL6
4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 G2 M_DA57 M_MA4 P8 H7 M_DA36
2
M_DQS#[7..0] 2 M_MA4 P8 A3 DQL6 H7 M_DA60 M_MA5 P2 A4 DQL7
[23,24] M_DQS#[7..0]
2
M_MA5 P2 A4 DQL7 M_MA6 R8 A5
M_MA6 R8 A5 M_MA7 R2 A6 D7 M_DA47
M_MA7 R2 A6 D7 M_DA52 M_MA8 T8 A7 DQU0 C3 M_DA43
M_MA8 T8 A7 DQU0 C3 M_DA51 M_MA9 R3 A8 DQU1 C8 M_DA46
M_MA9 R3 A8 DQU1 C8 M_DA55 M_MA10 L7 A9 DQU2 C2 M_DA42
M_MA10 L7 A9 DQU2 C2 M_DA50 M_MA11 R7 A10/AP DQU3 A7 M_DA44
M_MA11 R7 A10/AP DQU3 A7 M_DA54 M_MA12 N7 A11 DQU4 A2 M_DA41
M_MA12 N7 A11 DQU4 A2 M_DA49 M_MA13 T3 A12 DQU5 B8 M_DA45
M_MA13 T3 A12 DQU5 B8 M_DA53 M_MA14 T7 A13 DQU6 A3 M_DA40
M_MA14 T7 A13 DQU6 A3 M_DA48 M_MA15 M7 A14 DQU7
M_MA15 M7 A14 DQU7 A15/BA3 +1.35VGS
A15/BA3 +1.35VGS
M_BA0 M2 B2
M_BA0 M2 B2 M_BA1 N8 BA0 VDD D9
M_BA1 N8 D9 M_BA2 M3 G7
M_BA2 M3 G7 K2
[23,24] M_BA2 BA2 VDD VDD
M_CLK1 K2 K8
M_CLK#1 VDD K8 VDD N1
VDD N1 M_CLK1 J7 VDD N9
M_CLK1 J7 VDD N9 M_CLK#1 K7 CK VDD R1
[23] M_CLK1 CK VDD CK VDD
1
PX@ PX@ M_CLK#1 K7 R1 M_CKE1 K9 R9

[23] M_CLK#1 CK VDD CKE/CKE0 VDD +1.35VGS
RV139 RV140 M_CKE1 K9 R9
[23] M_CKE1 CKE/CKE0 VDD +1.35VGS
40.2_0402_1% 40.2_0402_1%
VRAM_ODT1 K1 A1
VRAM_ODT1 K1 A1 M_CS1B#0 L2 ODT/ODT0 VDDQ A8
[23] VRAM_ODT1
2
M_CS1B#0 L2 ODT/ODT0 VDDQ A8 M_RAS#1 J3 CS/CS0 VDDQ C1

B [23] M_CS1B#0 CS/CS0 VDDQ RAS VDDQ B
M_RAS#1 J3 C1 M_CAS#1 K3 C9
[23] M_RAS#1 RAS VDDQ CAS VDDQ
M_CAS#1 K3 C9 M_WE#1 L3 D2
[23] M_CAS#1 CAS VDDQ WE VDDQ
1 M_WE#1 L3 D2 E9
[23] M_WE#1 WE VDDQ VDDQ
PX@ E9 F1
CV154 VDDQ F1 M_DQS4 F3 VDDQ H2
0.01U_0402_16V7K M_DQS7 F3 VDDQ H2 M_DQS5 C7 DQSL VDDQ H9
2 M_DQS6 C7 DQSL VDDQ H9 DQSU VDDQ
DQSU VDDQ
M_DQM4 E7 A9
M_DQM7 E7 A9 M_DQM5 D3 DML VSS B3
M_DQM6 D3 DML VSS B3 DMU VSS E1
DMU VSS E1 VSS G8
VSS G8 M_DQS#4 G3 VSS J2
M_DQS#7 G3 VSS J2 M_DQS#5 B7 DQSL VSS J8
M_DQS#6 B7 DQSL VSS J8 DQSU VSS M1
DQSU VSS M1 VSS M9
VSS M9 VSS P1
VSS P1 DRAM_RST T2 VSS P9
DRAM_RST T2 VSS P9 RESET VSS T1
[23,24] DRAM_RST RESET VSS VSS
T1 L8 T9
L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS
1
J1 B1
NC/ODT1 VSSQ
1
J1 B1 PX@ L1 B9
PX@ L1 NC/ODT1 VSSQ B9 RV138 J9 NC/CS1 VSSQ D1
RV137 J9 NC/CS1 VSSQ D1 243_0402_1% L9 NC/CE1 VSSQ D8
243_0402_1% L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2
2
NCZQ1 VSSQ E2 VSSQ E8
SINGLE RANK:RV139,RV140 install 40.2 ohms
2
VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
VSSQ G1 VSSQ G9
VSSQ G9 VSSQ
VSSQ 96-BALL
96-BALL SDRAM DDR3
C SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 C
H5TC2G63FFR-11C_FBGA96 X76@
X76@
+1.35VGS +1.35VGS +1.35VGS

10U_0603_6.3V6M
CV128
1U_0402_6.3V6K
CV152
1U_0402_6.3V6K
CV158
1U_0402_6.3V6K
CV132
1U_0402_6.3V6K
CV164
0.1U_0201_10V7K
CV134
1U_0402_6.3V6K
CV135
1U_0402_6.3V6K
CV136
10U_0603_6.3V6M
CV138
10U_0603_6.3V6M
CV139
1U_0402_6.3V6K
CV141
1U_0402_6.3V6K
CV144
1U_0402_6.3V6K
CV145
1U_0402_6.3V6K
CV146
0.1U_0201_10V7K
CV147
1U_0402_6.3V6K
CV193
1U_0402_6.3V6K
CV148
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
D D

EXO/MESO_DDR3L_A2 Rank 0
Custom 0.1
1 2 3 4 5
5 4 3 2 1
W=60mils
LCD Power Circuit +3VS

Camera +3VS_CMOS
+3VS +LCDVDD_CONN
W=60mils U5 CMOS@
5 1 +LCDVDD_CONN_R 2 RS@ 1 +LCDVDD_CONN Q4
4.7U_0603_6.3V6K
IN OUT R271 0_0603_5% LP2301ALT1G_SOT23-3
2
C128
GND 1 W=20mils W=20mils
D
3 1
4 3 1 1
EN OC CMOS@
G524B1T11U SOT-23-5 2 C129 C130 @
G
2
D D
0.1U_0201_10V6K 10U_0603_6.3V6M
R119CMOS@ 2 2
150K_0402_5%
[5] PCH_ENVDD 4.7V
[34] CMOS_ON#
1
1
CMOS@
R120 C132
100K_0402_5% 0.1U_0201_10V6K
2 2
+3VS
5
U15
2
From PCH
P
[34,5] ENBKL B 4 DISPOFF#
1 Y
From EC [34] BKOFF# A
2
eDP CONN.
3
2
R124
C R211 U74AHC1G08G-AL5-R_SOT353-5 100K_0402_5% C
100K_0402_5%
1
+LEDVDD B+
1
RS@ R121
R123 1 2 0_0402_5% 0_0805_5%
1 RS@ 2
1
C133
4.7U_0805_25V6-K
2 @
JLVDS1
1
2 1 41
3 2 G1 42
RS@ 4 3 G2 43
R126 1 2 0_0402_5% EDP_HPD_R 5 4 G3 44
[5] EDP_HPD 5 G4
6 45
6 G5
1
7 46
[5] INVPWM 7 G6
DISPOFF# 8
R128 EDP_HPD_R 9 8
100K_0402_5% 10 9
W=60mils 11 10
+LCDVDD_CONN
2
12 11
13 12
eDP 14 13
C134 1 2 0.1U_0402_25V6 EDP_AUXN_C 15 14
[5] EDP_AUXN 15
C135 1 2 0.1U_0402_25V6 EDP_AUXP_C 16
[5] EDP_AUXP 17 16
C136 1 2 0.1U_0402_25V6 EDP_TXP0_C 18 17
[5] EDP_TXP0 18
C137 1 2 0.1U_0402_25V6 EDP_TXN0_C 19
[5] EDP_TXN0 20 19
EMI [5] EDP_TXP1

[5] EDP_TXN1
C138 1
C139 1
2 0.1U_0402_25V6
2 0.1U_0402_25V6
EDP_TXP1_C
EDP_TXN1_C
21
22
23
20
21
22
B
R125 2 RS@ 1 0_0402_5% R293 RS@ 1 2 0_0402_5% 24 23 B
[5] TS_Detect 25 24
Reserve T33 for Presence Detect [5] TS_INT#
26 25
[10] I2C_1_SDA 27 26
L6 @EMI@
[10] I2C_1_SCL 27
4 3 USB20_N5_R 28
[11] USB20_N5 28
USB20_P8_R 29
Touch Screen USB20_N8_R 30 29
Camera 1 2 USB20_P5_R 31 30
[11] USB20_P5 31
R122 RS@ 1 2 0_0402_5% TS_RST# 32
[34] TS_DISABLE# 32
HCM1012GH900BP_4P +3VS R270 RS@ 2 1 0_0603_5% +3VS_TS 33
34 33
+3VS_CMOS 34
R127 2 RS@ 1 0_0402_5% USB20_N5_R 35
USB20_P5_R 36 35
37 36
Camera 38 37
DMIC [38] DMIC_CLK
39 38
[38] DMIC_DAT 40 39
+3VS 40
R129 2 RS@ 1 0_0402_5%
E-T_0871K-F40N-00L
ME@
L7 @EMI@ 1 1 SP010011Z00
1 2 USB20_N8_R TS@ TS@
[11] USB20_N8
C242 C243
Touch Screen 0.1U_0201_10V6K 10U_0603_6.3V6M
4 3 USB20_P8_R 2 2
[11] USB20_P8
HCM1012GH900BP_4P
R130 2 RS@ 1 0_0402_5%

Close JLVDS1
A +3VS_TS A
R4452 1 2 100K_0402_5% TS_INT#

LVDS/CAMERA
C 0.1
5 4 3 2 1
5 4 3 2 1
For NoDocking
Near JHDMI1
EMI
For Docking Near JHDMI1
C229
0_0402_5% R1650 1 EMI@ 2 8.2_0402_1%
Docking@
C230 HCM1012GH900BP_4P
1
0_0402_5% [36] HDMI_CLK+_CK C229 1 2 0.1U_0402_25V6 HDMI_CLK+_CK_C 4 3 HDMI_CLK+_CONN
Docking@ R1008
NoDocking@ 150_0402_1%
[36] HDMI_CLK-_CK C230 1 2 0.1U_0402_25V6 HDMI_CLK-_CK_C 1 2 HDMI_CLK-_CONN EMI@
C231 For NoDocking For CRT and HDMI
2
0_0402_5% NoDocking@ L8 @EMI@
D D
Docking@ 1 2
C232 R1651 EMI@ 8.2_0402_1% +3VS
0_0402_5%
Docking@
R1652 1 EMI@ 2 8.2_0402_1%
2
+5V_Display
C233 HCM1012GH900BP_4P R133 U6
1
0_0402_5% [36] HDMI_TX0+_CK C231 1 2 0.1U_0402_25V6 HDMI_TX0+_CK_C 4 3 HDMI_TX0+_CONN 1M_0402_5% Q5 W=40mils
Docking@ R1009 NoDocking@ NoDocking@ +5VS 3
OUT
2
G
C234 NoDocking@ 150_0402_1% 2N7002H_SOT23-3 1
1
0_0402_5% [36] HDMI_TX0-_CK C232 1 2 0.1U_0402_25V6 HDMI_TX0-_CK_C 1 2 HDMI_TX0-_CONN EMI@ 1 C140
Docking@ 3 1 HDMI_DET IN
[36,5] TMDS_B_HPD 1
2
NoDocking@ L9 @EMI@ C141 2 0.1U_0201_10V6K
D
GND
2
1 2 2
C235 R1653 EMI@ 8.2_0402_1% R137 0.1U_0201_10V6K
0_0402_5% 2 AP2330W-7_SC59-3
20K_0402_5%
Docking@ NoDocking@
C236 R1654 1 EMI@ 2 8.2_0402_1%
1
0_0402_5%
Docking@ HCM1012GH900BP_4P
1
[36] HDMI_TX1+_CK C233 1 2 0.1U_0402_25V6 HDMI_TX1+_CK_C 4 3 HDMI_TX1+_CONN
R1010
NoDocking@ 150_0402_1%
[36] HDMI_TX1-_CK C234 1 2 0.1U_0402_25V6 HDMI_TX1-_CK_C 1 2 HDMI_TX1-_CONN EMI@
2
NoDocking@ L10 @EMI@
1 2
R1655 EMI@ 8.2_0402_1%
JHDMI1 ZZZ 45@

R1656 1 EMI@ 2 8.2_0402_1% HDMI_DET 19
[36] HDMI_DET 18 HP_DET
HCM1012GH900BP_4P +5V_Display +5V
For Docking 17
DDC/CEC_GND
1
[36] HDMI_TX2+_CK C235 1 2 0.1U_0402_25V6 HDMI_TX2+_CK_C 4 3 HDMI_TX2+_CONN HDMIDAT_R 16
R1011 HDMICLK_R 15 SDA
NoDocking@ 150_0402_1% 14 SCL
Reserved HDMI Logo
[36] HDMI_TX2-_CK C236 1 2 0.1U_0402_25V6 HDMI_TX2-_CK_C 1 2 HDMI_TX2-_CONN EMI@ 13
HDMI_CLK-_CONN 12 CEC 20 RO0000003HM
C C
2
NoDocking@ L11 @EMI@ 11 CK- G1 21
1 2 HDMI_CLK+_CONN 10 CK_shield G2 22
R1657 EMI@ 8.2_0402_1% HDMI_TX0-_CONN 9 CK+ G3 23
8 D0- G4
HDMI_TX0+_CONN 7 D0_shield
HDMI_TX1-_CONN 6 D0+
5 D1-
HDMI_TX2-_CONN 3 D1+
2 D2-
D2+
For NoDocking For NoDocking CONCR_099ATAC19NBLCNF
+3VS ME@
+3VS DC232001K00
R143 1NoDocking@2 2.2K_0402_5% HDMIDAT_NB

Q6A
R144 1NoDocking@2 2.2K_0402_5% HDMICLK_NB NoDocking@
2
L2N7002DW1T1G 2N SC88-6 For NoDocking

[36,5] HDMICLK_NB 1 6 HDMICLK_R
For Docking RP29
5
HDMI_TX1+_CK_C 5 4
HDMI_TX1-_CK_C 6 3
R143 4 3 HDMIDAT_R HDMI_CLK+_CK_C 7 2
[36,5] HDMIDAT_NB
10K_0402_5% HDMI_CLK-_CK_C 8 1
Docking@ Q6B
R144 NoDocking@ 470 +-5% 8P4R
10K_0402_5% L2N7002DW1T1G 2N SC88-6 NoDocking@
Docking@
RP30
HDMI_TX0+_CK_C 5 4
HDMI_TX0-_CK_C 6 3
+5V_Display For Docking HDMI_TX2+_CK_C 7 2
HDMI_TX2-_CK_C 8 1
R145 1 2 2.2K_0402_5% HDMIDAT_R [36] HDMICLK_R
B B
[36] HDMIDAT_R 470 +-5% 8P4R
R146 1 2 2.2K_0402_5% HDMICLK_R NoDocking@
+3VS
1
D
2
ESD S
G
Q7
3
NoDocking@
E14@ D1 E14@ D2 E14@ D3 2N7002H_SOT23-3
HDMIDAT_R 9 10 1 1 HDMIDAT_R HDMI_CLK-_CONN 9 10 1 1 HDMI_CLK-_CONN HDMI_TX0+_CONN 9 10 1 1 HDMI_TX0+_CONN
HDMICLK_R 8 9 2 2 HDMICLK_R HDMI_CLK+_CONN 8 9 2 2 HDMI_CLK+_CONN HDMI_TX0-_CONN 8 9 2 2 HDMI_TX0-_CONN
HDMI_DET 7 7 4 4 HDMI_DET HDMI_TX1-_CONN 7 7 4 4 HDMI_TX1-_CONN HDMI_TX2+_CONN 7 7 4 4 HDMI_TX2+_CONN
6 6 5 5 HDMI_TX1+_CONN 6 6 5 5 HDMI_TX1+_CONN HDMI_TX2-_CONN 6 6 5 5 HDMI_TX2-_CONN
3 3 3 3 3 3
8 8 8
L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD
D1 D2 D3
SC300002C00 SC300002C00 SC300002C00
S DIO(BR) L05ESDL5V0NA-4 SLP2510P8 ESD S DIO(BR) L05ESDL5V0NA-4 SLP2510P8 ESD S DIO(BR) L05ESDL5V0NA-4 SLP2510P8 ESD
E15@ E15@ E15@
A A

HDMI CONN
C 0.1
5 4 3 2 1
5 4 3 2 1
D +3VS_CRT D
1
@ RT24
100K_0402_5%
2
DDI1_AUX_C_DN
DDI1_AUX_C_DP
1
+3VS
@ RT23 CRT_R
100K_0402_5% RT19 2 1 +3VS_CRT
BLM15BD121SN1D_0402 CRT_G
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
2
2 2 2 2
CRT_B
CT4
8
7
6
5
10U_0603_6.3V6M
1 1 1 1 RP50 +5VS RT3
CT1
CT2
CT3
75_0804_8P4R_1%
1 RS@ 2
1
1
2
3
4
@ 0_0402_5%
CT5
20
U10 0.1U_0201_10V6K
9
2
1
DVCC_33
DVCC_33
VDD_DAC_33
DDI1_HPD RT5 1 RS@ 2 0_0402_5% VGA_HPD_R 1 @
OE#
P
[5] DDI1_HPD HPD VSYNC 2 4 CRT_VSYNC_1 RT4 1 @ 2 36_0402_1% CRT_VSYNC_2
A Y
1
CT9 2 1 0.1U_0201_10V6K DDI1_AUX_C_DN 27 6 CRT_DATA

[5] DDI1_AUX_DN AUX_N VGA_SDA
G
[5] DDI1_AUX_DP CT6 2 1 0.1U_0201_10V6K DDI1_AUX_C_DP 26 4 CRT_CLK UT1 1
RT2 AUX_P VGA_SCL 8 HSYNC SN74AHCT1G125DCKR_SC70-5
3
100K_0402_5% CT7 2 1 0.1U_0201_10V6K CPU_DP1_C_P0 29 HSYNC 7 VSYNC @ CT10
[5] CPU_DP1_P0 LANE0P VSYNC
C CT11 2 1 0.1U_0201_10V6K CPU_DP1_C_N0 30 10P_0402_50V8J C
[5] CPU_DP1_N0
2
LANE0N 15 CRT_R 2
CT8 2 1 0.1U_0201_10V6K CPU_DP1_C_P1 31 RED_P RT6 1 2 36_0402_1%
[5] CPU_DP1_P1 LANE1P
CT12 2 1 0.1U_0201_10V6K CPU_DP1_C_N1 32 12 CRT_G
[5] CPU_DP1_N1 LANE1N GREEN_P
+3VS RT20 RS@ 1 2 0_0402_5% 10 CRT_B
BLUE_P
22 POL1_SDA
CT13 2 1 2.2U_0402_6.3V6M POL1_SDA 23 POL2_SCL
POL2_SCL
CT14 2 1 0.1U_0201_10V6K VCCK_12 19 2 RT21 1 @ 2 0_0402_5%
VCCK_12 SMB_SCL 3 EC_SMB_CK2 [20,31,34,7]
RT22 1 @ 2 0_0402_5% +5VS RT7
SMB_SDA EC_SMB_DA2 [20,31,34,7]
CT15 2 1 0.1U_0201_10V6K AVCC_33 24
AVCC_33 1 RS@ 2
CT16 2 1 0.1U_0201_10V6K VCCK_12 25 1
AVCC_12 21 LDO_EN @ 0_0402_5%
RT8 1 2 12K_0402_1% 28 LDO_EN CT17
RRX
0.1U_0201_10V6K
18 2
XO
1
11 @
13 BLUE_N 17
OE#
P
14 GREEN_N XI/CKIN HSYNC 2 4 CRT_HSYNC_1 RT9 1 @ 2 36_0402_1% CRT_HSYNC_2
16 GND_DAC A Y
RED_N
G
33 UT2
EPAD_GND SN74AHCT1G125DCKR_SC70-5 1
3
@
2 CT18
RTD2168-CG_QFN32_5X5 10P_0402_50V8J
CT19 RT10 1 2 36_0402_1% 2
10U_0603_6.3V6M
1
+3VS +3VS +3VS

4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1
1
B B
RT13
RT11
@RT12
+5V_Display
2
1 2.2K_0402_5%
1 2.2K_0402_5%
POL2_SCL POL1_SDA LDO_EN
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1
1
@RT16
@RT14
RT15
2
2
+5V_Display
CRT
RT17
RT18
ESD EMI L42 EMI@ 6
JCRT1
DT1 DT2 BLM15BA220SN1D 0402 11

SC300001G00 SC300001G00 CRT_R 1 2 CRT_R_2 1
+5VS S DIO(BR) AZC099-04S.R7G SOT23 ESD S DIO(BR) AZC099-04S.R7G SOT23 ESD L45 EMI@ 7
E15@ E15@ BLM15BA220SN1D 0402 CRT_DATA 12
CRT_G 1 2 CRT_G_2 2
DT1 E14@ L46 EMI@ 8
CRT_HSYNC_2 6 3 CRT_DATA BLM15BA220SN1D 0402 CRT_HSYNC_2 13
I/O4 I/O2 CRT_B 1 2 CRT_B_2 3
9
10P_0402_50V8J
EMI@ C648
10P_0402_50V8J
EMI@ C615
10P_0402_50V8J
EMI@ C611
10P_0402_50V8J
EMI@ C647
10P_0402_50V8J
EMI@ C618
10P_0402_50V8J
EMI@ C616
CRT_VSYNC_2 14 16
G
5 2 1 1 1 1 1 1 4 17
VDD GND G
10
CRT_CLK 15
5
A CRT_VSYNC_2 4 1 CRT_CLK 2 2 2 2 2 2 A
I/O3 I/O1 C-H_13-12201557CP
AZC099-04S.R7G_SOT23-6 DC060006G00
ME@
+5VS DT2 E14@
CRT_R_2 6 3 CRT_B_2
I/O4 I/O2
5 2
VDD GND
CRT_G_2 4 1
I/O3 I/O1
CRT
AZC099-04S.R7G_SOT23-6 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
5 4 3 2 1
A B C D E F G H
HDD
SATA HDD Conn.
Near Connector
JHDD1
1
0.01U_0402_16V7K 2 1 C142 SATA_CTX_C_DRX_P0 2 GND
[11] SATA_CTX_DRX_P0 RX+
[11] SATA_CTX_DRX_N0 0.01U_0402_16V7K 2 1 C143 SATA_CTX_C_DRX_N0 3
4 RX-
C144 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_N0 5 GND
[11] SATA_CRX_DTX_N0 C145 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_P0 6 TX-
[11] SATA_CRX_DTX_P0 7 TX+
GND
1 1
8
R141 2 RS@ 1 0_0603_5% +3V_HDD 9 3.3V
+3VS 3.3V
10
11 3.3V
12 GND
13 GND
14 GND
R142 1 RS@ 2 0_0805_5% +5V_HDD 15 5V
+5VS 16 5V
17 5V
18 GND 23
19 Reserved GND1 24
Near HDD 20 GND GND2
21 12V
1 12V
+5V_HDD C199 22
@ESD@ 12V
0.1U_0201_10V6K ALLTO_C166KH-122H9-L
2 ME@
1 1 1
@ SP011310171
2
C146
1000P_0402_50V7K
2
C147
0.1U_0201_10V6K
2
C148
10U_0603_6.3V6M ESD
ODD
2 2
FOR 15"
SATA ODD FFC Conn.
JODD1
1
2 1
[11] SATA_CTX_DRX_P1 2
3
[11] SATA_CTX_DRX_N1 3
4
5 4
[11] SATA_CRX_DTX_N1 6 5
[11] SATA_CRX_DTX_P1 SATA_ODD_PRSNT_R 7 6
+5V_ODD 8 7
9 8
ODD_DA#_R 10 9
+5VS +5V_ODD 10 11
GND 12
JP5 GND
1 2 ACES_88058-100N
+5VALW 1 2 ME@
JUMP_43X39 SP010016C00
@
1
@
S
R149 3 1
10K_0402_5%
3 3
@ Q8 C151 C153
2
R150 LP2301ALT1G_SOT23-3 E14@ E14@

G
2
100K_0402_5% @ 0.01U_0402_16V7K 0.01U_0402_16V7K

1 2 C152 C154 FOR 14"
1 1 E14@ E14@
SATA ODD Conn.
1
0.01U_0402_16V7K 0.01U_0402_16V7K
C149 C150
OUT
0.01U_0402_16V7K 10U_0603_6.3V6M Near Connector

2 @ 2 JODD2
2
[10] ODD_EN IN 1
GND
SATA_CTX_DRX_P1 B14@ C151 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_P1_14 2 GND

Q9 SATA_CTX_DRX_N1 B14@ C152 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_N1_14 3 A+
DRC2124E0L NPN MINI3-G3-B 4 A-
3
@ SATA_CRX_DTX_N1 B14@ C153 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_N1_14 5 GND

SATA_CRX_DTX_P1 B14@ C154 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_P1_14 6 B-
7 B+
GND
R151 1 @ 2 0_0402_5% SATA_ODD_PRSNT_R 8

[11] SATA_ODD_PRSNT +5V_ODD 9 DP
10 +5V
R152 1 @ 2 0_0402_5% ODD_DA#_R 11 +5V
[11] ODD_DA# 12 MD 15
13 GND GND 14
GND GND
ALLTO_C185S1-113H9-L
ME@
SP011312061
4 4

HDD/ODD/BT Connector
C 0.1
A B C D E F G H
A B C D E
+3VS +3VS_WLAN
NGFF for WLAN / BT(Key E) R153 1 RS@ 2 0_0603_5%
Support ISCT(Intel Smart Connect Technology)
1 1
+3VS_WLAN C155
C156
JWLAN1 4.7U_0603_6.3V6K @ 0.1U_0201_10V6K
1 2 2 1
1 2
3 GND 3.3VAUX 4
[11] USB20_P7 USB_D+ 3.3VAUX
BT 5 6
[11] USB20_N7 7 USB_D- LED1# 8
9 GND PCM_CLK 10
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_WAKE# 22 R175 1 @ 2 0_0402_5%
23 SDIO_WAKE# UART_RX UART_2_CTXD_DRXD [10]
SDIO_RESET#
24 R176 1 @ 2 0_0402_5%
25 UART_TX 26 UART_2_CRXD_DTXD [10]
CC31 1 2 0.1U_0402_25V6 PCIE_CTX_C_DRX_P6 27 GND UART_CTS 28
[11] PCIE_CTX_DRX_P6 1 2 0.1U_0402_25V6 29 PETP0 UART_RTS 30
CC98 PCIE_CTX_C_DRX_N6 R155 1 2 0_0402_5%
[11] PCIE_CTX_DRX_N6 PETN0 RESERVED EC_TX [32,34]
31 32 R156 1 2 0_0402_5%
GND RESERVED EC_RX [32,34]
33 34
[11] PCIE_CRX_DTX_P6 35 PERP0 RESERVED 36
WLAN [11] PCIE_CRX_DTX_N6
37 PERN0 COEX3 38
39 GND COEX2 40
[9] CLK_PCIE_WLAN REFCLKP0 COEX1
41 42 SUSCLK_R R157 1 2 RS@ 0_0402_5%
[9] CLK_PCIE_WLAN# REFCLKN0 SUSCLK SUSCLK [9]
43 44 WL_RST#
R158 RS@ 1 2 0_0402_5% WLANCLK_REQ#_R 45 GND PERST0# 46 BT_DISABLE_R R159 1 2 RS@ 0_0402_5%
[9] WLANCLK_REQ# CLKEQ0# W_DISABLE2# WLBT_OFF# [10]
For ISCT [34,37] PCIE_WAKE# R162 RS@ 1 2 0_0402_5% WAKE#_R 47 48 R161 1 2 RS@ 0_0402_5%
49 PEWAKE0# W_DISABLE1# 50 EC_WL_OFF# [34]
51 GND I2C_DATA 52
53 RSRVD/PETP1 I2C_CLK 54
55 RSRVD/PETN1 ALERT 56
Note: The real behavior of BT_DISABLE are
57 GND RESERVED 58 BT_DISABLE=LOW, BT=OFF
59 RSRVD/PERP1 RESERVED 60 BT_DISABLE=HIGH, BT=ON
61 RSRVD/PERN1 RESERVED 62
63 GND RESERVED 64
65 RESERVED 3.3VAUX 66
67 RESERVED 3.3VAUX
2 2
GND
69 68
MTG77 MTG76
LCN_DAN05-67306-0102
ME@
SP070013F00
2
R507 WL_RST# R164 1 2 RS@ 0_0402_5% PCIRST# [19,31,34,37,39,9]
100K_0402_5%
1
NFC Conn
3 3
JNFC1
1
R1214 1 NFC@ 2 0_0402_5% +1.8VS_NFC 2 1
+1.8VS 2
3
4 3
NFC_DWL_REQ 5 4
[7] NFC_DWL_REQ 5
R1156 1 NFC@ 2 0_0402_5% VEN 6
[10] NFC_EN 7 6
I2C_0_SCL 8 7
[10] I2C_0_SCL 9 8
I2C_0_SDA
[10] I2C_0_SDA 9
10
R1159 1 NFC@ 2 0_0402_5% IRQ 11 10
[11] NFC_INT 11
+5VS R1160 1 NFC@ 2 0_0402_5% +5VS_NFC 12
13 12
14 13
R1161 1 NFC@ 2 0_0402_5% +3VS_NFC 15 14
+3VS 15
1 16
NFC@ GND 17
C2530 GND
10U_0603_6.3V6M E-T_6710K-Y15M-31L
2 ME@
4 4
2011/06/24
Compal Secret Data
2012/07/12 Title
Mini-Card/NEW Card/SIM
0.1
A B C D E
5 4 3 2 1
2 Channel +3VS +3VGS
2
@ @
R182 R181
0_0402_5% 0_0402_5%
1
+3V_Thermal
1
SMSC thermal sensor
D
C329
placed near JWLAN1 D
0.1U_0201_10V6K @ @
2 U17
1 8 EC_SMB_CK2
[20] REMOTE1+ VDD SCLK EC_SMB_CK2 [20,28,34,7]
1
@ REMOTE1+ 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 [20,28,34,7]
GPU C251
2200P_0402_50V7K REMOTE1- 3 6 THM_ALERT#
2 D- ALERT# THM_ALERT# [20]
[20] REMOTE1-
THERM# 4 5
THERM# GND
EMC1402-2-ACZL-TR MSOP 8P
Placed near U17 Address is 1001100xb
1 @ 2
+3V_Thermal
R183 10K_0402_5%
+5VS
FAN Conn
R168 JFAN1
1 RS@ 2 +FAN 1
2 1
C C
[34] FAN_SPEED1 3 2
0_0603_5% [34] EC_FAN_PWM1
4 3
5 4
2 G5
6
C162 G6
10U_0603_6.3V6M ACES_85205-04001
1 ME@
SP020008X00
CPU VGA NGFF NPTH Battery BD

H1 H2 H3 H17 H14 H15 H5 H13 H22 H23 H24 H8 H9
B B
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
H_2P6N H_2P6X4P0N H_2P6X4P0N H_2P0N
H_4P0 H_4P0 H_4P0 H_4P0 H_3P3 H_3P3 H_3P2 H_3P3 H_3P3
+3VS
TPM H10 H6 H18 H7 H20 H11 H21 H16 H19 H12 H25
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1 1 1
C297 C298 C299
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
TPM@ TPM@ TPM@
1
U24 TPM@ 2 2 2
LANGAN
1 24 H_2P8X4P6 H_2P8X5P1 H_2P8X4P8 H_2P5 H_2P5 H_2P8 H_2P8 H_3P3 H_6P0 H_2P8 H_2P8
2 NC 3V 10
3 NC 3V 19
7 NC 3V
PP 22 LPC_FRAME#
LFRAME# LPC_FRAME# [34,7]
6 28
9 NC LPCPD# FD1 FD2 FD3 FD4
NC 21
4 LCLK 27 CK_LPC_TPM [7]
GND SIRQ SERIRQ [34,7]
11
1
1
18 GND 26 LPC_AD0
25 GND LAD0 23 LPC_AD0 [34,7]
LPC_AD1
GND LAD1 LPC_AD1 [34,7]
20 LPC_AD2
5 LAD2 17 LPC_AD2 [34,7]
LPC_AD3
NC LAD3 LPC_AD3 [34,7]
8
12 NC 15
13 NC CLKRUN# 16 PCIRST#
NC LRESET# PCIRST# [19,30,34,37,39,9]
A 14 A
NC
Z32H320TC-LPC-T28-233_TSSOP28
SA00007YP00

Fintek-Thermal IC/FAN/screw
C 0.1
5 4 3 2 1
KB For B15/E15 KB For B14/E14
JKB2 JKB1
KSI[0..7] KSI1 1 KSI1 1
For Debug KSO[0..15]
KSI[0..7] [34]
KSI7
KSI6
2
3
1
2
KSI7
KSI6
2
3
1
2
KSO[0..15] [34] 4 3 4 3
KSO9 KSO9
JP3 +3VALW +3VALW +3VLP KSI4 5 4 KSI4 5 4
1 KSI5 6 5 KSI5 6 5
+3VALW 1 6 6
2 KSO0 7 KSO0 7
[30,34] EC_TX 2 7 7
2
3 KSI2 8 KSI2 8
[30,34] EC_RX 4 3 9 8 9 8
@ KSI3 KSI3
4 R274 R170 JPWRB1 KSO5 10 9 KSO5 10 9
ACES_85205-0400 100K_0402_5% 100K_0402_5% 1 KSO1 11 10 KSO1 11 10
2 1 KSI0 12 11 KSI0 12 11
ME@
1
PWR_LED# 3 2 KSO2 13 12 KSO2 13 12
ON/OFF# 4 3 R263 KSO4 14 13 KSO4 14 13
[34,35] ON/OFF# 4 14 14
5 470_0402_5% KSO7 15 KSO7 15
LID_SW# 6 5 KSO8 16 15 KSO8 16 15
[34] LID_SW# 6 E15@ 16 16
KSO6 17 KSO6 17
J11: TOP 7 R264 KSO3 18 17 KSO3 18 17
J12: BOT 8 GND 470_0402_5% KSO12 19 18 KSO12 19 18
J1 GND 19 19
E15@ KSO13 20 KSO13 20
20 20
2
1 2 ACES_88058-060N +3VS KSO14 21 KSO14 21
ESD@ ESD@ ME@ R263 KSO11 22 21 KSO11 22 21
SHORT PADS D24 D26 SP010010T00 470_0402_5% KSO10 23 22 KSO10 23 22
MESC5V02BD03 3P C/A SOT23 ESD
MESC5V02BD03 3P C/A SOT23 ESD KSO15 24 23 KSO15 24 23
J2 B14@ 24 24
KSO16 25 CAPS_LED#_R 25
1 2 [34] KSO16 26 25 26 25
ON/OFF# KSO17 CAPS_LED#
[34] KSO17
1
R263 2 B15@ 1 470_0402_5% CAPS_LED#_R 27 26 26 27
SHORT PADS 28 27 GND2 28
[34] CAPS_LED# 28 GND1
R264 2 B15@ 1 470_0402_5% NUM_LED#_R 29 31
30 29 GND 32
ESD [34] NUM_LED#
1 1 1 1
30
ACES_88514-3001
GND ACES_88514-02601-071
ME@
ESD C201 @ESD@ B15@ B15@ @ESD@ ME@ SP01000R500
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K C200 C201 C202 C203 SP010011A00
LED1
For B15/E14/E15 E15@
C202
2 2 2 2
C202
SC50000DN00
S LED 19-21/G6C-BM2P1B/3T 0603 YEL GREEN
0.1U_0201_10V6K 0.1U_0201_10V6K E15@
RP33 E15@ B14@ R171
0_0804_8P4R_5% E14@ 100_0402_5%
E15@ LED1 E14@ E15@
R171
RS@ RP34 PWR_LED# 1 2 1 2
R258 1 2 0_0402_5% 0_0804_8P4R_5%
Power (Green) [34] PWR_LED#
100_0402_5%
+3VALW
+3VS (E14/E15)
E15@
LTST-C190KGKT 0603 GRN
+5VS R259 1 @ 2 0_0402_5% RP33 SC50000DN00
0_0804_8P4R_5%
1 E14@
C163 RP34
@ 0.1U_0201_10V6K 0_0804_8P4R_5%
2 LED2
E14@
R172
Battery (Amber) [34] BATT_LOW_LED# BATT_LOW_LED# 1 2 1 2 +3VLP
RP33 JTP1 620_0402_5%
TP_VCC 1 8 B15_VCC_B14_R 1 (B14/B15/E14/E15)
TP_CLK 2 7 B15_CLK_B14_L 2 1 19-217/S2C-FM2P1VY/3T 0603 ORANGE
[34] TP_CLK 3 6 3 2
TP_DATA B15_DATA_B14_GND SC500005T00 R173
[34] TP_DATA 3
1 1 4 5 4 100_0402_5%
@ @ 5 4 R294 1 @ 2 0_0402_5% R173
5 E14@
C164 C165 0_0804_8P4R_5% 6 100_0402_5%
100P_0402_50V8J 100P_0402_50V8J B15@ 6 R173
2 2 E15@
7 330_0402_5%
GND
3
RP34 8 LED3 B14@ B15@

1 8 B15_GND_B14_DATA GND R173
@ESD@ 2 7 B15_L_B14_CLK ACES_88058-060N Battery (Green) [34] BATT_CHG_LED# BATT_CHG_LED# R295 1 2 0_0402_5% 1 2 1 2 +3VLP
D5 3 6 B15_R_B14_VCC ME@ RS@ 330_0402_5%
PSOT24C_SOT23-3 TP_L 4 5 SP010010T00 (B14/B15/E14/E15)
TP_R LTST-C190KGKT 0603 GRN
1
0_0804_8P4R_5% SC50000DN00 R174

B15@ 100_0402_5%
C166
C167
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 R174 E14@
100_0402_5%
E15@ R174
ESD @
2
@
2
For B14 LED4 B14@
R174
B15@
330_0402_5%
PCH_SATALED# 1 2 1 2
RP35
HDD (Green) [11] PCH_SATALED#
330_0402_5%
+3VS
TP_VCC 1 8 B15_R_B14_VCC (B14/B15/E14/E15)
TP_CLK 2 7 B15_L_B14_CLK LTST-C190KGKT 0603 GRN
TP_DATA 3 6 B15_GND_B14_DATA SC50000DN00
4 5
0_0804_8P4R_5%
B14@
1
RP36
8 B15_DATA_B14_GND
DC-In LED (Green) For B14 / E14
For B15/E14/E15 TP module(100*50) For B14 TP module(84*42) TP_L 2 7 B15_CLK_B14_L
TP_R 3 6 B15_VCC_B14_R +3VLP
4 5
1 1 VCC 1 VCC 6 1 VCC 1 VCC DC_LED R20 1 2 0_0402_5% DC_LED_Power
0_0804_8P4R_5% RS@ JLED1
B14@ 1
2 2 CLK 2 CLK 5 2 CLK 2 CLK 2 1
2
1
D 3 5
[35] DC_LED 3 G1
R298 1 2 0_0402_5% 2 Q20 4 6
3 3 DAT 3 DAT 4 3 DAT 3 DAT [20,34,43,9] VCIN1_AC_IN
G L2N7002LT1G SOT23-3 4 G2
S ACES_51512-0040N-P01
3
ME@
4 4 GND 4 L 3 4 GND 4 L SP01001J100
5 5 L 5 R 2 5 L 5 R
6 6 R 6 GND 1 6 R 6 GND
RS@ B15@
+3VALW R278 1 2 0_0402_5% +VCC_LID 1 R279 2
100K_0402_5% U16
TCS20DLR SOT-23F 3P
1 E15@
C198
2
@ESD@ C248
0.1U_0201_10V6K 1 0.1U_0201_10V6K
VDD
2 B15@ E15@
0.1U_0201_10V6K
C248
ESD 2 OUTPUT
3 LID_SW# R279
100K_0402_5%
E15@
GND
L L R R 2
B15@
C249
C249
10P_0402_50V8J
1
B15@ 10P_0402_50V8J E15@
B15@ E14@ SW3 B15@ SW2 E14@ U16 1
SW1 SW3 SMT1-05_4P SW2 SMT1-05_4P SW4
SMT1-05_4P SMT1-05_4P B14@ SMT1-05_4P B14@ SMT1-05_4P
5
6
5
6
5
6
5
6
TCS20DLR SOT-23F 3P
4 2 4 2 4 2 SW2 4 2
TP_L TP_L TP_R SMT1-05_4P TP_R
3 1 3 1 3 1 3 1
E15@
SW1
SMT1-05_4P
2011/06/24 2012/07/12 Title
E15@
Issued Date Deciphered Date ROM/KBD/PWR/CR/LED/TP Conn.
C 0.1
5 4 3 2 1
+3VS
ESD
Finger Print [11] USB20_P6
R291 1
RS@
2 0_0402_5% +3VS_FP 1
2
JFP1
1 U3RXDP1 8
E14@
U3RXDN1 9 10
9
D6
1 1 U3RXDN1
2 2 U3RXDP1 U3RXDP2 8
E14@
U3RXDN2 9 10
9
D7
1 1U3RXDN2
2 2U3RXDP2
U2DP1 3
E14@
I/O2 I/O4
D8
6 U2DP2 3
E14@
I/O2
D9
I/O4
6
3 2
Finger Print [11] USB20_N6
4 3 U3TXDN1 7 4 U3TXDN1 U3TXDN2 7 4U3TXDN2 2 5 2 5
7 4 7 4 +USB3_VCCA +USB3_VCCA
(For B14/E14/B15) 5 4 GND VDD GND VDD
6 5 U3TXDP1 6 5 U3TXDP1 U3TXDP2 6 5U3TXDP2
6 5 6 5
6
2
1 7 3 3 3 3 1 4 U2DN1 1 4 U2DN2
FP@ FP@ 8 GND I/O1 I/O3 I/O1 I/O3
D25 C247 GND 8 8
AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
0.1U_0201_10V6K
MESC5V02BD03 3P C/A SOT23 ESD ACES_88058-060N
2 ME@
1
D
SP010010T00 L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD D
D6 D7 D8 D9
SC300002C00 SC300002C00 SC300001G00 SC300001G00
ESD S DIO(BR) L05ESDL5V0NA-4 SLP2510P8 ESD

E15@
S DIO(BR) L05ESDL5V0NA-4 SLP2510P8 ESD
E15@
S DIO(BR) AZC099-04S.R7G SOT23 ESD
E15@
E15@
Intel_PCH_USB2.0
EMI R193
2 @EMI@ 1
0_0402_5%
L12 EMI@
USB3.0_Port [11] USB20_N2

4
1
3
2
U2DN2
U2DP2
For B14 / B15 [11] USB20_P2
USB2.0_Port
+3VALW +3VLP
MCM1012B900F06BP_4P
2
100K_0402_5%
100K_0402_5%
2 @EMI@ 1
@ R191 0_0402_5%
EMI R275 R169 +USB_VCCB
R196
2 RS@ 1
0_0402_5%
Left USB CONN
W=80mils Intel_PCH_USB3.0
1
R177 2 @EMI@ 1 0_0402_5% L13 @EMI@ +USB3_VCCA
JIO1 4 3 U3RXDN2
[11] USB3_RX_N2
12 14 W=80mils
[38] HGNDB 12 G2 13
L14 EMI@ 11
[38] HGNDA 11 G1
1 2 USB20_N4_R 10 1 2 U3RXDP2 JUSB1
[11] USB20_N4 [38] HPOUT_L 10 [11] USB3_RX_P2
9 U3TXDP2 9
8 9 HCM1012GH900BP_4P 1 SSTX+
Right USB2__I/O Port 4 3 USB20_P4_R
[38] HPOUT_R
7 8 U3TXDN2 8 VBUS
[11] USB20_P4 [38] PLUG_IN 7 SSTX-
6 2 RS@ 1 U2DP2 3
MCM1012B900F06BP_4P USB20_N4_R 5 6 R195 0_0402_5% 7 D+
USB20_P4_R 4 5 2 RS@ 1 U2DN2 2 GND 10
R178 2 @EMI@ 1 0_0402_5%
Right USB2__I/O Port 3 4 R199 0_0402_5% U3RXDP2 6 D- GND 11
2 3 C168 USB3@ 4 SSRX+ GND 12
C 2 GND GND 13 C
1 0.1U_0402_25V6 L15 @EMI@ U3RXDN2 5
[34] NOVO# 1 SSRX- GND
1 2 U3TXDN2_L 4 3 U3TXDN2
[11] USB3_TX_N2
ACES_88058-120N J-L_TNBNRAC70010009
ME@ ME@
SP010015H00 1 2 U3TXDP2_L 1 2 U3TXDP2 DC23300ET10
[11] USB3_TX_P2
0.1U_0402_25V6 HCM1012GH900BP_4P
Near HDMI CONN.
C169 USB3@ (Debug Port)
2 RS@ 1
R197 0_0402_5%
+5VALW_USBCH +5VALW
+5VALW
2A/Active Low +USB_VCCB
R1183 @ 2 @EMI@ 1
2 1 W=80mils U8 W=80mils R215 0_0402_5%
1
Intel_PCH_USB2.0
VL 0_0603_5% 5 OUT L16 EMI@
IN 2 4 3 U2DN1
GND [11] USB20_N1
R1169 E14@ 4 R179
[34] USB_EN# EN
2 1 3 1 1 3 USB_OC1#_U8 1 @ 2 USB_OC1#
OCB
LP2301ALT1G_SOT23-3
1 Q2411 1 1 2 U2DP1
[11] USB20_P1
E14@ 0_0603_5% E14@ C2535 E14@ C195 SY6288D20AAC_SOT23-5 0_0402_5%
C2536 4.7U_0603_6.3V6K MCM1012B900F06BP_4P
2 1
4.7U_0603_6.3V6K 2 1 0.1U_0201_10V6K 1
2
2 D37 RB491D_SC59-3 2 + @ 2 @EMI@ 1

@ C170 C171 R200 0_0402_5%
VL
220U_6.3V_M
2 2
470P_0402_50V7K
R217
2 RS@ 1
0_0402_5%
Left USB CONN
R1173 E14@
Intel_PCH_USB3.0
1 2 L17 @EMI@ +USB3_VCCA
4 3 U3RXDN1
[11] USB3_RX_N1
100K_0402_5%
W=80mils
1 2 U3RXDP1 JUSB2
[11] USB3_RX_P1
1
D U3TXDP1 9
1 SSTX+
B
2 E14@ C2537 HCM1012GH900BP_4P 1 B
[34,44] EC_ON VBUS
G Q2412 0.1U_0201_10V6K U3TXDN1 8
2N7002H_SOT23-3 E14@ 2 RS@ 1 U2DP1 3 SSTX-
S
3
2 R216 0_0402_5% 7 D+
2 RS@ 1 U2DN1 2 GND 10
R220 0_0402_5% U3RXDP1 6 D- GND 11
C172 USB3@ 4 SSRX+ GND 12
0.1U_0402_25V6 L18 @EMI@ U3RXDN1 5 GND GND 13
1 2 U3TXDN1_L 4 3 U3TXDN1 SSRX- GND
+3VLP +5VALW_USBCH [11] USB3_TX_N1
AIVE3 no PU J-L_TNBNRAC70010009
+5V_CHGUSB ME@
1 2 U3TXDP1_L 1 2 U3TXDP1 DC23300ET10
[11] USB3_TX_P1
Near End User
1
+USB_VCCB 0.1U_0402_25V6 HCM1012GH900BP_4P

R1107 E14@ +5V_CHGUSB C173 USB3@
100K_0402_5% R1164 2 RS@ 1
E14@ 10K_0402_5% 80mil R218 0_0402_5%
U65 Place TX AC coupling Cap (C843~C850). Close to connector
2
R131 1
0_0805_5%
1 12 R3 1 E14@ 2 0_0805_5%
9 IN OUT 10 USB20_P3_C
[34] USB_CHG_STATUS#
[11] USB_OC1#
R1165 1 @ 2 0_0402_5% USB_OC1#_U65 13
4
STATUS#
FAULT#
DP_IN
DM_IN
11
2
USB20_N3_C @ For E14
5 ILIM_SEL DM_OUT 3
USB20_N3 [11] Right USB2__I/O Port
[34] USB_CHG_EN USB20_P3 [11] (For E14) W=100mils
2
6 EN DP_OUT 15 R1166 1 @ 2 20K_0402_1%
[34] USB_CHG_CTL1 CTL1 ILIM_LO +5VALW
2A/Active Low+USB3_VCCA
7 16 R1167 1 E14@ 2 16.5K_0402_1% JIO2
[34] USB_CHG_CTL2 CTL2 ILIM_HI
8 14 HGNDB 18 20 W=80mils U12 W=80mils
[34] USB_CHG_CTL3 CTL3 GND 18 G2 19
17 HGNDA 17 1
T-PAD 17 G1 OUT
1
E14@ HPOUT_L 16 5
C2534 TPS2546RTER QFN 16P 15 16 IN 2
0.1U_0201_10V6K E14@ HPOUT_R 14 15 USB_EN# 4 GND R185
2
PLUG_IN 13 14 EN 3 USB_OC0#_R 1 @ 2
13 OCB USB_OC0# [11]
12 1
11 12 C196 SY6288D20AAC_SOT23-5 0_0402_5%
USB20_N3_R 10 11
10 1
USB20_P3_R 9 0.1U_0201_10V6K
Right USB2__I/O Port 8 9 2 +
1
@
(For E14) 7 8 C178 C177
6 7 220U_6.3V_M 470P_0402_50V7K
EMI
A 6 A
5 2 2
USB20_N4_R 4 5
USB20_P4_R 3 4
R186 2 @EMI@ 1 0_0402_5%
Right USB2__I/O Port 2 3
NOVO# 1 2
USB20_P3_C 4
L19 E14@
3 USB20_P3_R
ESD 1
ACES_50505-0184N-001
ME@
3
SP010010X00
USB20_N3_C 1 2 USB20_N3_R @ESD@ Security Classification Compal Secret Data Compal Electronics, Inc.
D27 2011/06/24 2012/07/12 Title
MCM1012B900F06BP_4P MESC5V02BD03 3P C/A SOT23 ESD
USB3.0/Left USB Ports
1
R187 2 @EMI@ 1 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
5 4 3 2 1
+3VLP +EC_VCCA
+3VLP
L20
FBMA-L11-160808-601LMT_2P
1 2 1@
1 1 C179
C184 C185 100P_0402_50V8J
0.1U_0201_10V6K @ 1000P_0402_50V7K
2
1 2 2 ECAGND 2
L21 1 1 1 1
+EC_VCCA
0.1U_0201_10V6K
C180
0.1U_0201_10V6K
C181
1000P_0402_50V7K
C182
1000P_0402_50V7K
C183
FBMA-L11-160808-601LMT_2P
+5VALW
ECAGND 2 2 @ 2 @ 2
111
125
USB_EN# R194 1 2 10K_0402_5%
22
33
96
67
9
U11
VCC2
VCC3
VCC4
VCC1/LPC
VCC5/SPI
AVCC
VSBY
+3VS
1 21
GPIO85/GA20 GPIO15/A_PWM VCCST_PWRGD [40,9]
2 23 BEEP#
[7] KB_RST# GPIO86/KBRST# GPIO21/B_PWM BEEP# [38]
3 PWM Output 26
[31,7] SERIRQ 4 SERIRQ/GPIOF0 GPIO32/D_PWM 27 EC_FAN_PWM1 [31]
EC_VCIN1_AC_IN_R R222 1 @ 2 0_0402_5% EC_VCIN1_AC_IN
EMI [31,7] LPC_FRAME#
[31,7] LPC_AD3
[31,7] LPC_AD2
LPC_AD3
LPC_AD2
LPC_AD1
5
7
8
LFRAME#/GPIOF6
LAD3/GPIOF4
LAD2/GPIOF3
GPIO45/E_PWM
63
TP_CLK R260 1 2 4.7K_0402_5%
[31,7] LPC_AD1 LAD1/GPIOF2 GPIO90/AD0 VCIN1_BATT_TEMP [42,43]
@EMI@ @EMI@ LPC_AD0 10 64
2 1 R190 2 1 10_0402_1% [31,7] LPC_AD0 LAD0/GPIOF1 LPC & MISC GPIO91/AD1 65
GPIO92/AD2 ADP_I [43]
C186 22P_0402_50V8J 12 AD Input 66 TP_DATA R261 1 2 4.7K_0402_5%
[7] CK_LPC_KBC 13 LCLK/GPIOF5 GPIO93/AD3 75 DCHG_I [43]
ADP_ID
[19,30,31,37,39,9] PCIRST# LRESET#/GPIOF7 GPIO05/AD4 ADP_ID [41]
1 2 EC_RST# 37 76
+3VLP R192 47K_0402_5% EC_SCI# 20 ECRST# GPIO04/AD5 VRAM_TEMP [24]
[5,9] EC_SCI# 38 GPIO54/ECSCI#
1 VCIN1_BATT_TEMP 1 2
C187 GPIO11/CLKRUN# 68 C189 100P_0402_50V8J
GPIO94/DA0 70 EC_CLEAR_CMOS [9]
0.1U_0201_10V6K
GPIO95/DA1 TS_DISABLE# [26]
DA Output 71 +3VALW
KSO[0..17] 2 GPIO96/DA2 DGPU_PWR_EN [10,21,48]
KSI0 55 72
[32] KSO[0..17] 56 KBSIN0/GPIOA0 GPIO97/DA3 EC_WL_OFF# [30]
KSI1
KSI[0..7] KSI2 57 KBSIN1/GPIOA1 EC_MUTE# R198 1 @ 2 10K_0402_5%
[32] KSI[0..7] KSI3 58 KBSIN2/GPIOA2 83
KBSIN3/GPIOA3 GPIO31/SCL3/PSCLK1 EC_MUTE# [38]
KSI4 59 84
KBSIN4/GPIOA4/N2TCK GPIO23/SDA3/PSDAT1 USB_EN# [33] +3VS
KSI5 60 85 EC_SMB_CK3
61 KBSIN5/GPIOA5/N2TMS GPIO47/SCL4/PSCLK2 86 EC_SMB_CK3 [35]
KSI6 PS2 Interface GPIO53/SDA4/PSDAT2 EC_SMB_DA3 R207
KBSIN6/GPIOA6 EC_SMB_DA3 [35]
KSI7 62 87 TP_CLK EC_SMB_CK3 2 1
39 KBSIN7/GPIOA7 GPIO50/PSCLK3 88 TP_CLK [32]
KSO0 TP_DATA 2.2K_0402_5%
KBSOUT0/GPIOB0/SOUT_CR/JENK# GPIO52/PSDAT3 TP_DATA [32]
+3VLP KSO1 40 R213
KSO2 41 KBSOUT1/GPIOB1/TEST# EC_SMB_DA3 2 1
R201 KSO3 42 KBSOUT2/GP(I)OB2/TRIST# 97 2.2K_0402_5%
KBSOUT3/GP(I)OB3/XORTR# GPIO02 ENBKL [26,5]
1 2 EC_SMB_CK1 KSO4 43 98
44 KBSOUT4/GPIOB4/SDP_VIS# GPIO75 99 SYS_PWROK [9]
2.2K_0402_5% KSO5 GPIO
KBSOUT5/GPIOB5/TDO GPIO76 ME_EN [8]
R202 KSO6 45 109
KBSOUT6/GPIOB6/RDY# VCIN1/GPIO16 VCIN0_PH1 [42]
1 2 EC_SMB_DA1 KSO7 46 Int. K/B
2.2K_0402_5% KSO8 47 KBSOUT7/GPIOB7
KSO9 48 KBSOUT8/GPIOC0 Matrix 119
49 KBSOUT9/GPIOC1 F_SDI&F_SDIO1/GPO80 120 EC_SPI_MISO [7]
KSO10
KBSOUT10&P80_CLK/GPIOC2 F_SDIO&F_SDIO0/GPIOC6 EC_SPI_MOSI [7]
KSO11 50 126
KSO12
KSO13
KSO14
51
52
53
KBSOUT11&P80_DAT/GPIOC3
KBSOUT12/GPIO64/TCK
KBSOUT13/GPIO63/TMS
F_CLK/GPIOC4
SPI Flash ROM F_CS0#/GPIOC5 128
EC_SPI_CLK [7]
EC_SPI_CS0# [7] ESD
KSO15 54 KBSOUT14/GPIO62/TDI 73
DS3 SYSON
KSO16 81 KBSOUT15/GPIO61/XOR_OUT GPIO03/AD6/CIRRXM 74
DDR_TEMP [17] Reserve for +5VALW EN
GPIO60/KBSOUT16 GPIO07/AD7/CIRTX1 CMOS_ON# [26]
KSO17 82 89
GPIO57/KBSOUT17 GPIO67/N2TMS SUSACK# [9]
1
90 1
GPIO51/N2TCK BATT_CHG_LED# [32]
91
77 GPIO36 92 CAPS_LED# [32]
EC_SMB_CK1 GPIO R239 C193
[42,43] EC_SMB_CK1 GPIO17/SCL1/N2TCK GPIO40/F_PWM PWR_LED# [32]
EC_SMB_DA1 78 93 DS3 100K_0402_5% 0.1U_0201_10V6K
[42,43] EC_SMB_DA1 GPIO22/SDA1/N2TMS GPIO35 BATT_LOW_LED# [32] 2
EC_SMB_CK2 79 95 SYSON @ESD@
[20,28,31,7] EC_SMB_CK2 SYSON [12,40,45]
2
EC_SMB_DA2 80 GPIO73/SCL2 GPIO06/IOX_DOUT 121
[20,28,31,7] EC_SMB_DA2 GPIO74/SDA2 SM Bus GPIO81/F_WP# PCH_PWR_EN [40,46]
127
GPIO84/IOX_SCLK DPWROK_EC [9]
6 100
DS3 [33] USB_CHG_STATUS# 14 GPIO24 GPIO26/RSMRST# 101 EC_RSMRST# [9]
[33] USB_CHG_CTL1 GPIO10/LPCPD# GPIO20/TA2/IOX_DIO
15 102
[9] SUSWARN# 16 GPIO65/SMI# VC_IN2/GPIO72 103
[33] USB_CHG_CTL3 GPIO34/1_WIRE/CIRRXL VC_OUT2/GPIO37 VCOUT1_PROCHOT# [43]
17 104 VCOUT1_PROCHOT# R204 1 @ 2 0_0402_5%
[33] USB_CHG_EN GPIO01/TB2 VC_OUT1/GPIO25 VCOUT0_MAIN_PWR_ON [44]
+3VALW 18 GPIO 105 BKOFF#
DS3 [33] USB_CHG_CTL2 19 GPIO43 GPIO77 106 BKOFF# [26]
[30,37] PCIE_WAKE# GPIO42/CIRTX2 GPIO GPIO44 PM_SLP_S3# [9]
25 107 R205 1 @ 2 0_0402_5% H_PROCHOT# [5]
1 2 [46,9] SLP_SUS# 28 GPIO13/C_PWM GPIO12 108 VR_PWRGD [49] [49] VR_HOT#
PCIE_WAKE#
[31] FAN_SPEED1 GPIO56/TA1 GPIO30/F_WP# VR_ON [40,49]
R212 1K_0402_5% VCIN1_AC_IN 29
[20,32,43,9] VCIN1_AC_IN GPIO14/TB1
EC_TX 30
[30,32] EC_TX 31 GPIO83/SOUT_CR/P80_DATA 110
EC_RX EC_VCIN1_AC_IN R2006 1 @ 2 0_0402_5% VCIN1_AC_IN 1
[30,32] EC_RX GPIO87/SIN_CR/P80_CLK AC_IN/GPIO41/F_WP#
PCH_PWROK 32 112 EC_ON @
[9] PCH_PWROK 34 GPIO27/RSMRST# EC_ON/GPIO71 114 EC_ON [33,44]
NOVO# GPIO ON/OFF# [32,35] C191
[33] NOVO# GPIO66/G_PWM ON_OFFBTN#/GPIO70
36 115 LID_SW# 47P_0402_50V8J
[32] NUM_LED# GPIO33/H_PWM GPO82/IOX_LDSH/LIDIN LID_SW# [32] 2
116 SUSP#
GPIO46/CIRRXM/PLCIN 117 SUSP# [12,40,45]
NUVOTON_VTT
VTT 118 PECI R208 1 2 43_0402_1%
PECI PECI H_PECI [5]
122
[9] PBTN_OUT# GPIO00/EXTCLK
2 RS@ 1 PM_SLP_S4#_R 123 124 +V18R R209 1 @ 2 0_0402_5% +3VLP
[40,9] PM_SLP_S4# GPIO55/CLKOUT/IOX_DIO VCORF
R269 0_0402_5% 1
AGND
GND1
GND2
GND3
GND4
GND5
1 2 VCIN1_AC_IN
C192
4.7U_0603_6.3V6K
C190 100P_0402_50V8J
1 2
R203 @ 4.7K_0402_5% 2
11
24
35
94
113
69
NPCE388NA0DX_LQFP128_14X14
+3VALW
ECAGND
ESD LID_SW# R206 1 2 100K_0402_5%
PCH_PWROK
+1.0V_VCCST
1
@ESD@
C250
100P_0402_50V8J NUVOTON_VTT R210 1 @ 2 0_0402_5%
2
+3VS
1 2 FAN_SPEED1
R214 10K_0402_5%

EC_NPCE388N
C 0.1
1 2 3 4 5
To Docking BD
+USB_VCCB
+3VS
A A
+3VLP
JDOCK1
1
1 2 D1-_Docking
2 3 D1+_Docking D1-_Docking [36]
3 4 D1+_Docking [36]
4 5 D0-_Docking
5 6 D0+_Docking D0-_Docking [36]
6 7 D0+_Docking [36]
7 8
8 9
9 10 USB3_TX_N3 [11]
10 11 USB3_TX_P3 [11]
11 12
12 USB3_RX_N3 [11]
13
13 14 USB3_RX_P3 [11]
14 15
15 16
16 17 Docking_DP_HPD
17 Docking_DP_HPD [36]
18
18 19
19 20 DC_LED [32]
20 21
21 AUXp_Docking [36]
22
22 AUXn_Docking [36]
23
23 24 Docking_Consumption [43]
24 ON/OFF# [32,34]
25 Docking_PRSNT#_R Docking@ 2 R227 1 1_0402_5%
31 25 26 Docking_PRSNT# [36,5]
32 G1 26 27
33 G2 27 28
34 G3 28 29
G4 29 USB20_P9 [11]
35 30
G5 30 USB20_N9 [11]
ACES_50406-03071-001
ME@
SP010015L00
B B
APS (G-Sensor)
C C
+3VS +3VS
RS@ UGS2 GS@
RGS2 1 2 0_0402_5% +3VS_GS_R 7 3
10 VDD VDDIO 11
2 CSB PS
0.1U_0201_10V6K
CGS3
GS@
5 4 2
INT1 NC
0.1U_0201_10V6K
6
1 [9] GS_INT2 INT2
CGS4
GS@
1
2 SDO 9
[34] EC_SMB_DA3 12 SDx GND 8 1
[34] EC_SMB_CK3 SCx GNDIO
BMA250E_LGA12
SMB Address: 0001 100X
D D
Security Classification Compal Secret Data

Title
Issued Date 2011/06/24 Deciphered Date 2012/07/12
Size
Docking
Document Number Rev
Date:
LA-D101P
Wednesday, March 04, 2015 Sheet 35 of 53
1 2 3 4 5
5 4 3 2 1
+3VS +3VS_DP +3VS_DP
JP4
1 2
1 2
D 1 CD56 1 CD57 1 CD58 1 CD59 D
0.1U_0201_10V6K
Docking@
0.01U_0402_16V7K
Docking@
0.1U_0201_10V6K
Docking@
0.01U_0402_16V7K
Docking@
JUMP_43X39
@
2 2 2 2
Pin14 Pin28 Pin41 Pin56

DP_Switching Function (For Automatic Switching)
+3VS_DP +3VS_DP
H TMDS output has higher priority
＊L
UD1
14 40
DP output has higher priority VDD33 DP_D0p D0+_Docking [35]
2
+3VS_DP RD34 1 @ 2 0_0402_5% 28 39
[35,5] Docking_PRSNT# VDD33 DP_D0n D0-_Docking [35]
[10] I2C_CTL_EN RD21 1 @ 2 0_0402_5% @ 41
RD24 56 VDD33 37
VDD33 DP_D1p D1+_Docking [35]
2
4.7K_0402_5% 36 D1-_Docking [35]

@ DP_CFG0 44 DP_D1n
1
RD14 DP_Switching 45 DP_CFG0/SCL_CTL 34
4.7K_0402_5%
TMDS_PRE Function I2C_CTL_EN_R 38 SW/SDA_CTL DP_D2p 33
To DP
I2C_CTL_EN DP_D2n For Docking
H DDC active buffer
1
2
TMDS_DDCBUF [5] CPU_DP2_P0 CD60 1 2 0.1U_0402_25V6 Docking@ CPU_DP2_P0_C 3 31
Docking@ Docking@ CD61 1 2 0.1U_0402_25V6 Docking@ CPU_DP2_N0_C 4 IN_D0p DP_D3p 30
M DDC pass through with 40 kohm pull up resistor [5] CPU_DP2_N0 IN_D0n DP_D3n
2
RD22 RD23
Docking@ L DDC pass through 4.7K_0402_5% 4.7K_0402_5% [5] CPU_DP2_P1 CD62 1 2 0.1U_0402_25V6 Docking@ CPU_DP2_P1_C 6 55
IN_D1p DP_AUXp_SCL AUXp_Docking [35]
RD17 [5] CPU_DP2_N1 CD63 1 2 0.1U_0402_25V6 Docking@ CPU_DP2_N1_C 7 54
AUXn_Docking [35]
1
4.7K_0402_5% IN_D1n DP_AUXn_SDA 32
DP_HPD Docking_DP_HPD [35]
[5] CPU_DP2_P2 CD64 1 2 0.1U_0402_25V6 Docking@ CPU_DP2_P2_C 9
1
CD65 1 2 0.1U_0402_25V6 Docking@ CPU_DP2_N2_C 10 IN_D2p

[5] CPU_DP2_N2 IN_D2n 42 RD20 1Docking@ 2 1M_0402_5%
CD66 1 2 0.1U_0402_25V6 Docking@ CPU_DP2_P3_C 12 DP_CA_DET
[5] CPU_DP2_P3 IN_D3p
From CPU [5] CPU_DP2_N3 CD67 1 2 0.1U_0402_25V6 Docking@ CPU_DP2_N3_C 13 29 DP_CFG1
+3VS_DP IN_D3n DP_CFG1
CD68 1 2 0.1U_0402_25V6 Docking@ DDI2_AUX_DP_C 52 19
HDMI_TX0+_CK [27]
[5] DDI2_AUX_DP IN_AUXp TMDS_CH0p
C CD69 1 2 0.1U_0402_25V6 Docking@ DDI2_AUX_DN_C 51 18 HDMI_TX0-_CK [27] C
[5] DDI2_AUX_DN IN_AUXn TMDS_CH0n
2
Docking@ 50 22 HDMI_TX1+_CK [27]

[27,5] HDMICLK_NB IN_DDC_SCL TMDS_CH1p
RD15 49 21
[27,5] HDMIDAT_NB IN_DDC_SDA TMDS_CH1n HDMI_TX1-_CK [27]
4.7K_0402_5% TMDS_RT Function 11 25 HDMI_TX2+_CK [27]
1
TMDS_RT IN_CA_DET TMDS_CH2p 24

H Open drain driver with termination resistors 5 TMDS_CH2n HDMI_TX2-_CK [27] To HDMI
[27,5] TMDS_B_HPD IN_HPD
2
16
@
L Standard open drain driver TMDS_CLKp 15
HDMI_CLK+_CK [27]
TMDS_CLKn HDMI_CLK-_CK [27]
RD18
4.7K_0402_5% 1 48
CEXT TMDS_SCL HDMICLK_R [27]
1 47
HDMIDAT_R [27]
1
CD70 TMDS_DDCBUF 2 TMDS_SDA

2.2U_0402_6.3V6M TMDS_DDCBUF 17
TMDS_HPD HDMI_DET [27]
Docking@ DPSW_PEQ 8
2 PEQ 23 TMDS_RT
+3VS_DP 27 TMDS_RT 20 TMDS_PRE
REXT TMDS_PRE
1
46 26
PD GND
2
RD33 RD31 35
Docking@ 4.42K_0402_1% 2 1 DP_MODE 53 GND 43
+3VS_DP MODE GND
RD16 TMDS_PRE Function Docking@ 57
Thermal/GND
2
4.7K_0402_5% 4.7K_0402_5%
2
H 1.5dB pre-emphasis Docking@ RD32 PS8339BQFN56GTR2-A0_QFN56_7X7
1
TMDS_PRE 4.7K_0402_5% Docking@

M 3.0dB pre-emphasis Docking@
2
1
@ L no pre-emphasis
RD19
4.7K_0402_5%
DP_MODE Function
1
H Automatic Switching Mode, HDMI ID disable

+3VS_DP ＊M (VDD33/2) Automatic Switching Mode, HDMI ID enable
B L Control Switching Mode, HDMI ID disable B
2
@
RD25 DPSW_PEQ Function
4.7K_0402_5%
H HEQ, compensate channel loss up to 15dB @ HBR2
1
DPSW_PEQ For NoDocking For NoDocking

M LLEQ, compensate channel loss up to 5dB @ HBR2 Near UD1.3, 4, 6, 7, 9, 10, 12, 13 Near UD1.15, 16, 18, 19, 21, 22, 24, 25
2
@ L default, LEQ, compensate channel loss up to 12dB @ HBR2 RP31 RP37

RD26 CPU_DP2_N1 1 8 CPU_DP2_N1_R 1 8 HDMI_TX1-_CK
4.7K_0402_5% CPU_DP2_P1 2 7 CPU_DP2_P1_R 2 7 HDMI_TX1+_CK
CPU_DP2_N0 3 6 CPU_DP2_N0_R 3 6 HDMI_TX2-_CK
1
CPU_DP2_P0 4 5 CPU_DP2_P0_R 4 5 HDMI_TX2+_CK
0_0804_8P4R_5% 0_0804_8P4R_5%
From CPU NoDocking@ NoDocking@
+3VS_DP
RP32 RP38
CPU_DP2_N3 1 8 CPU_DP2_N3_R 1 8 HDMI_CLK-_CK
2
CPU_DP2_P3 2 7 CPU_DP2_P3_R 2 7 HDMI_CLK+_CK

@ CPU_DP2_N2 3 6 CPU_DP2_N2_R 3 6 HDMI_TX0-_CK
RD27 DP_CFG0 Function CPU_DP2_P2 4 5 CPU_DP2_P2_R 4 5 HDMI_TX0+_CK
4.7K_0402_5%
H automatic EQ disable & AUX interception enable 0_0804_8P4R_5% 0_0804_8P4R_5%
1
DP_CFG0 NoDocking@ NoDocking@

M automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing
2
@ L default, automatic EQ enable & AUX interception enable

RD28
4.7K_0402_5%
1
+3VS_DP
A A
2
@
RD29 DP_CFG1 Function
4.7K_0402_5%
H auto test enable & input offset cancellation enable
1
DP_CFG1
M auto test disable & input offset cancellation disable
2
@ L default, auto test disable & input offset cancellation enable

RD30
4.7K_0402_5% 2011/06/24 2012/07/12 Title
HDMI CONN
1
C 0.1
5 4 3 2 1
5 4 3 2 1
+3VALW +3V_LAN CL15

RL18 1 RS@ 2 0_0603_5%
60mil W=60mil
2 +LAN_VDD
W=60mils
CL1 +LAN_SROUT1.05 RL11 1 RS@ 2 0_0603_5%
1U_0402_6.3V6K
1
1
CL15
0.1U_0201_10V6K
8111H_LDO@
2
D D
RJ-45 CONN.
+3V_LAN
要>1mS and <100mS

JLAN1 ME@
+LAN_VDD LED0 1 2 12
Yellow LED-
Rising time (10%~90%) RL15 510_0402_5%
W=40mils 11
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
+3V_LAN RL1 Yellow LED+
+3V_LAN 1 RS@ 2 +LAN_VDDREG RJ45_TX3- 8
1U_0402_6.3V6K
1 1 1 1 1 PR4-
CL8
0_0603_5% CL4 CL5 CL6 CL7 RJ45_TX3+ 7
0.1U_0201_10V6K
PR4+
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2 2 2 2 2 RJ45_RX1- 6
0.1U_0201_10V6K
1 1 1 1 PR2-
@ @
CL2 CL3 CL20 CL21 RJ45_TX2- 5
PR3-
2 2 2 2 RJ45_TX2+ 4
PR3+
C C
Close to Pin3, Pin8, Pin22, Pin30, Pin22 RJ45_RX1+ 3
PR2+
RJ45_TX0- 2
PR1- 13
RJ45_TX0+ 1 SHLD2 14
W=60mils +3V_LAN PR1+ SHLD1
LED2 1 2 10
RL16 510_0402_5% Green LED-
CL2 close to Pin 11 9
Green LED+
CL3 close to Pin 32 SANTA_130452-0P
DC234007O00 LANGAN1 LANGAN
RS@ RL4 1 2 0_0402_5% LANGAN

+LAN_VDD +LAN_VDD These components close to Pin 17, 18
RS@ RL5 1 2 0_0402_5%
+3VS
1 2 PCIE_CRX_DTX_P5 PCIE_CRX_DTX_P5 [11]
LAN_MDIP0 1 17 PCIE_CRX_C_DTX_P5 CL11 0.1U_0201_10V6K
MDIP0 HSOP
1
LANGAN LAN_MDIN0 2 18 PCIE_CRX_C_DTX_N5 1 2 PCIE_CRX_DTX_N5
MDIN0 HSON PCIE_CRX_DTX_N5 [11]
3 19 PCIRST# CL12 0.1U_0201_10V6K RL8
LAN_MDIP1 4 AVDD10 PERSTB 20 ISOLATE# PCIRST# [19,30,31,34,39,9] 1K_0402_5%
LAN_MDIN1 5 MDIP1 ISOLATEB 21 PCIE_WAKE#
@EMI@ RL6 1 2 0_0402_5% LAN_MDIP2 6 MDIN1 LANWAKEB 22 PCIE_WAKE# [30,34]
2
LAN_MDIN2 7 MDIP2 DVDD10 23 +LAN_VDDREG ISOLATE#
@EMI@ RL7 1 2 0_0402_5% 8 MDIN2 VDDREG 24 +LAN_SROUT1.05 +3V_LAN
LAN_MDIP3 9 AVDD10 REGOUT 25 LED2 TP@ TPL1
LAN_MDIN3 10 MDIP3 LED2 26 LED1_GPIO 1 @ 2
11 MDIN3 LED1/GPIO 27 LED0 TP@ RL17 10K_0402_5% RL10
+3V_LAN AVDD33 LED0
LANGAN1 LAN_CLKREQ# 12 28 XTLO TPL2 15K_0402_5%
[9] LANCLK_REQ# PCIE_ATX_C_GRX_P2 13 CLKREQB CKXTAL1 29 XTLI
[11] PCIE_CTX_C_DRX_P5 PCIE_ATX_C_GRX_N2 14 HSIP CKXTAL2 30
[11] PCIE_CTX_C_DRX_N5 CLK_PCIE_LAN 15 HSIN AVDD10 31 2.49K_0402_1% 2 1 RL9
B
[9] CLK_PCIE_LAN CLK_PCIE_LAN# 16 REFCLK_P RSET 32 reserved GPIO pin B
[9] CLK_PCIE_LAN# REFCLK_N AVDD33 +3V_LAN

33
GND
CL13
UL2 UL2 TL1
1 2 XTLO RTL8107E-CG QFN 32P E-LAN CTRL RTL8111H-CG QFN 32P E-LAN CTRL +V_DAC 1 24 MCT
SA000086300 TCT1 MCT1 RL19 CL19
SA000080P00
10P_0402_50V8J 8107E_LDO@ LAN_MDIP3 2 23 RJ45_TX3+ 1 2 1 2
8111H_LDO@ TD1+ MX1+
1
LAN_MDIN3 3 22 RJ45_TX3- 75_0805_5% 10P_0603_50V

YL2 CL18 TD1- MX1- EMI@ EMI@
OSC
NC
25MHZ_10PF_7V25000014 1 2 +V_DAC 4 21
SJ10000E800 EMI 0.01U_0402_16V7K LAN_MDIP2 5

TCT2 MCT2
20 RJ45_TX2+
LANGAN
OSC
EMI@ TD2 MX2+

NC
E14@ LAN_MDIN2 6 19 RJ45_TX2-

DL1 TD2- MX2-
2
LAN_MDIN3 1 4 LAN_MDIP2 +V_DAC 7 18 2 1

CL14 I/O1 I/O3 TCT3 MCT3
1 2 XTLI LAN_MDIP1 8 17 RJ45_RX1+ DL3
TD3+ MX3+ BS4200N-C-LV_SMB-F2
10P_0402_50V8J 2 5 LAN_MDIN1 9 16 RJ45_RX1- EMI@
GND VDD TD3- MX3-
+V_DAC 10 15
TCT4 MCT4
LAN_MDIP3 3 6 LAN_MDIN2 LAN_MDIP0 11 14 RJ45_TX0+
I/O2 I/O4 TD4+ MX4+
AZC099-04S.R7G_SOT23-6 DL4 LAN_MDIN0 12 13 RJ45_TX0-
DL1 Only For GIGA SC300001G00 SC300001G00 TD4- MX4-
A E15@ TL1 NS892407 1G A
E14@ S0 X'FORM_ HH-065 10/100 8111H_LDO@
DL2 8107E_LDO@
LAN_MDIN1 1 4 LAN_MDIP0
I/O1 I/O3
FOR 10/100 data transferring 2013/08/27
2 5
GND VDD

LAN_MDIP1 3 6 LAN_MDIN0 2013/04/12 2014/04/12 Title
I/O2 I/O4 Issued Date Deciphered Date
AZC099-04S.R7G_SOT23-6 DL5
LAN RTL8111G/8106E
SC300001G00 SC300001G00 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
S DIO(BR) AZC099-04S.R7G SOT23 ESD Custom 0.1
E15@
5 4 3 2 1
A B C D E
+5VS_PVDD
ALC3240 Input
0.1U_0201_10V6K
4.7U_0603_6.3V6K
+5VS
2 1
+3VDD_CODEC
+1.8VS 1 RS@ 2 0_0603_5%
CA1
CA3
RA1
4.7U_0603_6.3V6K
1 2
2 1 140916→The pull high voltage needs to be the same as DVDD
2 1
CA2
CA32
place close audio codec
CA17 CA9 0.1U_0201_10V6K
1 2
4.7U_0603_6.3V6K 0.1U_0201_10V6K
1 2 +3VDD_CODEC
@
+5VS_PVDD
Combo Jack
2
29
34
39
1
UA1
RA38 (Normal Open)
PVDD1
PVDD2
CPVDD
DVDD
[8] HDA_SDIN0 33_0402_5% 2 1 RA12 HDA_SDIN0_AUDIO 7 100K_0402_5%
1
4 SDATA-IN 25 HP_OUTL 1
[8] HDA_SDOUT_AUDIO Headphone
1
SDATA-OUT HPOUT-L(PORT-I-L) 26 HP_OUTR PLUG_IN_R RA13 1 2 200K_0402_1%
HPOUT-R(PORT-I-R) PLUG_IN [33]
PC_BEEP 11 CA27 1 2 1U_0402_6.3V6K
EMI 5
PCBEEP
VREF
22
27 CPVEE 2 1
22P_0402_50V8J @EMI@
[8] HDA_BITCLK_AUDIO
CA12 33_0402_5% 2 @EMI@ 1 RA10
BCLK CPVEE
CA20 1U_0402_6.3V6K EXT_MIC_SLEEVE
EMI LA2 2 EMI@ 1 FBMA-L11-160808-121LMT_0603 HGNDB
W=40mils EXT_MIC_RING2 2 1 FBMA-L11-160808-121LMT_0603 HGNDA
HGNDB [33]
W=40mils LA3 EMI@
HGNDA [33]
RA6 1 2 2.2K_0402_5% EXT_MIC_RING2 13 17 LINE1-R HP_OUTL RA22 1 EMI@ 2 47_0402_5% HPOUT_L
wide 40MIL RA7
1 2 2.2K_0402_5%
CA19 2
EXT_MIC_SLEEVE
1 2.2U_0402_6.3V6M
14
15
MIC2-L(PORT-F-L)/RING
MIC2-R(PORT-F-R)/SLEEVE
MIC2-CAP
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
LINE1-VREFO-L
18
24
LINE1-L
+LINE1-VREFO-R
HP_OUTR RA23 1 EMI@ 2 47_0402_5% HPOUT_R
HPOUT_L [33]
HPOUT_R [33]
@EMI@
@EMI@
+MIC2-VREFO 23 12 PLUG_IN_R
MIC2-VREFO HP/ LINE1-JD(JD1)
EMI@
EMI@
SPK_L2+ 35 2
External DMIC
SPK-OUT-LP GPIO0/DMIC-DATA12 For Universal Audio Jack
2
SPK_L1- 36 3 DMIC_CLK_R BLM15PX221SN1D_2P 2 1 LA1 DMIC_DAT [26]
SPK-OUT-LN GPIO1/DMIC-CLK 1 1 1 1
SPK_R1- 37 EMI@ DMIC_CLK [26] LINE1-L CA21 2 1 1U_0402_6.3V6K CA33 CA34 CA36 CA37
RA26
RA27
10K_0402_5%
10K_0402_5%
SPK_R2+ 38 SPK-OUT-RN 8 @ @
SPK-OUT-RP DVDD-IO +IOVDD_CODEC
LINE1-R CA22 2 1 1U_0402_6.3V6K
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
2.2U_0402_6.3V6M 1 2 CA26 2 2 2 2
1
1
LDO1 21 28
2.2U_0402_6.3V6M 1 2 CA16 LDO2 32 LDO1-CAP CBN 30 CA15
LDO3 6 LDO2-CAP CBP RA29 1 2 4.7K_0402_5%
LDO3-CAP 1U_0402_6.3V6K
2.2U_0402_6.3V6M 1 2 CA13 2
40 1 @ 2 EC_MUTE# [34] +LINE1-VREFO-R RA32 1 2 4.7K_0402_5%
10 PDB 0_0402_5% RA11 2 1
VD33STB
9 DC DET 41
AVDD1
AVDD2
AVSS1
AVSS2
[8] HDA_SYNC_AUDIO SYNC THERMAL PAD RA8 10K_0402_5%
@
ALC3240-CG_MQFN40_5X5
20
33
19
31
16
RA9 1 2 0_0402_5%
+3VALW
Place RA9 on AGND/DGND moat

2
Output 2
+1.8VS
EMI
：
+5VDDA_CODEC RA5 1 2
：40MIL
0_0402_5% SPEAK 4 ohm
Place RA5 on AGND/DGND moat SPEAK 8 ohm 20MIL
JSPK1
CA8 1 2 1U_0402_6.3V6K SPK_R1- RA41 1 RS@ 2 0_0603_5% SPK_R1-_CONN 1
SPK_R2+ RA42 1 RS@ 2 0_0603_5% SPK_R2+_CONN 2 1
SPK_L1- RA43 1 RS@ 2 0_0603_5% SPK_L1-_CONN 3 2
Place near Pin33 SPK_L2+ RA44 1 RS@ 2 0_0603_5% SPK_L2+_CONN 4 3
5 4
6 G5
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
G6
1 1 1 1 ACES_85205-04001
→ +5VDDA_CODEC
ME@
EMI@ CA28
EMI@ CA29
EMI@ CA30
EMI@ CA31
：
SP020008X00
+5VS Each PlaQorm Power Net Support List

2 2 2 2
+5VS +5VDDA_CODEC
+1.5VS +1.8VS +3VS +5VS +3VALW
RA4
0_0603_5% 1.5V(S0) 1.8V(S0) 3.3V(S0) 5V(S0) 3.3V(S0~S5) ESD protection needs to be placed near connector side
1 2
AMD Carrizo V V V V V
ESD
0.1U_0201_10V6K
1 1 AMD Carrizo-L V V V V V
1U_0402_6.3V6K
CA7
CA11
Place RA4 on AGND/DGND moat Intel Broadwell V V V V SPK_R1-_CONN SPK_L1-_CONN

2 2
Intel Braswell V V V V V
SPK_R2+_CONN SPK_L2+_CONN
Intel Skylake V V V V V
3 3
Intel Bay trail-M V V V V V
2
Place near Pin20 D4 @ESD@ D10 @ESD@
2
Each PlaQorm HDA Link Voltage Support (Pin 8)
3.3V 1.5V
1
AMD Carrizo V
1
AMD Carrizo-L V L03ESDL5V0CG3-2_SOT-523-3 L03ESDL5V0CG3-2_SOT-523-3
Intel Broadwell V V
Intel Braswell V
Intel Skylake V V
Intel Bay trail-M V
+1.8VS → +IOVDD_CODEC +3VS → +3VDD_CODEC PC Beep place close to audio codec

EMI
[34] BEEP# RA39 1 2 47K_0402_5% 1 2 PC_BEEP RA21 1 RS@ 2 0_0402_5%

CA25 1U_0402_6.3V6K
+1.8VS +IOVDD_CODEC +3VS +3VDD_CODEC RA40 1 2 47K_0402_5%
[8] HDA_SPKR
1
RA24 1 RS@ 2 0_0402_5%

RA3 RA2 CA35 RA36
0_0603_5% 0_0603_5% 100P_0402_50V8J 27K_0402_1%
4 1 2 1 2 @EMI@ RA25 1 RS@ 2 0_0402_5% 4
0.1U_0201_10V6K
1
RA28 1 RS@ 2 0_0402_5%
CA6
1U_0402_6.3V6K
0.1U_0201_10V6K
1
1
CA4
CA5
2 GNDA
Place near Pin8
GND GNDA
2

Place near Pin1 Issued Date 2014/09/01 Deciphered Date 2015/09/01 Title
HD Audio Codec_ALC3240
C 0.1
A B C D E
5 4 3 2 1
D D
+AV12 +DV12S
+3VS
1 1 1 1
CC105 CC106 CC107 CC108
CC109 1 2 4.7U_0603_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
2 2 2 2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 2 UCR2
CC110 0.1U_0201_10V6K 9
+DV33_18 15 3V3_IN
+AV12 7 DV33_18
+Card_3V3 +DV12S 11 AV12
DV12_S
+Card_3V3 LC3 1 RS@ 2 0_0603_5% +Card_3V3_R 10
Card_3V3 25
1 2 8 GND
RC76 6.2K_0402_1% RREF Close to UCR1
[11] PCIE_CTX_C_DRX_P9
1
2 HSIP SP1
12
13
RC68 RS@
RC69 RS@
1
1
2 0_0402_5%
2 0_0402_5%
SD_D1
SD_D0
EMI
[11] PCIE_CTX_C_DRX_N9 HSIN SP2
CC111 1 2 0.1U_0402_25V6 PCIE_CRX_C_DTX_P9 5 14 SD_CLK_R RC65 1 EMI@ 2 33_0402_5% SD_CLK
[11] PCIE_CRX_DTX_P9 1 2 0.1U_0402_25V6 6 HSOP SP3 16 1 2 0_0402_5%
CC112 PCIE_CRX_C_DTX_N9 RC56 RS@ SD_CMD
[11] PCIE_CRX_DTX_N9 HSON SP4
C 17 RC57 RS@ 1 2 0_0402_5% SD_D3 C
SP5 18 RC58 RS@ 1 2 0_0402_5% SD_D2
SP6 1
[9] CLK_PCIE_CR 3 @EMI@
4 REFCLKP CC13
[9] CLK_PCIE_CR# REFCLKN
+DV33_18 5.6P 50V D NPO 0402
23 20 SD_WP 2
[19,30,31,34,37,9] PCIRST# PERST# SP7
2 24 21 SD_CD#
EMI
1U_0402_6.3V6K
[9] CRCLK_REQ# CLK_REQ# SD_CD#

CC103
2 1 SD_GPIO1 19 22
+3VS GPIO NC
RC64 10K_0402_5%
1 RTS5220-GRT_QFN24_4X4
SA000085G00
+Card_3V3
JSD1
SD_D0 7 4
D0 VDD
B B
SD_D1 8
D1
SD_D2 9 10 SD_WP CC104 1 1
0.1U_0201_10V6K
D2 WP CC12
4.7U_0603_6.3V6K
SD_D3 1 11 SD_CD#
D3 CD
3 2 2
SD_CLK 5 VSS1 6
CLK VSS2 12
SD_CMD 2 Shading 13
CMD Shading
TAITW_PSDBTC-09GLBS1N14H0
ME@
SP07000LN00
A A

P24-CardRead/RTS5229
5 4 3 2 1
A B C D E
+3VALW to +3V_PCH
+3VALW +5VALW
DS3 +3VALW +3V_PCH
10U_0603_6.3V6M
NODS3@
1 1 2 R219 1
+3VALW to +3VS
C206
C205 0_0603_5%
@ +3VS
0.1U_0201_10V6K U13 J4
2 2 1 14 +3VALW_3VS 2 1 R235 1 @ 2 470_0603_5% 3 1
2 VIN1 VOUT1 13 2 1
VIN1 VOUT1 1 1
1
D
10U_0603_6.3V6M
JUMP_43X79 C208 DS3@ DS3@ DS3@
4.7U_0603_6.3V6K
C209
3 12 1 2 C207 1 1 2 SUSP 4.7U_0603_6.3V6K Q15
ON1 CT1
C211
470P_0402_50V7K C212 G LP2301ALT1G_SOT23-3
[12,34,45] SUSP#
2
1 2 2 1
4 11 @ S Q14 @
3
VBIAS GND 0.1U_0201_10V6K 2N7002H_SOT23-3
+5VALW 5 10 1 2 C213 2 2
ON2 CT2 220P_0402_50V7K
6 9 +5VALW_5VS +5VALW
VIN2 VOUT2
10U_0603_6.3V6M
7 8 DS3@
VIN2 VOUT2
1 1
C215
C214 15 1 R221 2 PCH_PWR_EN#

@ GPAD +5VS
0.1U_0201_10V6K EM5209VF_DFN14_2X3 J5 47K_0402_5%
2 2 2 1
2 1 1
1
D DS3@
+5VALW to +5VS
10U_0603_6.3V6M
JUMP_43X79 2 DS3@ C216
[34,46] PCH_PWR_EN
1 1 G Q17 0.1U_0201_10V6K
2
C217
C218 S
3
@ L2N7002LT1G SOT23-3
0.1U_0201_10V6K
2 2
VR_ON [34,49]
6
For meet tPLT17 & tCPU28 power down sequence.

2 2
tPLT17 : 1us (Max)
tCPU28 : 1us (Max) 2
Q5002A
L2N7002DW1T1G 2N SC88-6
1
VGS(Max) : 2 V
+3VALW
1
R5094
VCCST_PWRGD [34,9]
100K_0402_5%
3
2
Q5002B
L2N7002DW1T1G 2N SC88-6
PM_SLP_S3_H 5 VGS(Max) : 2 V
4
6
+5VALW +0.675VS
1
PM_SLP_S3# 2
[34,9] PM_SLP_S3# R230 R228
Q5003A SUSP# @ @
1
L2N7002DW1T1G 2N SC88-6 100K_0402_5% 470_0402_5%

VGS(Max) : 2 V
2
6
SUSP
1
@ Q23 D Q21 D
For meet tPLT15 power down sequence(Un-Stuff) 2 Q5004A SUSP# 2 @ SUSP 2 @
tPLT15 : 1us (Max) L2N7002DW1T1G 2N SC88-6 G G
VGS(Max) : 2 V S S
1
3
2N7002H_SOT23-3 2N7002H_SOT23-3
3 +3VALW 3
1
SYSON
R5095
3
100K_0402_5%
@
2
Q5004B
PM_SLP_S4_H 5 L2N7002DW1T1G 2N SC88-6
VGS(Max) : 2 V
3
+5VALW
5
2
[34,9] PM_SLP_S4# @
Q5003B R233
4
L2N7002DW1T1G 2N SC88-6 220K_0402_5% +1.35V

VGS(Max) : 2 V
1
SYSON#
@ Q24 R234
1
DRC2124E0L NPN MINI3-G3-B 470_0603_5%
@
OUT
1 2
D
2 2 SYSON#
[12,34,45] SYSON IN G
GND
S Q25
3
2N7002H_SOT23-3
@
3
4 4

DC Interface
C 0.1
A B C D E
5 4 3 2 1
EMI@ PL101 ADP_ID

JDCIN1 PF101
HCB2012KF-121T50_0805
1 2
VIN AC Adapter 90W 65W
1 APDIN 7A_32VDC_0437007.WRML
1 2 1 2 APDIN1 R(K ohm) open 10
2 3 EMI@ PL102
3 4 HCB2012KF-121T50_0805 ADP_ID(V) 3.3 1.65
4
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
5 1 2
5 Detection voltage >2.64 1.32~1.98
ACES_88299-0510
1
EMI@ PC101
EMI@ PC102
EMI@ PC103
EMI@ PC104
CONN@
2
D D
@ PR101
0_0402_5%
1 2
1 2
+3VALW PR102 ADP_ID [34]
680P_0603_50V7K
0.1U_0402_16V7K
750_0402_1% A/D
1
PC105
PC106
2
2
C C
+CHGRTC
PR105
1K_0603_5%
1 2
PD101
+3VLP
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT 1 JBATT1
3 PR106
1K_0603_5%
1 2 1 2
+ -
LOTES_AAA-BAT-054-K01
CONN@
B B
RTC Battery
A A

PWR DCIN / RTC Battery
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z_BDW
5 4 3 2 1
5 4 3 2 1
EMI@ PL201
VMB2 VMB HCB2012KF-121T50_0805
CONN@ PF201 1 2
JBAT1 F1206HB12V024TM 12A 24V UL FAST
1 1 2
1 2 BATT+
EMI@ PL202
2 3 EC_SMCA HCB2012KF-121T50_0805
3 4 EC_SMDA 1 2
4 5
D 5 6 D
6
1
7
7
1
100_0402_1%
100_0402_1%
8
GND 9 PC201 EMI@ PC202 EMI@
GND 1000P_0402_50V7K 0.01U_0402_25V7K
2
PR201
PR211
ALLTO_C144PF-K07H9-L
2
EC_SMB_CK1 [34,43]
EC_SMB_DA1 [34,43]
CONN@
JBAT3 1 2
+3VLP
PH201 under CPU botten side :
1 2 PR212 200K_0402_1%
3 1 2 4 1 2
+3VALW
CPU thermal protection at 93 +-3 degree C
5 3 4 6 @ PR213 200K_0402_1%
7 5 6 8 Recovery at 56 +-3 degree C
9 7 8 10 1 2
11 9 10 12 VCIN1_BATT_TEMP [34,43]
11 12
PR214 20120314
13 14 10K_0402_5%
15 13 14 16
A/D Change to +EC_VCCA from +3VLP
17 15 16 18
19 17 18 20
21 19 20 22
21 22
23
25 23 24
24
26
+EC_VCCA
27 25 26 28
27 28
14K_0402_1%
29 30
29 30
1
PR215
C 31 32 C
GND GND
2
[34] VCIN0_PH1
1
PH201
100K +-1% 0402 B25/50 4250K
2
ECAGND
B B
A A

PWR-BATTERY CONN/OTP
5 4 3 2 1
5 4 3 2 1
1
D
Rds(on) = 35mohm max
@ PR314 2
1 2 G
Vgs = 20V
Vds = 30V
S @ PQ307 max Power loss 0.22W for 90W;0.12W for 65W system B+ BA+
3
1M_0402_1% @ PR315 2N7002KW _SOT323-3 P3 CSR rating: 1W ID = 7.7A (Ta=70C) PQ302
1 2 VACP-VACN spec < 80.64mV AO4466L_SO8
8 1
PQ301 3M_0402_5% PQ303 7 2
MDU1512RH_POW ERDFN56-8-5 AON7506_PDFN33-8-5 PR302 6 3
1 1 0.01_1206_1% EMI@ PL301 5
2 2 1UH_NRS4018T1R0NDGJ_3.2A_30%
5 3 3 5 1 4 1 2
VIN
4
PC302
2 3 SH00000YG00
1 2
0.047U_0603_25V7M
4
4
D D
Rds(on) typ=35mohm max
1000P_0603_50V7
2200P_0402_50V7K
PC301
0.022U_0603_25V7K
68P_0402_50V8J
Vgs=20V
4.02K_0402_1%
1
10U_0805_25V6K
10U_0805_25V6K
PC303
@ PC306
PR301
EMI@ PC307
PC308
PC309
Vds=30V
1
PC311
PR329
4.7_0603_1%
PC310 PC312
1
Id=10.6A (Ta=70C) 0.1U_0603_25V7M 0.1U_0402_25V6
4.02K_0402_1%
2
1 2 1 2 1 2
PR303
PR304
2
10_0402_1%
2
PR1133 0.01U_0402_25V7K
2
SD028000080
S RES 1/16W 0 +-5% 0402
BATDRV
BATSRC
1
10_0402_1%
PR308 NoDock@
1 2 ACDRV
DOCK@ PR1134
10_0402_1%
PR1134
DOCK@ PR1133
SD028000080
4.02K_0402_1% S RES 1/16W 0 +-5% 0402
NoDock@
PR1132
2
CMSRC
1 2
DOCKING_CONSUMPTION [35]
10_0402_1%
VIN ACP ACN CHECK WITH FAE

PR312
PD303
10_1206_5% @ PC329
VIN 3 1 2
422K_0402_1%
1
1 1 2 Rds(on) = 30mohm max
AON7408L_DFN8-5
PR311
2 ACDRV 1000P_0402_50V7K
BA+ 1U_0603_25V6K PC313
Vgs = 20V
1 2 BQ24780VDD PC314 Vds = 30V
S SCH DIO BAS40CW SOT-323 ID = 7A (Ta=70C)
2
5
C C
PU301 2.2U_0805_25V6K Support max discharge 6A(55W)
1 2 Power loss: 0.36W
ACDRV
ACP
ACN
28 CSR rating: 1W
VCC
PQ305
2200P_0402_25V7K
66.5K_0402_1%
PR316 VSRP-VSRN spec < 81.28mV

1
1
PC315
CMSRC 3 24
CMSRC REGN PR317 PC316 1 2 4
PR313
@ PR348 6 0_0603_5% 0.047U_0603_25V7M 7X7X3

BATT+
2
0_0402_5% ACDET 25 BST_CHG 1 2 1 2 0_0603_5%

BTST
Isat: 6.5A
[34,42] EC_SMB_DA1 1 2 EC_SMB_DA1_1 11 DCR: 33mohm
2
SDA
Power loss:0.297W
3
2
1
[34,42] EC_SMB_CK1 1 2 EC_SMB_CK1_1 12 26 DH_CHG PR318
0_0402_5% SCL HIDRV PL302 0.01_1206_1%
@ PR349 VCIN1_AC_IN 5 4.7UH_PCMB063T-4R7MS_5.5A_20%
[34] ADP_I ACOK 27 LX_CHG 1 2CHG 1 4
1 2 7 PHASE
IADP 2 3
AON7408L_DFN8-5
5
100P_0603_50V8 PC317 DCHG_I 8 23 DL_CHG
IDCHG LODRV
1
[34] DCHG_I PC330 0.1U_0402_25V6
4.7_1206_5%
1 2 1 2 PMON_1 9
PMON
PQ306
PR320
@ @ PR322 PR321 316K_0402_1%
100P_0603_50V8 PC318 1 2 10 22 1 2 SRP SRN
10U_0805_25V6K
10U_0805_25V6K
/PROCHOT GND +3VLP 4
2
PR1126 0_0402_5% @ 0_0402_5% PR324 100K_0402_1% @EMI@
1
1 2 1 2
PC322
PC320
[49] PMON_SKYLAKE 13 21
680P_0603_50V7K
CMPIN ILIM
1
3
2
1
2
[34] VCOUT1_PROCHOT# 14
PC321
PR326 10_0402_1%
CMPOUT 20 1 2
2
SRP PR328 10_0402_1%
15 19 1 2 @EMI@
[34,42] VCIN1_BATT_TEMP /BATPRES SRN
B B
16 18 PC323
/TB_STAT BATDRV
BQ24780VDD 29 17 1 2
PWPD BATSRC
0.1U_0402_25V6
BATDRV
BATSRC
BQ24780RUYR_W QFN28_4X4
1
Reserve AMD GPU PROCHOT# level shift

PR319
100K_0402_1%
0.1U_0402_25V6
0.1U_0402_25V6
1
1
+1.8VGS +3VGS
PC324
PC325
**Design Notes**
For 65 /90W system, 3S1P/3S2P battery
2
Maximum Charging current 3A
2
1
[20,32,34,9] VCIN1_AC_IN
Maximum Battery discharge power 55W
1
@PR1130 #Register Setting

2
10K_0402_1% @PR1128
PR325 @PR1129
1. 0X12 bit2 set 1 (default 0) to enable turbo boost function
10K_0402_1% 2. Disable turbo when AC only
0_0402_5%
2 2
120K_0402_1% #Circuit Design

2
1. ILIM pull high voltage need base on 3/5V enable control

G
1
2. Use 7X7 choke and 3X3 H/L side MOSFET

3 1 Charge current 3A
AC_BATT [20] Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W)
S
Power density : 0.61 (23X16)

#Protect function
Vin Dectector @ PQ1104 1. ACOVP : VCC voltage > 24V
BSS138W _SOT323-3
Min. Typ Max. 2. Charger timeout : No communication within 175s(default)
L-->H 17.16V 17.63V 18.12V 3. ACOC : 3.33 X Input current DAC setting (default:Disable)
4. CHGOCP : based on charge current setting
H-->L 16.76V 17.22V 17.70V PQ1104=>SB00000T000,SB000005N00 5. BATOVP : 103-106%
6. BATLOWV : 2.6V
A A
VILIM = 20*ILIM*Rsr 7. TSHUT : 155C
ILIM = 3.3*100/(316+100)/20/0.01 8. IFAULT HI : 750mV (default:Disable)
= 3.966 A 9. IFAULT LOW : 230mV (default)

Title
BQ24780
Custom 0.1
5 4 3 2 1
A B C D E
Module model information

SY8208B_V2.mdd
1 EN1 and EN2 dont't floating 1
2014.10.30 reserve for ESD PR401

Change 3V5V_EN to 3VALW_EN 499K_0402_1%
ENLDO_3V5V 1 2
B+
1
150K_0402_1%
PU401 PC403 PR403
B+
PR404
EMI@ PL401 7 1 3V5V_EN 0.01U_0402_25V7K 1K_0402_5%
HCB2012KF-121T50_0805 EN2 EN1 1 2 1 2
2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB
IN FB PR405 PC404
2
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
6 1
BST_3V 2 1 2
BS
1
1
PC407
2.2_0603_5%
1
@EMI@ PC401
PC405
PC406
0.1U_0603_25V7K
PC1237
@ PL402
2
2
EMI@
10 LX_3V 1 2
+3VALWP
2
LX
@EMI@
9 4 1.5UH_PCMB053T-1R5MS_6A_20%
GND OUT
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR406
1
1
680P_0603_50V7K 4.7_1206_5%
2 5
PG LDO +3VLP
[46] 3V/5VALW_PG
@EMI@
PC408
PC409
PC410
PC411
1
PR402 SYX196BQNC_QFN10_3X3
2
100K_0402_1% PC412
1 3V_SN
1 2 4.7U_0603_6.3V6M
+3VLP
2
Check pull up resistor of SPOK at HW side
@EMI@ PC413
3.3V LDO 150mA~300mA
2
2 PR407 2
2.2K_0402_5%
Vout is 3.234V~3.366V
[33,34] EC_ON 1 2
@ PR408
TDC=6A
1 2
[34] VCOUT0_MAIN_PWR_ON 0_0402_5%
EC VDD0 is +3VL, PC13 UNPOP
1
@ PJ401
2
EC VDD0 is +3VALW, PC13 POP +3VALWP 1 2 +3VALW
JUMP_43X118
3V5V_EN EN1 and EN2 dont't floating
1M_0402_1%
4.7U_0402_6.3V6M
1
3V5V_EN
1
PR410
PC414
2
2
B+ EMI@ PL403
HCB2012KF-121T50_0805
1 2 5V_VIN
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PU902 PC415 PR412

8 1 6800P_0402_25V7K 1K_0402_5%
IN EN 1 2 1 2
Vout is 4.998V~5.202V
1
1
PC416
PC418
EMI@ PC419
@EMI@ PC420
3 5V_FB PR413 PC417

3 FB 2.2_0603_5% 0.1U_0603_25V7K 3
@ 6 BST_5V 1 2 1 2
TDC=6A
2
BS
PL404
9 10 LX_5V 1 2 +5VALWP
GND LX
5V_VCC 5 4 1.5UH_PCMB053T-1R5MS_6A_20%
VCC OUT
1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
@EMI@ PR414
680P_0603_50V7K 4.7_1206_5%
1
2 7
PG LDO VL
1
PC421
PC422
PC423
PC424
PC425
PC428
4.7U_0603_6.3V6M
SYX196CQNC_QFN10_3X3
2
1 5V_SN
@ PJ402
2
2
1
PC426
4.7U_0603_6.3V6M
+5VALWP 1 2 +5VALW
1 2
JUMP_43X118
2
@EMI@ PC427
2
Module model information 5V LDO 150mA~300mA
SY8208C_V2.mdd
4 4

+3VALW/+5VALW
A B C D E
5 4 3 2 1

RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer
D D
Pin19 need pull separate from +1.5VP.

If you have +1.5V and +0.75V sequence question, 0.75Volt +/- 5%
EMI@ PL501 you can change from +1.5VP to +1.5VS. TDC 0.7A
HCB2012KF-121T50_0805
B+ 1 2 1.35V_B+ PR501 Peak Current 1A
2.2_0603_5%
BST_1.35V 1 2 BOOT_1.35V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
1
1
PC501
PC502
PC503
PC504
DH_1.35V +0.675VSP
2
2
EMI@
@EMI@
SW _1.35V
10U_0805_10V6K
10U_0805_10V6K
1
1
PC505
PC506
PC507
PU501
5
0.1U_0603_25V7K
16
17
18
19
20
2
C RT8207PGQW _W QFN20_3X3 C
2
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PQ501 PAD
AON7408L_DFN8-5 4 DL_1.35V 15 1
LGATE VTTGND
Change CS R to your estimation value
14 2
PL502 PR502 PGND VTTSNS
1
2
3
1UH_11A_20%_7X7X3_M 27K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP PC508 CS GND
1
1U_0402_10V6K
PC521 22U_0603_6.3V6M
PC520 22U_0603_6.3V6M
PC519 22U_0603_6.3V6M
PC518 22U_0603_6.3V6M
PC517 22U_0603_6.3V6M
PC516 22U_0603_6.3V6M
5
1 2 12 4 +VTTREFP
EMI@ PR503 PQ502 PR504 VDDP VTTREF
1 1 1 1 1 1
4.7_1206_5% 5.1_0603_5%
1 2 VDD_1.35V 11 5
+5VALW +1.35VP
1 2
VDD VDDQ
1
PGOOD
PR1131
2 2 2 2 2 2 4 5.1_0603_5% PC509
TON
1
EMI@ PC513 1 2 0.033U_0402_16V7K
FB
S5
S3
2
680P_0402_50V7K PC512
2
1U_0402_10V6K
10
6
AON7406L_DFN8-5
1
2
3
FB_1.35V
EN_0.675VSP
TON_1.35V
EN_1.35V
PR506
8.2K_0402_1%
+5VALW 1 2 +1.35VP
PR507
B
2014/10/15 add PR1131 for module design B
1.35V_B+ 1 2 Change FB Rtop to 8.2K for 1.35V
MOSFET: 3x3 DFN
1
H/S Rds(on): 27mohm(Typ), 34mohm(Max) 470K_0402_1%
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C PR508
PR509 10K_0402_1%
L/S Rds(on): 9.9mohm(Typ), 13mohm(Max) 1 2
[12,34,40] SYSON
2
Mode Level +0.75VSP VTTREF_1.5V Idsm: 13.5A@Ta=25C, 11A@Ta=70C 0_0402_5%
S5 L off off
1
@ PC514
S3 L off on Choke: 7x7x3 0.1U_0402_10V7K
S0 H on on Rdc=8.3mohm(Typ), 10mohm(Max)
2
Note: S3 - sleep ; S5 - power off Switching Frequency: 285kHz
Ipeak=10A @ PR510
1 2 @ PJ501
Iocp~13A [12,34,40] SUSP# 0_0402_5% +1.35VP 1 2 +1.35V
OVP: 110%~120% 1 2
MOSFET footprint: SIS412DN PR505 JUMP_43X118
1 2 @ PJ502
[6] DDR_VTT_PG_CTRL 1 2
1 2
1
0_0402_5%
@ PC515 JUMP_43X118
0.1U_0402_10V7K
2
PJ503 @
1 2
+0.675VSP 1 2 +0.675VS
A
JUMP_43X39 A
Security Classification Compal Secret Data

Title
RT8207M
Custom 0.1
5 4 3 2 1
A B C D

SY8032_V2.mdd
1 1
@
PJ702
1 2
+1.8VALWP 1 2 +1.8VALW
JUMP_43X79
PC701
Imax= 2A, Ipeak= 3A
22U_0603_6.3V6M FB=0.6V
1 2
@ PL701
PJ701
JUMP_43X79
+3VALW 1 2 4 3 LX_1.8V 1 2
1 2 PR702 100K_0402_5% IN LX +1.8VALWP
1 2 5 2
68P_0402_50V8J
+3VALW PG GND 1UH_2.8A_30%_4X4X2_F
1
6 1
PC702
22U_0603_6.3V6M
22U_0603_6.3V6M
2 2
[47] PGOOD FB EN
1
PC703
PC704
1
2
PR701 @EMI@ PR703 PR704
2
0_0402_5% 4.7_0603_5% 20K_0402_1%
1 2 +1.8VSP_ON
[44] 3V/5VALW_PG
2
@ PR707
Rup
2
0_0402_5% PU701
0.1U_0402_16V7K
1
1 2
PC705
SY8032ABC_SOT23-6
[34,40] PCH_PWR_EN
1
PR705 FB_1.8V
@ PR708 1M_0402_1%
0_0402_5%
1
1 2 @
[34,9] SLP_SUS#
2
@EMI@ PC706
680P_0402_50V7K PR706
2
10K_0402_1%
Rdown
2
Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
3 3
4 4

+1.8V_PRIM
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z_SKL
A B C D
5 4 3 2 1
D D

SY8208D_V1.mdd
EN pin don't floating

If have pull down resistor at HW side, pls delete PR2
PR802
0_0402_5%
1 2
PGOOD [46]
C C
1
@ PC802
1M_0402_1%
0.22U_0402_10V6K
2
PR803
PJ801
2
+1.0VALWP 1 2 +1.0VALW
1 2
JUMP_43X118 @
@EMI@ PR804 @EMI@ PC803
4.7_1206_5% 680P_0603_50V7K
EMI@ PL801 1 2SNB_1.0V 1 2
PU801
HCB2012KF-121T50_0805
B+ 1 2 B+_1.0V 8
IN EN
1 PR805 PC804
2.2_0603_5% 0.1U_0603_25V7K
TDC 8A
10U_0805_25V6K
10U_0805_25V6K
6 BST_1.0V1 2 1 2 PL802
0.1U_0402_25V6
2200P_0402_50V7K
BS
1
1UH +-20% 11A 7X7X3 MOLDING

PC805
PC806
PC807
3VLDO_1.0 9 10 LX_1.0V 1 2
+1.0VALWP
PC801
GND LX
@EMI@
2
2
EMI@
15K_0402_1%
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
330P_0402_50V7K
1
1
PR806 4
PR807
FB
PC808
PC809
PC810
PC811
PC812
0_0402_5%
ILMT_1.0V 3 7
Rup
@ +3VALW
2
ILMT BYP
2
2
4.7U_0603_6.3V6K
ILMT_1.0V 1 21.0V_VS_PG_PWR 2 5 3VLDO_1.0
PG LDO
1
PR801
PC814
4.7U_0603_6.3V6K
1
+3VALW 10K_0402_5%
PC813
SYX198DQNC_QFN10_3X3
FB = 0.6V
2
1
PR808 @
2
0_0402_5% PR809
Rdown
2
20K_0402_1%
2
Pin 7 BYP is for CS.
B
The current limit is set to 8A, 12A or 16A when this pin Common NB can delete +3VALW and PC15 B
is pull low, floating or pull high
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.05V
A A

+1.0VS
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z_SKL
5 4 3 2 1
5 4 3 2 1
+VGA_CORE
GPU_B+ AMD Meso XT
Module model information TDC 36A, EDC 54A
OCP min 67.8A
EMI@ PL901
ISL62771_V1A.mdd for IC portion HCB2012KF-121T50_0805
B+
AMD EXO PRO
1 2 TDC 28A, EDC 42A
ISL62771_V1B.mdd for SW portion LGATE1 OCP min ?A
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PHASE1
22P_0402_50V8J
@ PC963
1
@EMI@ PC902
EMI@ PC903
PC904
PC905
PR905 PC906
2.2_0603_1% 0.22U_0603_25V7K
BOOT11 2 1 2
PQ901
2
D D
6
7 G2
0_0402_5% PR904 S1/D2 5
UGATE1 1 2 1 S2
G1 4
2 S2
D1 3
S2
AON6932A_DFN5X6-8-7
@ PR946
1 2 Fsw=400K Hz
1
0_0402_5% PR902
LGATE_NB1
10K_0402_1%
1 2 SH00000NX00 (DCR:1.4± 5%)
@ PR947 PR945
1 2 41.2K_0402_1% PHASE_NB1
0_0402_5% PR903 10K_0402_1% +VGA_CORE
2
UGATE_NB1 1 2
1 4
PL902
PR906
0.22UH_PCME064T-R22MS_28A_20%
BOOT_NB12 1 +5VALW
2 3
330U_D2_2V_Y
330U_D2_2V_Y
1 1 1 1
330U_2.5V_M
330U_2.5V_M
41
40
39
38
37
36
35
34
33
32
31
1_0402_5% + + + +
PC910
PC907
PC908
PC909
PU901 PR907 @EMI@ PR938 PR939
4.7_1206_5% 10K_0402_1% 10K_0402_1%
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
ISEN1 1 2 1 2 ISEN2
2 2 2 2
2
PR901 100K_0402_1%
1 2 1 30 BOOT2 PR908
1
NTC_NB BOOT2 PC911 @EMI@ 3.65K_0603_1%
[20] GPU_PROCHOT# PR909 100K_0402_1%
1 2 IMON_NB 2 29 UGATE2 680P_0603_50V7K VSUM+ 1 2
IMON_NB UGATE2
2
3 28 PHASE2
@ PR911 100K_0402_1% [20] GPU_SVC SVC PHASE2 PR910
1 2 4 27 LGATE2 +5VALW 1_0402_1%
+3VS VR_HOT_L LGATE2 VSUM- 1 2
5 26
[20] GPU_SVD SVD VDDP
PR912 0_0402_5% ISL62771HRTZ-T_TQFN40_5X5 PR913
+1.8VGS 1 2 VDDIO 6 25 1 2
VDDIO VDD 1_0603_5%
1U_0603_10V6K
1
@ PR1123 0_0402_5% 7 24 LGATE1

[20] GPU_SVT SVT LGATE1
1
C 1 2 GPU_B+ C
LGATE2
1U_0603_10V6K
+3VGS
8 23
PC913
PC901 ENABLE PHASE1
2
ENABLE PHASE1
PC912
0.1U_0402_25V6K
PR912 for MESO
2
1 PR937 2 @ 9 22 UGATE1
[10] DGPU_PWROK PWROK UGATE1
PR1123 for EXO pro 0_0402_5% PHASE2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1 2 IMON 10 21 BOOT1
IMON BOOT1 +3VS
@EMI@ PC915
PR916 PR928 PC922
1
PGOOD
EMI@ PC916
PC917
PC918
133K_0402_1% 2.2_0603_1% 0.22U_0603_25V7K
ISUMN
ISUMP
PQ902
COMP
ISEN2
ISEN1
VSEN
BOOT21 2 1 2
NTC
RTN
1 2 PC914 FB 6
2
G2
1
1000P_0402_50V7K 7
PR919 PR918 0_0402_5% PR921 S1/D2 5
11
12
13
14
15
16
17
18
19
27.4K_0402_1% 20K_0402_1% 20 @ PR917 UGATE2 1 2 1 S2

1 2 1 2 100K_0402_1% G1 4
2 S2
2
D1 3
ISEN2
ISEN1
DGPU_PWROK S2
1 2
PR932 PH901 AON6932A_DFN5X6-8-7
2
1 2 ENABLE
0_0402_5%
10K_0402_1%
[10,21,34] DGPU_PWR_EN 470K +-5% 0402 B25/50 4700K

PR944
PR920
0_0402_5%
1
0.22U_0402_10V6K
0.1U_0402_16V7K
0.22U_0402_10V6K
PC1236
@ @
1
PC962
PC961
+5VS
2
@ 2014.09.22 modify from FAE +VGA_CORE

2
PC920 PL903
2014.10.15 reserve for RC delay VSUM- PC919 PR922 330P_0402_50V7 @ PR923 1 4
1000P_0402_50V7K 301_0402_1% 32.4K_0402_1% 0.22UH_PCME064T-R22MS_28A_20%
VSUM+ 1 2 1 2 1 2 1 2 2 3
330P_0402_50V7K
@ PC921
PR940 PR943
2.61K_0402_1%
1
1
PR924 PR925 PC923 PR929 @EMI@ 10K_0402_1% 10K_0402_1%
10K +-5% 0402 B25/50 4250K
1 2 1 2
PR926
0.047U_0402_25V7K
0.15U_0603_16V7K
1.21K_0402_1% 137K_0402_1% 390P_0402_50V7K 4.7_1206_5% ISEN2 ISEN1

11K_0402_1%
1
1 2 1 2 1 2
PC924
2
1
1
PR927
PC925
PR942
1 2
1 2
PR930 PC926 3.65K_0603_1%
2
2K_0402_1% 330P_0402_50V7K VSUM+ 1 2

2014.09.22 modify from FAE
2
1 2 1 2 PC927 @EMI@
PH902
680P_0603_50V7K
2014.09.22 modify from FAE
2
B PR941 B
PR931 PR948 1_0402_1%
2
590_0402_1% 10_0402_5% VSUM- 1 2

VSUM- 1 2 1 2 +VGA_CORE
@ PC929 @ PR933 +VGA_CORE
1
@ PR934 820P_0402_50V7K 0_0402_5%

PC928 100_0402_1% 1 2
0.1U_0603_50V7K 1 2 1 2 GPU_VDD_SEN [20]
2
@ PR935
0_0402_5%
PR1046 set 536 ohm to OCP 26.32A 1 2
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
GPU_VDD_RUN_FB_L [20]
0.01U_0402_50V7K
1
PC931
PC932
PC933
PC934
PC935
PC936
PC937
PC938
PC939
PC940
PC941
PC942
PC943
PC944
PC945
PC946
PR949
1
PC930
10_0402_5%
1 2
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
PC947
PC948
PC949
PC950
PC951
PC952
PC953
PC954
PC955
PC956
PC957
PC958
PC959
PC960
2
2
A A

PWR-+VGA_CORE
Custom 0.1
5 4 3 2 1
1 2 3 4 5
CPU CORE
IccMAX@SA= 5A
RIccMAX@SA= 15.8K --->PRI65
RIccMAX@SA= IccMAX*2V/10uA/64A
NCP81208_U22_V1A.mdd for IC portion
IOUTSP@SA= 5A
NCP81208_U22_V1B.mdd for SW portion RIOUTSP@SA=69.8K --->PRI14
RIOUTSP= 2V/(gm*(Rth+RCSSP)*ICCMAX*DCR
/(RPHSP+Rth+RCSSP))
A PMON_SKYLAKE [43]
PSYS: A
Please confirm charger pull low resistance.
Charger side should be unpop. OCP@SA= 9.5A
RLIMSP@SA=24K --->PRI5
PCI1 PRI1
0.015U_0402_16V7K 1.5K_0402_1% RLIMSP= 1.3V/(gm*(Rth+RCSSP)*IoutLIMIT*DCR
OCP for VCCSA 1 2 1 2 /(RPHSP+Rth+RCSSP))
PRI2, PRI8 place near CPU side.
If the resisters are at HW side and POP. PRI2, PRI8 can be canceled.
PCI3 COMP_1b_CPU 1 2 PCI2 Load line@SA= 10.3m
1000P_0402_50V7K 15P_0402_50V8J
+VCCSA PRI2 1 2
RDRPSP@SA=1.78K --->PRI4
100_0402_1%
24K_0402_1%
1000P_0402_50V7K
1 2 PRI4 RDRPSP= Load line*(RPHSP+Rth+RCSSP)
2
@ PRI3 1.78K_0402_1% CSN_1b_VCCSA [50]
/(gm * DCR) /(Rth+RCSSP)
1
1 2 VSPP_1b_CPU_R 1 2 VSP_1b_CPU
PRI5
[12] VCCSA_SENSE
PHI1 Close to SA choke
1200P_0402_50V7K
1
0_0402_5%
1
RDRPSP 100K_0402_1%_NCP15WF104F03RC
PCI4
0.01U_0402_25V7K
PCI5 @ PRI7
1
@ PRI6 1000P_0402_50V7K 0_0402_5%
PCI7
2
1 2
1
1
1 2 VSNN_1b_CPU_R 1 2 VSN_1b_CPU CSN_1b_VCCSA_NTC
PCI6
[12] VSSSA_SENSE
1 2 0_0402_5% 1 2 PRI9
2
PRI8 100_0402_1% PCI8 @ 12K_0402_1%
+VCCGT PRI10 1000P_0402_50V7K CSP_1b_VCCSA +3VS
2 1 CSP_1b_VCCSA_R [50]
2
1 2 20K_0402_1% PRI14 1 2
1
PRI11 100_0402_1% @ PRI13 69.8K_0402_1% 7.5K_0603_1%
1 2 VSP_2ph_CPU 1 2 PRI12 PRI15
[14] VCCGT_SENSE
0_0402_5% 10K_0402_1%
1
1 2
[14] VSSGT_SENSE PCI9 PRI18 PCI10 470P_0402_50V7K
2
@ PRI17 1000P_0402_50V7K 1K_0402_1% VR_PWRGD [34]
2
1 2 1 2 VSN_2ph_CPU_R 1 2 VSN_2ph_CPU
PRI16 100_0402_1%
0_0402_5% 1 2 IMVP8_EN confirm with power sequence,
PCI11
Upper Threshold > 0.8V +1.0V_VCCSTit need behind +5VS.
B 1000P_0402_50V7K B
Lower Threshold < 0.3V
1
PRI26 and PRI33 pull high resistor are pop at the end of VR SVID.
PRI11, PRI16 place near CPU side. PRI19 Other VR is unpop.
1K_0402_1%
1
If the resisters are at HW side and POP. PRI11, PRI16 can be canceled. 49.9_0402_1% PRI21
0_0402_5%
PRI20
1 2
110_0402_1%
100_0402_1%
45.3_0402_1%
1 2
VR_ON [34,40]
IOUT_1b_CPU
RIOUT@GT
ILIM_1b_CPU
2
PCI12
EN_CPU
PWM_1b_CPU [50]
1
470P_0402_50V7K
470P_0402_50V7K
PCI13
2
1
CSCOMP_2ph_CPU_R
Close to VGT1 choke DRVON [50]
1
PRI23 PRI24 @
25.5K_0402_1% PCI14 110_0402_1% PRI34
2
1
4.75K_0402_1%
PHI2 7.5K_0603_1%
49
48
47
46
45
44
43
42
41
40
39
38
37
0.1U_0402_25V6
2
THERM_ 220K 5% 0402 @ 1 2
CSP_1a_VCORE_R [50]
PRI25
2
1
1 2
VSN_2ph
VSP_2ph
VSP_1b
VSN_1b
COMP_1b
ILIM_1b
CSN_1b
CSP_1b
IOUT_1b
EN
TAB
PSYS
VR_RDY
2
PCI15 PUI1 VR_HOT# [34] PRI29
PRI26
PRI27
PRI33
OCP for VGT 15P_0402_50V8J NCP81208-MNTXG_QFN48_6X6 12K_0402_1%
RPH@GT: 2
1 2
PRI31 PRI32 IOUT_2ph_CPU 1 36 PCI17 1 2
6800P_0402_25V7K
165K_0402_1% 75K_0402_1% DIFFOUT_2ph_CPU 2 IOUT_2ph PWM_1b 35 PRI36 49.9_0402_1% 470P_0402_50V7K CSN_1a_VCORE_NTC
0.022U_0402_16V7K
1 2 1 2 1 2 PRI39 PCI16 FB_2ph_CPU 3 DIFFOUT_2ph DRVON 34 SCLK_CPU 1 2 1 2
[50] CSP1_VGT1 FB_2ph SCLK VR_SVID_CLK [14]
1
1
PRI30 84.5K_0603_1% 12.4K_0402_1% 2200P_0402_50V7K COMP_2ph_CPU 4 33 @ PRI37 1
ALERT#_CPU 2 0_0402_5%
PCI20
VR_ALERT# [14] Close to VCORE choke
2
PCI18 PCI19 @ 1 2 ILIM_2ph_CPU 5 COMP_2ph ALERT# 32 SDIO_CPU PRI40 1 2 10_0402_1% PRI42 PHI3
PCI21
ILIM_2ph SDIO VR_SVID_DATA [14]
1
1000P_0402_50V7K 1000P_0402_50V7K CSCOMP_2ph_CPU 6 31 VR_HOTL# PRI41 1 2 100_0402_1% 64.9K_0402_1% 100K_0402_1%_NCP15WF104F03RC
2
CSSUM_2ph_CPU 7 CSCOMP_2ph VR_HOT# 30 IOUT_1a_CPU 1 2

1 2 CSREF_2ph_CPU 8 CSSUM_2ph IOUT_1a 29 CSP_1a_VCORE
[50] CSN1_VGT1
2
PRI44 10_0402_1% CSP2_2ph_CPU 9 CSREF_2ph CSP_1a 28
CSP2_2ph CSN_1a CSN_1a_VCORE [50]
1
CSP1_2ph_CPU 10 27 ILIM_1a_CPU
ROSC_COREGT
0.1U_0402_25V6
TSENSE_2ph_CPU_R 1 2 TSENSE_2ph_CPU 11 CSP1_2ph ILIM_1a 26 COMP_1a_CPU
ADDR_VBOOT
PCI22
TSENSE_2ph COMP_1a
1
1
TSENSE_1ph
RSOC_SAUS
ICCMAX_2ph
@ PRI45 0_0402_5% 1 2 12 25
ICCMAX_1a
ICCMAX_1b
B+ PCI24
2
VRMP VSN_1a
PWM1_2ph
PWM2_2ph
1
PCI26 PRI46 1000P_0402_50V7K PCI27
VRMP_CPU
100K_0402_1%_NCP15WF104F03RC
PWM_1a
1
1 2 VSN_1a_CPU_R
VSP_1a
0.01U_0402_50V7K 1K_0402_1% PCI25 PCI29 1000P_0402_50V7K
2
2
PHI4 PRI48 15P_0402_50V8J 1500P_0402_50V7K
VCC
1 2
1
61.9K_0402_1% PCI28 PRI49 @ PRI50 PRI51
1
1000P_0402_50V7K 1K_0402_1% 0_0402_5% 100_0402_1%
1
CSP1_VGT1 1 2 PCI30 1
VSN_1a_CPU 2 1 2 1 2 PRI52 PRI53
2
13
14
1ROSC_SAUS_CPU 15
16
17
18
19
20
21
22
23
24
PRI47 2K_0402_1% 0.01U_0402_50V7K 2.49K_0402_1% 33.2K_0402_1%
1
PCI31 VSSCORE_SENSE [14]
2
C C
1 2 1000P_0402_50V7K
ICCMAX_2ph_CPU
+5VS
2
ADDR_VBOOT_CPU
VCC_CPU
ICCMAX_1a_CPU
ICCMAX_1b_CPU
PRI54 Close to VGT1 MOS
2
+5VS PRI55 RDRPSP PRI56 @ PRI57 OCP for VCORE
1K_0402_1% 2_0402_1% 2.1K_0402_1% 0_0402_5%
1 2 1 2VSP_1a_CPU_R 1 2 VCCCORE_SENSE
+VCCCORE
[14]
1ROSC_COREGT_CPU
VSP_1a_CPU 1 2 1 2 1 2
24K_0402_1%
2.1K_0402_1% PRI58 100_0402_1%
1
472mV/120uA=3.933K PCI32 PRI115
PRI60
U22 OCP@GT= 40A Active Point110 degreeC = 4.206K PCI33 1000P_0402_50V7K
1U_0603_10V6K @ PRI61 PRI51, PRI58 place near CPU side.
RLIM@GT=12.4K --->PRI39
2
TSENSE_1ph_CPU 1 2 TSENSE_1ph_CPU_R If the resisters are at HW side and POP. PRI51, PRI58 can be canceled.
2 0_0402_5%
1
RLIM= IoutLIMIT * Load line/10
1000P_0402_50V7K
33.2K_0402_1%
61.9K_0402_1%
1
1
Fsw for SA
2
PWM_1a_CPU [50] PHI5 U22 Load line@VCORE= 2.35m
PRI59
PCI34
100K_0402_1%_NCP15WF104F03RC
RDRPSP@VCORE=2.1K --->PRI56
U22 IccMAX@GT= 31A
PRI62
10K_0402_1%
48.7K_0402_1%
88.7K_0402_1%
15.8K_0402_1%
RIccMAX2ph= 48.7K --->PRI63 Fsw for CORE & GT
2
2
Close to VCORE MOS RDRPSP= Load line*(RPHSP+Rth+RCSSP)
/(gm * DCR) /(Rth+RCSSP)
RIccMAX2ph= (IccMAX2Ph+32)*200K Ohn/ 127 NCP81208 Operating Frequency Rosc=24K
I/A and GT are 450KHz and SA is 450KHz
1
1
IccMAX@VCORE= 28A
472mV/120uA=3.933K RIccMAX@VCORE= 87.6K --->PRI64
Active Point110 degreeC = 4.206K
U22 Iout@GT= 31A
RIccMAX2ph RIccMAX@VCORE= IccMAX*2V/10uA/64A
PRI63
PRI64
PRI65
PRI66
RIOUT@GT=25.5K --->PRI23
2
RIOUT= 2* RLIM /(10 *IOUTICCMAX * Load line) IOUTSP@VCORE= 28A

RIOUTSP@VCORE=64.9K --->PRI42
VBOOT:
22.1K for debuge setting. RIOUTSP= 2V/(gm*(Rth+RCSSP)*ICCMAX*DCR
U22 Load line@GT= 3.1m /(RPHSP+Rth+RCSSP))
D D
RPH@GT=84.5K --->PRI30,PRI38
PWM1_2ph_CPU [50]
OCP@VCORE= 35A
Load line= (RCS2+(RCS1*Rth/(RCS1+Rth))) RLIMSP@VCORE=33.4K --->PRI53
*IOUTTOTAL * DCR/RPH
RLIMSP= 1.3V/(gm*(Rth+RCSSP)*IoutLIMIT*DCR
/(RPHSP+Rth+RCSSP))
Title
NCP81208
Size Document Number Rev
A

1 2 3 4 5
1 2 3 4 5
CPU POWER STAGES

InputCapacitor:
EMI@ PLI1
CPU_B+ 10uF_0805_X5R_25V 5A_Z120_25M_0805_2P B+
1 2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
22P_0402_50V8J
0.1U_0402_25V6
@EMI@ PCI40
PCI41
1
100U_25V_NC_6.3X6
@ PCI98
1
1
+
PCI38
PCI39
PCI94
PCI95
PC135
EMI@
2
2
2
5
PRI68 PCI42
2.2_0603_5% 0.22U_0603_16V7K
1 2BST_VCORE_R 1 2
A A
PRI114
BST_VCORE
0_0603_5%
UG_VCORE 1 2UG_VCORE_R 4
PQI6
MDU1516URH_POWERDFN56-8-5
PUI2 VCC_CORE
3
2
1
NCP81253MNTBG_DFN8_2X2 FSW=450kHz
PLI3
1 8 0.24UH_22A_+-20%_7X7X3_M +VCCCORE DCR = 1.19 mohm +/- 5%
BST DRVH
2 7 LX_VCORE 1 4
TYP MAX
[49] PWM_1a_CPU PWM SW H/S Rds(on) :11.7mohm , 14mohm
330U_D1_2VY_R9M
DRVON 3 6 2 3
+5VS EN GND 1
PCI90
L/S Rds(on) :2.7mohm , 3.3mohm
5
4 5 PQI7 +
PAD
VCC DRVL
1
@EMI@
MDU1511RH_POWERDFN56-8-5
1
PRI71 CSN_1a_VCORE [49] 2

9
PCI43 4.7_1206_5%
2.2U_0603_16V6K LG_VCORE 4
2
2
SNB_VCORE CSP_1a_VCORE_R [49]
3
2
1
1
@EMI@
PCI45
680P_0603_50V7K
2
B B
VCCGT_B+ EMI@ PLI2

5A_Z120_25M_0805_2P B+
1 2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
@EMI@ PCI46
PCI47
1
100U_25V_NC_6.3X6
PRI73
1
+
PCI50
PCI51
PCI96
PCI97
2.2_0603_5%
PC148
BST1_VGT1 1 2 BST1_VGT1_R
EMI@
2
2
5
PQI2 2
1
PCI57
VCCGT
UG_VGT1_R
0.22U_0603_16V7K 4
2
PUI3 FSW=450kHz
NCP81151MNTBG_DFN8_2X2
[49] PWM1_2ph_CPU
1 9 PRI112 MDU1516URH_POWERDFN56-8-5 DCR = 1.19 mohm +/- 5%
BST FLAG 0_0603_5% PLI4 TYP MAX
3
2
1
2 8 UG_VGT1 1 2 0.24UH_22A_+-20%_7X7X3_M
PWM DRVH +VCCGT H/S Rds(on) :11.7mohm , 14mohm
3 7 LX_VGT1 1 4
[49] DRVON EN SW L/S Rds(on) :2.7mohm , 3.3mohm
PRI77 @EMI@
4 6 2 3
VCC GND
5
4.7_1206_5%
+5VS 5 LG_VGT1 PQI3

DRVL
MDU1511RH_POWERDFN56-8-5
1
330U_D1_2VY_R9M
PCI58
2.2U_0603_16V6K 4 + PCI92
2
SNUB_VGT1 2
CSN1_VGT1 [49]
C C
2
PCI64 @EMI@
3
2
1
CSP1_VGT1 [49]
680P_0603_50V7K
1
2
CPU_B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
@EMI@ PCI67
PCI68
1
1
PCI65
PCI66
EMI@
PRI83 PCI69
2
2.2_0603_5% 0.22U_0603_16V7K
1 2 BST_VCCSA_R 1 2
VCCSA
BST_VCCSA
FSW=450kHz
UG_VCCSA
DCR 6.2mohm(TYP), 6.51mohm(Max)
TYP MAX
PUI5 PQI1 H/S Rds(on) :12.4mohm , 15.8mohm
4
NCP81253MNTBG_DFN8_2X2 AON7934_DFN3X3A8-10
L/S Rds(on) :9.1mohm , 11.6mohm
D1
D1
D1
G1
1 8
PLI6
+VCCSA
BST DRVH
[49] PWM_1b_CPU 2 7 10 9 LX_VCCSA 1 4
D
PWM SW D1 D2/S1 D
PRI84
DRVON 3 6 2 3
+5VS EN GND
4.7_1206_5%
G2
S2
S2
S2
4 5
PAD
VCC DRVL 0.47UH_MMD05CZR47M_12A_20%

5
@EMI@
1
9
2.2U_0603_16V6K
PCI70
CSN_1b_VCCSA [49]
2
SNB_VCCSA
680P_0603_50V7K
PCI71
1
LX_VCCSA CSP_1b_VCCSA_R [49] Title

Power Stage
2
@EMI@
LG_VCCSA Size Document Number Rev

A

1 2 3 4 5
A
B
C
D
2
1
PC1374
22U_0603_6.3V6M
2
1
+VCCGT
PC1375
22U_0603_6.3V6M
+VCCCORE
2
1
PC1376
22U_0603_6.3V6M
2
1
5
5
PC1377
22U_0603_6.3V6M
2
1
2 1 2 1 2 1
2
1
PC1378
22U_0603_6.3V6M PC1365 PC1350 PC1327 PC1301
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1 2 1 2 1
2
1
PC1379
22U_0603_6.3V6M PC1366 PC1351 PC1328 PC1302
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1 2 1 2 1
2
1
PC1391
22U_0603_6.3V6M PC1367 PC1352 PC1329 PC1303
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1 2 1 2 1
2
1
PC1392
22U_0603_6.3V6M PC1368 PC1353 PC1330 PC1304
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1 2 1 2 1
2
1
PC1393
22U_0603_6.3V6M PC1369 PC1354 PC1331 PC1305
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1 2 1 2 1
2
1
PC1394
22U_0603_6.3V6M PC1370 PC1355 PC1332 PC1306
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
22U_0603 * 13 pcs +1U_0201*35 pcs
2
1
2 1 2 1 2 1
2
1
PC1395
22U_0603_6.3V6M PC1371 PC1356 PC1333 PC1307
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
VCC_CORE Place on CPU Back Side @ V09
2
1
2 1 2 1 2 1
2
1
PC1396
22U_0603_6.3V6M PC1372 PC1357 PC1334 PC1308
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
PC1373 PC1358 PC1335 PC1309

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
4
4
2
1
PC1359 PC1336 PC1310

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
+VCCSA
2 1 2 1
PC1405
22U_0603_6.3V6M PC1360 PC1337
2
1
1U_0201_6.3V6M 1U_0201_6.3V6M
2
1
2 1 2 1 PC1311
PC1402 22U_0603_6.3V6M
22U_0603_6.3V6M PC1361 PC1338
2
1
1U_0201_6.3V6M 1U_0201_6.3V6M
2
1
2 1 2 1 PC1312
PC1404 22U_0603_6.3V6M
22U_0603_6.3V6M PC1362 PC1339
2
1
1U_0201_6.3V6M 1U_0201_6.3V6M
2
1
PC1313
PC1403 22U_0603_6.3V6M
22U_0603_6.3V6M
2
1
2
1
PC1406
PC1401 22U_0603_6.3V6M
22U_0603_6.3V6M
2
1
2
1
2
1
PC1410
@
PC1398 PC1414 22U_0603_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
2
1
2
1
PC1408
@
PC1399 PC1413 22U_0603_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
2
1
2
1
PC1409
@ PC1397 PC1415 22U_0603_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
2
1
PC1407
PC1417 22U_0603_6.3V6M
22U_0603_6.3V6M
2
1
2
1
2
1
PC1380 PC1411
3
3
22U_0603_6.3V6M PC1421 22U_0603_6.3V6M

22U_0603_6.3V6M
2
1
2
1
2
1
PC1381 PC1412
@
22U_0603_6.3V6M PC1419 22U_0603_6.3V6M

22U_0603_6.3V6M
2
1
2
1
PC1382
22U_0603_6.3V6M PC1418
22U_0603_6.3V6M
2
1
2
1
PC1383
Issued Date
22U_0603_6.3V6M PC1416
2 1 22U_0603_6.3V6M
2
1
2
1
PC1384
@
1U_0201_6.3V6M PC1420 PC1423

2 1 22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
2
1
PC1385
1U_0201_6.3V6M PC1422 PC1424
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
PC1386
1U_0201_6.3V6M PC1425
2 1 22U_0603_6.3V6M
VCC_SA Place on CPU Back Side @ V09
PC1387
1U_0201_6.3V6M
2011/06/24
2 1
PC1388
+VCCGT
1U_0201_6.3V6M
2 1
PC1389
1U_0201_6.3V6M
2 1
PC1390
2
2
1U_0201_6.3V6M
Compal Secret Data
22U_0603 * 12 (4 CPU back+8 outside)pcs + 1U_0201*7
2 1 2 1
2
1
Deciphered Date PC1363 PC1340 PC1314

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
PC1364 PC1341 PC1315

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1
PC1342 PC1316
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1
PC1343 PC1317
2012/07/12
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1
PC1344 PC1318
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1
PC1345 PC1319
1U_0201_6.3V6M 22U_0603_6.3V6M
Size
Title
Date:
2 1
2
1
PC1346 PC1320
1U_0201_6.3V6M 22U_0603_6.3V6M
VCC_GT Place on CPU @ V09
2 1
2
1
PC1347 PC1321
1U_0201_6.3V6M 22U_0603_6.3V6M
Document Number
2 1
2
1
PC1348 PC1322
1U_0201_6.3V6M 22U_0603_6.3V6M
22U_0603 * 32 pcs +1U_0201*12 pcs
2 1
2
1
Wednesday, March 04, 2015

1
1
PC1349 PC1323
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
PC1324
22U_0603_6.3V6M
Sheet
2
1
PC1325
51
22U_0603_6.3V6M
2
1
of
PC1326
22U_0603_6.3V6M
53
Rev
PWR-PROCESSOR_DECOUPLING
0.1
A
B
C
D
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase
1 reserve 0.1uF for ESD P41/P47 add PC1236,PC1237 2014.10.30 SIV

D D
C C
9
10
11
12
13
14
B B
15
16
17
A A

PIR (PWR)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
ZIWB2/ZIWB3/ZIWE1 HW PIR List

Item Page MODIFICATION LIST PURPOSE
EVT TO DVT
1 P.36 Modify DP_SEL schematic Because the first design is wrong.
D 2 P.34 Delete D28 It already reserve in sub BD D
3 P.36 Modify HPD schematic Because the first design is wrong.

4 P.36 Modify DP AUX schematic Cap already reserve in sub BD
5 P.20 Reserve +1.05VS to +0.95VGS AMD's suggestion
6 P.33 Add D26 for ESD
7 P.42 Add RV198, RV199 AMD's suggestion
8 P.22~24 Add GPU Termination Resistance AMD's suggestion
DVT TO PVT
1 P.35 change U11.111 power rail to +3VLP It only use +3VLP
2 P.33 un-pop R294, pop R295. B series's LED need to follow E series
3 P.10 Add R247, R248 For BIOS Stap Pin
4 P.20 Add RV60, delete RV36 for GPU Sequence
C C
5 P.20 Add RV61, delete RV240 for GPU Sequence

6 P.37 Change DP Switch IC solution For HDMI audio issue
7 P.35 Add C197 for ESD
PVT TO PRE-MP
1 P.33 Reserve R298, R299 for DC-in LED control To avoid LED shimmer
2 P.38 Change DL1 and DL2 footprint for ESD
B B
A A

HW-PIR1
5 4 3 2 1

Compal LA-D101P r0.1

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A B C D E

Security Classification Compal Secret Data Compal Electronics, Inc.

For DIS Memory Bus

VRAM 1GB/2GB DDR3L 1600MHz (1.35V)

eDP X1 Left USB3.0 x2 Right USB2.0 x1 Int. Camera

I2C X1 NFC Conn.

PCIe X1 Audio Codec

Thermal Sensor Touch Pad Int. KBD APS

Security Classification Compal Secret Data Compal Electronics, Inc.

Voltage Rails USB Port Table

D Full ON HIGH HIGH HIGH HIGH ON ON ON ON D

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

EXO Pro / MESO XT VRAM STRAP Power-Up/Down Sequence

ZZZ ZZZ ZZZ VDDR3(+3VGS)

JH2G@ JM2G@ JS2G@

JH1G@ JM1G@ JS1G@ VDDC/VDDCI(+VGA_CORE)

Global ASIC Reset

Security Classification Compal Secret Data Compal Electronics, Inc.

SOC_DP1_CTRL_DATA(Internal Pull Down):

Trace width=20 mils, Spacing=25mil, Max length=100mils

RC4 UC1D SKL-U

1 2 H_THERMTRIP# 1 2 H_PROCHOT#_R C65 PECI

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

SML0ALERT# (Internal Pull Down):

0 = LPC is selected for EC ==> Default

1 = eSPI is selected for EC

[31,34] SERIRQ SERIRQ AY11

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

RC37 1 2 20K_0402_5% SOC_RTCRST#

A RC53 1 2 60.4_0402_1% EC_VCCST_PG A

Security Classification Compal Secret Data Compal Electronics, Inc.

GSPI0_MOSI (Internal Pull Down):

0 = Disable No Reboot mode. ==> Default

1 = Enable No Reboot Mode. (PCH will disable the TCO

GSPI1_MOSI (Internal Pull Down):

Boot BIOS Strap Bit

0 = SPI Mode ==> Default

BIOS Strap Pin

Function GPPA23 Function GPPA12

RC120 1 @ 2 10K_0402_5% PCH_GPPA23 RC128 1 UMA@ 2 10K_0402_5% DGPU_PRSNT#

Function GPPC10 Function GPPA20

Security Classification Compal Secret Data Compal Electronics, Inc.

CC11 CC14 CC15 CC16

CC17 CC18 CC101 CC102

PCIE / USB3 / SATA SSIC / USB3

USB_OC0# RC72 1 2 10K_0402_5%

USB_OC1# RC73 1 2 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

TPS22961DNYR_W SON8 Close to A18 Close to K20 Close to A22

Security Classification Compal Secret Data Compal Electronics, Inc.

RC86 1 RS@ 2 0_0402_5% AF21

+3VS +1.0VALW +3VALW +1.8VALW

Close to AG15 Close to Y16 Close to T16 Close to AK17

Security Classification Compal Secret Data Compal Electronics, Inc.

+VCCCORE +VCCCORE +VCCGT +VCCGT

VSSGT_SENSE J69 AL61 VSSGTX_SENSE T162 TP@