DTE Question Bank Solution

(I) Attempt any four of the following (4x2=8 Marks)

1) Explain the necessity of multiplexer

Ans: - It reduces number of wires required to pass data from source to destination
- It is used to minimize hardware circuits
- It is used to simplify logic design
- Reduces the cost by reducing the number of input lines
2) State the necessity of demultiplexer

Ans: - It is used in communication system to carry out the process of data transmission
- The output of the ALU can be stored in multiple registers using demultiplexer
- It is used in serial to parallel convertor
- It is used at receivers end in the time-division multiplexing
3) What is an Encoder? List any two types of encoder.

Ans: An encoder is a combinational logic circuit that has 2n number of inputs and n number of
outputs. The 2n inputs are digital signals of a number and n number of outputs are the binary
encoded number of that signal
Types of Encoder:
1. Octal to Binary Encoder
2. Decimal to BCD Encoder
4) Draw a 4 variable K-Map

Ans:

5) What is a decoder? State any two uses of BCD to 7 segment decoder.

Ans: A decoder is a combinational logic circuit that has ‘n’ number of inputs and 2n number of
outputs. It takes coded binary input and generates digital signals for them.
Use of BCD to 7 segment decoder:
- Digital displays
- Calculator
- Indicators
- Digital Clocks
 6) Explain different triggering method

Ans: There are two types of triggering methods:

(i) Level Trigger: This is the type of triggering technique that allows circuit to become
active at a particular level. There are two types of level trigger: a) Positive Level
Trigger b) Negative Level Trigger

(ii) Edge Trigger: This is the type of triggering technique that allows circuit to become
active at the time of transition from positive to negative level or negative to positive
level. There are two types of edge trigger a) Positive edge trigger b) Negative edge
trigger

7) Draw Symbol and truth table for T flip flop

Ans:

8) Draw Symbol and truth table for D flip flop

Ans:

9) Write down number of flip flops required to count 16 clock pulses

Ans: No. of clock pulse: 16

No. of unique state = 16 i.e., 24

Therefore, it requires 4 flip-flops to count 16 clock pulses

 10) Define modulus of a counter. Write number of flip-flops required for MOD-5
counter

Ans: - The modulus of a counter refers to the number of times an event occurs inside a digital
circuit.
- For a MOD-5 counter, the number of flip-flops required is determined by calculating
the number of flip-flops needed to represent the number of states in binary form i.e., 0-4.
- Since max state is 4 which can be represented as 100 in binary and has three bits, the
number of flip flop required is 3

11) State the function of preset and clear in flip flop

Ans: In the flip flop, when the power is switched on, the state of the circuit is uncertain i.e.,
may be Q = 1 or Q = 0. Hence, the function of preset is to set a flip flop i.e., Q = 1and the
function of clear is to clear a flip flop i.e., Q = 0.

12) List the basic types of shift registers

Ans: Types of shift registers are as follows:

1. Serial-In-Serial-Out (SISO) Shift Register:
2. Serial-In-Parallel-Out (SIPO) Shift Register:
3. Parallel-In-Serial-Out (PISO) Shift Register:
4. Parallel-In-Parallel-Out (PIPO) Shift Register:
OR
1. Left Shift Register
2. Right Shift Register
3. Universal Shift Register
4. Bidirectional Register

13) List the types of DAC

Ans: Weighted Digital to Analog Converter

R-2R Network
14) Differentiate between SRAM and DRAM (any four points)

Ans:
 15) List different types of RAMs

Ans: Static Random Access Memory (SRAM)

Dynamic Random Access Memory (DRAM)

(II) Attempt any three of the following (3x4 = 12)

1) Minimize the following expression using K-Map and realize it.
F(ABCD) = ∑m (1,5,6,7,11,12,13,15)

Ans:

2) Describe function of full adder circuit with the help of logic diagram and truth
table

Ans: A full adder is a combinational logic circuit that has 3 inputs and 2 outputs. The two
outputs are Sum and Carry.

Truth table:
K-Map:

Circuit Diagram:

3) Design Binary-to-Gray converter

Ans: Truth table for 4-bit Binary to Gray Converter

Circuit Diagram:

4) Design 16:1 MUX using 4:1 MUX

Ans:
 5) Design 4-bit BCD adder using IC 7483

Ans:

6) Describe the working of SR flip flop with its truth table and logic diagram

Ans:

Fig: SR flip-flop

Truth Table:

Working:

When clock = 0, the outputs of NAND gates 3 and 4 will be forced to be 1 irrespective of the
values of S and R. That means R’= S’ = 1. Hence the outputs of basic SR FF i.e. Q n+1 and
will not change. Thus, if clock = 0, then there is no change in the output of the clocked SR flip-
flop.

Case I: S = R = 0, clock = 1: No change

If S=R=0 then outputs of NAND gate 3 and 4 are forced to become 1. Hence R' and S' both
will be equal to 1. Since R' and S' are the inputs of the basic S – R flip-flop using NAND gates.
There will be no change in the state of outputs.
Case II: S =1, R = 0, clock = 1: Set
Now S=0, R=1 and a positive going edge is applied to the clock Output of NAND 3 i.e., R’ =
0 and output of NAND 4 i.e., S’ = 1. Hence output of SR flip-flop is Q = 1 and Q’ = 0.
This is the set condition.

Case III: S =0, R = 1, clock = 1: Reset

Now S=0, R=1 and a positive edge is applied to the clock input.
Since S=0, output of NAND – 3 i.e., R ́= 1. And as R’ = 1 and clock = 1 the output of NAND-
4 i.e., S ́ = 0. Hence output of SR flip-flop is Q = 0 and Q’ = 1.
This is the reset condition.

Case IV: S =1, R = 1, clock = 1: Undefined/ forbidden

As S=1, R=1 and clock = 1, the outputs of NAND gates 3 and 4 both are 0 i.e., S' = R'=0. So,
both the outputs Q and Qn+1 = 1 and Hence output is Undefined/ forbidden.

7) Explain the working of MS JK flip flop with the help of logic diagram and truth
table

Ans: Master Slave JK flip flop

Truth table:

Working: The input signals J and K are connected to the gated “master” SR flip flop which
“locks” the input condition while the clock (Clk) input is “HIGH” at logic level “1”. As the
clock input of the “slave” flip flop is the inverse (complement) of the “master” clock input, the
“slave” SR flip flop does not toggle. The outputs from the “master” flip flop are only “seen”
by the gated “slave” flip flop when the clock input goes “LOW” to logic level “0”.
When the clock is “LOW”, the outputs from the “master” flip flop are latched and any
additional changes to its inputs are ignored. The gated “slave” flip flop now responds to the
state of its inputs passed over by the “master” section.
Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are
fed through to the gated inputs of the “slave” flip flop and on the “High-to-Low” transition the
same inputs are reflected on the output of the “slave” making this type of flip flop edge or
pulse-triggered.
Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to
the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop
is a “Synchronous” device as it only passes data with the timing of the clock
signal.
The input signals J and K are connected to the gated “master” SR flip flop which “locks” the
input condition while the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of
the “slave” flip flop is the inverse (complement) of the “master” clock input, the “slave” SR
flip flop does not toggle. The outputs from the “master” flip flop are only “seen” by the gated
“slave” flip flop when the clock input goes “LOW” to logic level “0”.
When the clock is “LOW”, the outputs from the “master” flip flop are latched and any
additional changes to its inputs are ignored. The gated “slave” flip flop now responds to the
state of its inputs passed over by the “master” section.
Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are
fed through to the gated inputs of the “slave” flip flop and on the “High-to-Low” transition the
same inputs are reflected on the output of the “slave” making this type of flip flop edge or
pulse-triggered.
Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to
the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop
is a “Synchronous” device as it only passes data with the timing of the clock signal.
8) Design Synchronous Decade Counter using D flip flop

Ans: Step 1: Find the number of flip-flops needed

M≤ N
M is the MOD which is 10 ≤ 24
Therefore, Number of flip-flops needed is 4
Step 2: Excitation table of D flip-flop
Step 3: Circuit state table using excitation table of D

Step 4: Prepare K-Map for each flip flop

K-Map for DA,

𝐷𝐴 = 𝑄𝐴 ̅̅̅̅
𝑄𝐷 + 𝑄𝐵 𝑄𝐶 𝑄𝐷
K-Map for DB,

𝐷𝐵 = 𝑄𝐵 ̅̅̅̅
𝑄𝐶 + 𝑄𝐵 ̅̅̅̅
𝑄𝐷 + ̅̅̅̅
𝑄𝐵 𝑄𝐶 𝑄𝐷
K-Map for DC,

𝐷𝐶 = ̅̅̅̅
𝑄𝐴 ̅̅̅̅ ̅̅̅̅
𝑄𝐶 𝑄𝐷 + 𝑄𝐶 𝑄 𝐷

K-Map for DD,

̅̅̅̅
𝐷𝐷 = 𝑄 𝐷

Circuit Diagram:

Fig: Decade Counter using D flip-flop

9) Design a 4-bit synchronous counter and draw its logic diagram

Ans: State Table:

K-Map:

Logic Diagram:
 10) Draw 4-bit Johnson counter and explain working and truth table

Ans: The twisted ring counter refers to as a switch-tail ring counter. The complimented output
of last flip flop is connected to the input of first flip-flop

Fig: 4-bit Twisted Ring Counter

A 4-bit Johnson ring counter passes blocks of four logic “0” and then four logic “1” thereby
producing an 8-bit pattern. As the inverted output Q is connected to the input D this 8-bit pattern
continually repeats. For example, “1000”, “1100”, “1110”, “1111”, “0111”, “0011”, “0001”,
“0000”

Observation Table:

Timing/Waveform Diagram:
 11) Describe the operation of 4 bit serial in serial out register

Ans: The input in this type of register is serially fed and output is received serially

Fig: 4-bit Serial-In-Serial-Out Register

Working:
• At first, all the four D flip-flops are set to reset mode so that each flip-flop’s output is
low i.e., ‘0’
• The data input is given at the left end of the flip flop
• In this 4-bit shift register we have taken input as ‘1111’.
• When the first clock signal is received, the first input is received at the D3 as ‘1’ which
in-turn converts Q3 to ‘1’. Meanwhile, D2=D1=D0=0
• When the second clock pulse is applied the output of the first flip-flop is applied to the
second flip-flop. Whereas, D3 accepts the second bit input. Now, both D2 and D3 is high
i.e., ‘1’ and D1=D0=0
• When the third clock pulse is applied the output of the first flip-flop goes into the second
flip-flop as input and the output of the second flip-flop goes into the third flip-flop as
input, thereby, turning Q3=Q2=Q1=1 and Q0 stays zero
• When the fourth pulse is applied all the four bits are read by the flip flop and the outputs
are Q3=Q2=Q1=Q0=1.
• This is how the four bits are stored in the flip-flop
• Similarly, for reading it takes 4 clock pulse and is done by shifting one bit right at every
clock pulse

Truth table:

CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
 12) Compare the following: (any four points) (i) EPROM and EEPROM (ii) Volatile
and Non-Volatile memory

Ans: EPROM and EEPROM:

Volatile and Non-Volatile Memory: