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    EX#1

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    Mariam Maher
    This document contains an exercise assignment for an electronic circuits course. It includes 7 problems analyzing various circuit configurations including cascode circuits, current mirrors, and amplifiers. The student is asked to determine output resistances, voltages, currents, and gains for the different circuits. They are also asked to design a CMOS cascode amplifier and current mirror circuits meeting specific requirements.

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    EX#1

    Uploaded by

    Mariam Maher
    21 views2 pages
    This document contains an exercise assignment for an electronic circuits course. It includes 7 problems analyzing various circuit configurations including cascode circuits, current mirrors, and amplifiers. The student is asked to determine output resistances, voltages, currents, and gains for the different circuits. They are also asked to design a CMOS cascode amplifier and current mirror circuits meeting specific requirements.

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    circuits

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    EX#1 (3)

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    This document contains an exercise assignment for an electronic circuits course. It includes 7 problems analyzing various circuit configurations including cascode circuits, current mirrors, and amplifiers. The student is asked to determine output resistances, voltages, currents, and gains for the different circuits. They are also asked to design a CMOS cascode amplifier and current mirror circuits meeting specific requirements.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    21 views2 pages

    EX#1

    Uploaded by

    Mariam Maher
    This document contains an exercise assignment for an electronic circuits course. It includes 7 problems analyzing various circuit configurations including cascode circuits, current mirrors, and amplifiers. The student is asked to determine output resistances, voltages, currents, and gains for the different circuits. They are also asked to design a CMOS cascode amplifier and current mirror circuits meeting specific requirements.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    Ain Shams University Electronic Circuits (2)

    Faculty of Engineering ECE 315


    ECE Dept. Fall 2023
    iCHEP Dr. Mostafa G. Ahmed
    Exercise 1
    1. Due to a manufacturing error, a parasitic resistor RP has appeared in the cascode circuits of Fig. 1.
    Determine the output resistance in each case.

    2. While constructing a cascode stage, a student adventurously swaps the collector and base terminals
    of the degeneration transistor, arriving at the circuit shown in Fig. 2.
    a. Assuming both transistors operate in the active region, determine the output impedance of the
    circuit.
    b. Compare the result with that of a cascode stage for a given bias current (IC1) and explain why
    this is generally not a good idea.

    3. The cascode current source shown in Fig. 3 must be designed for a bias current of 0.5 mA. Assume
    nCox = 100 A/V2 and VTH = 0.4 V.
    a. Neglecting channel-length modulation compute the required value of Vb2. What is the minimum
    tolerable value of Vb1 if M2 must remain in saturation?
    b. Assuming  = 0.1 V-1, calculate the output impedance of the circuit.

    4. Calculate the voltage gain of each stage illustrated in Fig. 4.

    5. Design the CMOS cascode amplifier of Fig. 5 for a voltage gain of 200 and a power budget of 2
    mW with VDD = 1.8 V. Assume (W/L)2 = (W/L)3 = (W/L)4 = 20/0.18 and p = 2n = 0.2 V-1. Determine
    the required DC levels of Vin and Vb3 and find (W/L)1. For simplicity, assume Vb1 = Vb2 = 0.9 V.

    6. We wish to generate two currents equal to 50 A and 230 A from a reference of 130 A. Design
    an npn current mirror for this purpose. Neglect the base currents.

    7. Calculate Icopy in each of the circuits shown in Fig. 6. Assume all of the transistors operate in
    saturation.

    8. (Simulation) Plot Vout/Vin as a function of frequency for the amplifier of problem 5.

    Figure 1
    Figure 2 Figure 3

    Figure 4

    Figure 5

    Figure 6

    Page 2 of 2

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