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    UEC750

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    Shivam Sharma
    This document appears to be an exam for a course on MOS Circuit Design. It contains 5 questions covering topics like inverter design, CMOS logic gates, transmission gates, and small signal analysis. The questions involve circuit analysis, design, and derivation of key parameters. The exam is out of 100 marks and has multiple sub-questions under each main question.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    UEC750

    Uploaded by

    Shivam Sharma
    72 views2 pages
    This document appears to be an exam for a course on MOS Circuit Design. It contains 5 questions covering topics like inverter design, CMOS logic gates, transmission gates, and small signal analysis. The questions involve circuit analysis, design, and derivation of key parameters. The exam is out of 100 marks and has multiple sub-questions under each main question.

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    question paper

    Original Title

    UEC750 (1)

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    This document appears to be an exam for a course on MOS Circuit Design. It contains 5 questions covering topics like inverter design, CMOS logic gates, transmission gates, and small signal analysis. The questions involve circuit analysis, design, and derivation of key parameters. The exam is out of 100 marks and has multiple sub-questions under each main question.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    72 views2 pages

    UEC750

    Uploaded by

    Shivam Sharma
    This document appears to be an exam for a course on MOS Circuit Design. It contains 5 questions covering topics like inverter design, CMOS logic gates, transmission gates, and small signal analysis. The questions involve circuit analysis, design, and derivation of key parameters. The exam is out of 100 marks and has multiple sub-questions under each main question.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    Roll No:

    Thapar Institute of Engineering & Technology, Patiala


    Department of Electronics and Communication Engineering

    B.E. 3rd Year (ECE) - EST Date: December 7, 2019


    Course Name: MOS Circuit Design Course Code: UEC750
    Time: 3 Hours MM: 100 Faculty: Dr. Alpana Agarwal, Dr. lilanu Bansal,
    Dr. Anil Singh, Dr Subimart Chatterjee

    1 (a) Given VDO = 5 V, kn' = 30 µA/V2 and VTO = 1 V, design a resistive load 8+2
    inverter circuit with VOL = 200 mV. Specifically, determine the (W/L)
    ratio of the driver transistor and the value of load resistor RL that
    achieves the required VOL. Find RL for various values of W/L ratio.

    (b) Derive the switching threshold voltage of a 2-input CMOS NOR gate 10
    using equivalent inverter approach.
    2 (a) Draw the schematic of 3-input NOR gate using CMOS logic style.

    (b) Write the Euler's paths for n and p networks and find the common 6
    Euler's path. Draw its colour stick diagram in 2-metal n-well CMOS
    process.

    (c) Design a pseudo nMOS inverter such that its switching threshold 10
    voltage is 1.5 V. Given the following device parameters:

    nM OS: VTO,n= 0.6 V, ki,' = 60 pA/V 2


    pM OS: VTO,p= -0.8 V, kp'.= 20 µA/V2
    VD!) = 3.0 V, A = 0 and y = O.
    3 (a) Consider a CMOS inverter circuit which contains following parameters: 10
    VOD = 3.3 V, V-ro.n= 0.6 V, VTO,p= -0.7 V, kp=200 pA/V 2, kp=80 pA/V2 . Find
    the noise margin of the circuit with the proper derivation of the
    parameters.

    (b) Consider a CMOS inverter circuit with supply voltage VDD = 3.3 V. The 10
    I-V characteristics of the nMOS transistor are specified as follows:
    when Vcs = 3.3 V, the drain current reaches its saturation level Isar = 2
    mA for VDS > 2.5 V. Assume that the input signal applied to the gate is a
    step pulse that switches instantaneously from 0 V to 3.3 V. Using the
    data above, calculate the delay time necessary for the output to fall
    from its initial value of 3.3 V to 1.65 V, assuming an output load
    capacitance of 1pF. Ignore the body effect for all the transistors.
    4 (a) Design a neat and labelled diagram for 4:1 MUX using pass transistor 5+5
    logic and transmission gates.

    (b) Draw the circuit diagram for the following Boolean function using 5+5
    CMOS logic. Implement the same circuit using transmission gate.

    F=A(B + C)+ DE

    5 (a) Name and discuss the second-order effects in a MOSFET that impact 10 '
    the performance of a MOS based circuits.

    (b) Drive the small-signal voltage gain of a resistive-load CS amplifier with 10


    the help of small- signal equivalent circuit. Assume A*0.

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