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    Assignment - VLSI

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    arkhit
    VLSI

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    © All Rights Reserved
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    Assignment - VLSI

    Uploaded by

    arkhit
    6 views1 page
    VLSI

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    Assignment _VLSI

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    VLSI

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    6 views1 page

    Assignment - VLSI

    Uploaded by

    arkhit
    VLSI

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
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    ASSIGNMENT QUESTIONS

    Q1.A CMOS process specifies that = 0.071 V1/2and 2|F| =0.58V for an nFET. The
    mobilities are given by n =560 cm2/V-secand p =220 cm-2/V-sec
    (a) Calculate the thickness of the gate oxide xox and then find Cox
    (b) Calculate the process transconductance factors for both nFETs and pFETs.

    Q2.Consider a MOS structure that is made with the following characteristics :xox = 200Å,
    Na = 1015 cm-3, n-poly gate with Nd= 21019cm-3, Qf = q (1010 ) C/cm-2 >>Qox,
    a. Calculate the value Cox and flatband voltage
    b. Find the value of the threshold voltage before a threshold adjustment ion
    implant.
    c. Now find the value of the acceptor implant dose needed to set to 0.7v.

    Q3.Consider an nFET process that uses an n-type poly gate. The important processing
    parameters are as follows: xox = 100Å, Na = 1015cm-3, n =580 cm-2/V-sec, VTOn = +0.7V.

    a. Calculate the value of Coxin units of F/cm2.


    b. Find the value of k’n.
    c. Find the value of the body-bias coefficient .
    d. Suppose that an nFET is made with W= 10m and L=1m. Calculate the drain
    current if the voltages are set to VGSn =2V, VDSn =1V and VSBn =+1V.

    Q4.Compare the advantages and disadvantages of Dynamic CMOS and static CMOS.
    Q5.Explain
    a. Constant field & Constant voltage scaling
    b. Effect of scaling on threshold voltage for small device
    c. Dynamic Logic,
    d. Domino Logic,
    e. NORA,
    f. Zipper Logic.
    Q6.Write VHDL code for 4x1 MUX, half adder, full adder and subtractor.
    Q7.Derive the expression for dynamic PDP for CMOS inverter and find its value having C out = 300fF
    operated with a 5V supply with f=0.5 fmax.

    Q8.Describe the VTC of CMOS Inverter circuit with neat sketch.

    Q9. Draw the stick diagram for NAND gate & NOR gate.

    Q10. Describe the λ- based design rules for circuit layout.

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