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VLSI Technology and Applications 10B11EC612: Tutorial Sheet - 4

(1) The document discusses the design and analysis of CMOS inverters, including calculating threshold voltages and sizing transistors based on process parameters. (2) It provides examples of calculating the threshold voltage for different inverter designs given transistor widths and lengths (W/L), threshold voltages (Vto), and transconductance parameters (k'). (3) The document also covers calculating noise margins and critical voltage levels for inverters built using resistive loads.

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harshit420
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70 views

VLSI Technology and Applications 10B11EC612: Tutorial Sheet - 4

(1) The document discusses the design and analysis of CMOS inverters, including calculating threshold voltages and sizing transistors based on process parameters. (2) It provides examples of calculating the threshold voltage for different inverter designs given transistor widths and lengths (W/L), threshold voltages (Vto), and transconductance parameters (k'). (3) The document also covers calculating noise margins and critical voltage levels for inverters built using resistive loads.

Uploaded by

harshit420
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Technology And Applications 10B11EC612

Tutorial Sheet 4

(1) Consider a CMOS inverter with the given parameters- kn=140 A/V2, kp=60 A/V2, Vto, n=0.7 V, Vto, p= - 0.7 V, VDD=3 V. (a) If the design is ideal and symmetrical, then find out the ratio of (W/L)p and (W/L)n. (b) Take the case when (W/L)p = (W/L)n, then find out the inverter threshold voltage. (2) A CMOS inverter is built in a process where kn=100 A/V2, kp=42 A/V2, Vto, n=0.7 V, Vto, p= - 0.8 V and a power supply of VDD=3.3 V is used. Calculate the inverter threshold voltage Vth if (W/L)n=10 and (W/L)p=14. (3) Find the ratio kn/kp needed to obtain a CMOS inverter threshold voltage of Vth=1.3 V with a power supply of 3 V. Assume that Vto, n=0.6 V and Vto, p= - 0.82 V. What would be the relative device sizes if the mobility values are related by n=2.2p? (4) Consider a resistive-load inverter circuit with VDD=5 V, k'n= 20 A/V2, Vt0= 0.8 V, RL= 200 K, and W/L = 2. Calculate the critical voltages-VOL, VOH, VIL, VIH on the VTC and find the noise margins of the circuit. (5) Design a resistive-load inverter with R=1 K, such that VOL = 0.6 V. The enhancement-type nMOS driver transistor has the following parameters: kn=22 A/V2, Vto, n=1 V, =0.2 V1/2, VDD=5 V. (a) Determine the required aspect ratio, W/L. (b) Determine VIL, VIH. (c) Determine noise margins NML and NMH.

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