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Cmos LP

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Electronics and Communications Engineering

LESSON PLAN ( R20)


COURSE : II B. Tech BRANCH : ECE
CLASS : II/II Sem.
SUBJECT: CMOS Digital IC Design SUBJECT CODE :

Course Objectives:

1. Introduce about Pseudo NMOS Logic characteristics.

2. Explain combinational and sequential MOS logic circuits.

3. Elaborate the basic principles of Dynamic logic circuits.

4. Explain elementary MOS semiconductor memory circuits.

Course Outcomes:
Upon completion of this course, students can

1. Interpret Pseudo NMOS Logic characteristics.

2. Analyze the operation and construction of combinational and sequential MOS circuits.

3. Identify the switching action of Dynamic Logic circuits.

4. Analyze the elementary MOS semiconductor designs.

CO-PO Mapping

CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12

CO1 3 2 2 - - - - - - - - -

CO2 3 2 2 2 - - - - - - - 2

CO3 3 2 - - - - - - - - - 1

CO4 2 2 1 - - - - - - - - 1

CO-PSO Mapping

CO/PSO PSO1 PSO 2

CO1 3 -

CO2 3 3

CO3 3 2

CO4 3 2

Lesson Plan:

S.No. No. of Hrs Name of the Topic


Required

1 2 Introduction to CMOS Digital IC Design, Course Outcomes

UNIT-I: MOS Design

2 2 Pseudo NMOS Logic – Inverter, Inverter threshold voltage

3 2 Gain at gate threshold voltage, Transient response


4 2 Rise time, Fall time, Pseudo NMOS logic gates

5 2 CMOS Gate design, Power dissipation in CMOS

UNIT-II: Combinational MOS Logic Circuits

6 2 Introduction, MOS logic circuits with NMOS loads

7 2 Primitive CMOS logic gates – NOR & NAND gate

8 2 AOI and OIA gates,

9 2 CMOS full adder, CMOS transmission gates,

10 2 Designing with Transmission gates.

UNIT-III: Sequential MOS Logic Circuits

11 2 Introduction, Behavior of bistable elements

12 2 SR Latch, Clocked latch, and flip flop circuits - Clocked SR Latch

13 2 Clocked JK Latch

14 2 CMOS D latch

15 2 Edge triggered flip-flop

UNIT-IV: Dynamic Logic Circuits

16 2 Introduction, Basic Principles of Pass Transistor Circuits

17 2 Voltage Bootstrapping,

18 2 Synchronous dynamic pass transistor circuits

19 2 CMOS transmission gate logic

20 2 High performance Dynamic CMOS circuits

UNIT-V: Semiconductor Memories

21 2 Introduction, Read-Only Memory (ROM) Circuits

22 2 Design of Row and Column Decoder

23 2 Static Read-Write Memory (SRAM) Circuits- SRAM Operation Principles

24 2 SRAM Write Circuitry, Dynamic Read-Write Memory (DRAM) Circuits

25 2 Tutorial.
TEXTBOOK’s:

T1 Digital Design, Morris Mano, PHI, 3rd Edition, 2001.

T2 Switching and Finite Automata Theory, 2nd Edition, ZviKohavi, Tata McGraw-Hill, 1978.

REFERENCE’s:

R1 Fundamentals of Digital Circuits by A. ANAND KUMAR, PHI learning Pvt. Ltd.

R2 Fundamentals of Logic Design, Charles H. Roth, Thomson Publications, 5th Edition, 2009.

Module Coordinator Course Coordinator

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