Lab 04

Digital Logic Design By Alishba Azam Malik
Lab 04
Introduction to MODELSIM Simulator and
a Simple Program
Objectives:
Introduction to MODELSIM
Software used:
MODELSIM
MODELSIM:
MODELSIM is a simulator which can be used for the simulations of both VHDL and
Verilog HDL. It has the following interface.
Basic Simulation Flow:

The following diagram shows the basic steps for simulating a design in ModelSim.
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In ModelSim, all designs are compiled into a library. You typically start a new simulation in ModelSim by
creating a working library called "work," which is the default library name used by the compiler as the
default destination for compiled design units.
Project Flow:
As you can see, the flow is similar to the basic simulation flow. However, there are two important
differences. You do not have to create a working library in the project flow; it is done for you
automatically. Projects are persistent. In other words, they will open every time you invoke ModelSim
unless you specifically close them.
How to use MODELSIM?
Step 1
Creating a new project
Select File > New > Project (Main window) to create a new project. This opens the Create Project dialog.
The dialog includes these options:
• Project Name
The name of the new project.
• Project Location
The directory in which the .mpf file will be created.
• Default Library Name
The name of the working library.
You can generally leave the Default Library Name set to "work." The name you specify will be used to
create a working library subdirectory within the Project Location.
After selecting OK, you will see a blank Project tab in the workspace area of the Main window and the
Add Items to the Project dialog.
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The name of the current project is shown at the bottom left corner of the Main window.
Step 2
Adding items to the project
The Add Items to the Project dialog includes these options:
Create New File
Create a new VHDL, Verilog, Tcl, or text file using the Source window. See below for
details.
Add Existing File
Add an existing file. See below for details.
Create Simulation
Create a Simulation Configuration that specifies source files and simulator options. See
Create New Folder
Create an organization folder.
Create New File
The Create New File command lets you create a new VHDL, Verilog, Tcl, or text file using the Source
window. You can also access this command by selecting File > Add to Project > New File (Main window) or right-
clicking (2nd button in Windows; 3rd button in UNIX) in the Project tab and selecting Add to Project > New File.
The Create Project File dialog includes these options:

File Name
The name of the new file
Add file as type
Add the type of the new file. Select VHDL, Verilog, TCL, or text.
Folder
The organization folder in which you want the new file placed. You must first create
folders to access them here
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When you select OK, the Source window opens with an empty file, and the file is listed in the Project tab of
the Main window workspace.
Add Existing File

You can also access this command by selecting File > Add to Project > Existing File (Main window) or
by right-clicking (2nd button in Windows; 3rd button in UNIX) in the Project tab and selecting Add to Project >
Existing File.
The Add file to Project dialog includes these options:

File Name
The name of the file to add. You can add multiple files at one time.
Add file as type
The type of the file. "Default" assigns type based on the file extension (e.g., .v is type Verilog).
Folder
The organization folder in which you want the file placed. You must first create folders in order to access them here.
Choose whether to reference the file from its current location or to copy it into the project directory. When you
select OK, the file(s) is listed in the Project tab of the Main window workspace.
Step 3
Compiling the files
The question marks next to the files in the Project tab denote either the files haven’t been compiled into the
project or the source has changed since the last compile. To compile the files, select Compile > Compile All (Main
window) or right click in the Project tab and select Compile > Compile All.
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Once compilation is finished, click the library tab, expand library work by clicking the "+", and you’ll see
the two compiled design units.
Step 4
Simulating a design
To simulate one of the designs, either double-click the name or right-click the name and select Simulate. A
new tab appears showing the structure of the active simulation. At this point you are ready to run the simulation and
analyze your results. You often do this by adding signals to the Wave window and running the simulation for a
given period of time.
Example:
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We must write Verilog code for the simulation of above circuit. In this module there are 3 inputs A, B and
C and two outputs D and E. This example 3.1 is taken from textbook 5th edition
Next, we should write

a test bench that will
provide inputs to the
declared module. In
test bench we can test
the module for
different inputs.
Testbench for above Module:
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This test bench will provide 2 different set of inputs (one after another) and will finish the simulation after
200ns. We can increase this duration,
Introducing gate delays:
In the above program

we have added delays
for every gate to see the
behavior and glitches
of the gates.
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Wave output after introducing gate delays
Another Program:
In this example we will see 2 bits input and output
Verilog vs. VHDL
When learning FPGA design, there are two languages to choose from, Verilog or VHDL. They are
called HDLs, or hardware design languages. Unlike a language like C, where they define what
you want the circuit to do, HDLs define how the hardware needs to be configured. VHDL was
written as a description language, whereas Verilog was written as a hardware modeling
language. Verilog, being the opposite in terms of its features, looks similar to C code, which is
why it is often easier to learn. The full form of VHDL is "VHSIC Hardware Description Language."
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VHSIC stands for "Very High Speed Integrated Circuit." VHDL is a programming language used to
describe the structure and behavior of digital logic circuits.
Lab tasks:
1. Write the Boolean expression/ function of the circuit in the above example 3.1
2. Test the above example for all possible combination of inputs (don’t use delays in
gates)
3. Implement the following equation where z is output and x1, x2, x3, x4, and x5 are inputs of
the circuit.
z = (y1 + y2)’
y1 = x1.x2
y2 = (x3.x4.x5)’
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Digital Logic Design By Alishba Azam Malik

Basic Simulation Flow:

The Create Project File dialog includes these options:

Add Existing File

The Add file to Project dialog includes these options:

Next, we should write

Testbench for above Module:

Introducing gate delays:

In the above program

Wave output after introducing gate delays

In this example we will see 2 bits input and output

Verilog vs. VHDL

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