®

EL7104

Data Sheet July 6, 2006 FN7113.2

High Speed, Single Channel, Power Features

MOSFET Driver • Industry-standard driver replacement
The EL7104 is a matched driver IC that improves the
• Improved response times
operation of the industry-standard TC-4420/29 clock drivers.
The Elantec version is a very high speed driver capable of • Matched rise and fall times
delivering peak currents of 1A into highly capacitive loads. • Reduced clock skew
The high speed performance is achieved by means of a
proprietary “Turbo-Driver” circuit that speeds up input stages • Low output impedance
by tapping the wider voltage swing at the output. Improved • Low input capacitance
speed and drive capability are enhanced by matched rise
• High noise immunity
and fall delay times. These matched delays maintain the
integrity of input-to-output pulse-widths to reduce timing • Improved clocking rate
errors and clock skew problems. This improved performance • Low supply current
is accompanied by a 10-fold reduction in supply currents
over bipolar drivers, yet without the delay time problems • Wide operating range
commonly associated with CMOS drivers. • Separate drain connections
The EL7104 is available in 8-pin SO and 8-pin PDIP • Pb-Free available (RoHS compliant)
packages and is specified for operation over the full -40°C to
+85°C temperature range. Applications
• Clock/line drivers
Ordering Information
• CCD drivers
PART PART TAPE & PKG.
NUMBER MARKING PACKAGE REEL DWG. # • Ultrasound transducer drivers
EL7104CN EL7104CN 8 Ld PDIP - MDP0031 • Power MOSFET drivers
EL7104CNZ EL7104CN Z 8 Ld PDIP* - MDP0031 • Switch mode power supplies
EL7104CS 7104CS 8 Ld SOIC - MDP0027 • Resonant charging
EL7104CS-T7 7104CS 8 Ld SOIC 7” MDP0027
• Cascoded drivers
EL7104CS-T13 7104CS 8 Ld SOIC 13” MDP0027
EL7104CSZ 7104CSZ 8 Ld SOIC - MDP0027
Pinout
(See Note) (Pb-free) EL7104
(8-PIN SO, PDIP)
EL7104CSZ-T7 7104CSZ 8 Ld SOIC 7” MDP0027 TOP VIEW
(See Note) (Pb-free)

EL7104CSZ-T13 7104CSZ 8 Ld SOIC 13” MDP0027 V+ 1 8 V+

(See Note) (Pb-free)
IN 2 7 P_OUT
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin NC 3 6 N_OUT
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free GND 4 5 GND
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
 EL7104

Absolute Maximum Ratings (TA = 25°C)

Supply (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+ Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4A Power Dissipation
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW
PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

DC Electrical Specifications V+ = 15V, TA = 25°C unless otherwise specified.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

INPUT
VIH Logic “1” Input Voltage 2.4 V

IIH Logic “1” Input Current @V+ 0.1 10 µA

VIL Logic “0” Input Voltage 0.8 V

IIL Logic “0” Input Current @0V 0.1 10 µA

VHVS Input Hysteresis 0.3 V

OUTPUT

ROH Pull-Up Resistance IOUT = -100mA 1.5 4 Ω

ROL Pull-Down Resistance IOUT = +100mA 2 4 Ω

IOUT Output Leakage Current V+/GND 0.2 10 µA

IPK Peak Output Current Source/Sink 4.0 A

IDC Continuous Output Current Source/Sink 200 mA

POWER SUPPLY

IS Power Supply Current Input = V+ 4.5 7.5 mA

VS Operating Voltage 4.5 16 V

AC Electrical Specifications V = 15V, TA = 25°C unless otherwise specified.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

SWITCHING CHARACTERISTICS (VDD = VH = 12V; VL = -3V)

tR Rise Time CL = 1000pF 7.5 ns

CL = 2000pF 10 20 ns

tF Fall Time CL = 1000pF 10 ns

CL = 2000pF 15 20 ns

tD-ON Turn-On Delay Time See Timing Table 18 25 ns

tD-OFF Turn-Off Delay Time See Timing Table 18 25 ns

2
 EL7104

Timing Table

5V

Input 2.5V

90%
Inverted
Output
EL7114
10%

Non-inverted 90%
Output
EL7104
10%

tD1 tF tD2 tR
tR tF

Standard Test Configuration

1 8 4.7µF

2 6

D.U.T.
Input 7 Output
Signal Signal

4 5 2000pF

Simplified Schematic

3
 EL7104

Typical Performance Curves

MAX POWER/DERATING CURVES SWITCH THRESHOLD vs SUPPLY VOLTAGE

PEAK DRIVE vs SUPPLY VOLTAGE

INPUT CURRENT vs VOLTAGE

QUIESCENT SUPPLY CURRENT “ON” RESISTANCE vs SUPPLY VOLTAGE

4
 EL7104

Typical Performance Curves (Continued)

AVERAGE SUPPLY CURRENT vs RISE/FALL TIME vs LOAD

VOLTAGE AND FREQUENCY

RISE/FALL TIME vs SUPPLY VOLTAGE

PROPAGATION DELAY vs SUPPLY VOLTAGE

RISE/FALL TIME vs TEMPERATURE RISE/FALL TIME vs TEMPERATURE

5
 EL7104

Small Outline Package Family (SO)

A

D h X 45°

N (N/2)+1

A
PIN #1
I.D. MARK
E E1
c
SEE DETAIL “X”

1 (N/2)
B
L1
0.010 M C A B

e
H
C
A2

GAUGE
SEATING PLANE 0.010
PLANE
A1 L 4° ±4°
0.004 C 0.010 M C A B b DETAIL X

MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16 SO16 (0.300”) SO20 SO24 SO28
SYMBOL SO-8 SO-14 (0.150”) (SOL-16) (SOL-20) (SOL-24) (SOL-28) TOLERANCE NOTES
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994

6
 EL7104

Plastic Dual-In-Line Packages (PDIP)

D E N

PIN #1
A2 A INDEX
E1
SEATING
PLANE c
L
A1
eA 1 2 N/2
NOTE 5
e b eB b2

MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES
A 0.210 0.210 0.210 0.210 0.210 MAX
A1 0.015 0.015 0.015 0.015 0.015 MIN
A2 0.130 0.130 0.130 0.130 0.130 ±0.005
b 0.018 0.018 0.018 0.018 0.018 ±0.002
b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015
c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002
D 0.375 0.750 0.750 0.890 1.020 ±0.010 1
E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010
E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2
e 0.100 0.100 0.100 0.100 0.100 Basic
eA 0.300 0.300 0.300 0.300 0.300 Basic
eB 0.345 0.345 0.345 0.345 0.345 ±0.025
L 0.125 0.125 0.125 0.125 0.125 ±0.010
N 8 14 16 18 20 Reference
Rev. B 2/99
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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