NCP308, NCV308

Low Quiescent Current,

Programmable Delay Time,
Supervisory Circuit
The NCP308 series is one of the ON Semiconductor Supervisory
circuit IC families. It is optimized to monitor system voltages from www.onsemi.com
0.405 V to 5.5 V, asserting an active low open−drain RESET output,
together with Manual Reset (MR) Input. The part comes with both MARKING
fixed and externally adjustable versions. DIAGRAMS

Features
• Wide Supply Voltage Range 1.6 to 5.5 V TSOP−6 XXXAYWG
• Very Low Quiescent Current 1.6 mA CASE 318G G
1
• Fixed Threshold Voltage Versions for Standard Voltage Rails 1

Including 0.9 V, 1.2 V, 1.25 V, 1.5 V, 1.8 V, 1.9 V, 2.5 V, 2.8 V, 3.0 V,
1
3.3 V, 5.0 V WDFN6 XX M
• Adjustable Version with Low Threshold Voltage 0.405 V (min) CASE 511BR

• High Threshold Voltage Accuracy: 0.31% typ

• Support Manual Reset Input ( MR)
XXX, XX= Specific Device Code
• Open−Drain RESET Output (Push−pull Output upon Request) A =Assembly Location
• Flexible Delay Time Programmability: 1.25 ms to 10 s Y = Year
• Temperature Range: −40°C to +125°C W
M
= Work Week
= Date Code
• Small TSOP−6 and WDFN6 2 x 2 mm, Pb−Free packages G = Pb−Free Package
• NCV Prefix for Automotive and Other Applications Requiring (Note: Microdot may be in either location)
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
ORDERING INFORMATION
• These are Pb−Free Devices See detailed ordering and shipping information in the ordering
information section on page 9 of this data sheet.
Typical Applications
• DSP or Microcontroller Applications
• Notebook/Desktop Computers
• PDAs/Hand−Held Products
• Portable/Battery−Powered Products
• FPGA/ASIC Applications

VIN VDD VIN VDD

NCP308XXADJ Rpullup Rpullup

RESET RESET RESET RESET

VDD VDD
DSP/ DSP/
R1 Processor Processor

SENSE CT SENSE CT
1 nF CT CT

R2 MR MR
(Optional) MR GND (Optional) MR GND (Optional)

Figure 1. Typical Application Circuit for Adjustable Figure 2. Typical Application Circuit for Fixed
Versions Versions

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

December, 2014 − Rev. 6 NCP308/D
 NCP308, NCV308

VDD VDD
VDD NCP308SNADJ/NCP308MTADJ VDD NCP308SNXXX/NCP308MTXXX
Adjustable Versions Fixed Versions

90k CT 90k CT

MR MR

− RESET − RESET
SENSE Control Logic SENSE Control Logic
+ and Timer + and Timer
R1

Vref Vref
R2
GND

GND
Figure 3. Functional Block Diagrams of Adjustable and Fixed Versions

RESET 1 6 VDD
VDD 1 6 RESET

GND 2 5 SENSE SENSE 2 5 GND

CT 3 4 MR
MR 3 4 CT

Figure 4. Pin Connections Diagram (Top View)

Table 1. PIN OUT DESCRIPTION

Pin Number

Name TSOP−6 WDFN6 Description

VDD 6 1 Supply Voltage. A 0.1uF ceramic capacitor placed close to this pin is helpful for transient and
parasitic.
SENSE 5 2 Sense Input, this is the voltage to be monitored. If the voltage at this terminal drops below the
threshold voltage VIT, then RESET is asserted. SENSE does not necessary monitor VDD, it can
monitor any voltage lower than VDD.
CT 4 3 Reset Delay Time Setting Pin. Connecting this pin to VDD through a 40 kW to 200 kW resistor or
leaving it open results in fixed reset delay times. Connecting this pin to a ground referenced
capacitor (≥ 100 pF) gives a user−programmable reset delay time. See the Setting Reset Delay
Time section for more information.
MR 3 4 Manual Reset input, MR low asserts RESET. MR is internally tied to VDD by a 90 kW pull−up
Resistor.
RESET 1 6 RESET Output, is an Active low open drain N−Channel MOSFET output, it is driven to a low
impedance state when RESET is asserted (either the SENSE input is lower than the threshold
voltage (VIT) or the MR pin is set to a logic low). RESET will keep low (asserted) for the reset
delay time after both SENSE is above VIT and MR is set to a logic high. A pull−up resistor from
10kW to 1MW should be used on this pin. See Figure 5 for behavior of RESET depends on VDD,
SENSE and MR conditions.
GND 2 5 Ground terminal. Should be connected to PCB ground reference
EXP − Exposed Exposed pad, under WDFN6 package, connect it to ground plane for better thermal dissipation.
PAD Pad

www.onsemi.com
2
 NCP308, NCV308

Uncertain State

VDD

VDD(min)

0.0 V

RESET

tD tP2 tD
SENSE

VIT + VHYS

VIT

tP1 tD

MR

0.7 VDD

0.3 VDD

Figure 5. Timing Diagram Showing MR and SENSE Reset Timing

Table 2. TRUTH TABLE

MR SENSE > VIT RESET
L N L
L Y L
H N L
H Y H

www.onsemi.com
3
 NCP308, NCV308

Table 3. MAXIMUM RATINGS

Rating Symbol Value Unit
Input voltage range, VDD VDD −0.3 to + 6.0 V
CT voltage range VCT, RESET, MR ICT −0.3 to VDD +0.3 ≤ 6.0 V
Current through CT pin 10 mA
SENSE pin voltage −0.3 to + 8.0 V
RESET pin current 5 mA
Thermal Resistance Junction−to−Air RqJA °C/W
TSOP−6 305
WDFN6 220
Human Body Model (HBM) ESD Rating (Note 1) ESD HBM 2000 V
Machine Model (MM) ESD Rating (Note 1) ESD MM 100 V
Charged Device Model (CDM) ESD Rating (Note 1) ESD CDM 500 V
Latch up Current: (Note 2) ILU mA
All pins, except digital pins ±100
Digital pins (MR) ±10
Storage Temperature Range TSTG −65 to + 150 °C
Maximum Junction Temperature TJ −40 to +150 °C
Moisture Sensitivity (Note 3) MSL Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) +/−2.0 kV per JEDEC standard: JESD22−A114
Machine Model (MM) +/−100 V per JEDEC standard: JESD22−A115
Charged Device Model (CDM) 500 V per JEDEC standard: JESD22−C101.
2. Latch up Current per JEDEC standard: JESD78 class II.
3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.

www.onsemi.com
4
 NCP308, NCV308

Table 4. ELECTRICAL CHARACTERISTICS 1.6 V ≤ VDD ≤ 5.5 V, Rpullup = 100 kW, CLRESET = 50 pF, over operating
temperature range (TJ = −40°C to +125°C), unless otherwise specified. Typical values are at TJ = +25°C.

Symbol Parameter Conditions Min Typ Max Unit

VDD Supply Voltage Range −40°C < TJ < +125°C 1.6 5.5 V
VDD(min) Minimum VDD Guaranteed RESET 0.5 0.8 V
Output Valid (Note 4)
IDD Supply Current (Current into VDD VDD = 3.3V, RESET not asserted 1.6 5.0 mA
pin) MR, RESET, CT open

VDD = 5.5V, RESET not asserted 1.6 6.0

MR, RESET, CT open
VOL Low−level output voltage of RESET 1.3V ≤ VDD < 1.6V, IOL = 0.4 mA 0.3 V
1.6V ≤ VDD ≤ 5.5V, IOL = 1.0 mA 0.4
VIT% Negative going SENSE threshold −1.75 ±0.75 +1.75 %
voltage accuracy
TJ = +25°C −0.31 − 0.31
−20°C < TJ < +85°C −1.0 ±0.5 +1.0
VHYS Hysteresis on 1.6V≤VDD≤4.2V 1.0 3.0 %VIT
VIT
4.2V≤VDD≤5.5V 1.75 3.75
RMR MR Internal pull−up resistance 90 kW
ISENSE Input current at NCP308XXADJ VSENSE = VIT 10 nA
SENSE pin
Fixed versions VSENSE = 5.5 V 110
IOH RESET leakage Current VRESET = 5.5 V, RESET not 300 nA
asserted
CIN Input CT pin VIN = 0 V to VDD 5 pF
capacitance, any
pin Other pins VIN = 0 V to 5.5 V 5

VIL MR logic low input 0 0.3 VDD V

VIH MR logic high input 0.7 VDD VDD V
tw Input pulse width SENSE VIH = 1.05 VIT, VIL = 0.95 VIT 20 ms
to assert RESET
MR VIH = 0.7 VDD, VIL = 0.3 VDD 150
tD Reset delay time CT = Open (Guaranteed by design and 20 ms
CT = VDD characterization) 300
CT = 100 pF 1.25
CT = 180 nF 1200

tP1 Propagation MR to RESET VIH = 0.7 VDD, VIL = 0.3 VDD 150 ns
delay from MR

tP2 Propagation SENSE to VIH = 1.05 VIT, VIL = 0.95 VIT 20 ms

delay from RESET
SENSE
4. The lowest supply voltage (VDD) at which RESET becomes active.
5. NCP308XX: XX = MT (WDFN6 package) or SN (TSOP−6 package).

www.onsemi.com
5
 NCP308, NCV308

TYPICAL OPERATING CHARACTERISTICS

4.0 10000
3.5

3.0 1000
+125°C
+25°C +125°C
2.5
100
IDD (mA)

(ms)
2.0 +85°C −40°C

1.5 10 +85°C

−40°C
1.0
+25°C 1
0.5

0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.1 1.0 10.0 100.0 1000.0
VDD (V) (nF)
Figure 6. Supply Current vs. Input Voltage Figure 7. RESET Timeout Period vs. CT
NORMALIZED RESET TIMEOUT PERIOD (%)

20
TRANSIENT DURATION BELOW VIT (ms) 100

15

10 10

5.0

0 1

−5.0

−10 0.1
−50 −30 −10 10 30 50 70 90 110 130 0 5 10 15 20 25 30 35 40 45 50
TEMPERATURE (°C) OVERDRIVE (%VIT)
Figure 8. Normalized RESET Timeout Period vs. Figure 9. Maximum Transient Duration at Sense
Temperature vs. Sense Threshold Overdrive Voltage

3.0 0.5
VOL LOW−LEVEL RESET VOLTAGE (V)

2.5
2.0
0.4
NORMALIZED VIT (%)

1.5 VDD = 1.6 V

1.0
0.5 0.3
0
−0.5 VDD = 5.5 V
0.2
−1.0
VDD = 3.3 V
−1.5
0.1
−2.0
−2.5
−3.0 0.0
−50 −30 −10 10 30 50 70 90 110 130 0.0 0.5 1.0 1.5 2.0
TEMPERATURE (°C) RESET CURRENT (mA)
Figure 10. Normalized Sense Threshold Voltage Figure 11. Low−Level RESET Voltage vs. RESET
(VIT) vs. Temperature Current

www.onsemi.com
6
 NCP308, NCV308

DETAILED DESCRIPTION

The NCP308 microprocessor supervisory product family SENSE Input

is designed to assert a RESET signal when either the SENSE The SENSE input should be connected to the monitored
pin voltage drops below VIT or the Manual Reset input (MR) voltage directly. If the voltage on this pin drops below VIT,
is driven low. The RESET output remains asserted for a then RESET is asserted. The comparator has a built−in
programmable delay time after both MR and SENSE hysteresis to prevent erratic reset operation. It is good
voltages return above the respective thresholds. A broad practice to put a 1 nF to 10 nF bypass capacitor on the
range of voltage threshold and reset delay time options are SENSE input to reduce its sensitivity to transients and layout
available, allowing NCP308 series to be used in a wide range parasitic.
of applications. The NCP308XXADJ can be used to monitor any voltage
Reset threshold voltages can be factory−set from 0.82 V rail down to 0.405 V by the circuit shown in Figure 12. The
to 3.3 V or from 4.4 V to 5.0 V, while the NCP308XXADJ new VIT’ can be derived from resistor divider network of R1
can be used for any voltage above 0.405 V using an external and R2 by:
resistor divider.
Flexible delay time can be easily got with CT pin V ITȀ + ǒR1 ) 1Ǔ V IT (eq. 1)
R2
according to Table 5:
VDD
VIN
Table 5. DELAY TIME SETTING TABLE
CT pin Configuration Delay Time (tD) NCP308XXADJ Rpullup
CT = VDD 300 ms (fixed)
VDD RESET
CT = Open 20 ms (fixed)
R1
Connecting a capacitor be- 1.25 ms ~ 10 s, depends on
tween pin CT and GND capacitor value (Refer to the SENSE CT CT
(Capacitor CT value > Setting Reset Delay Time 1 nF
100 pF) Section) R2
(Optional) MR (Optional)
MR GND

Output
The RESET output is typically connected to the RESET Figure 12. Using NCP308XXADJ to Monitor a
control pin of a microprocessor. For Open−Drain output User−Defined Threshold Voltage
versions, a pull−up resistor must be used to hold this line
high when RESET is not asserted. The RESET output is
active once VDD is over VDD(min), this voltage is much Manual Reset Input (MR)
lower than most microprocessors’ functional voltage range. The Manual Reset input (MR) allows a processor or other
RESET remains high as long as SENSE is above its logic circuits to initiate a reset. A logic low on MR causes
threshold (VIT) and the Manual Reset input (MR) is logic RESET to assert. After MR returns to a logic high and
high. If either SENSE falls below VIT or MR is driven low, SENSE is above its reset threshold, RESET is de−asserted
RESET is asserted. after the delay time set by CT pin. MR is internally tied to
Once MR is again logic high and SENSE is above (VIT + VDD by a 90 kW resistor so this pin can be left unconnected
VHYS), the RESET pin goes to a high impedance state after if MR will not be used.
delay time (tD). The open−drain structure of RESET is Figure 13 shows how MR can be used to monitor multiple
capable to allow the reset signal for the microprocessor to system voltages (e.g. I/O supply voltage of some
have a voltage higher than VDD (up to 5.5 V). The pull−up DSP/processors should be setup before core voltage, and
resistor should be no smaller than 10 kW as a result of the DSP/processor can only start after both I/O and core
finite impedance of the RESET line. voltages setup).

www.onsemi.com
7
 NCP308, NCV308

1.2 V

3.3 V

Vcore
VIO
RESET
VDD RESET VDD RESET
DSP/
Processor

SENSE CT SENSE CT

MR GND MR GND

NCP308XX120 NCP308XX330

Figure 13. Using MR to Monitor Multiple System Voltages

Setting Reset Delay Time 3.3V

The NCP308 has three options for setting the reset delay
time as shown in Table 5. Figure 14 shows the configuration
for a fixed 300 ms typical delay time by tying CT to VDD;
Rpullup
a resistor from 40 kW to 200 kW must be used. Figure 15
shows a fixed 20 ms delay time by leaving the CT pin
VDD RESET
unconnected.
Figure 16 shows a user−defined program time between
1.25 ms and 10 s by connecting a capacitor between CT pin
and ground. SENSE CT

3.3 V
MR
MR GND

Rpullup Figure 15. Delay Time Fixed to 20 ms when CT is

50k
Open
VDD RESET

3.3 V

SENSE CT

Rpullup
MR
MR GND
VDD RESET

Figure 14. Delay Time Fixed to 300 ms when CT

Connected to VDD by Resistor SENSE CT

CT

MR
MR GND

Figure 16. Delay Time Set by Capacitor

The capacitor CT should be ≥ 100 pF for NCP308 to

recognize that the capacitor is present. The capacitor value
for a given delay time can be calculated using the following
equation:

www.onsemi.com
8
 NCP308, NCV308

CT(nF) + ǒtD(s) * 0.5 10 −3(s)Ǔ 175 (eq. 2) threshold overdrive, as shown in the Maximum Transient
Duration at Sense vs. Sense Threshold Overdrive Voltage
Parasitic capacitances of CT pin should be considered to graph (Figure 9) in Typical Operating Characteristics
avoid reset delay time deviation or error. section.
Immunity to Sense Pin Voltage Transients
NCP308 is relatively immune to short negative transients
on SENSE pin. Sensitivity to transients is dependent on

ORDERING INFORMATION
Threshold Nominal
Voltage Monitored
Device Status (Note 6) (VIT) Voltage Marking Package Shipping†
NCP308SNADJT1G Active 0.405 V Adjustable ADJ
Version
NCV308SNADJT1G* Active 0.405 V VDJ
NCP308SN090T1G Active 0.84 V 0.9 V 090
NCP308SN120T1G Active 1.12 V 1.2 V 120
NCP308SN125T1G Active 1.16 V 1.25 V 125
NCP308SN150T1G Active 1.40 V 1.5 V 150
NCP308SN180T1G Active 1.67 V 1.8 V 180 TSOP−6
NCP308SN190T1G Active 1.77 V 1.9 V 190 (Pb−Free)

NCP308SN250T1G Active 2.33 V 2.5 V 250

NCP308SN280T1G Active 2.61 V 2.8 V 280
NCP308SN300T1G Active 2.79 V 3.0 V 300
NCP308SN330T1G Active 3.07 V 3.3 V 330
NCV308SN330T1G* Active 3.07 V 3.3 V 33A
NCP308SN500T1G Active 4.65 V 5.0 V 500 3000 / Tape & Reel

NCP308MTADJTBG Active 0.405 V Adjustable AA

Version

NCP308MT090TBG Active 0.84 V 0.9 V AC

NCP308MT120TBG Active 1.12 V 1.2 V AD
NCP308MT125TBG Active 1.16 V 1.25 V AE
NCP308MT150TBG Active 1.40 V 1.5 V AF
NCP308MT180TBG Active 1.67 V 1.8 V AG WDFN6
(Pb−Free)
NCP308MT190TBG Active 1.77 V 1.9 V AH
NCP308MT250TBG Active 2.33 V 2.5 V AJ
NCP308MT280TBG Active 2.61 V 2.8 V AK
NCP308MT300TBG Active 2.79 V 3.0 V AL
NCP308MT330TBG Active 3.07 V 3.3 V AM
NCP308MT500TBG Active 4.65 V 5.0 V AN
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
6. The marketing status are defined as below:
Active: Products in production and recommended for new designs;
Under Request: Device has been announced but is not in production. Samples may or may not be available.

www.onsemi.com
9
 NCP308, NCV308

PACKAGE DIMENSIONS

TSOP−6
CASE 318G−02
ISSUE U
NOTES:
D 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
H 2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

ÉÉÉ
6 5 4 L2 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
GAUGE PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR

ÉÉÉ
E1 E PLANE GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
1 2 3 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
L
MILLIMETERS
NOTE 5
M C SEATING
b PLANE DIM MIN NOM MAX
DETAIL Z A 0.90 1.00 1.10
e A1 0.01 0.06 0.10
b 0.25 0.38 0.50
c 0.10 0.18 0.26
D 2.90 3.00 3.10
c E 2.50 2.75 3.00
0.05 A E1 1.30 1.50 1.70
e 0.85 0.95 1.05
L 0.20 0.40 0.60
A1 L2 0.25 BSC
DETAIL Z
M 0° − 10°

RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60

3.20 6X
0.95

0.95
PITCH
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com
10
 NCP308, NCV308

PACKAGE DIMENSIONS

WDFN6 2x2, 0.65P

CASE 511BR
ISSUE O
NOTES:

ÇÇÇ
ÉÉÉ
1. DIMENSIONING AND TOLERANCING PER
D A EXPOSED Cu MOLD CMPD
ASME Y14.5M, 1994.

ÉÉÉ
B 2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25 mm FROM THE TERMINAL TIP.
DETAIL B 4. COPLANARITY APPLIES TO THE EXPOSED

ÍÍÍ
ALTERNATE PAD AS WELL AS THE TERMINALS.
PIN ONE CONSTRUCTIONS

ÍÍÍ
REFERENCE E MILLIMETERS
DIM MIN MAX
A 0.70 0.80

ÍÍÍ
A1 0.00 0.05
0.10 C L L A3 0.20 REF
b 0.25 0.35
0.10 C D 2.00 BSC
TOP VIEW L1 D2 1.50 1.70
E 2.00 BSC
DETAIL A E2 0.90 1.10
ALTERNATE e 0.65 BSC
DETAIL B A3 CONSTRUCTIONS
0.05 C L 0.20 0.40
L1 --- 0.15
A

6X 0.05 C
A1 RECOMMENDED
SEATING
NOTE 4 C PLANE
SIDE VIEW MOUNTING FOOTPRINT*
6X
1.72
0.45
D2
DETAIL A L
1 3

E2 1.12 2.30

6 4
6X b PACKAGE
OUTLINE
e 0.10 M C A B 1
0.65
0.05 M C NOTE 3 6X 0.40 PITCH
BOTTOM VIEW
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com
Literature Distribution Center for ON Semiconductor USA/Canada
P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local
Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative

www.onsemi.com NCP308/D
11