NCP1529

1.7MHz, 1A, High Efficiency,

Low Ripple, Adjustable
Output Voltage Step-down
Converter
The NCP1529 step−down DC−DC converter is a monolithic http://onsemi.com
integrated circuit for portable applications powered from one cell
Li−ion or three cell Alkaline/NiCd/NiMH batteries. The device is able MARKING
to deliver up to 1.0 A on an output voltage range externally adjustable DIAGRAM
from 0.9 V to 3.9 V or fixed at 1.2 V or 1.35 V. It uses synchronous
rectification to increase efficiency and reduce external part count. The 5
device also has a built−in 1.7 MHz (nominal) oscillator which reduces TSOP−5 DXJAYWG
component size by allowing a small inductor and capacitors. Automatic 5 SN SUFFIX G
1 CASE 483
switching PWM/PFM mode offers improved system efficiency. 1
Additional features include integrated soft−start, cycle−by−cycle
DXJ = Specific Device Code
current limiting and thermal shutdown protection. A = Assembly Location
The NCP1529 is available in a space saving, low profile Y = Year
2x2x0.5 mm UDFN6 package and TSOP−5 package. W = Work Week
G = Pb−Free Package
Features
(Note: Microdot may be in either location)
• Up to 96% Efficiency
• Best In Class Ripple, including PFM mode
UDFN6 1 6
• Source up 1.0 A MU SUFFIX 2 XXMG 5
• 1.7 MHz Switching Frequency CASE 517AB 3 G 4

• Adjustable from 0.9 V to 3.9 V or Fixed at 1.2 V or 1.35 V XX = Specific Device Code
• Synchronous rectification for higher efficiency M = Date Code
• 2.7 V to 5.5 V Input Voltage Range G = Pb−Free Package
(Note: Microdot may be in either location)
• Low Quiescent Current 28 mA
• Shutdown Current Consumption of 0.3 mA
• Thermal Limit Protection ORDERING INFORMATION
• Short Circuit Protection See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
• All Pins are Fully ESD Protected
• These are Pb−Free Devices
Typical Applications
• Cellular Phones, Smart Phones and PDAs
• Digital Still Cameras
• MP3 Players and Portable Audio Systems
• Wireless and DSL Modems
• USB Powered Devices
• Portable Equipment
L VOUT L
VIN VIN SW VIN VIN SW VOUT

CIN COUT CIN COUT

R1 Cff
OFF ON EN FB OFF ON EN FB
GND GND
R2

Figure 1. Typical Application for Adjustable Version Figure 2. Typical Application for Fixed Version

© Semiconductor Components Industries, LLC, 2010 1 Publication Order Number:

September, 2010 − Rev. 5 NCP1529/D
 NCP1529

PIN FUNCTION DESCRIPTION

Pin Pin
TSOP−5 UDFN6 Pin Name Type Description
1 6 EN Analog Input Enable for switching regulators. This pin is active HIGH and is turned off by
logic LOW on this pin.

2 2,4,7 GND Analog / This pin is the GND reference for the NFET power stage and the analog
(Note 1) Power Ground section of the IC. The pin must be connected to the system ground.

3 5 SW Analog Output Connection from power MOSFETs to the Inductor.

4 3 VIN Analog / Power supply input for the PFET power stage, analog and digital blocks. The
Power Input pin must be decoupled to ground by a 4.7 mF ceramic capacitor.

5 1 FB Analog Input Feedback voltage from the output of the power supply. This is the input to the
error amplifier.
1. Exposed pad for UDFN6 package, named Pin 7, must be connected to system ground.

PIN CONNECTIONS

EN 1 5 FB FB 1 6 EN

GND 2 GND 2 7 5 SW

SW 3 4 VIN VIN 3 4 GND

(Top View) (Top View)

Figure 3. Pin Connections − TSOP−5 Figure 4. Pin Connections − UDFN6

PERFORMANCES

100
90
80
70
EFFICIENCY (%)

60
50
40
30
20
10
0
0 500 1000
IOUT (mA)
Figure 5. Efficiency vs Output Current
VIN = 3.6 V, VOUT = 3.3 V

http://onsemi.com
2
 NCP1529

FUNCTIONAL BLOCK DIAGRAM

Q1

Q2
Vbattery 2.2 mH
VIN SW
PWM/PFM
CONTROL
10 mF
4.7 mF

GND R1 18 pF
ILIMIT

LOGIC
Enable CONTROL
EN & THERMAL FB
SHUTDOWN

REFERENCE
VOLTAGE R2

Figure 6. Simplified Block Diagram

http://onsemi.com
3
 NCP1529

MAXIMUM RATINGS
Rating Symbol Value Unit
Minimum Voltage All Pins Vmin −0.3 V
Maximum Voltage All Pins (Note 2) Vmax 7.0 V
Maximum Voltage EN Vmax VIN + 0.3 V
Thermal Resistance, Junction−to−Air (TSOP−5 Package) RqJA 300 °C/W
Thermal Resistance using TSOP−5 Recommended Board Layout (Note 9) 110

Thermal Resistance, Junction−to−Air (UDFN6 Package) RqJA 220 °C/W

Thermal Resistance using UDFN6 Recommended Board Layout (Note 9) 40

Operating Ambient Temperature Range (Notes 7 and 8) TA −40 to 85 °C

Storage Temperature Range Tstg −55 to 150 °C
Junction Operating Temperature (Notes 7 and 8) Tj −40 to 150 °C
Latchup Current Maximum Rating (TA = 85°C) (Note 5) Other Pins Lu $100 mA
ESD Withstand Voltage (Note 4) Vesd
Human Body Model 2.0 kV
Machine Model 200 V
Moisture Sensitivity Level (Note 6) MSL 1 per IPC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C.
3. According to JEDEC standard JESD22−A108B.
4. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) per JEDEC standard: JESD22−A114.
Machine Model (MM) per JEDEC standard: JESD22−A115.
5. Latchup current maximum rating per JEDEC standard: JESD78.
6. JEDEC Standard: J−STD−020A.
7. In applications with high power dissipation (low VIN, high IOUT), special care must be paid to thermal dissipation issues. Board design
considerations − thermal dissipation vias, traces or planes and PCB material − can significantly improve junction to air thermal resistance
RqJA (for more information, see design and layout consideration section). Environmental conditions such as ambient temperature TA brings
thermal limitation on maximum power dissipation allowed.
The following formula gives calculation of maximum ambient temperature allowed by the application:
TA MAX = TJ MAX − (RqJA x Pd)
Where: TJ is the junction temperature,
Pd is the maximum power dissipated by the device (worst case of the application),
and RqJA is the junction−to−ambient thermal resistance.
8. To prevent permanent thermal damages, this device include a thermal shutdown which engages at 180°C (typ).
9. Board recommended TSOP−5 and UDFN6 layouts are described on Layout Considerations section.

1200 1200
IOUTmax, MAXIMUM OUTPUT CUR-

UDFN6 UDFN6
PD, POWER DISSIPATION (mW)

1000 1000

TSOP−5
800 TSOP−5 800
RENT (mA)

600 600

400 400

200 200

0 0
−40 −20 0 20 40 60 80 2.7 3.2 3.7 4.2 4.7 5.2
TA, AMBIENT TEMPERATURE (°C) VIN, INPUT VOLTAGE (V)

Figure 8. Power Derating Figure 7. Maximum Output Current, TA = 455C

http://onsemi.com
4
 NCP1529

ELECTRICAL CHARACTERISTICS (Typical values are referenced to TA = +25°C, Min and Max values are referenced −40°C to
+85°C ambient temperature, unless otherwise noted, operating conditions VIN = 3.6 V, VOUT = 1.2 V, unless otherwise noted.)

Rating Conditions Symbol Min Typ Max Unit

INPUT VOLTAGE
Input Voltage Range Vin 2.7 − 5.5 V
Quiescent Current No Switching, No load IQ − 28 39 mA
Standby Current EN Low ISTB − 0.3 1.0 mA
Under Voltage Lockout VIN Falling VUVLO 2.2 2.4 2.55 V
Under Voltage Hysteretis VUVLOH − 100 − mV
ANALOG AND DIGITAL PIN
Positive going Input High Voltage Threshold VIH 1.2 − − V
Negative going Input High Voltage Threshold VIL − − 0.4 V
EN Threshold Hysteresis VENH − 100 − mV
EN High Input Current EN = 3.6 V IENH − 1.5 − mA
OUTPUT
Feedback Voltage Level Adjustable Version VFB − 0.6 − V
Fixed Version at 1.2 V − 1.2 −
Fixed Version at 1.35 V − 1.35 −
Output Voltage Range (Notes 10, 11) VOUT 0.9 − 3.3 V
USB or 5 V Rail Powered Applications 0.9 − 3.9
(VIN from 4.3 V to 5.5 V) (Note 12)
Output Voltage Accuracy Room Temperature (Note 13) DVOUT − $1 − %
Overtemperature Range −3 $2 +3
Maximum Output Current (Note 10) IOUTMAX 1 − − A
Output Voltage Load Regulation Load = 100 mA to 1000 mA (PWM Mode) VLOADR − −0.9 − %
Overtemperature Load = 0 mA to 100 mA (PFM Mode) − 1.1 −
Load Transient Response 10 mA to 100 mA Load Step VLOADT − 40 − mV
Rise/Fall Time 1 ms (PFM to PWM Mode)
200 mA to 600 mA Load Step − 85 −
(PWM to PWM Mode)
Output Voltage Line Regulation Load = 100 mA VIN = 2.7 V to 5.5 V VLINER − 0.05 − %
Line Transient Response Load = 100 mA 3.6 V to 3.2 V Line Step (Fall Time = 50 ms) VLINET − 6.0 − mVPP
Output Voltage Ripple IOUT = 0 mA VRIPPLE − 8.0 − mVPP
IOUT = 300 mA − 3.0 −
Switching Frequency FSW 1.2 1.7 2.2 MHz
Duty Cycle D − − 100 %
Soft−Start Time Time from EN to 90% of Output Voltage tSTART − 310 500 ms
POWER SWITCHES
High−Side MOSFET On−Resistance RONHS − 400 − mW
Low−Side MOSFET On−Resistance RONLS − 300 − mW
High−Side MOSFET Leakage Current ILEAKHS − 0.05 − mA
Low−Side MOSFET Leakage Current ILEAKLS − 0.01 − mA
PROTECTION
DC−DC Short Circuit Protection Peak Inductor Current IPK − 1.6 − A
Thermal Shutdown Threshold TSD − 180 − °C
Thermal Shutdown Hysteresis TSDH − 40 − °C
10. Functionality guaranteed per design and characterization.
11. Whole output voltage range is available for adjustable versions only. By topology, the maximum output voltage will be equal or lower than
the input voltage.
12. See chapter ”USB or 5 V Rail Powered Applications”.
13. For adjustable versions only, the overall output voltage tolerance depends upon the accuracy of the external resistor (R1 and R2). Specified
value assumes that external resistor have 0.1% tolerance.

http://onsemi.com
5
 NCP1529

TABLE OF GRAPHS
Typical Characteristics for Step−down Converter Figure
h Efficiency vs. Output Current 10, 11, 12
Iq ON Quiescent Current, PFM no load vs. Input Voltage 9
Iq OFF Standby Current, EN Low vs. Input Voltage 8
FSW Switching Frequency vs. Ambient Temperature 13
VLOADR Load Regulation vs. Load Current 14
VLOADT Load Transient Response 16, 17
VLINER Line Regulation vs. Output Current 15
VLINET Line Transient Response 18, 19
tSTART Soft Start 20
IPK Short Circuit Protection 21
VUVLO Under Voltage Lockout Threshold vs. Ambient Temperature 22
VIL, VIH Enable Threshold vs. Ambient Temperature 23
P, G Phase & Gain Performance 24

http://onsemi.com
6
 NCP1529

1.0 31
0.9

Iq, QUIESCENT CURRENT (mA)

Istb, STANDBY CURRENT (mA)

0.8
30
0.7
0.6
0.5 29
0.4
0.3
28
0.2
0.1
0 27
2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN, INPUT VOLTAGE (V) VIN, INPUT VOLTAGE (V)
Figure 9. Standby Current vs. Input Voltage Figure 10. Quiescent Current vs. Input Voltage
(Enable = 0, Temperature = 255C) (Open Loop, Feedback = 1,
Temperature = 255C)

100 100
90 90
80 −40°C 80
5.5 V
70 70
EFFICIENCY (%)

EFFICIENCY (%)

60 60
25°C
50 50 VBAT = 2.7 V
3.3 V
40 85°C 40
30 30
20 20
10 10
0 0
0 200 400 600 800 1000 0 200 400 600 800 1000

IOUT, OUTPUT CURRENT (mA) IOUT, OUTPUT CURRENT (mA)

Figure 11. Efficiency vs. Output Current Figure 12. Efficiency vs. Output Current
(VIN = 3.3 V, VOUT = 1.2 V) (Vout = 1.2 V, Temperature = 255C)

100 2.2
90 3.3 V 2.1
SWITCHING FREQUENCY (MHz)

80 2

70 1.2 V 1.9
EFFICIENCY (%)

1.8 VIN = 2.7 V

60
50 VOUT = 0.9 V 1.7
40 1.6
1.5 3.6 V
30 5.5 V
20 1.4

10 1.3

0 1.2
0 200 400 600 800 1000 −60 −20 20 60 100
IOUT, OUTPUT CURRENT (mA) TA, AMBIENT TEMPERATURE (°C)
Figure 13. Efficiency vs. Output Current Figure 14. Switching Frequency vs. Ambient
(VIN = 3.6 V, Temperature = 255C) Temperature (Vout = 1.2 V, Iout = 200 mA)

http://onsemi.com
7
 NCP1529

3.0 3.0

2.0 2.0
LOAD REGULATION (%)

LINE REGULATION (%)

1.0 1.0 100 mA

−40°C
0.0 0

−1.0 −1.0 IOUT = 800 mA 1 mA

25°C
−2.0 85°C −2.0

−3.0 −3.0
0 200 400 600 800 1000 2.7 3.2 3.7 4.2 4.7 5.2

IOUT, OUTPUT CURRENT (mA) VIN, INPUT VOLTAGE (V)

Figure 15. Load Regulation vs. Output Current Figure 16. Line Regulation vs. Input Voltage
(VIN = 5.5 V, VOUT = 1.2 V) (VOUT = 1.2 V, Temperature = 255C)

Figure 17. 10 mA to 100 mA Load Transient in 1 ms Figure 18. 200 mA to 600 mA Load Transient in 1 ms
(VIN = 3.6 V, VOUT = 1.2 V, Temperature = 255C) (VIN = 3.6 V, VOUT = 1.2 V, Temperature = 255C)

Figure 19. 3.0 V to 3.6 V Line Transient, Rise = 50 ms Figure 20. 3.6 V to 3.0 V Line Transient, Fall = 50 ms
(VIN = 1.2 V, IOUT = 100 mA, Temperature = 255C) (VIN = 1.2 V, IOUT = 100 mA, Temperature = 255C)

http://onsemi.com
8
 NCP1529

Figure 21. Typical Soft−Start (VIN = 3.6 V, VOUT = 1.2 V, Figure 22. Short−Circuit Protection (VIN = 3.6 V,
IOUT = 100 mA, Temperature = 255C) VOUT = 1.2 V, IOUT = CC, Temperature = 255C)
UNDERVOLTAGE LOCKOUT THRESHOLD (V)

2.60 1.2
ENABLE THRESHOLD VOLTAGES (V)

2.55 1.1
UVLOrise
2.50 1.0

2.45 0.9
UVLOfall
0.8 VIH
2.40

2.35 0.7
VIL
2.30 0.6

2.25 0.5

2.20 0.4
−50 −25 0 25 50 75 100 125 −40 −15 10 35 60 85
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)
Figure 23. Undervoltage Lockout Threshold Figure 24. Enable Threshold Voltages vs.
vs. Ambient Temperature Ambient Temperature
70 200

160
50
120
30 80
Phase
40
PHASE (°)
GAIN (dB)

10
0
Gain
−10 −40
−80
−30
−120

−50 −160
10 100 1000 10000 100000 1000000

FREQUENCY (Hz)
Figure 25. Phase and Gain Performance
(VIN = 3.6 V, VOUT = 1.2 V, IOUT = 200 mA, Temperature = 255C)

http://onsemi.com
9
 NCP1529

DC/DC OPERATION DESCRIPTION

Detailed Description
The NCP1529 uses a constant frequency, current mode VOUT
step−down architecture. Both the main (P−channel
MOSFET) and synchronous (N−channel MOSFET)
switches are internal.
The output voltage is set by an external resistor divider in ISW
the range of 0.9 V to 3.9 V and can source at least 1A.
The NCP1529 works with two modes of operation;
PWM/PFM depending on the current required. In PWM
mode, the device can supply voltage with a tolerance of VSW
$3% and 90% efficiency or better. Lighter load currents
cause the device to automatically switch into PFM mode to
reduce current consumption and extended battery life.
Additional features include soft−start, undervoltage
protection, current overload protection and thermal Figure 26. PWM Switching Waveforms
shutdown protection. As shown on Figure 1, only six (VIN = 3.6 V, VOUT = 1.2 V, IOUT = 600 mA,
external components are required. The part uses an internal Temperature = 255C)
reference voltage of 0.6 V. It is recommended to keep
NCP1529 in shutdown mode until the input voltage is 2.7 V
or higher. PFM Operating Mode
Under light load conditions, the NCP1529 enters in low
PWM Operating Mode current PFM mode of operation to reduce power
In this mode, the output voltage of the device is regulated consumption. The output regulation is implemented by
by modulating the on−time pulse width of the main switch pulse frequency modulation. If the output voltage drops
Q1 at a fixed 1.7 MHz frequency. below the threshold of PFM comparator a new cycle will be
The switching of the PMOS Q1 is controlled by a flip−flop initiated by the PFM comparator to turn on the switch Q1.
driven by the internal oscillator and a comparator that Q1 remains ON during the minimum on time of the structure
compares the error signal from an error amplifier with the while Q2 is in its current source mode. The peak inductor
sum of the sensed current signal and compensation ramp. current depends upon the drop between input and output
The driver switches ON and OFF the upper side transistor voltage. After a short dead time delay where Q1 is switched
(Q1) while the lower side transistor is switched OFF then OFF, Q2 is turned in its ON state. The negative current
ON. detector will detect when the inductor current drops below
At the beginning of each cycle, the main switch Q1 is zero and sends a signal to turn Q2 to current source mode to
turned ON by the rising edge of the internal oscillator clock. prevent a too large deregulation of the output voltage. When
The inductor current ramps up until the sum of the current the output voltage falls below the threshold of the PFM
sense signal and compensation ramp becomes higher than comparator, a new cycle starts immediately.
the error amplifier’s voltage. Once this has occurred, the
PWM comparator resets the flip−flop, Q1 is turned OFF
while the synchronous switch Q2 is turned ON. Q2 replaces
VOUT
the external Schottky diode to reduce the conduction loss
and improve the efficiency. To avoid overall power loss, a
certain amount of dead time is introduced to ensure Q1 is
VSW
completely turned OFF before Q2 is being turned ON.

ISW

Figure 27. PFM Switching Waveforms

(VIN = 3.6 V, VOUT = 1.2 V, IOUT = 0 mA,
Temperature = 255C)

http://onsemi.com
10
 NCP1529

Soft−Start temperature exceeds 180°C, the device shuts down. In this

The NCP1529 uses soft−start to limit the inrush current mode all power transistors and control circuits are turned
when the device is initially powered up or enabled. Soft start off. The device restarts in soft−start after the temperature
is implemented by gradually increasing the reference drops below 140°C. This feature is provided to prevent
voltage until it reaches the full reference voltage. During catastrophic failures from accidental device overheating.
startup, a pulsed current source charges the internal
soft−start capacitor to provide gradually increasing Short Circuit Protection
reference voltage. When the voltage across the capacitor When the output is shorted to ground, the device limits the
ramps up to the nominal reference voltage, the pulsed inductor current. The duty−cycle is minimum and the
current source will be switched off and the reference voltage consumption on the input line is 550 mA (typ). When the
will switch to the regular reference voltage. short circuit condition is removed, the device returns to the
normal mode of operation.
Cycle−by−cycle Current Limitation
From the block diagram, an ILIM comparator is used to USB or 5 V Rail Powered Applications
realize cycle−by−cycle current limit protection. The For USB or 5 V rail powered applications, NCP1529 is
comparator compares the SW pin voltage with the reference able to supply voltages up to 3.9 V, 600 mA, operating in
voltage, which is biased by a constant current. If the inductor PWM mode only, with high efficiency (Figure 28), low
current reaches the limit, the ILIM comparator detects the output voltage ripple and good load regulation results over
SW voltage falling below the reference voltage and releases all current range (Figure 29).
the signal to turn off the switch Q1. The cycle−by−cycle 100
current limit is set at 1600 mA (nom). 95 −40°C
90
Low Dropout Operation 85
The NCP1529 offers a low input to output voltage EFFICIENCY (%)
80 25°C
difference. The NCP1529 can operate at 100% duty cycle. 75 85°C
In this mode the PMOS (Q1) remains completely ON. The 70
minimum input voltage to maintain regulation can be 65
calculated as: 60

ǒ
V out + V OUT(max) ) I OUTǒR DS(on)_R INDUCTORǓ Ǔ (eq. 1)
55
50
• VOUT: Output Voltage (V) 45
40
• IOUT: Max Output Current 0 200 400 600 800 1000
• RDS(on): P−Channel Switch RDS(on) IOUT, OUTPUT CURRENT (mA)
• RINDUCTOR: Inductor Resistance (DCR) Figure 28. Efficiency vs. Output Current
(VIN = 5.0 V, VOUT = 3.9 V)
Undervoltage Lockout
The Input voltage VIN must reach 2.4 V (typ) before the 3.0
NCP1529 enables the DC/DC converter output to begin the 2.5
start up sequence (see soft−start section). The UVLO 2.0
1.5
LOAD REGULATION (%)

threshold hysteresis is typically 100 mV.

1.0
Shutdown Mode 0.5
Forcing this pin to a voltage below 0.4 V will shut down −40°C
0.0
the IC. In shutdown mode, the internal reference, oscillator −0.5
and most of the control circuitries are turned off. Therefore, −1.0
the typical current consumption will be 0.3 mA (typical −1.5 25°C
85°C
value). Applying a voltage above 1.2 V to EN pin will enable −2.0
the DC/DC converter for normal operation. The device will −2.5
go through soft−start to normal operation. −3.0
0 200 400 600 800 1000
Thermal Shutdown
IOUT, OUTPUT CURRENT (mA)
Internal Thermal Shutdown circuitry is provided to
Figure 29. Load Regulation vs. Output Current
protect the integrated circuit in the event that the maximum (VIN = 5.0 V, VOUT = 3.9 V)
junction Temperature is exceeded. If the junction

http://onsemi.com
11
 NCP1529

APPLICATION INFORMATION

Output Voltage Selection Input Capacitor Selection

In case of adjustable versions, the output voltage is In PWM operating mode, the input current is pulsating
programmed through an external resistor divider connected with large switching noise. Using an input bypass capacitor
from VOUT to FB then to GND. can reduce the peak current transients drawn from the input
For low power consumption and noise immunity, the supply source, thereby reducing switching noise
resistor from FB to GND (R2) should be in the [100k−600k] significantly. The capacitance needed for the input bypass
range. If R2 is 200 k given the VFB is 0.6 V, the current capacitor depends on the source impedance of the input
through the divider will be 3.0 mA. supply.
The formula below gives the value of VOUT, given the The maximum RMS current occurs at 50% duty cycle
desired R1 and the R1 value: with maximum output current, which is IO, max/2.
V out + V FB (1 ) R1ńR2) (eq. 2) For NCP1529, a low profile ceramic capacitor of 4.7 mF
should be used for most of the cases. For effective bypass
• VOUT: Output Voltage (V) results, the input capacitor should be placed as close as
• VFB: Feedback Voltage = 0.6 V possible to the VIN Pin
• R1: Feedback Resistor from VOUT to FB
• R2: Feedback Resistor from FB to GND

Table 1. LIST OF INPUT CAPACITORS

Manufacturer Part Number Case Size Value DC Bias Technology
(mF) (V)

MURATA GRM15 series 0402 4.7 6.3 X5R

MURATA GRM18 series 0603 4.7 10 X5R
TDK C1608 series 0603 4.7 6.3 X5R
TDK C1608 series 0603 4.7 10 X5R

Output L−C Filter Design Considerations Inductor Selection

The NCP1529 operates at 1.7 MHz frequency and uses The inductor parameters directly related to device
current mode architecture. The correct selection of the performances are saturation current and DC resistance and
output filter ensures good stability and fast transient inductance value. The inductor ripple current (DIL)
response. decreases with higher inductance:
Due to the nature of the buck converter, the output L−C
filter must be selected to work with internal compensation.
For NCP1529, the internal compensation is internally fixed
DI L +
L
V OUT
f SW
ǒ 1*
V OUT
V IN
Ǔ (eq. 4)

and it is optimized for an output filter of L = 2.2 mH and • DIL: Peak to peak inductor ripple current
COUT = 10 mF. • L: Inductor value
The corner frequency is given by: • fSW: Switching frequency
1 1 The saturation current of the inductor should be rated
f+ + + 34 kHz
2p ǸL C OUT 2p Ǹ2.2 mH 10 mF higher than the maximum load current plus half the ripple
(eq. 3)
current:
The device operates with inductance value of 2.2 mH. If
DI L
the corner frequency is moved, it is recommended to check I L(max) + I O(max) ) (eq. 5)
the loop stability depending of the accepted output ripple 2
voltage and the required output current. Take care to check • IL(max): Maximum inductor current
the loop stability. The phase margin is usually higher than • IO(max): Maximum Output current
45°. The inductor’s resistance will factor into the overall
efficiency of the converter. For best performances, the DC
Table 2. L−C FILTER EXAMPLE resistance should be less than 0.3 W for good efficiency.
Inductance (L) Output Capacitor (COUT)
2.2 mH 10 mF
4.7 mH 4.7 mF

http://onsemi.com
12
 NCP1529

Table 3. LIST OF INDUCTORS

Manufacturer Part Number Case Height L DCR DCR Rated Rated Structure
Size Max (mH) Typ Max Current (mA) Current (mA)
(mm) (mm) (W) (W) Inductance Temperature
Drop Drop
COILCRAFT DO1605T-222 5.5 x 4.2 1.8 2.2 NA 0.070 1800 (-10%) 1700 (+40°C) Wire Wound
COILCRAFT EPL3015-222 3.0 x 3.0 1.5 2.2 0.082 0.094 1600 (-30%) 2000 (+40°C) Wire Wound
COILCRAFT EPL2014-222 2.0 x 2.0 1.4 2.2 0.120 0.132 1300 (-30%) 1810 (+40°C) Wire Wound
MURATA LQM2HPN2R2 2.5 x 2.0 1.0 2.2 0.080 0.100 NA 1300 (+40°C) Multilayer
MURATA LQH3NPN2R2 3.0 x 3.0 1.2 2.2 0.065 0.085 1150 (-30%) 1460 (+40°C) Wire Wound
MURATA LQH44PN2R2 4.0 x 4.0 1.8 2.2 0.049 0.059 2500 (-30%) 1800 (+40°C) Wire Wound
TDK MLP2520S2R2L 2.5 x 2.0 1.0 2.2 0.080 0.104 1300 (-30%) NA Multilayer
TDK VLS252010T2R2 2.0 x 1.6 1.2 2.2 0.158 0.190 1400 (-30%) 1100 (+40°C) Wire Wound
WURTH ELEC 744 029 002 2.8 x 2.8 1.35 2.2 0.088 0.105 1150 (-35%) 1700 (+40°C) Wire Wound

Output Capacitor Selection The output ripple voltage in PWM mode is given by:

ǒ Ǔ
Selecting the proper output capacitor is based on the
1
desired output ripple voltage. Ceramic capacitors with low DV OUT + DI L ) ESR (eq. 6)
ESR values will have the lowest output ripple voltage and 4 f SW C OUT
are strongly recommended. The output capacitor requires
either an X7R or X5R dielectric.

Table 4. LIST OF OUTPUT CAPACITORS

Manufacturer Part Number Case Size Value DC Bias Technology
(mF) (V)

MURATA GRM15 series 0402 4.7 6.3 X5R

MURATA GRM18 series 0603 4.7 10 X5R
MURATA GRM18 series 0603 10 6.3 X5R
TDK C1608 series 0603 4.7 6.3 X5R
TDK C1608 series 0603 4.7 10 X5R
TDK C1608 series 0603 10 6.3 X5R

Feed−Forward Capacitor Selection (Adjustable Only) Having feed-forward capacitor of 1 nF or higher can
The feed-forward capacitor sets the feedback loop increase soft−start time and reduce inrush current. Choose a
response and acts on soft-start time. A minimum 18 pF small ceramic capacitor X7R or X5R or COG dielectric.
feed-forward capacitor is needed to ensure loop stability.

http://onsemi.com
13
 NCP1529

LAYOUT CONSIDERATIONS

Electrical Layout Considerations capacitor is recommended to meet compensation

Implementing a high frequency DC−DC converter requirements.
requires respect of some rules to get a powerful portable A four layer PCB with a ground plane and a power plane
application. Good layout is key to prevent switching will help NCP1529 noise immunity and loop stability.
regulators to generate noise to application and to
themselves. Thermal Layout Considerations
High power dissipation in small package leads to thermal
Electrical layout guide lines are:
consideration such as:
• Use short and large traces when large amount of current
• Enlarge VIN trace and added several vias connected to
is flowing.
power plane.
• Keep the same ground reference for input and output
• Connect GND pin to top plane.
capacitors to minimize the loop formed by high current
path from the battery to the ground plane. • Join top, bottom and each ground plane together using
several free vias in order to increase radiator size.
• Isolate feedback pin from the switching pin and the
current loop to protect against any external parasitic
For high ambient temperature and high power dissipation
signal coupling. Add a feed−forward capacitor between
requirements, UDFN6 package using exposed pad
VOUT and FB which adds a zero to the loop and
connected to main radiator is recommended. Refer to
participates to the good loop stability. A 18 pF
Notes 7, 8, and 9.

EN Trace
VOUT FB Trace
Trace

VIN Trace
SW
Trace
SW
Trace
VIN Trace
FB Trace VOUT
Trace

GND Plane
GND Plane
EN Trace

Figure 30. TSOP−5 Recommended Board Layout Figure 31. UDFN6 Recommended Board Layout

ORDERING INFORMATION
Nominal
Device Output Voltage Marking Package Shipping†
NCP1529ASNT1G Adj DXJ TSOP−5 3000 / Tape & Reel
NCP1529MUTBG Adj TL
NCP1529MU12TBG 1.2 V TC UDFN6 3000 / Tape & Reel
NCP1529MU135TBG 1.35 V RC
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

http://onsemi.com
14
 NCP1529

PACKAGE DIMENSIONS

TSOP−5
CASE 483−02
ISSUE G

NOTES:
1. DIMENSIONING AND TOLERANCING PER
NOTE 5 D 5X ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
0.20 C A B 3. MAXIMUM LEAD THICKNESS INCLUDES
2X 0.10 T LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
M OF BASE MATERIAL.
5 4 4. DIMENSIONS A AND B DO NOT INCLUDE
2X 0.20 T B S MOLD FLASH, PROTRUSIONS, OR GATE
1 2 3 BURRS.
K 5. OPTIONAL CONSTRUCTION: AN
L ADDITIONAL TRIMMED LEAD IS ALLOWED
DETAIL Z
IN THIS LOCATION. TRIMMED LEAD NOT TO
G EXTEND MORE THAN 0.2 FROM BODY.
A MILLIMETERS
DIM MIN MAX
DETAIL Z A 3.00 BSC
J B 1.50 BSC
C C 0.90 1.10
SEATING D 0.25 0.50
0.05 PLANE G 0.95 BSC
H H 0.01 0.10
T J 0.10 0.26
K 0.20 0.60
L 1.25 1.55
M 0_ 10 _
S 2.50 3.00

SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037

2.4
0.094

1.0
0.039

0.7
0.028 SCALE 10:1 ǒinches
mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com
15
 NCP1529

PACKAGE DIMENSIONS

UDFN6 2x2, 0.65P

CASE 517AB−01
ISSUE A

NOTES:
D A 1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
B 2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.

ÍÍ E MILLIMETERS

ÍÍ
PIN ONE DIM MIN MAX
REFERENCE A 0.45 0.55
A1 0.00 0.05
A3 0.127 REF
2X 0.10 C b 0.25 0.35
D 2.00 BSC
D2 1.50 1.70
E 2.00 BSC
2X 0.10 C E2 0.80 1.00
e 0.65 BSC
A3 K 0.20 ---
L 0.25 0.35
0.10 C
A
SOLDERING FOOTPRINT*
6X 0.08 C 6X
A1
0.95 0.47
C SEATING
PLANE 6X
0.40
D2 1

6X L e 4X
1 3

1.70
E2

6 4
0.65
6X K PITCH
6X b
2.30
0.10 C A B
BOTTOM VIEW DIMENSIONS: MILLIMETERS
0.05 C NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

The product described herein (NCP1529), may be covered by the following U.S. patents: TBD. There may be other patents pending.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com
Literature Distribution Center for ON Semiconductor USA/Canada
P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local
Email: orderlit@onsemi.com Phone: 81−3−5773−3850 Sales Representative

http://onsemi.com NCP1529/D
16