MCP6286

Low Noise, Low Power Op Amp

Features Description
• Low Noise: 5.4 nV/√Hz (typical) The Microchip Technology Inc. MCP6286 operational
• Low Quiescent Current: 520 µA (typical) amplifier (op amp) has low noise (5.4 nV/√Hz, typical),
• Rail-to-Rail Output low power (520 µA, typical) and rail-to-rail output
operation. It is unity gain stable and has a gain
• Wide Supply Voltage Range: 2.2V to 5.5V
bandwidth product of 3.5 MHz (typical). This device
• Gain Bandwidth Product: 3.5 MHz (typical) operates with a single supply voltage as low as 2.2V,
• Unity Gain Stable while drawing low quiescent current. These features
• Extended Temperature Range: -40°C to +125°C make the product well suited for single-supply, low
• No Phase Reversal noise, battery-powered applications.
• Small Package The MCP6286 op amp is offered in a space saving
SOT-23-5 package. It is designed with Microchip’s
Applications advanced CMOS process and available in the
extended temperature range, with a power supply
• Noise Cancellation Headphones range of 2.2V to 5.5V.
• Cellular Phones
• Analog Filters Package Types
• Sensor Conditioning
MCP6286
• Portable Instrumentation SOT-23-5
• Medical Instrumentation
VOUT 1 5 VDD
• Battery Powered Systems
VSS 2
VIN+ 3 4 VIN–
Design Aids
• SPICE Macro Models
• FilterLab® Software
• Mindi™ Circuit Designer & Simulator
• MAPS (Microchip Advanced Part Selector)
• Analog Demonstration and Evaluation Boards
• Application Notes

Typical Application
C1
47 nF

R1 R2
382 kΩ 641 kΩ
VIN +
C2 MCP6286 VOUT
22 nF
–

fP = 10 Hz G = +1 V/V

Second-Order, Low-Pass Butterworth Filter

© 2009 Microchip Technology Inc. DS22196A-page 1

MCP6286
NOTES:

DS22196A-page 2 © 2009 Microchip Technology Inc.

 MCP6286
1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD – VSS ........................................................................7.0V † Notice: Stresses above those listed under “Absolute
Current at Input Pins .....................................................±2 mA Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
Analog Inputs (VIN+, VIN-)†† .......... VSS – 1.0V to VDD + 1.0V
the device at those or any other conditions above those
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V indicated in the operational listings of this specification is not
Difference Input Voltage ...................................... |VDD – VSS| implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Output Short-Circuit Current .................................continuous
†† See 4.1.2 “Input Voltage And Current Limits”
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature (TJ).......................... +150°C
ESD protection on all pins (HBM; MM) ................ ≥ 4 kV; 400V

DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.2V to +5.5V, VSS= GND, TA= +25°C, VCM = VDD/3,
VOUT ≈ VDD/2, VL = VDD/2 and RL = 10 kΩ to VL. (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -1.5 — +1.5 mV
Input Offset Drift with Temperature ΔVOS/ΔTA — ±1 — µV/°C TA= -40°C to +125°C
Power Supply Rejection Ratio PSRR 80 100 — dB
Input Bias Current and Impedance
Input Bias Current IB — ±1 — pA
— 50 150 pA TA = +85°C
— 1500 3000 pA TA = +125°C
Input Offset Current IOS — ±1 — pA
Common Mode Input Impedance ZCM — 1013||20 — Ω||pF
Differential Input Impedance ZDIFF — 1013||20 — Ω||pF
Common Mode
Common Mode Input Voltage VCMR VSS−0.3 — VDD-1.2 V Note 1
Range
Common Mode Rejection Ratio CMRR 76 95 — dB VCM = -0.3V to 1.0V,
VDD = 2.2V
80 100 — dB VCM = -0.3V to 4.3V,
VDD = 5.5V
Open-Loop Gain
DC Open-Loop Gain AOL 100 120 — dB 0.2V < VOUT <(VDD-0.2V)
(Large Signal)
Output
Maximum Output Voltage Swing VOL, VOH VSS+15 — VDD–15 mV 0.5V Input overdrive
VSS+75 — VDD–75 mV 0.5V Input overdrive
RL = 2 kΩ
Output Short-Circuit Current ISC — ±20 — mA
Note 1: Figure 2-12 shows how VCMR changes across temperature.

© 2009 Microchip Technology Inc. DS22196A-page 3

MCP6286
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = +2.2V to +5.5V, VSS= GND, TA= +25°C, VCM = VDD/3,
VOUT ≈ VDD/2, VL = VDD/2 and RL = 10 kΩ to VL. (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
Power Supply
Supply Voltage VDD 2.2 — 5.5 V
Quiescent Current per Amplifier IQ 300 520 700 µA IO = 0, VDD = 2.2V
320 540 720 µA IO = 0, VDD = 5.5V
Note 1: Figure 2-12 shows how VCMR changes across temperature.

AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.2 to +5.5V, VSS = GND, VCM = VDD/3,
VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF. (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 3.5 — MHz
Phase Margin PM — 60 — ° G = +1 V/V
Slew Rate SR — 2 — V/µs
Noise
Input Noise Voltage Eni — 1.0 — µVP-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni — 22 — nV/√Hz f = 10 Hz
— 5.4 — nV/√Hz f = 10 kHz
Input Noise Current Density ini — 0.6 — fA/√Hz f = 1 kHz

TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.2V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Temperature Range TA -40 — +125 °C Note 1
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.

DS22196A-page 4 © 2009 Microchip Technology Inc.

 MCP6286
1.2 Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-1. It independently sets VCM and VOUT; see CF
Equation 1-1. The circuit’s common mode voltage is 6.8 pF
(VP + VM)/2, not VCM. VOST includes VOS plus the
effects of temperature, CMRR, PSRR and AOL.
RG RF
100 kΩ 100 kΩ VREF = VDD/2
EQUATION 1-1:
VP
G DM = R F ⁄ R G VDD
VIN+
G N = 1 + G DM
V CM = V P ( 1 – 1 ⁄ G N ) + V REF ( 1 ⁄ G N ) CB1 CB2
MCP6286 100 nF 1 µF
V OST = V IN– – V IN+
V OUT = V REF + ( V P – V M )G DM + V OST G N VIN–
Where:
VM VOUT
GDM = Differential Mode Gain (V/V) RG RF RL CL
GN = Noise Gain (V/V) 100 kΩ 100 kΩ 10 kΩ 60 pF
VCM = Op Amp’s Common Mode (V)
Input Voltage CF
6.8 pF VL
VOST = Op Amp’s Total Input Offset (mV)
Voltage
FIGURE 1-1: AC and DC Test Circuit for
Most Specifications.

© 2009 Microchip Technology Inc. DS22196A-page 5

MCP6286
NOTES:

DS22196A-page 6 © 2009 Microchip Technology Inc.

 MCP6286
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/3, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.

14% 800
Percentage of Occurrences

VDD = 2.2V Representative Part

12% 1360 Samples
600

Input Offset Voltage (µV)

10% 400

8% 200
0
6%
-200
TA = +125 °C
4%
-400 TA = +85°C
2% TA = +25°C
-600 TA = -40°C
0% -800
-800
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
800

-0.5

-0.3

-0.1

0.3

0.5

0.7

1.5

1.7
0.1

0.9

1.1

1.3
Input Offset Voltage (µV) Common Mode Input Voltage (V)

FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 2.2V.

40% 500
Percentage of Occurrences

400
Input Offset Voltage (µV)

35% 1360 Samples

300
30%
200
25% 100
20% 0 VDD = 2.2V

15% -100
-200
10%
-300 VDD = 5.5V
5%
-400
0% -500
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5
Input Offset Drift with Temperature (µV/°C) Output Voltage (V)

FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Input Offset Voltage vs.
Output Voltage.

800 600
VDD = 5.5V Representative Part VCM = VCMR-L Representative Part
Input Offset Voltage (µV)
Input Offset Voltage (µV)

600 400
400
200
200
0 0
-200 TA = +125°C TA = +125°C
-200
-400 TA = +85°C TA = +85°C
TA = +25°C -400 TA = +25°C
-600 TA = -40°C TA = -40°C
-800 -600
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Input Voltage (V)
Power Supply Voltage (V)

FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 5.5V. Power Supply Voltage with VCM = VCMR_L.

© 2009 Microchip Technology Inc. DS22196A-page 7

MCP6286
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/3, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.

600 120
VCM = VCMR-H Representative Part PSRR- Representative Part
110
Input Offset Voltage (µV)

400
100

CMRR, PSRR (dB)

200 90 CMRR
PSRR+
80
0 70
60
-200 TA = +125°C 50
TA = +85°C
40
-400 TA = +25°C
TA = -40°C 30
-600 20
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 11 10
10 100
100 1k
1000 10k 100000
10000 100k 1E+06
1M

Power Supply Voltage (V) Frequency (Hz)

FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: CMRR, PSRR vs.
Power Supply Voltage with VCM = VCMR_H. Frequency.

1,000
110
Input Noise Voltage Density

CMRR @ VDD = 5.5V

105
@ VDD = 2.2V

CMRR, PSRR (dB)

100 100
(nV/√ Hz)

95

90
PSRR
10
85
80

1 75
0.1 1.E+0
1 10 100 1.E+3
1k 10k 100k 1M -50 -25 0 25 50 75 100 125
1.E-1 1.E+1 1.E+2 1.E+4 1.E+5 1.E+6
Frequency (Hz) Ambient Temperature (°C)

FIGURE 2-8: Input Noise Voltage Density FIGURE 2-11: CMRR, PSRR vs. Ambient
vs. Frequency. Temperature.

7.0 1.20
Input Voltage Noise Density

Common Mode Input Voltage

6.5 f = 10 kHz 1.05

6.0 0.90 VDD - VCMR_H @ VDD = 5.5V
VDD = 5.5 V
0.75 @ VDD = 2.2V
Headroom (V)

5.5
(nV/√ Hz)

0.60
5.0 0.45
VDD = 2.2 V
4.5 0.30
4.0 0.15
VCMR_L - VSS @ VDD = 2.2V
0.00 VOL - VSS @ VDD = 5.5V
3.5
-0.15 V V
3.0
-0.30
-0.3
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5

-50 -25 0 25 50 75 100 125

Common Mode Input Voltage (V) Ambient Temperature (°C)

FIGURE 2-9: Input Noise Voltage Density FIGURE 2-12: Common Mode Input
vs. Common Mode Input Voltage. Voltage Headroom vs. Ambient Temperature.

DS22196A-page 8 © 2009 Microchip Technology Inc.

 MCP6286
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/3, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.

10000 700
Input Bias, Offset Currents (pA)

600

Quiescent Current (uA)

VDD = 5.5V

1000 500

400
Input Bias Current
100 TA = +125°C
300
TA = +85°C
200 TA = +25°C
10 TA = -40°C
100
Input Offset Current 0
1

0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C) Power Supply Voltage (V)

FIGURE 2-13: Input Bias, Offset Currents FIGURE 2-16: Quiescent Current vs.
vs. Ambient Temperature. Power Supply Voltage.

1600 120 0
VDD = 5.5V Open-Loop Gain
1400 100 -30
Input Bias Current (pA)

Open-Loop Gain (dB)

Open-Loop Phase (°)

1200 80 -60
Open-Loop Phase
1000 TA = +125°C
60 -90
800
40 -120
600
20 -150
400
TA = +85°C 0 -180
200 VDD = 5.5V
0 -20 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
-210
0.1 1 10 100 1k 10k 100k 1M 10M
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Frequency (Hz)
Common Mode Input Votlage (V)

FIGURE 2-14: Input Bias Current vs. FIGURE 2-17: Open-Loop Gain, Phase vs.
Common Mode Input Voltage. Frequency.

700 5.0 100

Gain Bandwidth Product

650 4.5 Gain Bandwidth Product 90

4.0 80
Quiescent Current (µA)

600
VDD = 5.5V 3.5 70
550

Phase (°)
3.0 60
(MHz)

500 2.5 50
Phase Margin
450 VDD = 2.2V 2.0 40
400 1.5 30
350 1.0 20
0.5 VDD = 5.5V 10
300
0.0 0
250
-0.4

0.2

0.8

1.4

2.0

2.6

3.2

3.8

4.4

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C) Common Mode Input Voltage (V)

FIGURE 2-15: Quiescent Current vs FIGURE 2-18: Gain Bandwidth Product,

Ambient Temperature. Phase Margin vs. Common Mode Input Voltage
with VDD = 5.5V.

© 2009 Microchip Technology Inc. DS22196A-page 9

MCP6286
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/3, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF

25
5.0 100

Output Short Circuit Current

4.5 90
Gain Bandwidth Product

Gain Bandwidth Product 20

4.0 80
3.5 70
15

Phase (°)
3.0 60

(mA)
(MHz)

2.5 50
Phase Margin 10 TA = +125°C
2.0 40 TA = +85°C
1.5 30 TA = +25°C
1.0 20 5 TA = -40°C
0.5 VDD = 2.2V 10
0.0 0 0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5
-0.4 -0.1 0.2 0.5 0.8 1.1
Common Mode Input Voltage (V) Power Supply Voltage (V)

FIGURE 2-19: Gain Bandwidth Product, FIGURE 2-22: Ouput Short Circuit Current
Phase Margin vs. Common Mode Input Voltage vs. Power Supply Voltage.
with VDD = 2.2V.

10
5.0 90 VDD = 5.5V

Output Voltage Swing (VP-P)

4.5 85
Gain Bandwidth Product

Gain Bandwidth Product

4.0 80 VDD = 2.2V
3.5 75
Phase (°)

3.0 70
(MHz)

2.5 65 1
2.0 60
Phase Margin
1.5 55
1.0 50
0.5 VDD = 5.5V 45
0.0 40
0.1
-50 -25 0 25 50 75 100 125 100
100 1k
1000 10k
10000 100k
100000 1M
1000000 10M
10000000
Ambient Temperature (°C) Frequency (Hz)

FIGURE 2-20: Gain Bandwidth Product, FIGURE 2-23: Output Voltage Swing vs.
Phase Margin vs. Ambient Temperature with Frequency.
VDD = 5.5V.

5.0 90 1000
Output Voltage Headroom

4.5 85
Gain Bandwidth Product

4.0 Gain Bandwidth Product 80

3.5 75 100
Phase (°)

3.0 70
(mV)
(MHz)

2.5 65
2.0 60
10
1.5 Phase Margin 55 VOL - VSS
1.0 50
VDD - VOH
0.5 VDD = 2.2V 45
0.0 40 1
-50 -25 0 25 50 75 100 125 0.01 0.1 1 10
Ambient Temperature (°C) Output Current (mA)

FIGURE 2-21: Gain Bandwidth Product, FIGURE 2-24: Output Voltage Headroom
Phase Margin vs. Ambient Temperature with vs. Output Current.
VDD = 2.2V.

DS22196A-page 10 © 2009 Microchip Technology Inc.

 MCP6286
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/3, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.

60
55
Output Voltage Headroom

Output Voltage (50 mV/div)

50
VDD - VOH, VOL - VSS (mV)

45
40 VDD - VOH @ RL = 2kΩ VDD = 5.5V
35 VOL - VSS @ RL = 2kΩ G = -1 V/V
30
25
VDD - VOH @ RL = 10kΩ
20 VOL - VSS @ RL = 10kΩ
15
10
5
0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C) Time (1 µs/div)

FIGURE 2-25: Output Voltage Headroom FIGURE 2-28: Small Signal Inverting Pulse
vs. Ambient Temperature. Response.

3.0 5.5
2.8 5.0
2.6 Falling Edge, VDD = 5.5V
4.5
Rising Edge, VDD = 5.5V
Slew Rate (V/µs)

Output Voltage (V)

2.4 4.0
2.2 3.5
2.0 3.0
1.8 2.5
1.6 2.0
Falling Edge, VDD = 2.2V VDD = 5.5V
1.4 Rising Edge, VDD = 2.2V 1.5 G = +2 V/V
1.2 1.0
1.0 0.5
-50 -25 0 25 50 75 100 125 0.0
Temperature (°C) Time (5 µs/div)

FIGURE 2-26: Slew Rate vs. Ambient FIGURE 2-29: Large Signal Non-Inverting
Temperature. Pulse Response.

5.5
5.0
Output Voltage (50 mV/div)

4.5
VDD = 5.5V
Output Voltage (V)

4.0
G = -2 V/V
3.5
VDD = 5.5V 3.0
G = +1 V/V 2.5
2.0
1.5
1.0
0.5
0.0
Time (1 µs/div) Time (5 µs/div)

FIGURE 2-27: Small Signal Non-Inverting FIGURE 2-30: Large Signal Inverting Pulse
Pulse Response. Response.

© 2009 Microchip Technology Inc. DS22196A-page 11

MCP6286
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/3, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.

1m
1m
1m
1000000000
6.0
100
100
100 µ
µµ
100000000
Input, Output Voltages (V)

5.0 VOUT 10µ

10µ
10µ
10000000

1µ
1µ
1µ
4.0
1000000
VIN

-I IN (A)
100n
100n
100000

3.0 10n
10n
10000

2.0 1n
1n
1000

100p
100p100

1.0 VDD = 5.5V 10p

10p10
G = +2 V/V
0.0 1p1
1p
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
-1.0
V IN (V)
Time (1 ms/div)

FIGURE 2-31: The MCP6286 Shows No FIGURE 2-33: Measured Input Current vs.
Phase Reversal. Input Voltage (below VSS).

1000
Closed Loop Output

100
Impedance (Ω)

10
GN:
101 V/V
11 V/V
1 1 V/V

0.1
10
10 100
100 1k
1000 10k 100000
10000 100k 1E+06
1M 10M
1E+07
Frequency (Hz)

FIGURE 2-32: Closed Loop Output

Impedance vs. Frequency.

DS22196A-page 12 © 2009 Microchip Technology Inc.

 MCP6286
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6286
Symbol Description
SOT-23-5
1 VOUT Analog Output
2 VSS Negative Power Supply
3 VIN+ Non-inverting Input
4 VIN– Inverting Input
5 VDD Positive Power Supply

3.1 Analog Output 3.3 Power Supply Pins

The output pin is low-impedance voltage source. The positive power supply (VDD) is 2.2V to 5.5V higher
than the negative power supply (VSS). For normal
3.2 Analog Inputs operation, the other pins are at voltages between VSS
and VDD.
The non-inverting and inverting inputs are
Typically, these parts are used in a single (positive)
high-impedance CMOS inputs with low bias currents.
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.

© 2009 Microchip Technology Inc. DS22196A-page 13

MCP6286
NOTES:

DS22196A-page 14 © 2009 Microchip Technology Inc.

 MCP6286
4.0 APPLICATION INFORMATION
VDD
The MCP6286 op amp is manufactured using
Microchip’s state-of-the-art CMOS process and is
specifically designed for low-power, low-noise D1 D2
applications.
V1
R1 MCP6286
4.1 Input
V2
4.1.1 PHASE REVERSAL R2
The MCP6286 op amp is designed to prevent phase
reversal when the input pins exceed the supply R3
voltages. Figure 2-31 shows the input voltage
exceeding the supply voltage without any phase VSS – (minimum expected V1)
R1 >
reversal. 2 mA
VSS – (minimum expected V2)
4.1.2 INPUT VOLTAGE AND CURRENT R2 >
2 mA
LIMITS
FIGURE 4-2: Protecting the Analog
The ESD protection on the inputs can be depicted as
Inputs.
shown in Figure 4-1. This structure was chosen to
protect the input transistors and to minimize input bias It is also possible to connect the diodes to the left of the
current (IB). The input ESD diodes clamp the inputs resistors R1 and R2. In this case, the currents through
when they try to go more than one diode drop below the diodes D1 and D2 need to be limited by some other
VSS. They also clamp any voltage that goes too far mechanism. The resistors then serve as in-rush current
above VDD; their breakdown voltage is high enough to limiters; the DC currents into the input pins (VIN+ and
allow normal operation and low enough to bypass ESD VIN-) should be very small. A significant amount of
events within the specified limits. current can flow out of the inputs when the common
mode voltage (VCM) is below ground (VSS). (See
Figure 2-33).
VDD Bond
Pad 4.1.3 NORMAL OPERATION
The input stage of the MCP6286 op amp uses a PMOS
input stage. It operates at low common mode input
voltage (VCM), including ground. With this topology, the
VIN+ Bond Input Bond
VIN–
Pad Stage Pad device operates with a VCM up to VDD - 1.2V and 0.3V
below VSS. (See Figure 2-12).The input offset voltage
is measured at VCM = VSS – 0.3V and VDD - 1.2V to
ensure proper operation.
VSS Bond
Pad For a unity gain buffer, since VOUT is the same voltage
as the inverting input, VOUT must be maintained below
FIGURE 4-1: Simplified Analog Input ESD VDD –1.2V for correct operation.
Structures.
4.2 Rail-to-Rail Output
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the The output voltage range of the MCP6286 op amp is
voltages and currents at the VIN+ and VIN- pins (see VSS + 15 mV (minimum) and VDD – 15 mV (maximum)
Absolute Maximum Ratings at the beginning of when RL = 10 kΩ is connected to VDD/2 and
Section 1.0 “Electrical Characteristics”). Figure 4-2 VDD = 5.5V. Refer to Figure 2-24 and Figure 2-25 for
shows the recommended approach to protecting these more information.
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN-) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN-) from going too far above VDD.
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.

© 2009 Microchip Technology Inc. DS22196A-page 15

MCP6286
4.3 Capacitive Loads 4.4 Supply Bypass
Driving large capacitive loads can cause stability MCP6286 op amp’s power supply pin (VDD for
problems for voltage feedback op amps. As the load single-supply) should have a local bypass capacitor
capacitance increases, the feedback loop’s phase (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high
margin decreases and the closed-loop bandwidth is frequency performance. It can use a bulk capacitor
reduced. This produces gain peaking in the frequency (i.e., 1 µF or larger) within 100 mm to provide large,
response, with overshoot and ringing in the step slow currents. This bulk capacitor can be shared with
response. While a unity-gain buffer (G = +1 V/V) is the other analog parts.
most sensitive to capacitive loads, all gains show the
same general behavior. 4.5 PCB Surface Leakage
When driving large capacitive loads with these op
In applications where low input bias current is critical,
amps (e.g., > 100 pF when G = +1 V/V), a small series
Printed Circuit Board (PCB) surface leakage effects
resistor at the output (RISO in Figure 4-3) improves the
need to be considered. Surface leakage is caused by
feedback loop’s phase margin (stability) by making the
humidity, dust or other contamination on the board.
output load resistive at higher frequencies. The
Under low humidity conditions, a typical resistance
bandwidth will be generally lower than the bandwidth
between nearby traces is 1012Ω. A 5V difference would
with no capacitance load.
cause 5 pA of current to flow; which is greater than the
MCP6286 op amp’s bias current at +25°C (±1 pA,
typical).
– The easiest way to reduce surface leakage is to use a
RISO
guard ring around sensitive pins (or traces). The guard
MCP6286 VOUT ring is biased at the same voltage as the sensitive pin.
VIN + CL An example of this type of layout is shown in
Figure 4-5.

FIGURE 4-3: Output Resistor, RISO Guard Ring VIN– VIN+ VSS
Stabilizes Large Capacitive Loads.
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-5: Example Guard Ring Layout
1000 for Inverting Gain.
VDD = 5.5 V
Recommended RISO (Ω)

RL = 10 kΩ 1. Non-inverting Gain and Unity-Gain Buffer:

100
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
GN:
1 V/V
PCB surface.
2 V/V b. Connect the guard ring to the inverting input
10
≥ 5 V/V
pin (VIN–). This biases the guard ring to the
common mode input voltage.
1 2. Inverting Gain and Transimpedance Gain
10p
1.E-11 100p
1.E-10 1n
1.E-09 10n
1.E-08 0.1µ
1.E-07 1µ
1.E-06 Amplifiers (convert current to voltage, such as
Normalized Load Capacitance; CL/GN (F)
photo detectors):
a. Connect the guard ring to the non-inverting
FIGURE 4-4: Recommended RISO Values
input pin (VIN+). This biases the guard ring
for Capacitive Loads. to the same reference voltage as the op
After selecting RISO for your circuit, double check the amp (e.g., VDD/2 or ground).
resulting frequency response peaking and step b. Connect the inverting pin (VIN–) to the input
response overshoot. Modify RISO’s value until the with a wire that does not touch the PCB
response is reasonable. Bench evaluation and surface.
simulations with the MCP6286 SPICE macro model are
very helpful.

DS22196A-page 16 © 2009 Microchip Technology Inc.

 MCP6286
4.6 Application Circuits 4.6.2 PHOTO DETECTION
The MCP6286 op amps can be used to easily convert
4.6.1 ACTIVE LOW-PASS FILTER the signal from a sensor that produces an output
The MCP6286 op amp’s low input bias current makes current (such as a photo diode) into a voltage (a
it possible for the designer to use larger resistors and transimpedance amplifier). This is implemented with a
smaller capacitors for active low-pass filter single resistor (R2) in the feedback loop of the
applications. However, as the resistance increases, the amplifiers shown in Figure 4-8 and Figure 4-9. The
noise generated also increases. Parasitic capacitances optional capacitor (C2) sometimes provides stability for
and the large value resistors could also modify the these circuits.
frequency response. These trade-offs need to be A photodiode configured in the Photovoltaic mode has
considered when selecting circuit elements. zero voltage potential placed across it (Figure 4-8). In
Figure 4-6 and Figure 4-7 show low-pass, this mode, the light sensitivity and linearity is
second-order, Butterworth filters with a cut-off maximized, making it best suited for precision
frequency of 10 Hz. The filter in Figure 4-6 has a applications. The key amplifier specifications for this
non-inverting gain of +1 V/V, and the filter in Figure 4-7 application are: low input bias current, low noise,
has an inverting gain of -1 V/V. common mode input voltage range (including ground),
and rail-to-rail output.

C1 G = +1 V/V
C2
47 nF fP = 10 Hz
R2
R1 R2 VOUT
ID1
382 kΩ 641 kΩ VDD
VIN + –
D1
C2 MCP6286 VOUT Light MCP6286
22 nF
– +
VOUT = ID1*R2
FIGURE 4-6: Second-Order, Low-Pass
Butterworth Filter with Sallen-Key Topology. FIGURE 4-8: Photovoltaic Mode Detector.
In contrast, a photodiode that is configured in the
Photoconductive mode has a reverse bias voltage
R2 G = -1 V/V across the photo-sensing element (Figure 4-9). This
618 kΩ fP = 10 Hz decreases the diode capacitance, which facilitates
high-speed operation (e.g., high-speed digital
communications). The design trade-off is increased
R1 R3 C1 diode leakage current and linearity errors. The op amp
618 kΩ 1.00 MΩ 8.2 nF needs to have a wide Gain Bandwidth Product
VIN VOUT (GBWP).
C2
–
47 nF
MCP6286 C2

VDD/2 +
R2
ID1 VOUT
FIGURE 4-7: Second-Order, Low-Pass VDD
Butterwork Filter with Multiple-Feedback –
D1
Topology. Light MCP6286

VBIAS + VOUT = ID1*R2

VBIAS < 0V

FIGURE 4-9: Photoconductive Mode

Detector.

© 2009 Microchip Technology Inc. DS22196A-page 17

MCP6286
NOTES:

DS22196A-page 18 © 2009 Microchip Technology Inc.

 MCP6286
5.0 DESIGN AIDS 5.4 Microchip Advanced Part Selector
(MAPS)
Microchip provides the basic design tools needed for
the MCP6286 op amp. MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
5.1 SPICE Macro Model fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
The latest SPICE macro model for the MCP6286 op maps, the MAPS is an overall selection tool for
amp is available on the Microchip web site at Microchip’s product portfolio that includes Analog,
www.microchip.com. The model was written and tested Memory, MCUs and DSCs. Using this tool you can
in official Orcad (Cadence) owned PSPICE. For the define a filter to sort features for a parametric search of
other simulators, it may require translation. devices and export side-by-side technical comparison
The model covers a wide aspect of the op amp's reports. Helpful links are also provided for Datasheets,
electrical specifications. Not only does the model cover Purchase, and Sampling of Microchip parts.
voltage, current, and resistance of the op amp, but it
also covers the temperature and noise effects on the 5.5 Analog Demonstration and
behavior of the op amp. The model has not been Evaluation Boards
verified outside of the specification range listed in the
op amp data sheet. The model behaviors under these Microchip offers a broad spectrum of Analog
conditions can not be guaranteed that it will match the Demonstration and Evaluation Boards that are
actual op amp performance. designed to help you achieve faster time to market. For
a complete listing of these boards and their
Moreover, the model is intended to be an initial design corresponding user’s guides and technical information,
tool. Bench testing is a very important part of any visit the Microchip web site at www.microchip.com/
design and cannot be replaced with simulations. Also, analogtools.
simulation results using this macro model need to be
validated by comparing them to the data sheet Some boards that are especially useful are:
specifications and characteristic curves. • MCP6XXX Amplifier Evaluation Board 1
• MCP6XXX Amplifier Evaluation Board 2
5.2 FilterLab® Software • MCP6XXX Amplifier Evaluation Board 3
• MCP6XXX Amplifier Evaluation Board 4
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using • Active Filter Demo Board Kit
op amps) design. Available at no cost from the • 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams 5.6 Application Notes
of the filter circuit with component values. It also
The following Microchip Analog Design Note and
outputs the filter circuit in SPICE format, which can be
Application Notes are available on the Microchip web
used with the macro model to simulate actual filter
site at www.microchip.com/appnotes and are
performance.
recommended as supplemental reference resources.

5.3 Mindi™ Circuit Designer & • ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
Simulator
• AN722: “Operational Amplifier Topologies and DC
Microchip’s Mindi™ Circuit Designer & Simulator aids Specifications”, DS00722
in the design of various circuits useful for active filter, • AN723: “Operational Amplifier AC Specifications
amplifier and power-management applications. It is a and Applications”, DS00723
free online circuit designer & simulator available from
• AN884: “Driving Capacitive Loads With Op
the Microchip web site at www.microchip.com/mindi.
Amps”, DS00884
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams, • AN990: “Analog Sensor Conditioning Circuits –
simulate circuits. Circuits developed using the Mindi An Overview”, DS00990
Circuit Designer & Simulator can be downloaded to a • AN1177: “Op Amp Precision Design: DC Errors”,
personal computer or workstation. DS01177
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
These application notes and others are listed in the
design guide:
• “Signal Chain Design Guide”, DS21825

© 2009 Microchip Technology Inc. DS22196A-page 19

MCP6286
NOTES:

DS22196A-page 20 © 2009 Microchip Technology Inc.

 MCP6286
6.0 PACKAGING INFORMATION
6.1 Package Marking Information

5-Lead SOT-23 Example:

5 4 5 4

XXNN WENN

1 2 3 1 2 3

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

© 2009 Microchip Technology Inc. DS22196A-page 21

MCP6286


 


 
 .#  #$ #
/ !- 0
   # 
1/
%## !#
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+22---
2
/

b
N

E
E1

1 2 3
e
e1
D

A A2 c φ

A1 L

L1

3# 44""
  4# 5 56 7
5$8 %1 5 (
4 !1# ()*
6$# ! 4 !1#  )*
6, 9 #   : (
! !1/ /  ; : 
#!%%   : (
6, <!# "  : 
! !1/ <!# "  : ;
6, 4 #   : 
.#4 # 4  : =
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.#  > : >
4 !/  ; : =
4 !<!# 8  : (

    !"!#$! !% 
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#$   # & !
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"'(
)*+ )     # &#,$  --#$##  

  - * )

DS22196A-page 22 © 2009 Microchip Technology Inc.

 MCP6286
APPENDIX A: REVISION HISTORY

Revision A (August 2009)

• Original Release of this Document.

© 2009 Microchip Technology Inc. DS22196A-page 23

MCP6286
NOTES:

DS22196A-page 24 © 2009 Microchip Technology Inc.

 MCP6286
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX Examples:

a) MCP6286T-E/OT: Tape and Reel,
Device Temperature Package 5-LD SOT-23 package
Range

Device: MCP6286T: Single Op Amp (Tape and Reel)

Temperature Range: E = -40°C to +125°C

Package: OT = Plastic Small Outline Transistor, 5-lead

© 2009 Microchip Technology Inc. DS22196A-page 25

MCP6286
NOTES:

DS22196A-page 26 © 2009 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
rfPIC and UNI/O are registered trademarks of Microchip
MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries.
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip
QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard,
arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
hold harmless Microchip from any and all damages, claims, Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net,
conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
intellectual property rights. Endurance, TSHARC, WiperLock and ZENA are trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

© 2009 Microchip Technology Inc. DS22196A-page 27

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DS22196A-page 28 © 2009 Microchip Technology Inc.