Received: 20 September 2020 Revised: 30 December 2020 Accepted: 4 February 2021

DOI: 10.1002/2050-7038.12834

RESEARCH ARTICLE

Extracted DC component-based pilot relaying

for series-compensated lines

Jai Prakash Sharma1 | Kasala Vijetha2 | Priya Bharti3 | Balla Satya Sravani4 |
Om Hari Gupta1

1
Department of Electrical Engineering,
National Institute of Technology
Summary
Jamshedpur, Jamshedpur, Jharkhand, Integration of a series capacitor in a transmission line not only has advantages
India such as system stability and power factor improvements, voltage profile regula-
2
ALSTOM Transport India Limited,
tion, and power flow maximization but also shows some unwanted effects such
Bengaluru, Karnataka, India
3 as current and voltage inversion, change in line impedance, and subharmonic
Analytics Quotient Services India Private
Limited, Bengaluru, Karnataka, India frequency that leads to mal-operation of the conventional protection scheme.
4
Oracle Financial Services Software This paper introduces a fault detection method for a series-compensated line.
Limited, Bengaluru, Karnataka, India An algorithm is proposed that uses the extracted DC component of currents at
Correspondence both sending and receiving ends to detect the fault and generate a trip signal.
Om Hari Gupta, Department of Electrical The proposed protection criterion is successfully examined for diversified
Engineering, National Institute of
(adverse) conditions using PSCAD/EMTDC simulations.
Technology Jamshedpur, Jamshedpur,
Jharkhand 831014, India.
KEYWORDS
Email: omhari.ee@nitjsr.ac.in
current reversal, DC component, series compensation, transmission line protection, voltage
Handling AE: Dr. Jalilzadeh- reversal
Hamidi, Reza

1 | INTRODUCTION

The insertion of a capacitive reactive element in series with a transmission line (TL) improves the load ability as well as stabil-
ity (both transient and voltage) of the line by reducing voltage drop and angular deviation.1 It maximizes power transfer

List of Symbols and Abbreviations: CT, current transformer; DC, direct current; EDCC, extracted direct current component; EHV, extra high
voltage; MOV, metal oxide varistor; PSCAD/EMTDC, power system computer aided design/electromagnetic transients including DC; Rf, fault
resistance; TL, transmission line; kA, kilo ampere; kV, kilo volt; μF, micro farad; p.u., per unit; Fig., figure; XS, source reactance; XL, line reactance
between circuit breaker and fault point; XC, capacitive reactance of the series capacitor; Vswoc, voltage at end-s during a fault without compensation;
Iswoc, current at end-s during a fault without compensation; Vswc, voltage at end-s during a fault with a series compensation in TL; Iswc, current at
end-s during a fault with a series compensation in TL; Es, source voltage at end-s; Is, current being measured at end-s relay; idc, DC component; Vm,
maximum value of voltage v(t) = Vm sin(ωt + θ); V, voltage; I, current; R, resistor; L, inductor; C, capacitor; ω, angular velocity in radians per second;
t, time in seconds; θ, phase angle; Idcs, EDCC being measured at end-s; Idcr, EDCC being measured at end-r; Tzs, zero-crossing time of Idcs; Tzr,
zero-crossing time of Idcr; ZCTs, zero-crossing times; DZ, difference of ZCTs; IRIG-B, inter-range instrumentation group timecodes-B; IEDs,
intelligent electronic devices; GPS, global positioning system; DZa, difference of ZCTs for phase-a; DZb, difference of ZCTs for phase-b; DZc,
difference of ZCTs for phase-c; Ta, time of trip signal generation for phase-a breakers; Tb, time of trip signal generation for phase-b breakers; Tc, time
of trip signal generation for phase-c breakers; A-G fault, phase-a-to-ground fault; B-G fault, phase-b-to-ground fault; C-G fault, phase-c-to-ground
fault; AB-G fault, phase-a-to-b-to-ground fault; BC-G fault, phase-b-to-c-to-ground fault; CA-G fault, phase-c-to-a-to-ground fault; AB fault, phase-a-
to-b fault; BC fault, phase-b-to-c fault; CA fault, phase-c-to-a fault; ABC fault, three-phase fault; km, kilometer; ms, micro second; IasCR, fault current
with current reversal condition; IasNCR, fault current without current reversal condition; TS, trip signal; VasVR, phase voltage with voltage reversal
condition; VasNVR, phase voltage without voltage reversal condition; FDOST, fast discrete orthonormal s-transform.

Int Trans Electr Energ Syst. 2021;e12834. wileyonlinelibrary.com/journal/etep © 2021 John Wiley & Sons Ltd 1 of 18
https://doi.org/10.1002/2050-7038.12834
2 of 18 SHARMA ET AL.

capability and also optimizes power-sharing between the parallel circuits. Therefore, the series compensation is mostly pre-
ferred for optimizing the performance of TLs and increasing their efficiency. Since it alters the electrical characteristics of the
line and pushes extra power through the same line, the protection system applied to the transmission network gets affected.2,3
The distance protection, normally preferred as a primary TL protection scheme, does not provide expected performance
when used for series-compensated lines.4 During faults, a series capacitor with an MOV causes nonlinear operation. Also, it may
cause the presence of subharmonics, DC decaying component, and underreaching or overreaching—which are also explained in
Reference 5. There are many relaying schemes, proposed for the aforementioned problems, and some of the latest schemes have
been discussed next. Some adaptive distance relaying techniques have been proposed earlier to cope with the impact of series
capacitor compensation in TL, for example, in Reference 6, adaptive distance protection for a series-compensated TL is proposed
and the nonlinear characteristic of an MOV is taken into consideration. The distance protection is modified by computing the
voltage drop across the series capacitor but is not reliable for the detection of a high resistance fault. In Reference 7, the mutual
impedance between phases of a TL is considered and used in implementing the protection scheme for series-compensated lines.
This scheme overcomes the effects caused by variation in positive sequence impedance and prevents mal-operation of distance
relays. However, it may find limitations when it comes to three-phase and phase-phase faults since zero sequence components
are not available. A new active and reactive power variation based protection scheme has been introduced in Refer-
ence 8. The scheme is tested for 0% to 50% compensation levels variation and is sensitive up to 100 Ω fault resistance
(Rf). With some basic advantages, differential relaying scheme is dominant over distance relaying in the presence of
series compensation in TL9; however, it also finds limitations in detecting high resistance faults.10 Some recently
proposed pilot-based relaying algorithms have been discussed next. The paper11 introduces a fault location method
for a series-compensated line based on synchronized phasor measurement that uses voltages of terminals at pre-fault
and during-fault intervals to detect a fault. In Reference 11, the authors have introduced a high-speed intelligent
scheme where the differential phase angle of superimposed current based on the decision tree is used. This scheme
is complex and requires memory space and time for execution. Another article12 presents a new differential
admittance-based pilot relaying scheme for the protection of a fixed series-compensated EHV TL. The scheme works
fine for most of the cases. However, it was unable to distinguish between close-in bolted external and internal faults
and the reason behind that is the voltage becomes close to zero, thereby making the admittance to be very high.
Addressing all such limitations, this manuscript introduces the use of extracted DC components of current (EDCC)
measured during transient conditions13 in identifying the internal fault. This proposed pilot-based communication-
aided relaying scheme is immune to the aforementioned problems in protecting a series-compensated TL. The availabil-
ity of high-speed communication channels in most modern transmission systems makes it easy to implement the
pilot-based schemes.12 The applicability of the scheme presented in this paper is investigated for a variety of faulty
situations using PSCAD/EMTDC simulations. Following are the highlights/contributions of the proposed scheme:

• Detects the internal faults successfully incepted at any line length.

• Classifies the types of internal faults successfully.
• Can detect the faults up to 500 Ω fault resistance.
• Gives better response if compared with one of the recent schemes.
• Unaffected by the variations in the compensation level.
• Unaffected by the location of the compensating device.
• Hardly affected by the inception angle variation.
• Accurately detects the evolving faults.
• Performance is unaffected by the simultaneous faults.
• Unaffected by the measurement errors due to CT.

The remainder of the paper is organized as follows. Section 2 discusses the effects of a series capacitor in TL. The
proposed methodology is explained in Section 3. The obtained results and corresponding discussions are presented in
Section 4. The conclusion is added to Section 5, and in the end, references are provided.

2 | E F F E C T S O F SE R I E S CA P A C I T O R

Faults in a TL result in the flow of heavy current through the line and series capacitor. Therefore, metal oxide varistor
(MOV), spark gap, and circuit breaker are connected across the terminals of the capacitor as shown in Figure 1A.
SHARMA ET AL. 3 of 18

FIGURE 1 A, Overvoltage protection of capacitor, B, MOV V-I characteristics14

T A B L E 1 MOV's current and

Voltage (in p.u.) Current (in p.u.)
voltage per unit data
1.1 0.001
1.6 0.01
1.7 0.1
1.739 0.2
1.777 0.38
1.815 0.65
1.853 1.11
1.881 1.5
1.91 2
1.948 2.8
3.2 200

During a fault, voltage across the capacitor is very high and if it is more than the threshold voltage of MOV, it starts
conducting and current is bypassed. Since the rated current during normal operating condition is 3.2 kA through the
series capacitor of 95.58 μF (30% compensation), hence the voltage rating of MOV used is 106.5 kV as per.15 The voltage
(V)-current (I) characteristic of MOV is depicted in Figure 1B and corresponding voltage and current data, in per unit,
are given in Table 1, below. Now, the major impacts of a series compensation have been included next.

2.1 | Changes in compensating unit impedance

For high fault currents, the impedance of the series compensating unit is equal to the MOV, whereas, during low fault
currents, it is equal to the parallel combination of MOV and series capacitor impedances. Therefore, the presence of a
series compensating unit causes abrupt changes in apparent impedance seen by the relay, and the relay may overreach
and lose its directional integrity.

2.2 | Voltage and current inversions

Voltage inversion is defined as a phenomenon in which the voltage at relay bus becomes negative.16 Considering the
relay at end-s, as shown in Figure 2, the conditions for a voltage inversion will be as mentioned below in (1):
4 of 18 SHARMA ET AL.

F I G U R E 2 An equivalent circuit for a fault in a series-

compensated line

F I G U R E 3 Current and voltage phasor recorded at relay-end

bus for, A, Voltage inversion, B, Current inversion phenomena

XC > XL
ð1Þ
XC < XL + XS

where XS = Source reactance, XL = Line reactance between circuit breaker and fault point, XC = Capacitive reactance
of the series capacitor.
Two different phasor diagrams are depicted in Figure 3 for the explanation of voltage and current inversion phe-
nomena, where Vswoc and Iswoc are the voltage and current at end-s during a fault without compensation and Vswc and
Iswc are the voltage and current at end-s with the presence of a series compensation in TL, respectively.
From the phasor diagram of Figure 3A, it can be evaluated that for a fault without series capacitor in TL, Vswoc leads
the line current Is as impedance seen by relay at bus is inductive in nature. Whereas in the case of a fault with series
compensation, Vswc may lag Is by 90 if (E.1.1) is satisfied, that is, creates a situation of voltage reversal.
On other hand, the current inversion is defined as a phenomenon in which the current through the relay bus
becomes negative.16 The condition at which current inversion occurs is given in (2):

XC > XL + XS ð2Þ

It can be observed from Figure 3B, that a fault current lags Es by 90 in the case when there is no compensation,
whereas in the case when compensation is provided, the fault current may lead Es by 90 if (2) is satisfied. Such a phe-
nomenon is called a current reversal phenomenon. Moreover, by observing the above conditions, it can be concluded
that voltage and current inversions do not occur simultaneously.

3 | P R O P O S ED W O R K

First, an uncompensated line has been considered to observe the extracted DC component of current (EDCC). The line
charging component has been ignored for this analysis since it has a minor impact on EDCC. However, a practical dis-
tributed model of a TL is considered for the simulation study. The approximate equivalent TL circuit during a line fault
is given in Figure 4. Now, applying Kirchhoff's voltage law and solving the first-order differential equation, the current
equation consisting of an EDCC can be obtained as given by idc in (3).
SHARMA ET AL. 5 of 18

idc = I o e − t=τ ð3Þ

  
where I o = − pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Vm
sin θ −tan − 1 ωL , and Vm is the maximum value of voltage v(t) = Vm sin(ωt + θ).
ðR + ω L Þ
2 2 2 R

It is clear from (3) that the EDCC (ie, idc) is an exponentially decaying function for an uncompensated line.
Now, consider a capacitor in the line as manifested in Figure 5. The second-order differential equation is solved,17
and it is observed that the outcome will be under-damped sinusoidal current. The EDCC is given in (4) below.

idc = eαt ½K1 cosðβt Þ + K2 sinðβt Þ ð4Þ

where values of K1 and K2 depend on the initial states of L and C (the values of K1 and K2 hardly affect the characteris-
rhffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiiffi
 R 2 1
tics of DC component of the current and its zero-crossing time), α = −2LR and β = 2L − LC .

It can be seen from (3) and (4) that the nature of EDCC is different in both cases. When a capacitor is not included
in the circuit, the response is exponentially decaying and with the capacitor, it is under-damped—the corresponding
responses are illustrated in Figure 6.
It can be concluded that in series-compensated lines, the nature of waveform of EDCCs at end-s (ie, Idcs) and end-r
(ie, Idcr) will differ depending upon the location of the internal fault with respect to the capacitor—while these currents

FIGURE 4 Equivalent circuit of an uncompensated TL during a line fault

FIGURE 5 Equivalent circuit of a series-compensated TL during a line fault

F I G U R E 6 The DC component of a fault current without and

with a capacitor
6 of 18 SHARMA ET AL.

FIGURE 7 Flowchart of the proposed scheme

will almost be the same for external faults. This observation has been used for an internal fault detection by capturing
the corresponding zero-crossing times (ZCTs) of EDCCs, that is, Idcs and Idcr as Tzs and Tzr, respectively. The flow-
chart of the proposed algorithm, explaining the step-by-step approach, is shown in Figure 7 and its practical implemen-
tation is presented in Figure 8.
First of all, the phase currents are recorded at both ends. After that, EDCCs are computed by taking one cycle mov-
ing average of instantaneous sampled phase currents,18 by using Equation (5) at both the relaying ends.
SHARMA ET AL. 7 of 18

FIGURE 8 Practical implementation of the proposed scheme

1X N
Idcax ðk + NÞ = Iax ðk + nÞ ð5Þ
N n=1

where x = s or r for sending or receiving relaying ends.

Initially, the flags, that is, n and m are kept equal to zero. If Idcs has crossed zero then the zero-crossing of Idcr is
checked and vice versa. If both crosses zero within the span of seven samples (ie, m < 7 and the difference of ZCTs,
DZ = jTzs-Tzrj < 7 ms), it is an external disturbance, else if one of the currents (ie, Idcs or Idcr) crosses zero and other
does not, it will be an internal fault and a trip signal will be generated. The flag n stores the information of zero-
crossing while flag m reflects the timer count. If m ≥ 7 (ie, DZ ≥ 7 ms), an internal fault is declared.
With the advancement in time synchronization communication,19-21 inter-range instrumentation group
timecodes-B (IRIG-B) signals are preferred for precise operation of intelligent electronic devices (IEDs) in a power sys-
tem with an accuracy of 1 μs as per.22 Relays are synchronized with GPS satellite to record the sampled GPS time-
tagged line currents at both ends for the proposed scheme. Optical fiber-based communication link has been used for
communication between the relays.22 Both relays exchange the measured data to others, to execute the proposed algo-
rithm at their end for TL protection. Moreover, with IRIG-B time-tagged signals and optical fiber as a communication
link, the fault can be detected within the specified time (under 50 ms as per23).

4 | R ESULTS A ND DISCUSSIONS

In order to validate the performance of the proposed scheme, a series-compensated TL is considered. The system is ana-
lyzed by creating faults at different locations for various fault resistances, fault inception angles, and fault types using
PSCAD/EMTDC simulations.24
The location of the capacitor in line is decided using several factors such as economic and technical parameters,
characteristics of the line, and degree of compensation of the line. Installing the capacitor at the terminals of the line is
more preferred and is cost-effective as it will save installation cost.7,25-27 However, a lot of studies have also used mid-
point series-compensated lines.6,28-30 Therefore, in this study, both the locations are considered for performance investi-
gation. The sampling frequency is 1000 Hz. The system data are given below:
System voltage = 400 kV, frequency = 50 Hz, Generator-s: phase angle = 45 , Generator-r: phase angle = 0 , total
length of line = 300 km, positive sequence resistance = 0.018 × 10−3 Ω/m, positive sequence inductive reactance of line
(XL) = 0.37 × 10−3 Ω/m and considering 30% compensation, the value of series capacitor = 95.58 μF. The single line
diagram of the abovementioned series-compensated transmission system is displayed in Figure 9.

4.1 | Performance analysis with variation in fault location and fault type

In an electrical power system, faults can occur at any line length. Therefore, to investigate the performance and accuracy of
the proposed scheme, a variety of faults at different locations in the line are created at time t = 2.8 s. The obtained results
are shown in Table 2. All fault conditions considered have been identified successfully and corresponding trip signals are
generated with an average time of 23.1 ms. The difference of ZCTs (DZs) of differential EDCCs measured from both relay
8 of 18 SHARMA ET AL.

F I G U R E 9 Single-line diagram of mid-point series-

compensated TL

TABLE 2 DZs and trip timing for different faults at various locations

Fault location from end-s (km) Fault Type DZa (ms) DZb (ms) DZc (ms) Ta (ms) Tb (ms) Tc (ms)
0 (F2) A-G 19 1 1 22 - -
0 (F2) B-G 2 13 2 - 16 -
0 (F2) C-G 3 3 18 - - 25
0 (F2) AB 16 16 0 19 19 -
0 (F2) ABC 18 13 17 21 16 25
150 (F2) A-G 17 5 5 21 - -
150 (F2) B-G 3 14 3 - 18 -
150 (F2) CA 16 0 15 23 - 22
200 (F3) B-G 6 14 6 - 18 -
200 (F3) C-G 1 1 15 - - 26
200 (F3) AB 17 17 1 21 21 -
200 (F3) BC-G 6 13 16 - 16 30
200 (F3) ABC 20 14 18 24 18 29
300 (F3) C-G 1 1 16 - - 29
300 (F3) BC 0 14 14 - 33 33
300 (F3) BC-G 0 14 15 - 18 31
300 (F3) ABC 22 16 17 26 20 30
−15 (F1) C-G 1 1 1 - - -
−15 (F1) CA 1 0 1 - - -
−15 (F1) AB-G 0 0 1 - - -
−15 (F1) ABC 1 0 1 - - -
−0 (F1) A-G 1 1 1 - - -
−0 (F1) AB 1 1 0 - - -

ends of phase-a, b, and c are DZa, DZb, and DZc, respectively. Similarly, Ta, Tb, and Tc represent tripping times for phase-a,
b, and c, respectively. From Table 2, it is clear that all the internal faults are successfully identified by the EDCC scheme.
For an internal A-G fault at 00 km (F2-side) from end-s, it can be seen from Figure 10A that ZCTs of EDCCs of
phase-a at end-s and end-r are different compared to phase-b and phase-c. Also, as mentioned in Table 2, the value of
DZa ≥ 7. Hence, phase-a is perceived as faulty phase and trip signal (ie, Trip-A) is generated at 2.822 seconds as shown
in Figure 10A. The measured three-phase voltage and current from both relaying ends are depicted in Figure 10B.
Similarly, from Figure 11A, it can be seen that ZCTs of EDCCs of phase-b and phase-c, measured from both relaying
ends, are different for an internal BC fault at 300 km (F3-side) from end-s. Also, the values of DZb and DZc are equal or
more than 7, hence the faulty phases are identified as phase-b and phase-c. Therefore, the trip signals are generated.
Figure 11B portrays EDCCs and trip signals for an external AB fault at 00 km (F1-side) from end-s. It can be seen that
the corresponding DZs are less than 7 (ie, DZa = DZb = 1 and DZc = 0). So, the fault is detected as an external fault
and there is no generation of the trip signal.
SHARMA ET AL. 9 of 18

F I G U R E 1 0 A, EDCCs and trip signals, B, three-phase voltage

and current from both relaying ends for A-G fault at 00 km (F2-side)
from end-s, respectively

4.2 | Performance analysis in the presence of high resistance faults

Sometimes a high resistance fault affects the relaying scheme.31 Hence, it is necessary to examine the proposed
scheme against the high resistance fault. Various types of faults with different fault resistances are introduced at
200 km (F3-side) from end-s, and the obtained results are listed in Table 3. All fault conditions considered are suc-
cessfully identified by the EDCC method and accordingly trip signals are generated with an average time of
22.11 ms.
Figure 12 depicts EDCCs and trip signals for an internal C-G fault at 200 km (F3-side) from end-s with Rf = 500 Ω.
It can be observed that DZc ≥ 7 and other phases of DZs are less than 7. So, the faulty phase is perceived as phase-c and
the trip signal (Trip-C) is generated at 2.821 seconds.

4.3 | Performance analysis with the variations in fault inception angle

The proposed scheme uses the EDCC, which can be affected by the angle of inception of the fault. 28
Therefore, it is essential to test the performance of the proposed scheme for variations in fault inception angle.
10 of 18 SHARMA ET AL.

F I G U R E 1 1 EDCCs and trip signals for, A, an internal BC fault

at 200 km (F3-side), and for, B, an external AB fault at 00 km (F1-
side) from end-s, respectively

TABLE 3 DZs and trip timing for various fault resistances Rf

Rf (Ω) Fault Type DZa (ms) DZb (ms) DZc (ms) Ta (ms) Tb (ms) Tc (ms)
50 A-G 15 1 1 19 - -
100 15 1 1 19 - -
500 14 1 1 18 - -
50 B-G 1 12 1 - 16 -
100 1 11 1 - 15 -
500 1 10 1 - 14 -
50 C-G 1 1 13 - - 23
100 1 1 12 - - 22
500 1 1 12 - - 21

For that, an A-G fault at 200 km (F 3 -side) is introduced from end-s with different inception angles as listed in
Table 4.
It can be seen that all the considered faults have been identified successfully by the proposed scheme and accord-
ingly trip signals are generated with an average time of 32.57 ms. Figure 13A represents EDCCs from end-s and end-r
SHARMA ET AL. 11 of 18

F I G U R E 1 2 EDCCs for C-G fault at 200 km (F3-side) from

end-s with Rf = 500 Ω

TABLE 4 DZs and trip timing for variation in fault inception angle

Fault inception angle (degree) Rf (Ω) DZa (ms) DZb (ms) DZc (ms) Ta (ms) Tb (ms) Tc (ms)
45 00 16 6 6 22 - -
90 50 11 1 1 30 - -
135 100 14 6 6 29 - -
180 00 17 6 6 31 - -
225 500 12 1 1 28 - -
270 70 11 4 4 40 - -
315 30 15 6 6 40 - -

with fault inception angle of 180 . It can be observed that DZa ≥7. Hence, phase-a is sensed as a faulty phase. In
Figure 13B, EDCCs and trip signals are shown for an internal fault with a fault inception angle of 315 . It can be seen
that DZa ≥7. So, phase-a is, again, detected as a faulty phase.

4.4 | Performance with CT error

Though there are methods to avoid the CT saturation effect,32 it needs to be studied in detail. To show the impact of CT
measurement error, JA-modeled CTs (available in PSCAD software) are used, and the CT ratio is changed to 1:75 from
5:3000, intentionally. For an internal bolted A-G fault at 150 km (F2-side), it can be seen from Figure 14A that the pri-
mary current is not transferred accurately to secondary and cause CT saturation error. It can be observed from
Figure 14B that ZCTs of EDCCs of phase-a at end-s and end-r are different, and analogous DZs, measured during the
disturbance, are DZa = 17, DZb = DZc = 3. So, phase-a is detected as a faulty phase as DZa ≥ 7 as compared to other
phases.

4.5 | Performance analysis in the case of evolving fault

To create an evolving fault condition, a C-G fault is incepted at 2.8 seconds with a distance of 200 km from end-s
and after 0.6 second, that is, at 2.86 seconds, a B-G fault is introduced at the same location. It can be seen from
Figure 15A that ZCTs of EDCCs of the phase-c measured at both relaying ends are different and the corresponding
DZs are as follow: DZa = DZb = 1, DZc = 13. So, trip signal, Tc, is generated at 2.624 seconds for faulty phase-c as
DZc ≥ 7 compared to other phases. Likewise, ZCTs of EDCCs of phase-b are different after 2.86 seconds and DZs
are DZa = 1, DZb = 23, and DZc = 13. It reflects that a C-G fault is evolved to a BC-G fault. So, Tb is high at
2.887 seconds.
12 of 18 SHARMA ET AL.

F I G U R E 1 3 EDCCs and trip signals with fault inception angle

of, A, 180 , B, 315

Overall, the proposed method is able to detect fault as an internal fault and classifies the faulty phases. Therefore,
the scheme remains valid for the aforementioned case. The difference in trip times is because of the unequal detection
times since the fault inception angles of phase-b and phase-c are not the same.

4.6 | Performance analysis in the case of simultaneous faults

For such a case, an external bolted A-G fault is created at 00 km (F1-side), and at the same time, an internal BC-G fault
is incepted at 150 km (F2-side) from end-s, respectively. The ZCTs of EDCCs of phase-a are equal, whereas, in the case
of phase-b and phase-c, ZCTs are different as shown in Figure 15B. Also, DZs obtained are as follow: DZa = 1,
DZb = 11, and DZc = 11. It can be seen that both DZb and DZc are greater than 7. Hence, phase-b and phase-c are iden-
tified as the faulty phases and corresponding Tb = 15 ms and Tc = 23 ms, respectively.

4.7 | Performance analysis with variation in location and compensation level

The location and level of compensation can affect the performance of the relaying scheme.33 Hence, it is necessary to
test the performance of the proposed scheme for change in compensation level and location. For that, the same system
has been used with 70% compensation, the value of the series capacitor is 41 μF and the series-compensation is located
at 00 km from end-s as shown in Figure 16.
SHARMA ET AL. 13 of 18

F I G U R E 1 4 A, Phase-a primary and secondary currents of

CT, B, EDCCs of all three phases and trip signal for an internal
bolted A-G fault at 150 km (F2-side) from end-s

As the rated current during normal operating condition is increased to 3.4 kA, so accordingly MOV rated
voltage has changed to 264 kV as per. 15 A variety of faults is introduced at F1 (external fault) and F 2 sides (inter-
nal fault) for the validation of the proposed scheme. The acquired results are shown in Table 5. It can be seen
that all the considered faults are detected suitably with the proposed method and corresponding trip signals are
generated with an average time of 19.3125 ms.
Figure 17A depicts EDCCs from end-s and end-r and trip signals for an internal A-G fault at 00 km from
end-s. It can be seen that DZa ≥ 7 as compared to other phases. So, the fault is declared in phase-a, and Ta
becomes high at 2.814 s. Similarly, for an external ABC at -30 km (F1 -side), DZs are as follows:
DZa = DZb = DZc = 1, as depicted in Table 5. Hence, all the three phases are considered as healthy phases and
no trip signals are generated as manifested in Figure 17B. The proposed method is found to be selective for the
variations in the compensation level.

4.8 | Performance analysis with current and voltage inversion scenarios

The test system, as shown in Figure 16, has been used with 70% compensation for the investigation under
voltage/current reversals. Moreover, to procreate the aforesaid conditions, MOV operations have been ignored.
With end-point compensation, current reversal is identified up to 135.8 km of line length and there onwards
voltage reversal can be experienced up to 209.8 km. Firstly, to have a current inversion, a three-phase fault is
created at 50 km (F2 -side) from end-s, and the corresponding results are manifested in Figure 18A. To show the
current reversal, phase-A current at end-s for three-phase fault at 50 km is plotted together with that of
three-phase fault at 300 km.
14 of 18 SHARMA ET AL.

F I G U R E 1 5 EDCCs and trip signals for, A, an evolving fault at

200 km (F3-side) from end-s, B, simultaneous faults condition

F I G U R E 1 6 Single line diagram of series-compensated at 00 km

from end-s of TL

It can be seen in Figure 18A that phase-a fault current during three-phase fault at 50 km (F2-side; ie, IasCR—fault
current with current reversal condition) is shifted by 180 with that of three-phase fault at 300 km (F2-side; ie, IasNCR—
fault current without current reversal condition). This scenario is termed as current reversal. Moreover, as ZCTs of
EDCCs of all three-phases are different after fault inception, the fault is identified as a symmetrical fault and
corresponding trip signals (TS) are generated.
Similarly, to have a voltage inversion, a symmetrical fault is created at 180 km (F2-side) from end-s and the obtained
results are depicted in Figure 18B. It can be seen from Figure 18B that phase-a voltage during three-phase fault at
180 km (F2-side; ie, VasVR—phase voltage with voltage reversal condition) is shifted by 180 with that of three-phase
fault at 300 km (F2-side; ie, VasNVR—phase voltage without voltage reversal condition). Since DZs of all three-phases
are more than 6, fault is perceived as symmetrical fault. As a final observation, it can be concluded that scheme remains
valid for current and voltage reversal scenarios.
SHARMA ET AL. 15 of 18

TABLE 5 DZs and trip timing with a 70% compensation level

Fault location from end-s (km) Fault Type DZa (ms) DZb (ms) DZc (ms) Ta (ms) Tb (ms) Tc (ms)
0 (F2) A-G 9 1 1 14 - -
0 (F2) AB 8 8 1 19 19 -
150 (F2) ABC 14 10 15 18 13 22
150 (F2) BC-G 4 10 13 - 24 23
200 (F2) C-G 2 2 13 - - 23
200 (F2) ABC 16 12 13 20 16 24
300 (F2) CA 15 0 15 22 - 22
300 (F2) BC 0 11 11 - 15 15
−0 (F1) A-G 1 1 1 - - -
−30 (F1) ABC 1 1 1 - - -

F I G U R E 1 7 EDCCs and trip signals for, A, an internal A-G

fault at 00 km (F2-side), B, an external ABC fault at −30 km (F1-side)
from end-s, respectively

4.9 | Comparison with a recently published method

The proposed scheme has been compared with a fast discrete orthonormal s-transform (FDOST)-based method as pro-
posed in Reference 4, and the acquired analysis is elaborated in Table 6. The performance of the FDOST-based
16 of 18 SHARMA ET AL.

F I G U R E 1 8 EDCCs and trip signal for, A, Current reversal, B,

Voltage reversal scenarios

TABLE 6 Summary of comparison with the recently published method

Attributes FDOST-based scheme Proposed scheme

Maximum Rf (Ω) 200 500
Applicable for compensation level 60% 70%
Performance analysis in the case of evolving fault No Yes
Performance analysis in the case of simultaneous faults No Yes
The dependency on the variations of system parameters Highly dependent Not dependent

algorithm was not examined under evolving and simultaneous faults, as the aforementioned cases may impact the reli-
ability of a relaying scheme. The sensitivity of the FDOST-based scheme is limited to 200 Ω fault resistance only while
the proposed method has a better sensitivity up to 500 Ω. Another limitation of the FDOST-based algorithm is that with
the variations in system parameters, the scheme needs to be trained again. On the other hand, the proposed method
did not have any impact on variations in the system parameters.
SHARMA ET AL. 17 of 18

5 | C ON C L U S I ON

The impact of a series-compensation on pilot relaying scheme for a TL is addressed in this paper. A new extracted DC
component of current-based pilot relaying has been proposed, which is unaffected by series compensation. The perfor-
mance of the proposed scheme has been validated by using PSCAD/EMTDC simulations for different situations like dif-
ferent fault types, fault locations, fault resistances, inception angles, evolving faults, voltage/current inversion
problems, and simultaneous faults. The proposed scheme is also tested for change in compensation level and also com-
pared with recently published scheme. Moreover, as currents from both relying-ends are required to be recorded for the
proposed algorithm, the impact of CT error has also been evaluated in this paper. Based on rigorous simulation results,
the proposed scheme is found to be accurate, selective, able to classify the faults, and reliable for the protection of the
series-compensated TL system.

P EE R R EV IE W
The peer review history for this article is available at https://publons.com/publon/10.1002/2050-7038.12834.

DATA AVAILABILITY STATEMENT

Data sharing is not applicable to this article as no new data were created or analyzed in this study.

ORCID
Om Hari Gupta https://orcid.org/0000-0001-6171-809X

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How to cite this article: Sharma JP, Vijetha K, Bharti P, Satya Sravani B, Gupta OH. Extracted DC component-
based pilot relaying for series-compensated lines. Int Trans Electr Energ Syst. 2021;e12834. https://doi.org/10.
1002/2050-7038.12834