Digital Circuits MCQ (Multiple Choice

Questions)
1. What is Digital Electronics?
a) Field of electronics involving the study of digital signal
b) Engineering of devices that digital signal
c) Engineering of devices that produce digital signal
d) All pf the mentioned
View Answer

Answer: d
Explanation: Digital electronics is a branch of electronics concerned with the study of digital
signals as well as the design of systems that use or generate them. For electronics, gadgets, and
equipment, “boolean logic” and “discrete signal electronics” are used.

2. Which of the following is correct for Digital Circuits?

a) Less susceptible to noise or degradation in quality
b) Use transistors to create logic gates to perform Boolean logic
c) Easier to perform error detection and correction with digital signal
d) All of the mentioned
View Answer

Answer: d
Explanation: A digital circuit is a circuit that has a signal that must fall into one of two discrete
levels. Each level is read as one of two states (on/off, 0/1, true/false, for example). To perform
Boolean logic, digital circuits use transistors to generate logic gates.

3. What is a Circuit?
a) Open-loop through which electrons can pass
b) Closed-loop through which electrons can pass
c) Closed-loop through which Neutrons can pass
d) None of the mentioned
View Answer

Answer: b
Explanation: A circuit is a closed-loop through which electrons can pass. Electrical energy is
provided in the circuit by a source of electricity, such as a battery.

4. Which of the following is an example of a digital Electronic?

a) Computers
b) Information appliances
c) Digital cameras
d) All of the mentioned
View Answer
Answer: d
Explanation: Computers, information appliances, digital cameras, digital televisions, flash
memory, key USB memory, mobile phones, hard discs, and computer memory devices are
examples of digital electronics. After analog signals have been transformed to digital form,
digital signal processing is applied to them.

5. Which of the following is a type of digital logic circuit?

a) Combinational logic circuits
b) Sequential logic circuits
c) Both Combinational & Sequential logic circuits
d) None of the mentioned
View Answer

Answer: c
Explanation: There are two main types of digital logic circuits in digital electronics. They are:
a) Combinational logic circuits
b) Sequential logic circuits

6. Which of the following options comes under the non – saturated logic family in Digital
Electronics?
a) Emitter – coupled Logic
b) High-Threshold Logic
c) Integrated – injection Logic
d) Diode – Transistor Logic
View Answer

Answer: a
Explanation: Bipolar IC’s can be classified as saturated and non – saturated logic families. ECL
(Emitter – coupled Logic) and Schottky TTL are said to come under the non – saturated logic
family.

7. What is a switching function that has more than one output called in Digital Electronics?
a) Multi-gate function
b) Multi-output function
c) Multiple-gate function
d) Multiple-output function
View Answer

Answer: b
Explanation: multi-output function is a switching function that will have more than one output. A
multiple output gate network will have the digital logic circuit corresponding to the multi-output
function.

8. Which characteristic of IC in Digital Circuits represents a function of the switching time of a

particular transistor?
a) Fan – out
b) Fan – in
c) Power dissipation
d) Propagation delay
View Answer

Answer: d
Explanation: Propagation delay represents a function of the switching time of a particular
transistor or MOSFET. The propagation delay helps in determining the speed of logic circuits.

9. When can one logic gate drive many other logic gates in Digital Electronics?
a) When its output impedance is low and the input impedance is low
b) When its output impedance is high and the input impedance is high
c) When its output impedance is high and the input impedance is low
d) When its output impedance is low and the input impedance is high
View Answer

Answer: d
Explanation: When the output impedance of a logic gate is low and its input impedance is high,
then one logic gate can drive many other logic gates. High impedance in the output will resist the
driving of many logic gates.

10. Which of the following digital logic circuits can be used to add more than 1 – bit
simultaneously?
a) Full – adder
b) Ripple – carry adder
c) Half – adder
d) Serial adder
View Answer

Answer: b
Explanation: A Ripple – carry adder is a parallel binary adder in which the addition of more than
1 – bit data can be done simultaneously. The inputs to a parallel circuit can be sent and processed
at once unlike series circuits in which inputs are sent one by one.

11. Which gates in Digital Circuits are required to convert a NOR-based SR latch to an SR flip-
flop?
a) Two 2 input AND gates
b) Two 3 input AND gates
c) Two 2 input OR gates
d) Two 3 input OR gates
View Answer

Answer: a
Explanation: Two 2 input AND gates are placed with a NOR – based S – R latch to convert it to
an S – R flip – flop. One AND gate is given R in one input and clock in the other. Similarly the
second AND gate is given S in one input and clock in the other.
12. When does a negative level triggered flip-flop in Digital Electronics changes its state?
a) When the clock is negative
b) When the clock is positive
c) When the inputs are all zero
d) When the inputs are all one
View Answer

Answer: a
Explanation: A negative level triggered flip – flop has a NOT gate present between clock input
and the input of AND gate. Thus, the negative level triggered flip – flop change its state when
the clock is negative.

13. Which of the following options represent the synchronous control inputs in an S – R flip
flop?
a) S
b) R
c) Clock
d) Both S and R
View Answer

Answer: d
Explanation: The input for which the flip flop changes its state when synchronized with the clock
is called the synchronous control inputs. For the S – R flip flop, both S and R are synchronous
control inputs.

14. What must be used along with synchronous control inputs to trigger a change in the flip flop?
a) 0
b) 1
c) Clock
d) Previous output
View Answer

Answer: c
Explanation: A clock must be used along with synchronous control inputs to trigger a change in
the flip flop. These flip – flops may be edge – triggered or level – triggered. A change should
occur only when the clock changes from 0 to 1 or vice versa.

15. Which of the following majorly determines the number of emitters in a TTL digital circuit?
a) Fan – in
b) Fan – out
c) Propagation delay
d) Noise immunity
View Answer

Answer: a
Explanation: The TTL circuit uses multi – emitter transistors with many emitters in the input.
Thus, the number of emitters is determined by the fan – in. Fan – in determines the number of
inputs the particular gate can handle.

16. What will be the output from a D flip – flop if the clock is low and D = 0?
a) 0
b) 1
c) No change
d) Toggle between 0 and 1
View Answer

Answer: c
Explanation: When the clock is low, the input given to D will have no effect. This is because the
set and reset pins of the NAND gates are kept high. When HIGH value is given to NAND gates
the output result will be zero.

17. What are the basic gates in MOS logic family?

a) NAND and NOR
b) AND and OR
c) NAND and OR
d) AND and NOR
View Answer

Answer: a
Explanation: The MOS logic family uses the MOSFET devices to perform its operation. NAND
and NOR are the basic gates that are the building blocks of most digital circuits.

18. How must the output of a gate in a TTL digital circuit act when it is HIGH?
a) Acts as a voltage source
b) Acts as a current sink
c) Acts as a current source
d) Acts as a voltage sink
View Answer

Answer: c
Explanation: If the gate output is high in a TTL circuit, the current must be given to the input of
the gate being driven. Thus, the output must act as a current source. In a normal TTL circuit,
about 40μA of current is drawn from the input from a output that is HIGH.

19. What is the minimum distance required for single error detection according to Hamming’s
analysis in Digital Electronics?
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: b
Explanation: According to Hamming’s analysis, a minimum distance of 2 is required for single
error detection. This Hamming distance represents the number of bits that are changed from one
code word to the other.

20. Which of these error-detecting codes enables to find double errors in Digital Electronic
devices?
a) Parity method
b) Check sum method
c) Bit generation method
d) Odd-Even method
View Answer

Answer: b
Explanation: Check sum enables to find double errors and also find the erroneous bits. The parity
method can help in finding only single errors within a word as a double error will not change the
parity bits.

21. What will be the output from a D flip-flop if D = 1 and the clock is low?
a) No change
b) Toggle between 0 and 1
c) 0
d) 1
View Answer

Answer: a
Explanation: When the clock is low, the input given to D will have no effect. The set and reset
pins of the NAND gates are high. When a NAND gate is given 1 as an input to any of the pins,
the output will always be 0.

22. What characteristic will a TTL digital circuit possess due to its multi-emitter transistor?
a) Low capacitance
b) High capacitance
c) Low inductance
d) High inductance
View Answer

Answer: a
Explanation: TTL circuit uses multi – emitter transistors which have a smaller area. The
capacitance can be represented in terms of area and distance between the plates using the
expressions C = Aε0/d. As “C” is directly proportional to “A”, a smaller area leads to a lower
capacitance.

23. What input should be given to “S” when SR flip – flop is converted to JK flip – flop?
a) K.Q
b) K.Q
c) J.Q
d) J.Q
View Answer

Answer: d
Explanation: To convert SR flip – flop to JK flip – flop the “S” input in the SR flip – flop is
given input “J” and “Q” through an AND gate. This is obtained by combining the truth table of
SR flip – flop and JK flip – flop.

24. What value is to be considered for a “don’t care condition”?

a) 0
b) 1
c) Either 0 or 1
d) Any number except 0 and 1
View Answer

Answer: c
Explanation: A don’t care condition can take 0 or 1 according to the requirement. SOP
expressions may consider it to be 1 to increase the number of 1s and POS expressions may
consider it to be 0 to increase the number of 0s.

25. What is the group of 1s in 4 cells of a K – map called?

a) Pair
b) Quad
c) Octet
d) Octave
View Answer

Answer: b
Explanation: A group of 1s in 4 cells of a K – map is called Quad. A group of 1s in 2 cells of a K
– map is called Pair and a group of 1s in 8 cells of a K – map is called Octet.

26. What will be the frequency of the output from a JK flip – flop, when J = 1, K = 1, and a clock
with pulse waveform is given?
a) Half the frequency of clock input
b) Equal to the frequency of clock input
c) Twice the frequency of clock input
d) Independent of the frequency of clock input
View Answer

Answer: a
Explanation: A single flip flop is a divide – by – two device. The frequency of the output from a
JK flip – flop, when J = 1, K = 1, and a clock with pulse waveform is given is half the frequency
of clock input.
27. What gate is placed between clock input and the input of AND gate to convert a positive
level triggered flip – flop to a negative level triggered flip – flop?
a) NOR gate
b) NOT gate
c) Buffer
d) NAND gate
View Answer

Answer: a
Explanation: The negative level triggered the flip – flop in Digital Electronics changes its state
when the clock is negative. Thus, a negative level triggered flip – flop has a NOT gate present
between clock input and the input of AND gate.

28. In Digital Circuits, which of the following options represent the synchronous control inputs
in a T flip flop?
a) T
b) 0
c) Clock
d) 1
View Answer

Answer: T
Explanation: The input at which the flip flop changes its state when synchronized with the clock
is called the synchronous control inputs. For T flip flop T is the synchronous control input.

29. What will a TTL digital circuit possess due to the presence of a multi – emitter transistor?
a) Smaller resistance
b) Larger area
c) Smaller area
d) Larger resistance
View Answer

Answer: c
Explanation: TTL circuit uses multi – emitter transistors. These transistors have a smaller area.
As Capacitance is directly proportional to area, a smaller area leads to a lower capacitance.

30. How must the output of a gate act when it is LOW in a TTL circuit?
a) Acts as a voltage source
b) Acts as a current sink
c) Acts as a current source
d) Acts as a voltage sink
View Answer

Answer: b
Explanation: If the gate output is Low in a TTL digital circuit, the gate must be capable of
sinking current drawn from the input of gates. Thus, the output must act as a current sink.
31. Which of the following gives the correct number of multiplexers required to build a 32 x 1
multiplexer?
a) Two 16 x 1 mux
b) Three 8 x 1 mux
c) Two 8 x 1 mux
d) Three 16 x 1 mux
View Answer

Answer: a
Explanation: Two 16 x 1 mux will enable to give 32 inputs. The final output can be obtained
after passing the output from each 16 x 1 mux through an OR gate. The select lines will help in
selecting a particular output.

32. What must be the input given to “R” when SR flip – flop is converted to JK flip – flop?
a) K.Q
b) K.Q
c) J.Q
d) J.Q
View Answer

Answer: b
Explanation: In Digital Electronics, to convert SR flip – flop to JK flip – flop the “R” input in the
SR flip – flop is given input “K” and “Q” through an AND gate. The truth table of SR flip – flop
and JK flip – flop are combined to get the expression.

33. What minimum distance is required for a single error correction according to Hamming’s
analysis in Digital Electronics?
a) 1
b) 2
c) 3
d) 4
View Answer

Answer: c
Explanation: According to Hamming’s analysis, a minimum distance of 3 is required for a single
error correction. Hamming distance represents the number of bits that change from one code
word to the other.

34. How many errors can the Digital Electronics parity method can find in a single word?
a) Single error
b) Double error
c) Triple error
d) Multiple errors
View Answer
Answer: a
Explanation: The parity method can help in finding only single errors within a word. The double
errors cannot be found as the parity of the bits does not change. If double errors need to be
identified, the check – sum method can be used.

35. What is the group of 1s present in 8 cells of a K – map called?

a) Pair
b) Quad
c) Octet
d) Octave
View Answer

Answer: c
Explanation: In a K – map if a group of 1s in eight cells are present, it makes an Octet. A group
of 1s in two cells is called a Pair and a group of 1s in four cells is a Quad.

36. Which of these flip – flops cannot be used to construct a serial shift register?
a) D – flip flop
b) SR flip – flop
c) T flip – flop
d) JK flip – flop
View Answer

Answer: c
Explanation: SR, D, and JK flip flops can be used to construct a serial shift register. A T flip –
flop gives the output 0 when input 1 is given and gives output 1 when input 0 is given. Thus, it
cannot be used as a serial shift register.

37. Which of these options represent the other name of Inter – Integrated logic?
a) Merged Transistor Logic
b) Emitter – Coupled Logic
c) High threshold logic
d) Resistor – Transistor logic
View Answer

Answer: a
Explanation: Inter – Integrated circuits can be represented by IIC or I2C is also called the
Merged Transistor Logic. They use n – p – n or p – n – p transistors to form IC’s.

38. Which of the following options is a Current – Mode logic used in Digital Circuits?
a) TTL
b) RTL
c) ECL
d) IIC
View Answer
Answer: c
Explanation: Emitter coupled logic or ECL is a Current – Mode logic. While operating in active
mode, they help in eliminating the turn – off delay of saturated transistors. ECL family has a
higher switching speed and dissipates more power.

39. How many AND gates are required to construct a 4 – bit parallel multiplier if four 4 – bit
parallel binary adders are given?
a) Four 2 – input AND gates
b) Eight 2 – input AND gates
c) Sixteen 2 – input AND gates
d) Two 2 – input AND gates
View Answer

Answer: c
Explanation: Four 4 – bit parallel binary adders along with 16 number of 2 – input AND gates
will be required to construct a 4 – bit parallel multiplier. The AND gate helps in getting the
partial products while the parallel – adder are used to add the partial products.

40. How many cycles of addition and shifting in a 4 – bit multiplier are required to perform
multiplication using the shift method?
a) 1
b) 2
c) 4
d) 8
View Answer

Answer: c
Explanation: In Digital Electronics, 4 cycles of addition and shifting in a 4 – bit multiplier are
required to perform multiplication using the shift method. The multiplicand is copied as a partial
product when multiplier bit is 1 and multiplicand is 0 when multiplier bit is 0.

41. How many 4 – bit parallel binary adders will be required to construct a 4 – bit parallel
multiplier?
a) 1
b) 2
c) 4
d) 8
View Answer

Answer: c
Explanation: Four 4 – bit parallel binary adders along with 16 number of 2 – input AND gates
will be required to construct a 4 – bit parallel multiplier. The parallel adders are used to add the
partial products which are calculated using the AND gates.

42. What kind of operation occurs in a J – K flip flop when both inputs J and K are equal to 1?
a) Preset operation
b) Reset operation
c) Clear operation
d) Toggle operation
View Answer

Answer: d
Explanation: Toggle operation in Digital Circuits like J – K flip – flop occurs when J = 1 and K
= 1. The output toggles between 0 and 1 continuously. This oscillation between 0 and 1 leads to a
race – around condition which can be solved using a Master – slave flip flop.

43. Which of the following codes is a sequential code?

a) 8421 code
b) 2421 code
c) 5421 code
d) 2441 code
View Answer

Answer: a
Explanation: A sequential code is a code where each succeeding code is one binary number more
than the preceding code. Thus, 8421 is a sequential code. Sequential codes are useful in
manipulating mathematical data.

44. Which of these code pairs correctly represent Digital Electronics reflective codes?
a) 2421 and 5211
b) 2421 and 8421
c) 5211 and 8421
d) 5421 and 2421
View Answer

Answer: a
Explanation: A reflexive code is the one where the code for 9 is the complement of code for 0,
code for 8 is the complement of code for 1, and so on. Thus, 2421 and 5211 are reflexive codes.

45. Which of the following options correctly represent the characteristic of Excess – 3 code?
a) It is a reflexive as well as a sequential code
b) It is a reflexive code but not a sequential code
c) It is a sequential code but not a reflexive code
d) It is neither a reflexive code nor a sequential code
View Answer

Answer: a
Explanation: A reflexive code is a code where the code for 9 is the complement of code for 0 and
so on. A sequential code is a code where each succeeding code is one binary number more than
the preceding code. Excess – 3 code satisfies both these properties.
46. The result “X + XY = X” follows which of these laws?
a) Consensus law
b) Distributive law
c) Duality law
d) Absorption law
View Answer

Answer: d
Explanation: The results “X + XY = X” and “X(X + Y) = X” follows the absorption law. The
expression given can be written in the form X + XY = X(1 + Y). Any value – added with 1 will
give 1 itself. Therefore 1 + Y = 1 and X + XY = X.

47. Which of the following options correctly represents the consensus law of Digital Circuits?
a) AB + AC + BC = AB + AC
b) AB + AC + BC = AB + AC
c) AB + AC + BC = AB + AC
d) AB + AC + BC = AB + AC
View Answer

Answer: a
Explanation: The consensus law of Digital Electronics can be represented by the expression
AB + AC + BC = AB + AC

48. Which of the following points is not correct regarding an Ex – NOR gate in Digital
Electronics?
a) It is a one – bit comparator
b) It is a buffer
c) It is a one – bit inverter
d) It is a universal gate
View Answer

Answer: a
Explanation: Ex – NOR gate is a one – bit comparator as the output for the gate is 1 if similar
inputs are given to the gate and output is 0 if different inputs are given to the gate.

49. Which gate is called the anti – coincidence and coincidence gate respectively?
a) XNOR and XOR
b) AND and OR
c) OR and AND
d) XOR and XNOR
View Answer

Answer: d
Explanation: XNOR gate is called coincidence gate and gives 1 if similar inputs are given to the
gate and output is 0 if different inputs are given to the gate. XOR gate is called anti –
coincidence gate and gives 0 if similar inputs are given to the gate and output is 1 if different
inputs are given to the gate.

50. What frequency division of the pulsed clock signal can be obtained by connecting 4 flip –
flops in cascade?
a) 2
b) 4
c) 8
d) 16
View Answer

Answer: d
Explanation: In Digital Circuits, a frequency division of 2n of the pulsed clock signal can be
obtained by connecting n flip – flops in cascade. Thus, for 4 flip – flops clock frequency can be
divided by 16.

51. Which of the following options represent the correct reduction of XYZ + XYZ ?
a) 0
b) YZ
c) X + X
b) 2YZ
View Answer

Answer: b
Explanation: Using Boolean identities of Digital Electronics the expression XYZ + XYZ can be
reduced. According to Complementarity identity X + X = 1. Thus, YZ + XYZ = (X + X)YZ =
YZ.

52. A priority encoder has four inputs I0, I1, I2, and I3 where I3 has the highest priority and I0 has
the least priority. If I2 = 1, what will be the output?
a) 00
b) 01
c) 10
d) 11
View Answer

Answer: c
Explanation: In digital circuits, if an input has 1 then the other inputs with lower priority can be
considered with the “don’t care” condition. I2 = 1, thus, I3 = 0, I1 = x and I0 = x. The output will
be 10.

53. Which of the following options are correct for a 4×1 multiplexer?
a) It has four 3 – input AND gates
b) It has four 2 – input AND gates
c) It has one 3 – input AND gate
d) It has one 3 – input AND gate
View Answer

Answer: a
Explanation: A 4 x 1 multiplexer has 2 select lines, 4 input lines, and 1 output line. AND gates
are required to pass the inputs. Thus 4 AND gates will be used for each input. 3 – input AND
gate is used, where 2 inputs come from each of the select lines and 1 input for the data.

54. What determines the output from the combinational logic circuit in Digital Electronics?
a) Input signals from the past condition
b) Input signals at the present moment
c) Input signals from both past and present
d) Input signals expected in future
View Answer

Answer: b
Explanation: The output in a combinational circuit depends on the mixture of input signals
present at that moment. It is not determined by the past conditions. The output in a synchronous
circuit depends on the mixture of input signals present at that moment and also the past
conditions.

55. Which of these pins will allow to activate and deactivate a multiplexer?
a) Enable pin
b) Selection pin
c) Logic pin
d) Preset pin
View Answer

Answer: a
Explanation: An enable pin allows to activate and deactivate the multiplexer. When enable pin is
0, the output is obtained while when enable pin is 0, the multiplexer is disabled.

Chapterwise Multiple Choice Questions on Digital Circuits

Digital Circuits Questions and Answers – Number System – 1
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Number System – 1”.

1. Any signed negative binary number is recognised by its ________

a) MSB
b) LSB
c) Byte
d) Nibble
View Answer

Answer: a
Explanation: Any negative number is recognized by its MSB (Most Significant Bit).
If it’s 1, then ít’s negative, else if it’s 0, then positive.

2. The parameter through which 16 distinct values can be represented is known as ________
a) Bit
b) Byte
c) Word
d) Nibble
View Answer

Answer: c
Explanation: It can be represented up to 16 different values with the help of a Word. Nibble is a
combination of four bits and Byte is a combination of 8 bits. It is “word” that is said to be a
collection of 16-bits on most of the systems.

3. If the decimal number is a fraction then its binary equivalent is obtained by ________ the
number continuously by 2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting
View Answer

Answer: b
Explanation: On multiplying the decimal number continuously by 2, the binary equivalent is
obtained by the collection of the integer part. However, if it’s an integer, then it’s binary
equivalent is determined by dividing the number by 2 and collecting the remainders.

4. The representation of octal number (532.2)8 in decimal is ________

a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10
View Answer

Answer: a
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base
index along with the value at that index position.
(532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 = (346.25)10
5. The decimal equivalent of the binary number (1011.011)2 is ________
a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
View Answer

Answer: a
Explanation: Binary to Decimal conversion is obtained by multiplying 2 to the power of base
index along with the value at that index position.
1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2-2 + 1 * 2-3 = (11.375)10
Hence, (1011.011)2 = (11.375)10
6. An important drawback of binary system is ________
a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) It requires small string of 1’s and large string of 0’s to represent a decimal number
View Answer
Answer: a
Explanation: The most vital drawback of binary system is that it requires very large string of 1’s
and 0’s to represent a decimal number. Hence, Hexadecimal systems are used by processors for
calculation purposes as it compresses the long binary strings into small parts.

7. The decimal equivalent of the octal number (645)8 is ______

a) (450)10
b) (451)10
c) (421)10
d) (501)10
View Answer

Answer: c
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base
index along with the value at that index position.
The decimal equivalent of the octal number (645)8 is 6 * 82 + 4 * 81 + 5 * 80 = 6 * 64 + 4 * 8 + 5
= 384 + 32 + 5 = (421)10.

8. The largest two digit hexadecimal number is ________

a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
View Answer

Answer: c
Explanation: (FE)16 is 254 in decimal system, while (FD)16 is 253. (EF)16 is 239 in decimal
system. And, (FF)16 is 255. Thus, The largest two-digit hexadecimal number is (FF)16.
9. Representation of hexadecimal number (6DE)H in decimal:
a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
View Answer

Answer: a
Explanation: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of
base index along with the value at that index position.
In hexadecimal number D & E represents 13 & 14 respectively.
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160.

10. The quantity of double word is ________

a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits
View Answer

Answer: b
Explanation: One word means 16 bits, Thus, the quantity of double word is 32 bits.

Digital Circuits Questions and Answers – Number System – 2

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Number System – 2”.

1. The given hexadecimal number (1E.53)16 is equivalent to ____________

a) (35.684)8
b) (36.246)8
c) (34.340)8
d) (35.599)8
View Answer

Answer: b
Explanation: First, the hexadecimal number is converted to it’s equivalent binary form, by
writing the binary equivalent of each digit in form of 4 bits. Then, the binary equivalent bits are
grouped in terms of 3 bits and then for each of the 3-bits, the respective digit is written. Thus, the
octal equivalent is obtained.
(1E.53)16 = (0001 1110.0101 0011)2
= (00011110.01010011)2
= (011110.010100110)2
= (011 110.010 100 110)2
= (36.246)8.
2. The octal number (651.124)8 is equivalent to ______
a) (1A9.2A)16
b) (1B0.10)16
c) (1A8.A3)16
d) (1B0.B0)16
View Answer

Answer: a
Explanation: First, the octal number is converted to it’s equivalent binary form, by writing the
binary equivalent of each digit in form of 3 bits. Then, the binary equivalent bits are grouped in
terms of 4 bits and then for each of the 4-bits, the respective digit is written. Thus, the
hexadecimal equivalent is obtained.
(651.124)8 = (110 101 001.001 010 100)2
= (110101001.001010100)2
= (0001 1010 1001.0010 1010)2
= (1A9.2A)16.

3. The octal equivalent of the decimal number (417)10 is _____

a) (641)8
b) (619)8
c) (640)8
d) (598)8
View Answer

Answer: a
Explanation: Octal equivalent of decimal number is obtained by dividing the number by 8 and
collecting the remainders in reverse order.
8 | 417
8 | 52 — 1
8|6–4
So, (417)10 = (641)8.
4. Convert the hexadecimal number (1E2)16 to decimal.
a) 480
b) 483
c) 482
d) 484
View Answer
Answer: c
Explanation: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of
base index along with the value at that index position.
(1E2)16 = 1 * 162 + 14 * 161 + 2 * 160 (Since, E = 14)
= 256 + 224 + 2 = (482)10.

5. (170)10 is equivalent to ____________

a) (FD)16
b) (DF)16
c) (AA)16
d) (AF)16
View Answer

Answer: c
Explanation: Hexadecimal equivalent of decimal number is obtained by dividing the number by
16 and collecting the remainders in reverse order.
16 | 170
16 | 10 – 10
Hence, (170)10 = (AA)16.

6. Convert (214)8 into decimal.

a) (140)10
b) (141)10
c) (142)10
d) (130)10
View Answer

Answer: a
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base
index along with the value at that index position.
(214)8 = 2 * 8v + 1 * 81 + 4 * 80
= 128 + 8 + 4 = (140)10.

7. Convert (0.345)10 into an octal number.

a) (0.16050)8
b) (0.26050)8
c) (0.19450)8
d) (0.24040)8
View Answer

Answer: b
Explanation: Converting decimal fraction into octal number is achieved by multiplying the
fraction part by 8 everytime and collecting the integer part of the result, unless the result is 1.
0.345*8 = 2.76 2
0.760*8 = 6.08 6
00.08*8 = 0.64 0
0.640*8 = 5.12 5
0.120*8 = 0.96 0
So, (0.345)10 = (0.26050)8.

8. Convert the binary number (01011.1011)2 into decimal.

a) (11.6875)10
b) (11.5874)10
c) (10.9876)10
d) (10.7893)10
View Answer
Answer: a
Explanation: Binary to Decimal conversion is obtained by multiplying 2 to the power of base
index along with the value at that index position.
(01011)2 = 0 * 24 + 1 * 23 + 0 * 22 + 1 * 21 + 1 * 20 = 11
(1011)2 = 1 * 2-1 + 0 * 2-2 + 1 * 2-3 + 1 * 2-4 = 0.6875
So, (01011.1011)2 = (11.6875)10.

9. Octal to binary conversion: (24)8 =?

a) (111101)2
b) (010100)2
c) (111100)2
d) (101010)2
View Answer

Answer: b
Explanation: Each digit of the octal number is expressed in terms of group of 3 bits. Thus, the
binary equivalent of the octal number is obtained.
(24)8 = (010100)2.

10. Convert binary to octal: (110110001010)2 =?

a) (5512)8
b) (6612)8
c) (4532)8
d) (6745)8
View Answer

Answer: b
Explanation: The binary equivalent is segregated into groups of 3 bits, starting from left. And
then for each group, the respective digit is written. Thus, the octal equivalent is obtained.
(110110001010)2 = (6612)8.

Digital Circuits Questions and Answers – Arithmetic Operation

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Arithmetic Operation”

1. What is the addition of the binary numbers 11011011010 and 010100101?

a) 0111001000
b) 1100110110
c) 11101111111
d) 10011010011
View Answer

Answer: c
Explanation: The rules for Binary Addition are :
0+0=0
0+1=1
1+0=1
1 + 1 = 0 ( Carry 1)
1

1 1 0 1 1 0 1 1 0 1 0

+ 0 0 0 1 0 1 0 0 1 0 1
_______________________
1 1 1 0 1 1 1 1 1 1 1
_______________________

2. Perform binary addition: 101101 + 011011 = ?

a) 011010
b) 1010100
c) 101110
d) 1001000
View Answer

Answer: d
Explanation:The rules for Binary Addition are :
0+0=0
0+1=1
1+0=1
1 + 1 = 0 ( Carry 1)
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1 1 1 1 1 1
1 0 1 1 0 1
+ 0 1 1 0 1 1
_______________
1 0 0 1 0 0 0
_______________

Therefore, the addition of 101101 + 011011 = 1001000.

3. Perform binary subtraction: 101111 – 010101 = ?

a) 100100
b) 010101
c) 011010
d) 011001
View Answer

Answer: c
Explanation: The rules for Binary Subtraction are :
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
1 0 1 1 1 1
- 0 1 0 1 0 1
____________
0 1 1 0 1 0
_____________

Therefore, The subtraction of 101111 – 010101 = 011010.

4. Binary subtraction of 100101 – 011110 is?

a) 000111
b) 111000
c) 010101
d) 101010
View Answer

Answer: a
Explanation: The rules for Binary Subtraction are :
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
1 0 0 1 0 1
- 0 1 1 1 1 0
___________
0 0 0 1 1 1
___________

Therefore, The subtraction of 100101 – 011110 = 000111.

5. Perform multiplication of the binary numbers: 01001 × 01011 = ?

a) 001100011
b) 110011100
c) 010100110
d) 101010111
View Answer

Answer: a
Explanation: The rules for binary multiplication are:
0*0=0
0*1=0
1*0=0
1*1=1
0 1 0 0 1
x 0 1 0 1 1
____________
0 1 0 0 1
 0 1 0 0 1 0
0 0 0 0 0 0 0
0 1 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0
___________________
0 0 1 1 0 0 0 1 1
___________________

Therefore, 01001 × 01011 = 001100011.

6. 100101 × 0110 = ?
a) 1011001111
b) 0100110011
c) 101111110
d) 0110100101
View Answer

Answer: c
Explanation: The rules for binary multiplication are:
0*0=0
0*1=0
1*0=0
1*1=1
1 0 0 1 0 1
x 0 1 1 0
___________
0 0 0 0 0 0
1 0 0 1 0 1 0
1 0 0 1 0 1 0 0
0 0 0 0 0 0 0 0 0
__________________
0 1 1 0 1 1 1 1 0
___________________

Therefore, 100101 x 0110 = 011011110.

7. On multiplication of (10.10) and (01.01), we get ____________

a) 101.0010
b) 0010.101
c) 011.0010
d) 110.0011
View Answer

Answer: c
Explanation: The rules for binary multiplication are:
0*0=0
0*1=0
1*0=0
1*1=1
1 0.1 0
 x 0 1.0 1
__________
1 0 1 0
0 0 0 0 0
1 0 1 0 0 0
0 0 0 0 0 0 0
_______________
0 1 1.0 0 1 0
_________________

Therefore, 10.10 x 01.01 = 011.0010.

8. Divide the binary numbers: 111101 ÷ 1001 and find the remainder.
a) 0010
b) 1010
c) 1100
d) 0111
View Answer

Answer: d
Explanation: Binary Division is accomplished using long division method.
1 0 0 1 ) 1 1 1 1 0 1 ( 1 1
1 0 0 1
__________
0 1 1 0 0
1 0 0 1
___________
0 1 1 1

Therefore, the remainder of 111101 ÷ 1001 = 0111.

9. Divide the binary number (011010000) by (0101) and find the quotient.
a) 100011
b) 101001
c) 110010
d) 010001
View Answer

Answer: b
Explanation:
0 1 0 1 ) 0 1 1 0 1 0 0 0 0 ( 0 1 0 1 1 1
0 0 0 0
_____________________
0 1 1 0 1
0 0 1 0 1
______________
0 1 0 0 0 0
0 0 0 0 0 0
______________________
1 0 0 0 0
0 0 1 0 1
 ____________________
0 1 0 1 1 0
0 0 0 1 0 1
____________________
1 0 0 0 1 0
0 0 0 1 0 1
________________________
1 1 1 0 1 0
0 0 0 1 0 1
________________________
1 0 1 0 1
0 0 1 0 1
________________________
1 0 0 0 0

Therefore, the quotient of 011010000 ÷ 1001 = 101001.

10. Binary subtraction of 101101 – 001011 = ?

a) 100010
b) 010110
c) 110101
d) 101100
View Answer

Answer: a
Explanation: The rules for binary subtraction are:
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
1 0 1 1 0 1
- 0 0 1 0 1 1
____________
1 0 0 0 1 0
____________

Therefore, the subtraction of 101101 – 001011 = 100010.

Digital Circuits Questions and Answers – 1’s, 2’s, 9’s & 10’s
Complements – 1
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “1’s, 2’s, 9’s & 10’s Complements – 1”.

1. 1’s complement of 1011101 is ____________

a) 0101110
b) 1001101
c) 0100010
d) 1100101
View Answer

Answer: c
Explanation: 1’s complement of a binary number is obtained by reversing the binary bits. All the 1’s to
0’s and 0’s to 1’s.

Thus, 1’s complement of 1011101 = 0100010.

2. 2’s complement of 11001011 is ____________

a) 01010111
b) 11010100
c) 00110101
d) 11100010
View Answer

Answer: c
Explanation: 2’s complement of a binary number is obtained by finding the 1’s complement of the
number and then adding 1 to it.
2’s complement of 11001011 = 00110100 + 1 = 00110101.
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3. On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________

a) 01001
b) 11010
c) 10101
d) 10100
View Answer

Answer: d
Explanation: Steps For Subtraction using 1’s complement are:
-> 1’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and 1 is added to the last bit of the result.
-> Else, if there is no carry, then 1’s complement of the result is found out and a ‘-’ sign preceeds the
result.
1 1 1
Minuend - 1 1 1 1 0
1’s complement of subtrahend - 1 0 1 0 1
____________
Carry over - 1 1 0 0 1 1
1
_____________
1 0 1 0 0

4. On subtracting (010110)2 from (1011001)2 using 2’s complement, we get ____________

a) 0111001
b) 1100101
c) 0110110
d) 1000011
View Answer

Answer: d
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the
result.
1’s complement of subtrahend - 1 1 0 1 0 0 1
_________________
1 1 1
Minuend - 1 0 1 1 0 0 1
2’s complement of subtrahend - 1 1 0 1 0 1 0
_________________

Carry over - 1 1 0 0 0 0 1 1

Answer: 1000011

5. On subtracting (001100)2 from (101001)2 using 2’s complement, we get ____________

a) 1101100
b) 011101
c) 11010101
d) 11010111
View Answer

Answer: b
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the
result.

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1’s complement of subtrahend - 1 1 0 0 1 1
_________________
Minuend - 1 0 1 0 0 1
2’s complement of subtrahend - 1 1 0 1 0 0
_________________
Carry over - 1 0 1 1 1 0 1

Answer: 011101

6. On addition of 28 and 18 using 2’s complement, we get ____________

a) 00101110
b) 0101110
c) 00101111
d) 1001111
View Answer

Answer: b
Explanation: Steps for Binary Addition Using 2’s complement:
-> The binary equivalent of the two numbers are obtained and added using the rules of binary addition.
Augend - 0 0 1 1 1 0 0

Addend - 0 0 1 0 0 1 0
_________________
0 1 0 1 1 1 0

Answer: 0 1 0 1 1 1 0

7. On addition of +38 and -20 using 2’s complement, we get ____________

a) 11110001
b) 100001110
c) 010010
d) 110101011
View Answer

Answer: c
Explanation: Steps for Binary Addition Using 2’s complement:
-> The 2’s complement of the addend is found out and added to the first number.
-> The result is the 2’s complement of the sum obtained.
Augend - 0 1 0 0 1 1 0
2’s Complement of Subtrahend: 1 1 0 1 1 0 0
_________________
1 0 0 1 0 0 1 0

Answer: 0 1 0 0 1 0

8. On addition of -46 and +28 using 2’s complement, we get ____________

a) -10010
b) -00101
c) 01011
d) 0100101
View Answer

Answer: a
Explanation: The BCD form is written of the two given numbers, in their signed form. After which,
normal binary addition is performed.
Augend is 28 and Subtrahend is -46.
Augend - 0 0 1 1 1 0 0 .....(a)
 2’s Complement of Subtrahend: 1 0 1 0 0 1 0 .....(b)
_________________
Addiing (a) and (b): 1 1 0 1 1 1 0
Since, there is no carry, so answer will be negative
and 2's complement of the above result is determined.
0 0 1 0 0 0 1
+ 1
_________________
0 0 1 0 0 1 0

Answer: - 1 0 0 1 0

9. On addition of -33 and -40 using 2’s complement, we get ____________

a) 1001110
b) -110101
c) 0110001
d) -1001001
View Answer

Answer: d
Explanation: The BCD form is written of the two given numbers, in their signed form. After which,
normal binary addition is performed.
Augend is -40 and Subtrahend is -33.
Augend - 1 0 1 0 0 0 0 1 .....(a)
2’s Complement of Subtrahend: 1 1 0 1 1 0 0 1 .....(b)
______________________
Addiing (a) and (b): 1 0 1 0 0 1 0 0 0
Since, there is no carry, so answer will be negative
and 2's complement of the above result is determined.
1 0 0 1 0 0 0
+ 1
_________________
1 0 0 1 0 0 1
Answer: -1001001

10. On subtracting +28 from +29 using 2’s complement, we get ____________
a) 11111010
b) 111111001
c) 100001
d) 1
View Answer

Answer: d
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the
result.
 1’s complement of subtrahend - 1 0 0 0 1 1
Minuend - 0 1 1 1 0 1
2’s complement of subtrahend - 1 0 0 1 0 0
____________________

Carry over - 1 0 0 0 0 0 1

Answer: 000001 = 1

Digital Circuits Questions and Answers – 1’s, 2’s, 9’s & 10’s
Complements – 2
This set of Digital Electronic Circuits Interview Questions and Answers focuses on “1’s,2’s,9’s
& 10’s Complements-2”.

1. If the number of bits in the sum exceeds the number of bits in each added numbers, it results in
_________
a) Successor
b) Overflow
c) Underflow
d) Predecessor
View Answer

Answer: b
Explanation: If the number of bits in the sum exceeds the number of bits in each added numbers, it
results in overflow and is also known as excess-one. In case of any arithmetic operation, if the result has
less number of bits than the operands, then it is known as underflow condition.

2. An overflow is a _________
a) Hardware problem
b) Software problem
c) User input problem
d) Input Output Error
View Answer

Answer: b
Explanation: An overflow is a software problem which occurs when the processor cannot handle the
result properly when it produces an out of the range output.

3. An overflow occurs in _________

a) MSD position
b) LSD position
c) Middle position
d) Signed Bit
View Answer
Answer: a
Explanation: An overflow occurs at the Most Significant Digit position. It occurs when the processor
cannot handle the result properly when it produces an out of the range output.
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4. Logic circuitry is used to detect _________

a) Underflow
b) MSD
c) Overflow
d) LSD
View Answer

Answer: c
Explanation: To check the overflow logic circuitry is used in each case. Overflow occurs when the
processor cannot handle the result properly when it produces an out of the range output.

5. 1’s complement can be easily obtained by using _________

a) Comparator
b) Inverter
c) Adder
d) Subtractor
View Answer

Answer: b
Explanation: With the help of inverter the 1’s complement is easily obtained. Since, during the operation
of 1’s complement 1 is converted into 0 and vice-versa and this is well suited for the inverter.

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6. The advantage of 2’s complement system is that _________

a) Only one arithmetic operation is required
b) Two arithmetic operations are required
c) No arithmetic operations are required
d) Different Arithmetic operations are required
View Answer

Answer: a
Explanation: The advantage of 2’s complement is that only one arithmetic operation is required for 2’s
complement’s operation and that is only addition. Just by adding a 1 bit to 1’s complement, we get 2’s
complement.

7. The 1’s complements requires _________

a) One operation
b) Two operations
c) Three operations
d) Combined Operations
View Answer

Answer: a
Explanation: Only one operation is required for 1’s complement operation. This includes only inversion
of 1’s to 0’s and 0’s to 1’s.

8. Which one is used for logical manipulations?

a) 2’s complement
b) 9’s complement
c) 1’s complement
d) 10’s complement
View Answer

Answer: c
Explanation: For logical manipulations, 1’s complement is used, as all logical operations take place with
binary numbers.

9. For arithmetic operations only _________

a) 1’s complement is used
b) 2’s complement
c) 10’s complement
d) 9’s complement
View Answer

Answer: b
Explanation: Only 2’s complement is used for arithmetic operations, as it is more fast.

10. The addition of +19 and +43 results as _________ in 2’s complement system.
a) 11001010
b) 101011010
c) 00101010
d) 0111110
View Answer

Answer: d
Explanation: The decimal numbers are converted to their respective binary equivalent and then the
binary addition rules are applied.

Digital Circuits Questions and Answers – Binary Coded Decimal(BCD)

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Binary Coded Decimal(BCD)”.
1. Binary coded decimal is a combination of __________
a) Two binary digits
b) Three binary digits
c) Four binary digits
d) Five binary digits
View Answer

Answer: c
Explanation: Binary coded decimal is a combination of 4 binary digits. For example-8421.

2. The decimal number 10 is represented in its BCD form as __________

a) 10100000
b) 01010111
c) 00010000
d) 00101011
View Answer

Answer: c
Explanation: The decimal number 10 is represented in its BCD form as 0001 0000, in accordance to 8421
for each of the two digits.

3. Add the two BCD numbers: 1001 + 0100 = ?

a) 10101111
b) 01010000
c) 00010011
d) 00101011
View Answer

Answer: c
Explanation: Firstly, Add the 1001 and 0100. We get 1101 as output but it’s not in BCD form. So, we add
0110 (i.e. 6) with 1101. As a result we get 10011 and it’s BCD form is 0001 0011.

4. Carry out BCD subtraction for (68) – (61) using 10’s complement method.
a) 00000111
b) 01110000
c) 100000111
d) 011111000
View Answer

Answer: a
Explanation: First the two numbers are converted into their respective BCD form using 8421 sequence.
Then binary subtraction is carried out.

5. Code is a symbolic representation of __________ information.

a) Continuous
b) Discrete
c) Analog
d) Both continuous and discrete
View Answer

Answer: b
Explanation: Code is a symbolic representation of discrete information, which may be present in the
form of numbers, letters or physical quantities. Mostly, it is represented using a particular number
system like decimal or binary and such like.
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6. When numbers, letters or words are represented by a special group of symbols, this process is
called __________
a) Decoding
b) Encoding
c) Digitizing
d) Inverting
View Answer

Answer: b
Explanation: When numbers, letters or words are represented by a special group of symbols, this
process is called encoding. Encoding in the sense of fetching the codes or words in a computer. It is done
to secure the transmission of information.

7. A three digit decimal number requires ________ for representation in the conventional BCD
format.
a) 3 bits
b) 6 bits
c) 12 bits
d) 24 bits
View Answer

Answer: c
Explanation: The number of bits needed to represent a given decimal number is always greater than the
number of bits required for a straight binary encoding of the same. Hence, a three digit decimal number
requires 12 bits for representation in BCD format.

8. How many bits would be required to encode decimal numbers 0 to 9999 in straight binary
codes?
a) 12
b) 14
c) 16
d) 18
View Answer
Answer: b
Explanation: Total number of decimals to be represented = 10000 = 104 = 2n (where n is the number of
bits required) = 213.29. Therefore, the number of bits required for straight binary encoding = 14.

9. The excess-3 code for 597 is given by __________

a) 100011001010
b) 100010100111
c) 010110010111
d) 010110101101
View Answer

Answer: a
Explanation: The addition of ‘3’ to each digit yields the three new digits ‘8’, ’12’ and ’10’. Hence, the
corresponding four-bit binary equivalents are 100011001010, in accordance to 8421 format.

10. The decimal equivalent of the excess-3 number 110010100011.01110101 is _____________

a) 970.42
b) 1253.75
c) 861.75
d) 1132.87
View Answer

Answer: a
Explanation: The conversion of binary numbers into digits ‘1100’, ‘1010’, ‘0011’, ‘0111’ and ‘0101’ gives
’12’, ‘5’, ‘3’, ‘7’ and ‘5’ respectively. Hence, the decimal number is 970.42.

Digital Circuits Questions and Answers – Boolean Logic Operations

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Boolean Logic Operations”.

1. In boolean algebra, the OR operation is performed by which properties?

a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned
View Answer

Answer: d
Explanation: The expression for Associative property is given by A+(B+C) = (A+B)+C & A*(B*C) = (A*B)*C.
The expression for Commutative property is given by A+B = B+A & A*B = B*A.
The expression for Distributive property is given by A+BC=(A+B)(A+C) & A(B+C) = AB+AC.

2. The expression for Absorption law is given by _________

a) A + AB = A
b) A + AB = B
c) AB + AA’ = A
d) A + B = B + A
View Answer

Answer: a
Explanation: The expression for Absorption Law is given by: A+AB = A.
Proof: A + AB = A(1+B) = A (Since 1 + B = 1 as per 1’s Property).

3. According to boolean law: A + 1 = ?

a) 1
b) A
c) 0
d) A’
View Answer

Answer: a
Explanation: A + 1 = 1, as per 1’s Property.
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4. The involution of A is equal to _________

a) A
b) A’
c) 1
d) 0
View Answer

Answer: a
Explanation: The involution of A means double inversion of A (i.e. A”) and is equal to A.
Proof: ((A)’)’ = A

5. A(A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A
View Answer

Answer: d
Explanation: A(A + B) = AA + AB (By Distributive Property) = A + AB (A.A = A By Commutative Property) =
A(1 + B) = A*1 (1 + B = 1 by 1’s Property) = A.

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6. DeMorgan’s theorem states that _________
a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B
View Answer

Answer: a
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the Dual Property.

7. (A + B)(A’ * B’) = ?
a) 1
b) 0
c) AB
d) AB’
View Answer

Answer: b
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the Dual Property.

8. Complement of the expression A’B + CD’ is _________

a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
View Answer

Answer: b
Explanation: (A’B + CD’)’ = (A’B)'(CD’)’ (By DeMorgan’s Theorem) = (A” + B’)(C’ + D”) (By DeMorgan’s
Theorem) = (A + B’)(C’ + D).

9. Simplify Y = AB’ + (A’ + B)C.

a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A
View Answer

Answer: a
Explanation: Y = AB’ + (A’ + B)C = AB’ + (AB’)’C = (AB’ + C)( AB’ + AB’) = (AB’ + C).1 = (AB’ + C).

10. The boolean function A + BC is a reduced form of ____________

a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B
View Answer

Answer: b
Explanation: (A + B)(A + C) = AA + AC + AB + BC = A + AC + AB + BC (By Commutative Property) = A(1 + C +
B) + BC = A + BC (1 + B + C =1 By 1’s Property).

Digital Circuits Questions and Answers – Sum of Products and Products

of Sum
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Sum of Products and Products of Sum”.

1. The logical sum of two or more logical product terms is called __________
a) SOP
b) POS
c) OR operation
d) NAND operation
View Answer

Answer: a
Explanation: The logical sum of two or more logical product terms, is called SOP (i.e. sum of product).
The logical product of two or more logical sum terms is called POS (i.e. product of sums).

2. The expression Y=AB+BC+AC shows the _________ operation.

a) EX-OR
b) SOP
c) POS
d) NOR
View Answer

Answer: b
Explanation: The given expression has the operation product as well as the sum of that. So, it shows SOP
operation. POS will be the product of sum terms.

3. The expression Y=(A+B)(B+C)(C+A) shows the _________ operation.

a) AND
b) POS
c) SOP
d) NAND
View Answer

Answer: b
Explanation: The given expression has the operation sum as well as the product of that. So, it shows
POS(product of sum) operation. SOP will be the sum of product terms.
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4. A product term containing all K variables of the function in either complemented or

uncomplemented form is called a __________
a) Minterm
b) Maxterm
c) Midterm
d) ∑ term
View Answer

Answer: a
Explanation: A product term containing all K variables of the function in either complemented or
uncomplemented form is called a minterm. A sum term containing all K variables of the function in
either complemented or uncomplemented form is called a maxterm.

5. According to the property of minterm, how many combination will have value equal to 1 for K
input variables?
a) 0
b) 1
c) 2
d) 3
View Answer

Answer: b
Explanation: The main property of a minterm is that it possesses the value 1 for only one combination of
K input variables and the remaining will have the value 0.

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6. The canonical sum of product form of the function y(A,B) = A + B is __________

a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) AB’ + A’B + A’B’
View Answer

Answer: b
Explanation: A + B = A.1 + B.1 = A(B + B’) + B(A + A’) = AB + AB’ + BA +BA’ = AB + AB’ + A’B = AB + AB’ +
A’B.

7. A variable on its own or in its complemented form is known as a __________

a) Product Term
b) Literal
c) Sum Term
d) Word
View Answer
Answer: b
Explanation: A literal is a single logic variable or its complement. For example — X, Y, A’, Z, X’ etc.

8. Maxterm is the sum of __________ of the corresponding Minterm with its literal
complemented.
a) Terms
b) Words
c) Numbers
d) Nibble
View Answer

Answer: a
Explanation: Maxterm is the sum of terms of the corresponding Minterm with its literal complemented.

9. Canonical form is a unique way of representing ____________

a) SOP
b) Minterm
c) Boolean Expressions
d) POS
View Answer

Answer: c
Explanation: Boolean Expressions are represented through a canonical form. An example of canonical
form is A’B’C’ + AB’C + ABC’.

10. There are _____________ Minterms for 3 variables (a, b, c).

a) 0
b) 2
c) 8
d) 1
View Answer

Answer: c
Explanation: Minterm is given by 2n. So, 23 = 8 minterms are required.

11. _____________ expressions can be implemented using either (1) 2-level AND-OR logic
circuits or (2) 2-level NAND logic circuits.
a) POS
b) Literals
c) SOP
d) POS
View Answer

Answer: c
Explanation: SOP expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-
level NAND logic circuits.
Digital Circuits Questions and Answers – Karnaugh Map
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Karnaugh Map”.

1. A Karnaugh map (K-map) is an abstract form of ____________ diagram organized as a matrix

of squares.
a) Venn Diagram
b) Cycle Diagram
c) Block diagram
d) Triangular Diagram
View Answer

Answer: a
Explanation: A Karnaugh map (K-map) is an abstract form of Venn diagram organized as a matrix of
squares, where each square represents a Maxterm or a Minterm.

2. There are ______ cells in a 4-variable K-map.

a) 12
b) 16
c) 18
d) 8
View Answer

Answer: b
Explanation: There are 16 = (24) cells in a 4-variable K-map.

3. The K-map based Boolean reduction is based on the following Unifying Theorem: A + A’ = 1.
a) Impact
b) Non Impact
c) Force
d) Complementarity
View Answer

Answer: b
Explanation: The given expression A +A’ = 1 is based on non-impact unifying theorem.
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4. Each product term of a group, w’.x.y’ and w.y, represents the ____________ in that group.
a) Input
b) POS
c) Sum-of-Minterms
d) Sum of Maxterms
View Answer
Answer: c
Explanation: In a minterm, each variable w, x or y appears once either as the variable itself or as the
inverse. So, the given expression satisfies the property of Sum of Minterm.

5. The prime implicant which has at least one element that is not present in any other implicant is
known as ___________
a) Essential Prime Implicant
b) Implicant
c) Complement
d) Prime Complement
View Answer

Answer: a
Explanation: Essential prime implicants are prime implicants that cover an output of the function that no
combination of other prime implicants is able to cover.

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6. Product-of-Sums expressions can be implemented using ___________

a) 2-level OR-AND logic circuits
b) 2-level NOR logic circuits
c) 2-level XOR logic circuits
d) Both 2-level OR-AND and NOR logic circuits
View Answer

Answer: d
Explanation: Product-of-Sums expressions can be implemented using 2-level OR-AND & NOR logic
circuits.

7. Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible
product term of the given ___________
a) Function
b) Value
c) Set
d) Word
View Answer

Answer: a
Explanation: Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible
product term of the given function.

8. Don’t care conditions can be used for simplifying Boolean expressions in ___________
a) Registers
b) Terms
c) K-maps
d) Latches
View Answer

Answer: c
Explanation: Don’t care conditions can be used for simplifying Boolean expressions in K-maps which
helps in pairing with 1/0.

9. It should be kept in mind that don’t care terms should be used along with the terms that are
present in ___________
a) Minterms
b) Expressions
c) K-Map
d) Latches
View Answer

Answer: a
Explanation: It should be kept in mind that don’t care terms should be used along with the terms that
are present in minterms as well as maxterms which reduces the complexity of the boolean expression.

10. Using the transformation method you can realize any POS realization of OR-AND with only.
a) XOR
b) NAND
c) AND
d) NOR
View Answer

Answer: d
Explanation: Using the transformation method we can realize any POS realization of OR-AND with only
NOR.

11. There are many situations in logic design in which simplification of logic expression is
possible in terms of XOR and _________________ operations.
a) X-NOR
b) XOR
c) NOR
d) NAND
View Answer

Answer: a
Explanation: There are many situations in logic design in which simplification of logic expression is
possible in terms of XOR and XNOR operations.
Expression of XOR : AB’ + A’B
Expression of XNOR : AB + A’B’

12. These logic gates are widely used in _______________ design and therefore are available in
IC form.
a) Sampling
b) Digital
c) Analog
d) Systems
View Answer

Answer: b
Explanation: These logic gates(XOR, XNOR, NOR) are widely used in digital design and therefore are
available in IC form as digital circuits deal with data transmission in the form of binary digits.

13. In case of XOR/XNOR simplification we have to look for the following _______________
a) Diagonal Adjacencies
b) Offset Adjacencies
c) Straight Adjacencies
d) Both diagonal and offset adjencies
View Answer

Answer: d
Explanation: In case of XOR/XNOR simplification we have to look for the following diagonal and offset
adjacencies. XOR gives output 1 when odd number of 1s are present in input while XNOR gives output 1
when even number of 1s or all 0s are present in input.

14. Entries known as _______________ mapping.

a) Diagonal
b) Straight
c) K
d) Boolean
View Answer

Answer: a
Explanation: Entries known as diagonal mapping. The diagonal mapping holds true when for any
relation, there is a projection of product on the factor.

Digital Circuits Questions and Answers – Logic Gates and Networks – 1

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Logic Gates and Networks – 1”.

1. The output of a logic gate is 1 when all the input are at logic 0 as shown below:

INPUT OUTPUT

A B C

0 0 1
0 1 0

1 0 0

1 1 0

INPUT OUTPUT

A B C

0 0 1

0 1 0

1 0 0

1 1 1

The gate is either _________

a) A NAND or an EX-OR
b) An OR or an EX-NOR
c) An AND or an EX-OR
d) A NOR or an EX-NOR
View Answer

Answer: d
Explanation: The output of a logic gate is 1 when all inputs are at logic 0. The gate is NOR. The output of
a logic gate is 1 when all inputs are at logic 0 or all inputs are at logic 1, then it is EX-NOR. (The truth
tables for NOR and EX-NOR Gates are shown in the above table).

2. The code where all successive numbers differ from their preceding number by single bit is
__________
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray
View Answer

Answer: d
Explanation: The code where all successive numbers differ from their preceding number by single bit is
gray code. It is an unweighted code. The most important characteristic of this code is that only a single
bit change occurs when going from one code number to next. BCD Code is one in which decimal digits
are represented by a group of 4-bits each, whereas, in Excess-3 Code, the decimal numbers are
incremented by 3 and then written in their BCD format.
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3. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
View Answer

Answer: c
Explanation: 4 to 16 line decoder as the minterms are ranging from 1 to 14.

4. How many AND gates are required to realize Y = CD + EF + G?

a) 4
b) 5
c) 3
d) 2
View Answer

Answer: d
Explanation: To realize Y = CD + EF + G, two AND gates are required and two OR gates are required.

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5. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11
View Answer

Answer: a
Explanation: In 01, 10 or 11 output is low if any of the I/P is high. So, the correct option will be 00.

6. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) 3, 2
View Answer

Answer: a
Explanation: Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.
7. A universal logic gate is one which can be used to generate any logic function. Which of the
following is a universal logic gate?
a) OR
b) AND
c) XOR
d) NAND
View Answer

Answer: d
Explanation: An Universal Logic Gate is one which can generate any logic function and also the three
basic gates: AND, OR and NOT. Thus, NOR and NAND can generate any logic function and are thus
Universal Logic Gates.

8. A full adder logic circuit will have __________

a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
View Answer

Answer: d
Explanation: A full adder circuit will add two bits and it will also accounts the carry input generated in
the previous stage. Thus three inputs and two outputs (Sum and Carry) are there. In case of half adder
circuit, there are only two inputs bits and two outputs (SUM and CARRY).

9. How many two input AND gates and two input OR gates are required to realize Y = BD + CE
+ AB?
a) 3, 2
b) 4, 2
c) 1, 1
d) 2, 3
View Answer

Answer: a
Explanation: There are three product terms. So, three AND gates of two inputs are required. As only two
input OR gates are available, so two OR gates are required to get the logical sum of three product terms.

10. Which of the following are known as universal gates?

a) NAND & NOR
b) AND & OR
c) XOR & OR
d) EX-NOR & XOR
View Answer

Answer: a
Explanation: The NAND & NOR gates are known as universal gates because any digital circuit can be
realized completely by using either of these two gates, and also they can generate the 3 basic gates
AND, OR and NOT.

11. The gates required to build a half adder are __________

a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate
View Answer

Answer: c
Explanation: The gates required to build a half adder are EX-OR gate and AND gate. EX-OR outputs the
SUM of the two input bits whereas AND outputs the CARRY of the two input bits.