stk6032 Ds v1

STK6032
8051-based
8-bit microcontroller
with
ISP-programmable
64K flash memory
for Program Memory
The STK6032 is not designed for use in life support appliances, V1 2008 Jul 09
devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Syntek
customers using or selling STK6032 for use in such applications do
so at their own risk and agree to fully indemnify Syntek for any
damages resulting from such improper use or sale.
Syntek Semiconductors Product specification
Table of Contents STK6032
1 FEATURES
2 ORDERING INFORMATION
3 FUNCTIONAL BLOCK DIAGRAM
4 PINNING INFORMATION
4.4 Pin description
5 REDUCING ELECTROMAGNETIC EMISSION
5.1 Filtering
5.2 Turning off ALE
6 CENTRAL PROCESSING UNIT (CPU)
6.1 Instruction Set and addressing modes
6.2 CPU clock and Chip Configuration Register (SFR CHIPCON)
6.3 Instruciton Cycle
6.4 Program Status Word
7 MEMORY ORGANIZATION
7.1 Program Memory
7.1.1 Proram ROM space
7.1.2 On-chip Program Memory versus External program Memory
7.1.3 ISP prgramming for the 64K flash memory
7.1.4 ROM code protection
7.2 Main Data RAM and Special Function Register (SFR)
7.2.1 The lower 128 bytes of the Main Data RAM
7.3 AUX Memory
7.3.1 AUX Memory space
7.3.2 On-chip AUX Memory
7.3.3 Dual Data Pointer (Data Pointer 0 and Data Pointer 1) and DPTR Select Register (SFR DPS)
7.3.4 Stretch Memory Cycles for accessing external AUX memory and Clock Control Register
8 SPECIAL FUNCTION REGISTERS
8.1 SFR Map Overview
8.2 SFR of Each Functional Block
9 PORT 0, PORT 1, PORT 2, PORT 3, AND PORT 4
9.1 General Description
9.2 Port 0
9.3 Port 1, Port 2, and Port 3
9.4 Port 4
9.5 MOVX instruction, Port 0, Port 2, P3.6, P3.7
9.6 Multiple-Function Port Pins
10 TIMER/COUNTER 0, TIMER/COUNTER 1
10.2 Mode Selection Regiser, SFR TMOD ( at 89H of SFR space)
10.3 Timer 0/1 Control Register (SFR TCON at 88 H of the SFR space)
10.4 Clock Control Register, SFR CKCON, at address 8E hex of the SFR map
10.5 Operating Modes
10.5.1 Mode 0 (13-bit timer/counter)
10.5.2 Mode 1 (16-bit timer/counter)
10.5.3 Mode 2 (8-bit counter with auto-reload)
10.5.4 Mode 3 (two 8-bit counters from timer 0)
11 RESET
V1 2008 Jul 09 2
11.1 Sources of RESET

11.2 Power-On- Reset (POR) with fast-rising power supply
11.3 Asynchronous reset by adding a HIGH pulse to the RESET pin
11.4 Low-power detection and reset
11.5 Reset by the Watchdog Timer overflow
12 TIMER/COUNTER 2
12.1 General Description and operation modes
12.2.1 The T2M bit of Clock Control Register (SFR CKCON)
12.2.2 Timer 2 Control Register (SFR T2CON)
12.2.3 Timer 2 mode control register
12.3 16-bit Timer/Counter Mode
12.5 16-bit Timer/Counter with Auto-Reload capability (Auto-Reload Mode)
12.6 Baud Rate Generator Mode
12.6.1 calculating the value of RCAP2H and RCAP2L for a desired baud rate
13 OSCILLATOR
13.1 The Oscillator Circuit
13.2 The values for R, C1, and C2
14 INTERRUPTS
14.2 Interrupt Enable Registers
14.3 Interrupt Priority Register SFR IP
14.4 Interrupt Vectors
15 OVERALL VIEW OF THE INTERRUPT SYSTEM
16 UART0
16.4.1 transmission and reception of mode 0
16.4.2 Baud rate of Mode 0
16.4.3 Transmission timing of mode 0
16.4.4 Reception timing of mode 0
16.5.1 Operation of mode 1
16.5.2 baud rate of mode 1
16.5.3 Data transmission timing in mode 1
16.6.2 baud rate of mode 2
16.7.2 baud raTe of mode 3
16.7.3 Data transmission in mode 3
16.7.4 Data reception in mode 3
16.8.1 Using Timer 1 to generate baud rates
16.8.2 Using Timer 2 to generate baud rates
17 POWER-SAVING MODES
17.1 Idle Mode
17.2 Stop mode
17.3 Status of external pins during power-saving modes
17.4 Summary of Power-saving Modes
18 WATCHDOG TIMER
18.1 Functional Block Diagram
18.2 Watchdog Timer Control Register
V1 2008 Jul 09 3
19 PWM (PULSE WIDTH MODULATED OUTPUT)

19.1 General description
19.2 Port 1 Option Register (SFR P1_OPT)
19.3 Pulse Width Register 0 ~ 4 (PWM0D ~ PWM4D)
20 ANALOG-TO-DIGITAL CONVERTER (ADC)
20.1 ADC functional description
20.2 ADC during Idle and Stop mode
20.3 ADC SFRs and their reset value
20.3.3 ADCVAL Registers
21 PIN CIRCUITS
21.1 Port 0 (P0.0 ~ P0.7) circuit (Bidirectional Input/Output)
21.2 Port 1 (P1.0 ~ P1.7), Port 2 (P2.0 ~ P2.7), Port 3 (P3.0 ~ P3.7) circuit (Bidirectional I/O, with weak Pull-up)
21.3 ALE and PSEN (Output)
21.4 EA (Input), with weak internal pull-up PMOS
21.5 RST (Input), with weak internal pull-low NMOS.
21.6 XTAL1, XTAL2
22 ABSOLUTE MAXIMUM RATING
23 DC/AC CHARACTERISTICS
24 EXTERNAL PROGARM MEMORY READ CYCLE
25 EXTERNAL AUX MEMORY READ/WRITE TIMING WITH STRETCH= 0
25.1 External AUX Memory Read timing with stretch= 0
26 INSTRUCTION SET
26.1 Addressing modes
26.2 80C51 family instruction set
27 PLCC44 PACKAGE OUTLINE DWRAWING
28 QFP44 PACKAGE OUTLINE DRAWING
29 LQFP48 PACKAGE OUTLINE DRAWING
V1 2008 Jul 09 4
List of Table STK6032
Table 1 Ordering information.....Page [10]

Table 3 Chip Configuration Register.....Page [18]
Table 4 Description of Chip Configuration Register (CHIPCON).....Page [19]
Table 5 Program Status Word.....Page [20]
Table 6 Description of Program Status Word (PSW).....Page [20]
Table 7 Data Pointer 0, Data Pointer 1, and DPTR Select Register.....Page [25]
Table 8 Instructions that use the DPTR.....Page [25]
Table 9 Clock Control Register, SFR CKCON.....Page [26]
Table 10 Description of the CKCON Register.....Page [26]
Table 11 Data Memory Stretch Values.....Page [26]
Table 12 SFR of each functional block.....Page [29]
Table 13 SFRs associated with Timer/Counter 0 and Timer/Counter 1......Page [33]
Table 14 Timer 0/1 Mode Selection Register.....Page [33]
Table 15 Description of Timer 0/1 Mode Selection Register.....Page [34]
Table 16 Timer 0/1 Control Register.....Page [34]
Table 17 Description of Timer 0/1 Control Register.....Page [35]
Table 18 Configuring Timer 2 into various operating modes.....Page [41]
Table 19 Timer 2 SFRs.....Page [42]
Table 20 T2M bit of SFR CKCON.....Page [42]
Table 21 Description of the T2M bit of SFR CKCON.....Page [42]
Table 22 Timer 2 Control Register (SFR T2CON, C8 hex).....Page [43]
Table 23 Description of Timer 2 Control Register.....Page [43]
Table 24 Timer 2 Mode Control Register (SFR T2MOD).....Page [45]
Table 25 Description of Timer 2 Control Register.....Page [45]
Table 26 Timer 2 reload value for UART Mode 1 and Mode 3 baud rate......Page [49]
Table 27 Overview of the interrupt system.....Page [53]
Table 28 Interrupt Enable Register SFR IE.....Page [54]
Table 29 Description of Interrupt Enable Register SFR IE.....Page [54]
Table 30 Interrupt Priority Register SFR IP.....Page [55]
Table 31 Description of Interrupt Priority Register SFR IP.....Page [55]
Table 32 UART0 Operation Modes......Page [58]
Table 33 Serial Port Control and Status Register (SFR SCON0, 98h).....Page [59]
Table 34 Description of SFR SCON0.....Page [59]
Table 35 Timer 1 reload value for UART0 Mode 1 and Mode 3 baud rate......Page [68]
Table 36 Power Control Register, SFR PCON at address 87(hex) of the SFR map.....Page [70]
Table 37 Status of external pins during Idle and Stop modes......Page [72]
Table 38 .Summary of power-saving modes.....Page [72]
Table 39 Watchdog Timer Register.....Page [74]
Table 40 Description of SFR WDT.....Page [74]
Table 41 SFRs for PWM .....Page [75]
Table 42 Port 1 Option Register(address D1H).....Page [77]
Table 43 Description of SFR P1_OPT bits.....Page [77]
Table 44 Pulse width register (address D2 ~ D6 hex, R/W).....Page [77]
Table 45 ADC Special Function Registers overview.....Page [78]
Table 46 P4_OPT register (address D9 hex).....Page [79]
Table 47 Description of P4_OPT Register bits.....Page [79]
Table 48 ADCSEL Register (address DA hex).....Page [80]
Table 49 Description of ADC Register bits.....Page [80]
V1 2008 Jul 09 5
List of Table STK6032
Table 50 ADCVAL Register (address DB hex).....Page [80]

Table 51 Absolute Maximum Rating.....Page [85]
Table 52 DC/AC Characteristics.....Page [86]
Table 53 Instructions that affect flag settings; note 1.....Page [95]
Table 54 Instruction set: Arithmetic operations.....Page [96]
Table 55 Instruction set: Logic operations.....Page [97]
Table 56 Instruction set: Data transfer.....Page [98]
Table 57 Instruction set: Boolean variable manipulation, Program and machine control.....Page [99]
Table 58 Description of the mnemonics in the Instruction set.....Page [100]
Table 59 Instruction map.....Page [101]
V1 2008 Jul 09 6
List of Figures STK6032
Fig. 1 Functional block diagram...Page 11

Fig. 2 Pin configuration of QFP44 package....Page 12
Fig. 3 Pin configuration of LQFP48 version....Page 13
Fig. 4 Pin configuration PLCC44 version....Page 14
Fig. 5 CPU clock...Page 18
Fig. 6 CPU timing for single-cycle instruction....Page 19
Fig. 7 The overall memory space...Page 21
Fig. 8 Program Memory....Page 22
Fig. 9 Main Data Memory and SFRs...Page 23
Fig. 10 The AUX Memory Spae...Page 24
Fig. 11 Port 0 schematic...Page 31
Fig. 12 Schematic of Port 1, Port 2, and Port 3...Page 31
Fig. 13 Port 4 schematic...Page 32
Fig. 14 Mode 0 (13-bit timer/counter) and Mode 1 (16-bit timer/counter)...Page 36
Fig. 15 Mode 2 operation of Timer 0, Timer 1....Page 37
Fig. 16 Mode 3 operation of Timer 0, Timer 1...Page 38
Fig. 17 Functional diagram of reset circuit...Page 39
Fig. 18 Timing of Power-On-Reset with fast rising VDD....Page 40
Fig. 19 T2OE bit...Page 45
Fig. 20 Timer 2 configuration in 16-bit timer/counter mode...Page 46
Fig. 21 Timer 2 in 16-bit timer/counter mode with capture capability...Page 47
Fig. 22 Timer 2 in auto-reload mode...Page 48
Fig. 23 Timer 2 in baud-rate generator mode...Page 51
Fig. 24 Oscillator Circuit....Page 52
Fig. 25 crystal parameters...Page 52
Fig. 26 Overall view of interrupt system....Page 56
Fig. 27 Programmer’s model of the UART0...Page 57
Fig. 28 UART0 mode 0 transmission timing when baud rate is XTAL1/4....Page 60
Fig. 29 UART0 mode 0 reception timing when baud rate is XTAL1/4....Page 60
Fig. 30 UART0 mode 1 transmission timing...Page 61
Fig. 31 UART0 mode 1 reception timing...Page 62
Fig. 32 UART0 mode 2 transmission timing...Page 64
Fig. 33 UART0 mode 2 reception timing...Page 65
Fig. 34 baud rate generation from Timer 1 or Timer 2 overflow...Page 67
Fig. 35 word format for multiprocessor communication...Page 69
Fig. 36 UART0 multiprocessor communication...Page 69
Fig. 37 Power-saving modes....Page 70
Fig. 38 Watchdog Timer....Page 73
Fig. 39 PWM functional block diagram...Page 76
Fig. 40 value of a PWM SFR and the pulse width...Page 77
Fig. 41 ADC SFRs...Page 78
V1 2008 Jul 09 7
List of Figures STK6032
Fig. 42 Converted digital code versus analog input voltage....Page 81

Fig. 43 Port 0 pad...Page 82
Fig. 44 Pad of Port 1, Port 2, and Port 3...Page 82
Fig. 45 Pad for ALE and PSEN.....Page 82
Fig. 46 EA pad...Page 83
Fig. 47 RST pad...Page 83
Fig. 48 XTAL1, XTAL2 pads...Page 83
Fig. 49 Port 4 pad...Page 84
Fig. 50 External program memory read cycle...Page 88
Fig. 51 STK6032 PLCC44 Package Outline Drawing...Page 103
Fig. 52 STK6032 QFP44 Package Outline Drawing...Page 104
Fig. 53 STK6032 LQFP48 Package Outline Drawing...Page 105
V1 2008 Jul 09 8
Syntek Semiconductors STK6032
1 FEATURES
• 80C51 Central Processing Unit (CPU).
– Option for multiple CPU clock (XTAL1, XTAL1 x 2, or XTAL1 / 3.
– Binary-code compatible with industrial standard 80C51 instruction set.
– Normal mode, idle mode, and stop mode.
• Program Memory : 64 kbytes on-chip flash memory.
– with hardware ISP (In-System Programming).
– Program code protection.
• Main Data RAM: 256 bytes (upper 128 + lower 128 bytes) of on-chip SRAM.
• Aux Memory (AUX RAM): 768 bytes of SRAM.
• Stretched memory cycle for the MOVX instruction.
• SFRs (Special Function Register): 46 SFRs.
• Timers: Timer 0, Timer 1, and Timer 2.
• On-chip Watchdog Timer.
• Full-duplex UART
• Five 8-bits I/O ports: Port 0, Port 1, Port 2, Port 3, and Port 4.
• On-chip power-on-reset with low-voltage detection and reset.
• Interrupts: 6 sources, 2 priority level, 6 vectored addresses.
• Software enable/disable of ALE output pulse to reduce EMI.
• 6-channel, 6-bit ADC.
• 5-channel, 8-bit PWM.
• CPU operating frequency range: 2 to 30 MHz
• Operating temperature range: -40 to +85°C
• Operating voltage range: 4.5 to 5.5 V.
• ESD, Human Body Model: > 3 KV
• ESD, Machines model: > 350 V
• Latch-up > 100 mA.
• Relibility of 64K flash memory:
– Data retention: 10 years at room temperature.
– Number of read/write cycle: > 20K.
• Available in 3 types of Pb-free package: PLCC44, QFP44, LQFP48.
V1 2008 Jul 09 9
2 ORDERING INFORMATION
Table 1 Ordering information
TYPE NUMBER PACKAGE OUTLINE DRAWING

STK6032BPLG PLCC44 (Pb-free) please refer to Figure 51 on page 103
STK6032BQPG QFP44 (Pb-free) please refer to Figure 52 on page 104.
STK6032BLQG LQFP48 (Pb-free) please refer to Figure 53 on page 105.
V1 2008 Jul 09 10
3 FUNCTIONAL BLOCK DIAGRAM
P0.0/AD0
ALE Internal Bus P0.1/AD1
PSEN 8051 CPU P0.2/AD2
EA Port 0 P0.3/AD3
P0.4/AD4
P0.5/AD5
data bus and
Program Flash P0.6/AD6
address bus for
Memory (64K) P0.7/AD7 external memory
P2.0/A8 access
P2.1/A9
Main Data Memory P2.2/A10
ISP CONTROL (256 bytes)
Port 2 P2.3/A11
P2.4/A12
AUX Memory P2.5/A13
(768 bytes) P2.6/A14
P2.7/A15
P3.1/TXD Full-duplex P1.0/PWM0/T2
P3.0/RXD UART P1.1/PWM1/T2EX
P1.2/PWM2
Port 1 P1.3/PWM3
P3.4/T0 Timer 0 P1.4/PWM4
P3.5/T1 Timer 1 P1.5
P1.6
P1.0/ PWM0/T2 P1.7
P1.1 / PWM1/T2EX Timer2
P3.0/RXD
P3.2/INT0 P3.1/TXD
Interrupt
P3.3/INT1 Control P3.2/INT0
Port 3 P3.3/INT1
P3.4/T0
P4.0/ ADC0 P3.5/T1
P4.1/ ADC1 P3.6/WR
P4.2 /ADC2 P3.7/ RD
P4.3/ ADC3 6-bit ADC
P4.4 /ADC4 P4.0/ ADC0
P4.5/ ADC5 P4.1/ADC1
P4.2 /ADC2
P1.0 / PWM0/T2 Port 4 P4.3/ ADC3
P1.1 /PWM1/T2EX P4.4/ ADC4
P1.2/ PWM2 8-bit PWM P4.5/ADC5
P1.3/ PWM3 P4.6
P1.4/ PWM4 P4.7
Watchdog timer
RST Power-On-Reset
XTAL1
Low-voltage detection OSC
XTAL2
Fig.1 Functional block diagram
V1 2008 Jul 09 11
4 PINNING INFORMATION
4.1 Pinning diagram(QFP44 package)
P1.1/PWM1/T2EX
P1.0/PWM0/T2
P1.4/PWM4
P1.3/PWM3
P1.2/PWM2
P4.2/ADC2
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
VDD
44
43
42
41
40
39
38
37
36
35
34
P1.5 1 33 P0.4/AD4
P1.6 2 32 P0.5/AD5
P1.7 3 31 P0.6/AD6
RST 4 30 P0.7/AD7
P3.0/RXD/SCL 5
STK6032BQPG 29 EA
P4.3/ADC3 6 (QFP44) 28 P4.1/ADC1
P3.1/TXD/SDA 7 27 ALE
P3.2/INT0 8 26 PSEN
P3.3/INT1 9 25 P2.7/A15
P3.4/T0 10 24 P2.6/A14
P3.5/T1 11 23 P2.5/A13
12
13
14
15
16
17
18
19
20
21
22
P3.6/WR
P3.7/RD
XTAL22
XTAL1
VSS
P4.0/ADC0
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
Fig.2 Pin configuration of QFP44 package.
V1 2008 Jul 09 12
4.2 Pinning diagram(LQFP48 package)
P1.1/PWM1/T2EX
P1.0/PWM0/T2
P1.4/PWM4
P1.3/PWM3
P1.2/PWM2
P4.4/ADC4
P4.2/ADC2
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
VDD
48
47
46
45
44
43
42
41
40
39
38
37
P1.5 1 36 P4.7
P1.6 2 35 P0.4/AD4
P1.7 3 34 P0.5/AD5
RST 4 33 P0.6/AD6
P3.0/RXD/SCL 5 STK6032BLQG 32 P0.7/AD7
P4.3/ADC3 6 31 EA
(LQFP48)
P3.1/TXD/SDA 7 30 P4.1/ADC1
P3.2/INT0 8 29 ALE
P3.3/INT1 9 28 PSEN
P3.4/T0 10 27 P2.7/A15
P3.5/T1 11 26 P2.6/A14
P4.5/ADC5 12 25 P2.5/A13
13
14
15
16
17
18
19
20
21
22
23
24
P4.6
P3.6/WR
P3.7/RD
XTAL22
XTAL1
VSS
P4.0/ADC0
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
Fig.3 Pin configuration of LQFP48 version.
V1 2008 Jul 09 13
4.3 Pinning diagram(PLCC44)
P1.1/PWM1/T2EX
P1.0/PWM0/T2
P1.4/PWM4
P1.3/PWM3
P1.2/PWM2
P4.2/ADC2
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
VDD
6
5
4
3
2
1
44
43
42
41
40
P1.5 7 39 P0.4/AD4
P1.6 8 38 P0.5/AD5
P1.7 9 37 P0.6/AD6
RST 10 36 P0.7/AD7
P3.0/RXD/SCL 11 STK6032BPLG 35 EA
P4.3/ADC3 12 (PLCC44) 34 P4.1/ADC1
P3.1/TXD/SDA 13 33 ALE
P3.2/INT0 14 32 PSEN
P3.3/INT1 15 31 P2.7/A15
P3.4/T0 16 30 P2.6/A14
P3.5/T1 17 29 P2.5/A13
18
19
20
21
22
23
24
25
26
27
28
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P4.0/ADC0
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
Fig.4 Pin configuration PLCC44 version.
V1 2008 Jul 09 14
4.4 Pin description

Table 2 Pin description for QFP44 package
To avoid a latch-up effect at power-on: VSS − 0.5 V < voltage at any pin at any time < VDD + 0.5 V .
SYMBOL PIN TYPE DESCRIPTION

P1.5, P1.6, P1.7 1~3 I/O Bits 5, 6, 7 of Port 1.
These pins are pure I/O pins.
RST 4 I External reset input pin, active HIGH.
A HIGH level on this pin for at least 8 XTAL1 clocks, while the oscillator is
running, resets the STK6032.
P3.0/RXD/SCL 5 I/O Bit 0 of Port 3, or data receiver pin of the UART, or clock pin for ISP
programming.
P4.3/ADC3 6 I/O Bit 3 of Port 4 or the third channel input of the 6-bit ADC.
P3.1/ TXD/SDA 7 I/O Bit 1 of Port 3, data transmitter pin of the UART, or data pin for ISP progamming.
P3.2 / INT0 8 I/O Bit 2 of Port 3 or input of External Interrupt 0.
P3.3/ INT1 9 I/O Bit 3 of Port 3 or input of External interrupt 1.
P3.4/T0 10 I/O Bit 4 of Port 3 or Timer 0 input.
P3.5/T1 11 I/O Bit 5 of Port 3 or Timer 1 input.
P3.6 / WR 12 I/O Bit 6 of Port 3 or external AUX data memory write strobe.
When selected as write strobe to external AUX RAM, the function of P3.6 is
disabled.
P3.7/RD 13 I/O Bit 7 of Port 3, or external AUX data memory read strobe.
When selected as read strobe to external AUX RAM, the function of P3.7 is
disabled.
XTAL2 14 O Crystal pin 2: output of the inverting amplifier that forms the oscillator. This pin
should be left open-circuit when an external oscillator clock is used.
XTAL1 15 I Crystal pin 1: input to the inverting amplifier that forms the oscillator. Receives
the external oscillator clock signal when an external oscillator is used.
VSS 16 I Ground pin.
P4.0/ADC0 17 I/O Bit 0 of Port 4 or channel 0 input of the 6-bit ADC.
P2.0/A8~ 18~2 I/O Port 2, or Address 8~15 when fetching external program ROM or read/write
P2.7/A15 5 external AUX data memory.
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
1s written to them are pulled high by the internal pull-up PMOS and can be used
as inputs. As inputs, port 2 pins that are externally pulled low will source current
because of the internal pull-up PMOS.
Port 2 sends out the high-order address (A8 ~ A15) during read from external
program memory and during read/write access to external AUX data memory,
using 16-bit address lines (MOVX @DPTR). In this application, it uses strong
internal pull-ups when emitting 1s.
PSEN 26 O Program Strobe Enable
This is read strobe to external program memory. When the CPU is executing
code coming from external program memory, PSEN is activated once each
instruction cycle.
Please refer to Fig.50 for external program memory read timing.
V1 2008 Jul 09 15
SYMBOL PIN TYPE DESCRIPTION

ALE 27 O Address Latch Enable
Output pulse for latching the low byte of the address during an access to
external program memory or AUX data memory. In normal operation, ALE is
sent out at a constant rate of 1/4 oscillator frequency, and can be used for
external clocking or timing.
Note that, when executing a stretched MOVX instruction, CPU will send out two
ALE pulses.
The ALE output can be disabled by setting bit 3 (ALEDIS) of SFR CHIPCON at
location BF(hex) to HIGH. With this bit set to HIGH, the pin is weakly pulled high.
The ALE disable feature is terminated by reset. Setting the ALEDIS bit has no
effect, if the CPU is in external memory access mode.
P4.1/ADC1 28 I/O Bit 1 of Port 4 or channel 1 input of the on-chip ADC.
EA 29 I External Access Enable. The CPU checks this input during power-on reset.
If EA=0, the CPU fetches instruction from external (off-chip) program memory.
If EA=1, the CPU fetches instructions from internal (on-chip) program memory.
P0.0/AD0~ 30~3 I/O Port 0, Address 0~7 or Data 0~7 when CPU performs a read from external
P0.7/AD7 7 program memory, or a read/write operation to external AUX data memory.
Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during access to
external program memory or AUX memory. In this application, it uses strong
internal pull-ups when emitting 1s.
VDD 38 Power supply.
P4.2/ADC2 39 I/O Bit 2 of Port 4 or channel 2 input of the 6-bit ADC.
P1.0/PWM0/T2 40 I/O Bit 0 of Port 1, PWM0 output, or T2 input of Timer 2.
P1.1/PWM1/T2EX 41 I/O Bit 1 of Port 1, PWM1 output, or T2EX input of Timer 2.
P1.2/PWM2, 42, I/O Bit 2, 3, 4 of Port 1 or outputs PWM 2, 3,4 of the Pulse Width Modulator.
P1.3/PWM3, 43,
P1.4/PWM4 44
V1 2008 Jul 09 16
5 REDUCING ELECTROMAGNETIC EMISSION

There are two recommended ways to reduce chip’s EMI emission: filtering and turning off ALE.
5.1 Filtering
Primary attention has been paid to the reduction of electromagnetic emission in the design of the STK6032. For example,
the internal clock routing has been carefully arranged and internal decoupling capacitance has been added. However, in
application, it is recommended that external capacitors should be connected across VDD and VSS pins. Lead length
should be as short as possible. Ceramic chip capacitors are recommended (100 nF).
5.2 Turning off ALE

For applications that require no external memory or temporarily no external memory: the ALE output (pulses at a
frequency of 1⁄4 × fOSC) can be disabled by setting CHIPCON.3=1 (bit 3 of SFR CHIPCON at SFR address BF hex); if
disabled, no ALE pulse will occur. ALE pin will be weakly pulled high internally, switching an external address latch to a
quiet state. The MOVX instruction will still toggle ALE (when external Data Memory is accessed).
Additionally during internal access (EA = 1) ALE will toggle normally when the address exceeds the internal Program
Memory size. During external access (EA = 0) ALE will always toggle normally, without regard to if bit 3 of SFR CHIPCON
is set or not.
For detailed description of the SFR CHIPCON, please refer to Table 3 and Table 4.
V1 2008 Jul 09 17
6 CENTRAL PROCESSING UNIT (CPU)
6.1 Instruction Set and addressing modes

The STK6032’s instruction set and addressing modes are completely compatible with that of industrial standard 80C51.
User codes written in traditional 80C51 instruction set can be ported directly to the STK6032. Howerver, due to difference
in CPU instruction clocks and timing, applications in which timer loops are used may need modification in the number of
loops.
For a description of instruction set, please refer to Chapter 26, Instruction set.
6.2 CPU clock and Chip Configuration Register (SFR CHIPCON)

The STK6032 can be configured to run at different clock rates by use of bit 2 and bit 1 of the Chip Configuration Register
(SFR CHIPCON), as illustrated in Fig.5.
XTAL1
multiplexer
divided by 3 CPU CLK
CPU clock control

CPUCLK CLKRATE CPU CLK
X2
CPU CLK=XTAL1
0 0
(default value after reset)
CPUCLK
CPURATE
0 1 CPU CLK=XTAL1/3.
1 1 CPU CLK=XTAL1/3.
1 0 CPU CLK=XTAL1X2.
Fig.5 CPU clock
The Chip Configuration Register (SFR CHIPCON, at SFR map address BF hex) controls the following:
• Enable or disable the on-chip AUX memory access,
• Enable or disable of the ALE output,
• Selection of CPU clock, and
• Enable or disable of low-power reset.
Table 3 Chip Configuration Register

Chip Configuraton Register (SFR CHIPCON), located at BF hex of the SFR map, Read/Write
Bit Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Mnemonics x x x XRAMEN ALEDIS CPUCLK CLKRATE LVR
Reset value x x x 1 0 0 0 0
V1 2008 Jul 09 18
Table 4 Description of Chip Configuration Register (CHIPCON)
MNEMONIC BIT POSITION FUNCTION

Bits 5, 6, 7 Not implemented.
XRAMEN CHIPCON.4 Enable or disable of the on-chip AUX memory access.
• XRAMEN= 1 enables the read/write access to the on-chip AUX memory.
• XRAMEN= 0 disable the read/write access to the address AUX memory.
ALEDIS CHIPCON.3 Disable of the ALE output.
• When ALEDIS=1, the ALE Disable is turned on, that is, the ALE output will not
toggle and EMI can be lowered.
• When ALEDIS=0, the ALE output toggles.
CPUCLK CHIPCON.2 This two bits are used to select the CPU clock rate. The CPU clock can be
CLKRATE CHIPCON.1 selected to be XTAL1, XTAL1 ÷ 3, or XTAL1x 2.
Please refer to Fig.5. for detail.
LVR CHIPCON.0 Enable the low-voltage reset function.
• LVR=0 enables the low-voltage reset function.
• LVR=1 disables the low-voltage reset functon.
6.3 Instruciton Cycle

The following diagram illustrates the relation among system clock (CPU CLK), instruciton cycle, CPU cycle, and ALE.
Simple instructions can be executed in just one instruction cycle, which consists of 4 CPU clocks.
1 2 3 4 5 6 7 8 9
CPU CLK
instruction n+1 n+2

cycle
cpu cycle C1 C2 C3 C4 C1 C2 C3 C4 C1
ALE
Fig.6 CPU timing for single-cycle instruction.
V1 2008 Jul 09 19
6.4 Program Status Word

The current state of the CPU is reflected in the Program Status Word (PSW) register, which is located at SFR address
D0(hex).
Table 5 Program Status Word
PROGRAM STATUS WORD (SFR PSW), LOCATED AT D0H OF THE SFR MAP
Mnemonics CY AC F0 RS1 RS0 OV F1 P
Table 6 Description of Program Status Word (PSW)

CY PSW.7 Carry flag.
The Carry flag receives Carry-out from bit 7 of ALU. It is set to HIGH, when last
arithmetic operation resulted in a carry (during addition) or borrow (during
subtraction); otherwise, it is cleared to LOW by all arithmetic operations.
AC PSW.6 Auxiliary Carry Flag.
Auxiliary Carry Flag receives Carry-out from bit 3 of addition operands. It is set
to HIGH, when last arithmetic operation resulted in a carry into (during addition)
or borrow from (during subtraction) the high-order nibble; otherwise, it is cleared
to LOW by all arithmetic operations
F0 PSW.5 General purpose flag.
This bit is uncommitted and may be used as general purpose status flag.
RS1, RS0 PSW.4, Register Bank select control bits.
PSW.3
• RS1, RS0 = 00 selects register bank 0, address 00h ~ 07h.
• RS1, RS0 = 01 selects register bank 1, address 08h ~ 0Fh.
• RS1, RS0 = 10 selects register bank 2, address 10h ~ 17h.
• RS1, RS0 = 11 selects register bank 3, address 18h ~ 1Fh.
OV PSW.2 Overflow flag.
This bit is set to HIGH, when last arithmetic operation resulted in a carry
(addition), borrow (subtraction), or overflow (multiply or divide); otherwise, it is
cleared to LOW by all arithmetic operation.
F1 PSW.1 General purpose flag.
This bit is uncommitted and may be used as general purpose status flag.
P PSW.0 Parity flag.
Set/Clear by hardware each instruction cycle to indicate an odd/even number of
1s in the accumulator, i.e., even parity.
V1 2008 Jul 09 20
7 MEMORY ORGANIZATION
The STK6032 has 4 blocks of on-chip memories. These are:
• 65536 bytes of flash program memory,
• 256 bytes of Main Data Memory,
• 768 bytes of AUX memory, and
• 46 bytes of Special Function Register.
The following diagram shows the overall memory spaces available in the microcontroller.
(1) The memory areas shown with dash lines are not
implemented on-chip. 65535
65535 65535
(2) The area drawn for each memory block is not
FFFF(hex)
proportional
l to its physical size.
Internal External External

Program Program AUX RAM
ROM ROM (off-chip)
Space Space
(on-chip) (off-chip)
768
767
Internal
Main RAM AUX RAM
255
128 bytes SFR (on-chip)
128
127 53 bytes
128 bytes (on-chip)
0 0 0
(on-chip)
Program Memory on-chip Data Memory External Data

Memory
Fig.7 The overall memory space
V1 2008 Jul 09 21
7.1 Program Memory
7.1.1 PRORAM ROM SPACE

The STK6032 CPU fetches instructions either from the on-chip program memory or the off-chip program memory. For
both memories, the adddress range is from 0000(hex) to FFFF(hex).
7.1.2 ON-CHIP PROGRAM MEMORY VERSUS EXTERNAL PROGRAM MEMORY

If, during reset, the EA (External Access) pin, is held HIGH, the STK6032 always executes out of the on-chip Program
Memory. If the EA pin is held LOW during reset, the STK6032 fetches instructions from off-chip Program Memory. The
EA input is latched during reset and is ignored after reset. After reset, the CPU starts fetching program ROM code at
location 0000H.
The off-chip memory is acceseed via Port 0 and Port 2.
7.1.3 ISP PRGRAMMING FOR THE 64K FLASH MEMORY

The on-chip program memory is implemented using flash memory, with ISP (In-System Programming) capability.
Detailed description of ISP programming is given in another document.
7.1.4 ROM CODE PROTECTION

ROM code protection is implemented in the 64K flash memory.
Address=65535 Address=65535
(FFFFh) (FFFFh)
Internal External
( EA= 1 ) (EA= 0 )
Address=0 Address=0
on-chip program memory Off-chip program memory,

(implemented on-chip) (externally expandable)
Fig.8 Program Memory.
V1 2008 Jul 09 22
7.2 Main Data RAM and Special Function Register (SFR)

The STK6032 has 256 bytes of on-chip Main Data RAM and 53 bytes of SFR. Although the Main Data RAM and the
SFRs shares overlapped memory space, they are two physically separate blocks. The upper 128 bytes of the Main Data
RAM, from address 80H to FFH can be accessed only by Indirect Addressing. The lower 128 bytes of the Main RAM,
from address 00H to 7FH, can be accessed by Direct Addressing or Indirect Addressing.
The SFRs occupy the address range from 80H to FFH and are only accessible using Direct Addressing.
Lower 128 bytes

of Main Data RAM
7Fh
Indirect addressing
only
Direct RAM
FF(hex) Direct addressing
only
upper SFR
128 bytes
30h
2Fh
80(hex)
Bit-Addressable 7F(hex)
Registers
Direct or indirect
lower
addressing
20h 128 bytes
1Fh
Bank 3
18h 00(hex)
17h
10h
Bank 2
0Fh Main Data RAM
Bank 1
08h
07h
Bank 0
00h
PSW SFR
Bit 4 Bit 3 selected bank
1 1 3
1 0 2
0 1 1
Fig.9 Main Data Memory and SFRs
0 0 0
7.2.1 THE LOWER 128 BYTES OF THE MAIN DATA RAM

The lower 128 bytes are organized as shown in Fig.9. The lower 32 bytes form 4 banks of eight registers (R0 - R7). Two
bits on the Program Status Word (PSW) select which bank is active (in use). The next 16 bytes, from 20 (hex) to 2F (hex)
, form a block of bit-addressable memory space, at bit address 00(hex) ~ 07(hex).
V1 2008 Jul 09 23
7.3 AUX Memory
7.3.1 AUX MEMORY SPACE

The STK6032 has 64K bytes of auxiliary memory (AUX RAM) space, which can be accessed by executing MOVX
instruction. The AUX RAM space is physically divided into two blocks: the on-chip block and the off-chip block. The
on-chip block has a capacity of 768 bytes and starts from address 0 to address 767(decimal). The off-chip block starts
from address 768(decimal) to address 65535.
The MOVX @Ri instruction, where i=0 or 1, can access only the lowest 256-bytes of the on-chip AUX RAM. The MOVX
@DTPR instruction can access the whole range of the AUX RAM space.
AUX RAM space from address 768 to address 65535 is allocated as external AUX RAM and can only be accessed by
the MOVX @DPTR instruction. The external AUX RAM is externally expandable, with Port 0 used as low-byte
address/data, Port 2 used as high-byte address, P3.6 used as Write strobe, and P3.7 used as Read strobe.
65535
Externally
Total AUX Memory Space
Read/write to this block

can be disbabled by expandable
programming bit 4 of
SFR CHIPCON to LOW.
768
767
on-chip
AUX memory
0 Fig.10 The AUX Memory Spae
7.3.2 ON-CHIP AUX MEMORY

The on-chip AUX RAM from address 0 to address 767 can be accessed by the CPU as normal data memory, by
performing a MOVX instructon. Read/Write access to this memory can be disabled by setting bit 4 of the SFR CHIPCON
to LOW. Please refer to Table 3 and Table 4 for detailed description of the SFR CHIPCON.
When executing MOVX instruction from internal program memory, an access (read or write) to the internal AUX RAM will
not affect the status of Port 0, Port 2, P3.6(write) and P3.7.(read).
7.3.3 DUAL DATA POINTER (DATA POINTER 0 AND DATA POINTER 1) AND DPTR SELECT REGISTER (SFR DPS)
The STK6032 has two data pointers, Data Pointer 0 and Data Pointer 1. Data Pointer 0 is the traditional 8051 data pointer
for MOVX instrucitons. Data Pointer 1 is an extra data pointer for fast moving a block of data. Before executing a MOVX
instruction, an active data pointer must be selected by programming the Data Pointer Select Register (SFR DPS). Please
refer to Table 7 for detailed description of SFR DPS.
V1 2008 Jul 09 24
Table 7 Data Pointer 0, Data Pointer 1, and DPTR Select Register

Address Reset Value
R/W SYMBOLS DESCRIPTION
(Hex)
82 R/W DPL0 Data Pointer 0 Low (traditional 80C51 data pointer) 0000 0000
83 R/W DPH0 Data Pointer 0 High (traditional 80C51 data pointer) 0000 0000
84 R/W DPL1 Data Pointer 1 Low (extra data pointer), specific to the 0000 0000
STK6032.
85 R/W DPH1 Data Pointer 1 High (extra data pointer), specific to the 0000 0000
STK6032.
86 R/W DPS DPTR Select Register (DPS), specific to the STK6032. 0000 0000
The DPS register has only one bit. Only its bit 0, called SEL bit,
is implemented on-chip. When SEL=0, instructions that use the
DPTR will use SFR DPL0 and SFR DPH0. When SEL=1,
instructions that use the DPTR will use SFR DPL1 and
SFR DPH1.
Bits 7~1 of SFR DPS can not be written to, and, when read,
always return a 0 for any of these 7 bits.
All DPTR-related instrucitons use the currently selected data pointer. To switch the active pointer, toggle the SEL bit, by
use of the instruciton INC DPS. The 6 instructions that use the DPTR are given in the following table. An active DPTR
must be selected before executing these intructions.
Table 8 Instructions that use the DPTR

INSTRUCITON DESCRIPTION
INC DPTR Increment the data pointer by1.
MOV DPTR, #data16 Load the DPTR with a 16-bit constant.
MOV A, @ A+DPTR Move code byte relative to DPTR to Accumulator (ACC).
MOVX A, @DPTR Move AUX Memory byte (16-bit address) to Accumulator (ACC)
MOVX @DPTR, A Move ACC to AUX memory byte.
JMP @ A+DPTR Jump indirect relative to DPTR.
7.3.4 STRETCH MEMORY CYCLES FOR ACCESSING EXTERNAL AUX MEMORY AND CLOCK CONTROL REGISTER
By default (after a reset), the MOVX instruction is executed in 3 instruciton cycles. However, it is possible to shorten or
lengthen, dynamically by user program, the instruction cycles needed to execute a MOVX instruction, by use of the M2,
M1, and M0 bits of the Clock Control Register (SFR CKCON).
The added extra cycles affects the width of the read/write strobe and all related timing. Using a higher stretch value
results in a wider read/write strobe, which then allows the memory more time to respond.
Table 9 and Table 10 give decription of the Clock Control Register and Table 11 gives decription about the stretched
cycles for various values of M2, M1, and M0.
V1 2008 Jul 09 25
Table 9 Clock Control Register, SFR CKCON

Clock Control Register (SFR CKCON), located at 8E(hex) of the SFR map
Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonics Reserved T2M T1M T0M MD2 MD1 MD0
Reset value 0 0 0 0 0 0 0 1
Table 10 Description of the CKCON Register

BIT
MNEMONIC FUNCTION
POSITION
T2M CKCON.5 Select Timer 2 clock frequecny.
When T2M=0, Timer 2 uses (CPU CLK / 12) as clock frequency.
MD2 CKCON.2 Control the number of cycles to be used for accessing external AUX memory, using the
MD1 CKCON.1 MOVX instruction.
MD0 CKCON.0
Table 11 Data Memory Stretch Values

Intruction cycles for Read/Write Strobe Strobe Width
MD2 MD1 MD0
executing MOVX Width (CPU CLK) Time @25 MHz
0 0 0 2 2 80 ns
0 0 1 3 (default) 4 160 ns
0 1 0 4 8 320 ns
0 1 1 5 12 480 ns
1 0 0 6 16 640 ns
1 0 1 7 20 800 ns
1 1 0 8 24 960 ns
1 1 1 9 28 1120 ns
Assume that XTAL1=CPU CLK. Please refer to Fig.5.
V1 2008 Jul 09 26
8 SPECIAL FUNCTION REGISTERS
8.1 SFR Map Overview

The STK6032 has 46 bytes of SFRs implemented on-chip.
Address Reset Value
(Hex)
80 R/W P0 Port 0 output latch (bit-addressable). 1111 1111
81 R/W SP Stack Pointer 0000 0111
82 R/W DPL0 Data Pointer 0 Low (traditional 80C51 data pointer) 0000 0000
83 R/W DPH0 Data Pointer 0 High (traditional 80C51 data pointer) 0000 0000
84 R/W DPL1 Data Pointer 1 Low (extra data pointer), specific to the 0000 0000
STK6032.
85 R/W DPH1 Data Pointer 1 High (extra data pointer), specific to the 0000 0000
STK6032.
86 R/W DPS DPTR Select Register (DPS), specific to the STK6032. 0000 0000
87 R/W PCON Power Control Register. 0011 0000

88 R/W TCON Timer0/1 Control Register (bit-addressable) 0000 0000
89 R/W TMOD Timer0/1 Mode Register 0000 0000
8A R/W TL0 Timer0, Low byte 0000 0000
8B R/W TL1 Timer1, Low byte 0000 0000
8C R/W TH0 Timer0, High byte 0000 0000
8D R/W TH1 Timer1, High byte 0000 0000
R/W CKCON Clock Control register, specific to the STK6032. 0000 0001
8E The register is for controlling the frequency of the clock added

to Timer 0, Timer 1, and Timer 2, and memory stretch cycle for
the MOVX instruction.
8F not used.
90 R/W P1 Port 1 output latch (bit-addressable). 1111 1111
91, 92, 93, 94, 95, 96, 97, not used.
98 R/W SCON0 Serial Port Control/Status Register 0(bit-addressable) 0000 0000
99 R/W SBUF0 Serial Port Buffer Register 0 0000 0000
9A, 9B, 9C, 9D, 9E, 9F not used
A0 R/W P2 Port 2 output latch (bit-addressable ) 1111 1111
A1, A2, A3, A4, A5, A6, A7 not used.
A8 R/W IE Interrupt Enable Register (bit-addressable) 0000 0000
A9, AA, AB, AC, AD, AE, AF not used.
B0 R/W P3 Port 3 output latch (bit-addressable) 1111 1111
B1, B2, B3, B4, B5, B6, B7, not used.
B8 R/W IP Interrupt Priority Register (bit-addressable) 1000 0000
B9, BA, BB, BC, BD, BE, not used.
BF R/W CHIPCON Chip Configuration Register xxx1 0000
C0 R/W P4 Port 4 output latch. 1111 1111
C1, C2, C3, C4, C5, C6, C7, not used.
C8 R/W T2CON Timer 2 Control Register (bit-addressable) 0000 0000
C9 not used.
V1 2008 Jul 09 27
Address Reset Value

(Hex)
CA R/W RCAP2L Timer 2 Reload Capture Register, Low byte 0000 0000
CB R/W RCAP2H Timer 2 Reload Capture Register, High byte 0000 0000
CC R/W TL2 Timer 2, Low byte 0000 0000
CD R/W TH2 Timer 2, High byte 0000 0000
CE, CF not used.
D0 R/W PSW Program Status Word Register (bit-addressable) 0000 0000
R/W P1_OPT Selecting Port 1 pin function, as normal port pin or PWM xxx0 0000
D1
output.
D2 R/W PWM0D Pulse width modulation, channel 0 1000 0000
D7, D8 not used.
D9 R/W P4_OPT Selecting Port 4 pin function, as normal port pin or ADC input. 1111 1111
DA R/W ADCSE Configuring P4.0 ~ P4.5 pins as ADC input pins. 0xxx 0000
DB R ADCVAL Buffer for storing the converted digital value of the 6-bit ADC. xx00 0000
DC, not used.
P0_OPT Port 0 pin option for normal I/O or external memory 1111 1111
DD
address/data.
DE P2_OPT Port 2 pin option for normal I/O or external memory address. 1111 1111
DF not used
E0 R/W ACC Accumulator (bit-addressable) 0000 0000
E1 R/W WDT Watchdog Timer Control. 00xx x000
E2 R/W ISPSLV ISP Control Slave address 0000 0000
E3 R/W ISPEN ISP Enable register (write 93hex to enable the ISP mode) 0000 0000
E4 ~EF not used.
F0 R/W B B Register (bit-addressable) 0000 0000
F1 ~ FF not used.
V1 2008 Jul 09 28
8.2 SFR of Each Functional Block
Table 12 SFR of each functional block
Address RESET
BLOCK SYMBOL NAME
(Hex format) VALUE
CPU ACC Accumulator. E0 0000 0000
B B register F0 0000 0000
SP Stack Pointer 81 0000 0111
DPL0 Data Pointer 0, Low byte 82 0000 0000
DPH0 Data Pointer 0, High byte 83 0000 0000
DPL1 Data Pointer 1, Low byte 84 0000 0000
DPH1 Data Pointer 1, High byte 85 0000 0000
DPS Selection for active Data Pointer 86 0000 0000
PCON Power Control Register 87 0011 0000
PSW Program Status Word D0 0000 0000
CHIPCON Chip Configuration Register BF xxx1 0000
CKCON Clock Control Register 8E 0000 0001
Interrupt System IE Interrupt Enable Register A8 0000 0000
IP Interrupt Priority Register B8 x000 0000
Ports P0 Port 0 latch 80 1111 1111
P0_OPT Port 0 pin option for I/O or external memory DD 1111 1111
access
P1 Port 1 latch 90 1111 1111
P1_OPT Port 1 pin option for I/O or PWM outputs D1 xxx0 0000
P2 Port 2 A0 1111 1111
P2_OPT Port 2 pin option for I/O or external memory DE 1111 1111
access
P3 Port 3 latch B0 1111 1111
P4 Port 4 latch C0 1111 1111
P4_OPT Port 4 pin option for I/O or ADC inputs D9 xx00 0000
UART SBUF0 Serial Port Buffer Register 99 ???? ????
SCON0 Serial Port Control/Status Register 98 0000 0000
Timer 0 / Time 1 TCON Timer 0/1 Control Register 88 0000 0000
TMOD Timer 0/1 Mode Register 89 0000 0000
TL0 Timer 0, Low byte 8A 0000 0000
TL1 Timer 1, Low byte 8B 0000 0000
TH0 Timer 0, High byte 8C 0000 0000
TH1 Timer 1, High byte 8D 0000 0000
Timer 2 T2CON Timer 2 Control Register C8 0000 0000
RCAP2L Timer 2 Reload Capture Register, Low byte CA 0000 0000
RCAP2H Timer 2 Reload Capture Register, High byte CB 0000 0000
TL2 Timer 2, Low byte CC 0000 0000
TH2 Timer 2, High byte CD 0000 0000
V1 2008 Jul 09 29
Address RESET
BLOCK SYMBOL NAME
(Hex format) VALUE
Watchdog Timer WDT Watchdog Timer Control Register E1 00xx x000
PWM P1_OTP Port 1 pin selection for PWM outputs D1 xxx0 0000
PWM0D PWM0 width D2 1000 0000
P4_OPT Selet Port 4 pin function D9 xxxx 0000
ADC ADCSEL Select ADC input channel for conversion DA 0xxx 0000
ADCVAL Buffer for converted ADC value. DB xx00 0000
ISP ISPSLV ISP Control slave address E2 0000 0000
ISPEN Write 93 (hex) to enable the ISP mode E3 0000 0000
V1 2008 Jul 09 30
9 PORT 0, PORT 1, PORT 2, PORT 3, AND PORT 4

The STK6032 has five 8-bits ports (Ports 0 ~ 4). All bits of Port 0 are push-pull output. All bits of Port 1, Port 2, Port 3
and Port 4 are push-pull outputs with internal weak pull-high PMOS.
9.2 Port 0
Port 0 pins are push-pull outputs. It has three functions:
• Pure bidirectional I/O data ports
• Low-byte address (A0 ~ A7) output and OP code input, when executing program in external program ROM mode
(EA= 0, during power-on reset).
• Low-byte address (A0 ~ A7) and data bus during read/write to off-chip AUX memory.
SFR P0_OPT must be properly programmed to ensure proper operation of Port 0.
Output_enable
Port 0 pins are push-pull
Data_out outputs. The output
Output
sinking and sourcing
capability is 4 mA (typ.).
Input_enable
Data_in
Fig.11 Port 0 schematic
9.3 Port 1, Port 2, and Port 3

Figure 12 shows Port 1, Port 2, and Port 3. They are push-pull outputs with internal weak pull-up.
Port 1shares with the 5-channel, 8-bit, PWM for data input/output. SFR P1_OPT needs to be properly programmed to
ensure porper operation of Port 1. Please refer to Section 19.2 for detailed description of SFR P1_OPT.
Port 2 acts as data I/O or address bus (A8 ~ A15) during access to external Program ROM and AUX memory.
SFR P2_OPT must be properly programmed to ensure proper operation of Port 2.
Port 3 are multi-functional I/O port.
.
VDD
Pins of Port 1, Port 2, and
Port 3 are push-pull outputs
Pull-up
with weak internal pull-up. The
output sinking and sourcing
Output_enable
capability is 4 mA (typ.). The
typical value of the equivalent
Data_out Output resistance of the pull-up PMOS
is 15K ohm.
Input_enable
Data_in
Fig.12 Schematic of Port 1, Port 2, and Port 3
V1 2008 Jul 09 31
9.4 Port 4
Port 4 is an 8-bit port. It shares inputs with the 6-bit ADC. SFR P4_OPT needs to be programmed to select
P4.0 - P4.5 pins as general-purpose I/O pins or ADC input pins. Please refer to Section 20.3.1 for more description of
Port 4.
VDD Weak pull-up PMOS must be

turned off when used as ADC
SFR P4_OTP input.
Output_enable
Data_out Output
Input_enable
Data_in
Analog_In
ESD
Fig.13 Port 4 schematic
9.5 MOVX instruction, Port 0, Port 2, P3.6, P3.7

When executing MOVX instruction from internal program memory, an access to the internal AUX RAM will not affect Port
0, Port 2, P3.6 and P3.7.
9.6 Multiple-Function Port Pins

Some port pins have multiple functions. Port pins which are not used for alternate functions may be used as normal
bidirectional I/O pins. The configuration of a port pin as an alternate function is carried out automatically by writing the
associated SFR bit with proper value.
Please refer to Table 2 for a detailed decription of multiple-function pins.
V1 2008 Jul 09 32
10 TIMER/COUNTER 0, TIMER/COUNTER 1

There are seven SFRs associtated with Timer/Counter 0 and Timer/Counter 1, as given in Table 13. Both
Timer/Counter 0 and Timer/Counter 1 can be configured to operate either as timers or event counters.
Table 13 SFRs associated with Timer/Counter 0 and Timer/Counter 1.

SFR name Address Description Reset
(hex) in SFR value
space (hex)
TL0 8A These two SFRs are the lower 8 bits and higher 8 bits of Timer/Counter 0. 00
TH0 8C 00
TL1 8B These two SFRs are the lowr 8 bits and higher 8 bits of Timer/Counter 1. 00
TH1 8D 00
TCON 88 Control register for Timer/Counter 0 and Timer/Counter 1. 00
TMOD 89 Mode selection register for Timer/Counter 0 and Timer/Counter 1. 00
CKCON 8E Clock frequency selection for Timer/Counter 0 and Timer/Counter 1. 01
Four operating modes are available from Timer/Counter 0 and Timer/Couter 1:

• Mode 0: 13-bit timer/counter
• Mode 1: 16-bit timer/counter
• Mode 2: 8-bit counter with auto-reload
• Mode 3: Two 8-bit counters (only available from Timer 0)
10.2 Mode Selection Regiser, SFR TMOD ( at 89H of SFR space)

)
MSB LSB
Gate C/T M1 M0 Gate C/T M1 M0
Timer 1 Timer 0
Table 14 Timer 0/1 Mode Selection Register
TIMER 0/1 MODE REGISTER (TMOD), LOCATED AT 89H OF THE SFR SPACE
Bit Address TMOD.7 TMOD.6 TMOD.5 TMOD.4 TMOD.3 TMOD.2 TMOD.1 TMOD.0
Mnemonics Gate C/T M1 M0 Gate C/T M1 M0
(Timer1) (Timer1) (Timer1) (Timer1) (Timer0) (Timer0) (Timer0) (Timer 0)
V1 2008 Jul 09 33
Table 15 Description of Timer 0/1 Mode Selection Register

BIT
MNEMONIC FUNCTION
POSITION
GATE TMOD.7 Gating control for Timer 1.
When set, Timer 1 is enabled only while INT1 pin is high and TR1 control bit is set.
When cleared, Timer 1 is enabled whenever TR1 control bit is set.
C/T TMOD.6 Timer or Counter selection of Timer 1.
When set, counter operation is selected.
When cleared, timer operation is selected.
M1, M0 TMOD.5 Mode selection of Timer 1
TMOD.4 • (M1, M0) = 00 selects Mode 0 operation.
• (M1, M0) = 01 selects Mode 1 operation.
• (M1, M0) = 11 selects Mode 3 operation.( In mode 3, Timer/Counter 1 is stopped.)
GATE TMOD.3 Gating control for Timer 0.
When set, Timer 0 is enabled only while INT0 pin is high and TR0 control bit is set.
When cleared, Timer 0 is enabled whenever TR0 control bit is set.
C/T TMOD.2 Timer or Counter selection of Timer 0.
When set, counter operation is selected.
When cleared, timer operation is selected.
M1, M0 TMOD.1, Mode selection of Timer 0
TMOD.0
• (M1, M0) = 11 selects Mode 3 operation. ( In mode 3, Timer/Counter 1 is stopped.)
10.3 Timer 0/1 Control Register (SFR TCON at 88 H of the SFR space)
Table 16 Timer 0/1 Control Register

TIMER 0/1 CONTROL REGISTER ( TCON ), LOCATED AT 88H OF THE SFR SPACE
Bit Address TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0
Mnemonics TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
V1 2008 Jul 09 34
Table 17 Description of Timer 0/1 Control Register
BIT
MNEMONIC FUNCTION
POSITION
TF1 TCON.7 Timer 1 overflow flag.
Set by hardware on Timer/Counter 1 overflow.
Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in
software.
TR1 TCON.6 Timer 1 Run control bit.
Set/cleared by software to turn Timer/Counter on/off.
TF0 TCON.5 Timer 0 overflow flag.
Set by hardware on Timer/Counter 0 overflow.
Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in
software.
TR0 TCON.4 Timer 0 Run control bit.
Set/cleared by software to turn Timer/Counter on/off.
IE1 TCON.3 External Interrupt 1 Flag.
Set by hardware when external interrupt 1 is detected.
This bit is cleared after the interrupt is processed. That is, when the Return from Interrupt
instruction is executed.
IT1 TCON.2 Interrupt 1 Type Control bit.
Set/cleared by software to specify falling edge/low level triggered external interrupt.
IE0 TCON.1 External Interrupt 0 Flag.
Set by hardware when external interrupt 0 is detected.
This bit is cleared after the interrupt is processed. That is, when the Return from Interrupt
instruction is executed.
IT0 TCON.0 Interrupt 0 Type Control bit.
Set/cleared by software to specify falling edge/low level triggered external interrupt.
10.4 Clock Control Register, SFR CKCON, at address 8E hex of the SFR map
For a description of the Clock Control Regsiter, please refer to Table 9 and Table 10.
V1 2008 Jul 09 35
10.5 Operating Modes
10.5.1 MODE 0 (13-BIT TIMER/COUNTER)

When in mode 0, either of Timer 0 and Timer1 acts as a 13-bit counter. Fig.14 shows the operation of both Timer 0 and
Timer 1 in mode 0 operation.
CPU CLK Divide-by-12

T0M=0 T1M=0
T0M=1 T1M=1
Divide-by-4
C/T=0 SFR TL1
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
P35/T1 Pin
C/T=1
(TMOD.5, TMOD.4)=00
TR1
(TCON.6)
Enable (TMOD.5, TMOD.4)=01
Gate
(TMOD.7) overflow flag
Interrupt
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
P3.3/INT1 Pin TF1
SFR TH1 (TCON.7)
C/T=0 SFR TL0

bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
P3.4/T0 Pin
C/T=1
(TMOD.1, TMOD.0)=00
Mode0
TR0
(TCON.4) Enable
(TMOD.1, TMOD.0)=01
Gate
(TMOD.3) overflow flag
Interrupt
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
P3.2/INT0 Pin TF0

SFR TH0 (TCON.5)
Fig.14 Mode 0 (13-bit timer/counter) and Mode 1 (16-bit timer/counter)
In this mode, the Timer 0/Timer 1 registers are configured as a 13-bit register, which is composed of all the 8 bits of the
TH1 (TH0) and the lower 5 bits of TL1 (TL0). The upper 3 bits of the TL1 (TL0) are indeterminate. The Timer Interrupt
flag TF1 (TF0) is set to HIGH when the 13-bit register, acting as a counter, rolls over from all 1s to all 0s.
The 13-bit register(counter) is enabled only under the following conditions:
1. TR0 (TR1)=1, and
2. Either Gate=0 or INT1 (INT0)=1.
V1 2008 Jul 09 36
10.5.2 MODE 1 (16-BIT TIMER/COUNTER)

The configuration and operation of Mode 1 is the same as that of Mode 0, except that the registers are now 16 bits,
instead of 13 bits when in Mode 0. Please refer to Fig.14.
10.5.3 MODE 2 (8-BIT COUNTER WITH AUTO-RELOAD)

Mode 2 configures the SFR TL0 and SFR TL1 as an 8-bit counter, respectively, with automatic reloading from SFR TH0
and SFR TH1, respectively. When the contents of TL1(TL0) changes from all 1s to all 0, the corresponding flags TF1
(TF0) is set to HIGH and the content of TH1(TH0) is reloaded into TL1 (TL0).The action of this reloading does not change
the content TH1(TH0). The content of TH1 (TH0) can only be changed via programming these two SFRs.
As illustrated in Fig.14 and Fig.15, the control (enable) signal for mode 0, mode 1 and mode 2 are all the same.
Fig.15 shows the operation of Timer 0 and Timer 1 in mode 2.

T0M=0 T1M=0
T0M=1 T1M=1
Divide-by-4
C/T=0 SFR TL1 overlfow flag

Interrupt
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
P35/T1 Pin bit 7
TF1
C/T=1
(TCON.7)
TR1 Reload
(TCON.6)
Enable
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Gate
(TMOD.7)
P3.3/INT1 Pin SFR TH1
C/T=0 SFR TL0 overlfow flag

Interrupt
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
P3.4/T0 Pin TF0

C/T=1
(TCON.5)
TR0 Reload
(TCON.4) Enable
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Gate
(TMOD.3)
SFR TH0
P3.2/INT0 Pin
Fig.15 Mode 2 operation of Timer 0, Timer 1.
V1 2008 Jul 09 37
10.5.4 MODE 3 (TWO 8-BIT COUNTERS FROM TIMER 0)

When in Mode 3, Timer 1 stops counting and holds it value, and Timer 0 is configured into two separate counters: TL0
and TH0. The logic of Timer 0 in Mode 3 is shown below.
TL0 uses the Timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 is configured into a timer function(counting
machines cycles) and takes over the use of TR1 and TF1 from Timer 1. Hence, TH0 now controls the Timer 1 interrupt.

T0M=0
T0M=1
Divide-by-4
SFR TH0 overflow flag
Interrupt
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TF1
TR1
(TCON.6) (TCON.7)
C/T=0 SFR TL0 overflow flag

Interrupt
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
P3.4/T0 Pin TF0
C/T=1
(TCON.5)
TR0
(TCON.4) Enable
Gate
(TMOD.3)
P3.2/INT0 Pin
Fig.16 Mode 3 operation of Timer 0, Timer 1
V1 2008 Jul 09 38
11 RESET
11.1 Sources of RESET

There are 5 sources to reset STK6032:
• external RESET pin,
• power-on reset,
• low-voltage detection reset,
• watchdog timer overflow, and
• ISP programming.
The functional diagram of the reset circuitis is shown in Fig.17.
Low-voltage
detection and reset
Power-on-reset
RESET pin Reset

Delay and Control the whole chip
external
resistor
watchdog timer overflow

ISP programming mode
Fig.17 Functional diagram of reset circuit
11.2 Power-On- Reset (POR) with fast-rising power supply

The STK6032 can be reset by the on-chip power-on-reset, whose switching level is 2.7 ± 0.2 volts. The sequence of the
power-on-reset is as follows:
1. As soon as the power supply (VDD) reaches the POR switching level, the on-chip POR generates a pulse, called
POR Pulse.
2. This POR pulse then triggers an internal reset, POC. Also, this POR pulse resets the internal reset counter.
3. When the oscillator is stable enough, the oscillator clocks starts triggering the internal reset counter to count.
4. When the internal reset counter counts up to 2048 and overflows, the internal reset (POC) is released and the CPU
starts executing instruction.
The above sequence is further illustrated in Fig.18.
V1 2008 Jul 09 39
Switching level of POR

= 2.7 volts
Supply
Voltage
POR Pulse
Internal
Reset
Oscillator
CPU running CPU starts instruction fetch

from Program ROM address 0000H.
Oscillator
Time = 0
Start-up 2048 oscillator
time period delay
The oscillator clock is stable enough

to trigger the internal divided-by-2048
Fig.18 Timing of Power-On-Reset with fast rising VDD. counter.
11.3 Asynchronous reset by adding a HIGH pulse to the RESET pin

The STK6032 can be reset by adding a HIGH pulse to the RESET pin. The RESET pin is an input with an internal
Schmitt-trigger for noise reduction. The CPU checks if there is a reset at cycle 4 (C4) of every instruction cycle. A reset
is accomplished by holding the RESET pin HIGH for at least two instruction cycles while the oscillator is running. The
CPU responds by executing an internal reset.
11.4 Low-power detection and reset

The STK6032 has the capability of low-power detection and reset. The reset due to low power can be enabled or disabled
by use of the LVR bit (bit 0) of SFR CHIPCON, at SFR address BF(hex). Setting LVR=0 enables low-power reset and
setting LVR=1 disables low-power reset.
Due to fabrication process variations from different production lots, the threshold voltage for low-power detection is in the
range of 2.52 ~ 2.94 volts, without regard to the supply voltage to the VDD pin. The typical low-power threshold voltage
is 2.7 volts.
11.5 Reset by the Watchdog Timer overflow

The microcontroller can also be reset by the Watchdog Timer overflow. Please refer to Chapter 15 .
V1 2008 Jul 09 40
12 TIMER/COUNTER 2
12.1 General Description and operation modes

Timer 2 is mainly composed of four SFRs, TH2, TL2, RCAP2L, RCAP2H, and their contorl logic.
SFR TH2 and SFR TL2 are cascaded into a 16-bit timer or counter, called Timer 2, which can be driven by either XTAL1
clock or off-chip clock pulse.
SFR RCAP2L and SFR RCAP2H are also cascaded into a 16-bit register. This register is used as a capture register or
reload register. When used as a capture register, it can captures the content of Timer 2. When used as a reload register,
it can reloads its content into Timer 2.
Timer 2’s clock source can be from on-chip XTAL1 clock or off-chip clock pulse, depending on the state of the C/T2 bit,
bit 1 of SFR T2CON.
Timer 2 can operate in four different modes, listed below:
• 16-bit timer/counter,
• 16-bit timer/counter with capture,
• 16-bit timer/counter with auto-reload, or
• Baud-rate generator for UART.
Table 18 describes how to configigure Timer T2 to operate in different operating modes.
Table 18 Configuring Timer 2 into various operating modes
RCLK TCLK CP/RL2 TR2

OPERATING MODE
(T2CON.5) (T2CON.4) (T2CON.0) (T2CON.2)
• 16-bit timer/counter, or
0 0 1 1
• 16-bit timer/counter with capture capability.
0 0 0 1 16-bit timer/counter with auto-reload.
1 X X 1 Baud rate generator for UART.
• Either RCLK=1 or TCLK=1 will configure Timer 2 into
Baud Rate Generator mode.
X 1 X 1
• When Timer 2 is in Baud Rate Generator Mode,
bit CP/RL2 is ignored.
When TR=1, clock pulses is blocked from entering into
X X X 0
Timer 2. That is, Timer 2 is disabled.
X=don’t care
V1 2008 Jul 09 41
12.2 Special Function Registers associated with Timer 2

Timer 2 is associated with the 7 SFRs, listed in Table 19. Three SFRs, CKCON, T2CON, and T2MOD, must be properly
programmed to have timer 2 work properly.
Table 19 Timer 2 SFRs
VALUE AFTER
ADDRESS R/W MNEMONICS DESCRIPTION
RESET
Select clock frequency for Timer 0, Timer 1, and Timer 2, 0000 0000
8E R/W CKCON
and memory stretch cycle for the MOVX instruciton.
C8 R/W T2CON Timer 2 Control Register ( bit-addressable ) 0000 0000
C9 R/W T2MOD Timer 2 Mode Control register xxxx xx 0x
CA R/W RCAP2L Timer 2 Reload/Capture Register, Low byte 0000 0000
CB R/W RCAP2H Timer 2 Reload/Capture Register, High byte 0000 0000
CC R/W TL2 Timer 2, Low byte 0000 0000
CD R/W TH2 Timer 2, High byte 0000 0000
12.2.1 THE T2M BIT OF CLOCK CONTROL REGISTER (SFR CKCON)

The T2M bit (bit 5) of the Clock Control Register (CKCON SFR), located at 8E(hex) of the SFR memory space, selects
the frequency of the clock used to drive Timer 2.
When the T2M bit is programmed to LOW (T2M=0), (XTAL1 ÷ 12) clock is selected to drive Timer 2. When the T2M bit
is programmed to HIGH (T2M=1), (XTAL1 ÷ 4) clock is selected to drive Timer 2. This bit has no effect when Timer 2 is
programmed to work as a baud rate generator.
Table 20 T2M bit of SFR CKCON

Clock Control Register (SFR CKCON), located at 8E(hex) of the SFR map
Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonics Reserved T2M T1M T0M MD2 MD1 MD0
Reset value 0 0 0 0 0 0 0 1
Table 21 Description of the T2M bit of SFR CKCON

BIT
MNEMONIC FUNCTION
POSITION
When T2M=0, Timer 2 uses (XTAL1 / 12) as clock frequency.
When T2M=1, Timer 2 uses (XTAL1 / 4) as clock frequency.
For detailed description of the SFR CKCON, please refer to Table 9.
V1 2008 Jul 09 42
12.2.2 TIMER 2 CONTROL REGISTER (SFR T2CON)

Table 22 and Table 23 give description for SFR T2CON.
Table 22 Timer 2 Control Register (SFR T2CON, C8 hex)

Mnemonics TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
Reset Value 0 0 0 0 0 0 0 0
Table 23 Description of Timer 2 Control Register
BIT
MNEMONIC FUNCTION
POSITION
Timer 2 overflow flag.
• This bit is set to HIGH when Timer 2 overflows from FFFF(hex) to 0000(hex). It must
be cleared by software.
TF2 T2CON.7
• TF2 will not be set when either RCLK or TCLK is 1. That is, when Timer 2 is in Baud
Rate Generator mode, TF2 will never be set.
• Writing a 1 to TF2 bit forces a Timer 2 interrupt, if this interrupt function is enabled.
Timer 2 External flag.
• This bit is set to HIGH when a capture or reload action is triggered by a high-to-low
transition on the T2EX input pin and when EXEN2=1.
EXF2 T2CON.6
• When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to jump to Timer 2
interrupt subroutine. It must be cleared by software.
• Writing a 1 to the EXF2 bit forces a Timer 2 interrupt, if it is enabled.
UART Receiver clock selection.
This bit is used to select the receiver clock of the UART.
RCLK T2CON.5 • If this bit is programmed to 1 (RCLK=1), UART uses Timer 2 overflow pulses as its
receiver clock in Modes 1 and 3.
• If this bit is programmed to 0 (RCLK=0) , UART uses Timer 1 overflow pulses as its
receiver clock.
UART Transmitter clock selection.
This bit is used to select the transmitter clock of the UART.
TCLK T2CON.4 • If this bit is programmed to 1 (TCLK=1), UART uses Timer 2 overflow pulses as its
transmitter clock in Modes 1 and 3.
• If this bit is programmed to 1 (TCLK=0) , UART uses Timer 1 overflow pulses as its
transmitter clock.
Timer 2 external enable.
EXEN2 T2CON.3 • EXEN2=1 allows a capture or reload to occur as a result of a high-to-low transition on
the T2EX input, if Timer 2 is not in baud rate generator mode.
• EXEN2=0 causes Timer 2 to ignore all events at T2EX input.
V1 2008 Jul 09 43
BIT
MNEMONIC FUNCTION
POSITION
Start/Stop control for Timer 2.
TR2 T2CON.2 • TR2=1 allows clocks to be added to Timer 2.
• TR2=0 prevent clocks from being added to Timer 2.
Select timer function or counter function of Timer 2.
• C/T2= 0 selects the timer fucntion.
• When used as a timer, Timer 2 runs at four XTAL1 clocks per increment or twelve
XTAL1 clocks per increment, as selected by the T2M bit (CKCON.5) of the SFR
C/T2 T2CON.1 CKCON, in all modes except baud rate generator mode.
• When used in baud rate generator mode, Timer 2 runs at two XTAL1 per increment,
independent of the state of the T2M bit.
• C/T2=1 selects the external event counter function; falling-edge-triggered on the T2
input.
CP/RL2 T2CON.0 Selection of capture or reload function.
• When this bit is programmed to HIGH (CP/RL2 =1), Timer 2 is in capture mode and
capture occurs on a high-to-low transitions (falling edge) at T2EX, if EXEN2=1.
• When this bit is programmed to LOW (CP/RL2 =0), Timer 2 is in auto-reload mode
and auto-reload occurs either with Timer 2 overflows or a high-to-low transitions at
T2EX when EXEN2=1.
• When RCLK=1 or TCLK=1, this bit is ignored and the timer is forced to auto-reload on
a Timer 2 overflow.
V1 2008 Jul 09 44
12.2.3 TIMER 2 MODE CONTROL REGISTER

Timer 2 Mode Control Register, located at C9(hex) of the SFR memory space, is a one-bit SFR. It is used to turn on
Timer 2 pulse output to the P1.0/PWM0/T2 pin, when Timer 2 overflows from FFFFH.
Table 24 Timer 2 Mode Control Register (SFR T2MOD)
Timer 2 Control Register ( SFR T2CON ), located at C8(hex) of the SFR memory space.
Mnemonics T2OE
Reset Value X X X X X X 0 X
Table 25 Description of Timer 2 Control Register
BIT
MNEMONIC FUNCTION
POSITION
T2OE T2MOD.1 Timer 2 output enable bit.
Programming this bit to HIGH (T2OE=1) enables Timer 2 overflow pulse to be sent to
the P1.0/PWM0/T2 pin, as illustrated in the following figure.
P1.0/PWM0/T2
pin
Clock overflow pulse P1.0/PWM0/T2
Timer 2
Control
T2OE
Bit PWM0E
of SFR P1_OPT
Fig.19 T2OE bit
V1 2008 Jul 09 45
12.3 16-bit Timer/Counter Mode

In this mode, SFR TL2 and SFR TH2 are cascaded into a 16-bit timer or counter. SFR RCAP2L and SFR RCAP2H are
not used. This 16-bit timer can then be used to count pulses from on-chio XTAL1 clock or off-chip external pulses, by
properly programming bits T2M and C/T2. The TR2 bit, Timer 2 enable bit, must always be HIGH.
When Timer 2 overflows from FFFFH to 0000H, a clock pulse with the duration of one cycle of XTAL1 clock is sent
out.This pulse then sets the Timer 2 overflow flag, which, if enabled, can generate an interrupt. The overflow pulse can
also be sent to Pin1.0, if the T2OE bit is enabled.
Fig.21 shows Timer 2 configuration when it works as a 16-bit Timer/Counter.
XTAL1 Divide-by-12
T2M=0 (CKCON.5)
T2M=1
Divide-by-4 C/T2=0
TR2
falling-edge C/T2=1 (T2CON.2)
P1.0/PWM0/T2 Pin detection
Timer 2 clock
To Pin1.0
SFR TL2 SFR TH2 overflow flag

T2OE
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TF2 (T2MOD.1=1)
(T2CON.7)
Timer 2
capture interrupt
This portion of circuit external flag
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
is ignored. EXF2
(T2CON.6)
SFR RCAP2L SFR RCAP2H
P1.1/PWM1/T2EX Pin
falling-edge
detection
EXEN2
(T2CON.3)
CP/RL2
(T2CON.0)
Fig.20 Timer 2 configuration in 16-bit timer/counter mode
V1 2008 Jul 09 46
12.4 16-bit Timer/ Counter with Capture capability (Capture Mode)

When Timer 2 works in this mode, the content of SFR TL2 and SFR T2H can be captured into SFR RCAP2L and
SFR RCAP2H, respectively, by an external triggering on the T2EX pin. Therefore, this mode is called Capture Mode.
Bit EXEN2 is used to enable external trigger.
• If EXEN2=0, external trigger is disabled and Timer 2 is a pure 16-bit timer/counter which, upon overflowing, sets the
Timer 2 overflow flag bit TF2. This flag may then be used to generate an interrupt.
• If EXEN2=1, Timer 2 also operates as a 16-bit timer/counter, but with the additional capability that a High-to-Low
transition at the T2EX input causes the current value in TL2 and TH2 to be captured into SFR RCAP2L and
SFR RCAP2H. The falling transition at T2EX also causes the EXF2 flag bit in T2CON to be set; this flag may also be
used to generate an interrupt. The triggering pulse is also conditioned by the CP/RL2 bit. To enable the capture action,
The CP/RL2 bit must be set to HIGH.
In addition, Timer2 overflow pulse, whose duration is one cycle of Timer 2 clock, can be sent out to Pin 1.0, if T2OE=1.
Fig.21 shows Timer 2, working as a 16-bit Timer/Counter with Capture capability.
XTAL1 Divide-by-12
T2M=0 (CKCON.5)
T2M=1
Divide-by-4 C/T2=0
TR2
falling-edge C/T2=1 (T2CON.2)
P1.0/PWM0/T2 Pin detection
Timer 2 clock
To Pin1.0
SFR TL2 SFR TH2 overflow flag

T2OE
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TF2 (T2MOD.1=1)
(T2CON.7)
Timer 2
capture interrupt
external flag
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
EXF2
(T2CON.6)
P1.1/PWM1/T2EX Pin
falling-edge
Capture/Reload
detection
Selection
EXEN2
(T2CON.3)
CP/RL2 =1
(T2CON.0)
Fig.21 Timer 2 in 16-bit timer/counter mode with capture capability
V1 2008 Jul 09 47
12.5 16-bit Timer/Counter with Auto-Reload capability (Auto-Reload Mode)

When CP/RL2=0, Timer 2 is configured into Auto-reload mode. In the Auto-Reload mode, the Timer 2’s starting value is
reloaded from SFR RCAP2L and SFR RCAP2H.
There are two options selected by the EXEN2 bit in T2CON.
• If EXEN2=0, then, when Timer 2 overflows from FFFFH, it sets the TF2 flag bit and also causes the Timer 2 registers
to be reloaded with the 16-bit value held in SFR RCAP2L and SFR RCAP2H. The 16-bit value held in RCAP2L and
RCAP2H should be pre-loaded by software.
• If EXEN2= 1, Timer 2 operates as described above, but with the additional feature that a High-to-Low transition at the
external input pin T2EX will also trigger the16-bit reload and set the EXF2 flag bit.
In this mode, Timer 2 overflow pulse can also be sent to the P1.0 pin by setting the T2OE bit.
Fig.22 shows Timer 2 configuratin in Auto-reload mode.
XTAL1 Divide-by-12
T2M=0 (CKCON.5)
T2M=1
Divide-by-4 C/T2=0
To Pin1.0
P1.0/PWM0/T2 Pin C/T2=1
T2OE
(T2MOD.1=1)
SFR TL2 SFR TH2 overflow flag (T2CON.7)

bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TF2
TR2
(T2CON.2) Timer 2
interrupt
Reload
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
EXF2
SFR RCAP2H external flag
SFR RCAP2L
(T2CON.6)
P1.1/PWM1/T2EX Pin
falling-edge
detection Capture/Reload
Selection
EXEN2
(T2CON.3)
CP/RL2=0
(T2CON.0)
Fig.22 Timer 2 in auto-reload mode
V1 2008 Jul 09 48
12.6 Baud Rate Generator Mode

When either RCLK=1 or TCLK=1, Timer 2 is a baud rate generator for UART, without regard to the setting of CP/RL2
bit. The overflow pulse from Timer 2, after being divided by a divided-by-16 counter, is used as the trasmitting clock or
receiving clock of the UART in Mode 1 or Mode 3.
The Baud Rate Generator mode is similar to the Auto-Reload mode, in that an overflow of Timer 2 causes Timer 2
registers (SFR TH2 and SFR TL2) to be reloaded with the 16-bit value held in the registers SFR RCAP2H and
SFR RCAP2L, which should be preloaded by software.
As a baud rate generator, Timer 2 counts at a frequency of 1/2 fxtal1, as shown in Fig.23.
Baud rates of the UART in Modes 1 and 3 are determined by the following equation.
f ( XTAL1 )
Baud Rate = Timer 2 overflow rate
-------------------------------------------------------- = -------------------------------------------------------------------------------------------------------- Equation (1)
16 ( 32 ) × [ 65536 – ( RCAP2H ;RCAP2L ) ]
In the above equation, (RCAP2H ; RCAP2L) is the content of registers RCAP2H and RCAP2L taken as a 16-bit unsigned
integer. The 32 in the denominator is the result of the XTAL1 clock being divided by 2 and the Timer 2 overflow rate being
divided by 16. Setting TCLK=1 or RCLK=1 automatically causes the XTAL1 clock to be divided 2.
12.6.1 CALCULATING THE VALUE OF RCAP2H AND RCAP2L FOR A DESIRED BAUD RATE
If a programmer has decided to use a certain baud rate, the required value of RCAP2H and RCAP2L and be derived
from Equation (2), which is re-manipulated from the Equation (1).
XTAL1
( RCAP2H, RCAP2L ) = 65536 – ----------------------------------------- Equation (2)
32 × Baudrate
Table 26 gives calculated value of RCAP2H and RCAP2L for some desired baud rates.
Table 26 Timer 2 reload value for UART Mode 1 and Mode 3 baud rate.
BAUD 33 MHz XTAL1 25 MHz XTAL1 11.0592 MHz XTAL1

C/T2
RATE RCAP2H RCAP2L RCAP2H RCAP2L RCAP2H RCAP2L
57.6 Kb/s 0 FF EE FF F2 FF FA
19.2 Kb/s 0 FF CA FF D7 FF EE
9.6 Kb/s 0 FF 95 FF AF FF DC
4.8 Kb/s 0 FF 29 FF 5D FF B8
2.4 Kb/s 0 FE 52 FE BB FF 70
1.2 Kb/s 0 FC A5 FD 75 FE E0
V1 2008 Jul 09 49
12.6.2 MORE ABOUT TIMER 2

When either RCLK or TCLK is set to logic high, Timer 2 overflow does not set the TF2 bit of SFR T2CON and therefore
will not generate interrupt. Consequently, the Timer 2 interrupt does not need to be disabled when in the baud rate
generator mode.
If EXEN2 is set to HIGH, a HIGH-to-LOW transition on T2EX will set the EXF2 bit of T2CON, but will not cause a reload
from (RCAP2H; RCAP2L) to (TH2; TL2). Therefore, in this mode T2EX may still be used as an additional external
interrupt.
When Timer 2 is operating in the baud rate generator mode, registers SFR TH2 and SFR TL2 should not be accessed.
Because in this mode, the timer is being incremented every two XTAL1 clock and therefore the results of a read or write
may not be accurate. The SFRs RCAP2H and RCAP2L, however, may be read out but not written to. A write might
overlap a reload and cause write and/or reload errors. If a write operation is required, Timer 2 should first be turned off
by clearing the TR2 bit.
V1 2008 Jul 09 50
12.6.3 TIMER 2 IN BAUD RATE GENERATOR MODE

The configuration of Timer 2 in baud rate generator mode is shown in Fig.23.
XTAL1 Divide-by-2
C/T2=0
P1.0/PWM0/T2 Pin C/T2=1
SFR TL2 SFR TH2

Timer 2 overflow pulse
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TR2
(T2CON.2)
Reload
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Timer1
overflow
1⁄2
0 1
SMOD0
RCLK (PCON.7)
1 0
RX CLOCK (baud rate)

TCLK 1 ⁄ 16
1 0
TX CLOCK (baud rate)

1 ⁄ 16
P1.1/PWM1/T2EX Pin
falling-edge Timer 2
detection EXF2
interrupt
external flag
EXEN2 (T2CON.6)
(T2CON.3)
Fig.23 Timer 2 in baud-rate generator mode
V1 2008 Jul 09 51
13 OSCILLATOR
13.1 The Oscillator Circuit
idle
CLK
stop
XTAL1 XTAL2
Note:
C1 C2
1. C1=C2=22P ceramic.
2. R=1M ohm.
Fig.24 Oscillator Circuit.
XTAL1 is the high gain amplifier input, and XTAL2 is the output. To drive the STK6032 externally, XTAL1 is driven from
an external clock source and XTAL2 is left open.
13.2 The values for R, C1, and C2

The recommended values for R, C1, and C2 given Fig.24 is for the frequency range from 2M Hz to 30M Hz.
Since the performance of the crystal oscillator is closely related to the characteristics of the crystal itself, the user should
contact the crystal manufacturer for its characteristics. The crystal parameters we used for design is shown in Fig.25.
The parameter for the crystal is:

R1=10 ohm, C1=25 fF, and
C0=7 pF.
Fig.25 crystal parameters
V1 2008 Jul 09 52
14 INTERRUPTS

The STK6032 support s 6-source, 2-level, 6 vectored-address interrupt system. Interrupts come from the sources listed
below:
• External interrupt 0
• Enternal interrupt 1
• Timer 0 overflow
• Timer 1 overflow
• Timer 2 overflow or External event
• Tranmission or reception of the UART
Each interrupt can be individually enabled or disabled and can be assigned a low-level or high-level priority. All interrupts
can be globally disabled. When an interrupt event occurs, its corresponding interrupt flag is raised to HIGH. This flag
should be cleared by the user interrupt service routine.
In addition to being assigned a low level or a high-level, interrupts within a level have a natural priority level, as shown in
Table 27.
Table 27 gives an overview of the interrupt system.
Table 27 Overview of the interrupt system
Source Interrupt sources Flags generated Interrupt Interrupt Priority within Vector
number by the interrupt enable bit priority bit level Address
1 External Interrupt 0 IE0 (TCON.1) EX0 (IE.0) PX0 (IP.0) 1 (the highest) 0003H
2 Timer 0 Overflow TF0 (TCON.5) ET0 (IE.1) PT0 (IP.1) 2 000BH
3 External Interrupt 1 IE1 (TCON.3) EX1 (IE.2) PX1 (IP.2) 3 0013H
4 Timer 1 Overflow TF1 (TCON.7) ET1 (IE.3) PT1 (IP.3) 4 001BH
5 UART Interrupt TI (SCON0.1) ES (IE.4) PS (IP.4) 5 0023H
(UART receive or RI (SCON0.0)
transmit)
6 Timer 2 overflow TF2 (T2CON.7) EX2 (IE.5) PT2 (IP.5) 6 002BH
T2EX pin EXF2 (T2CON.6)
Note:
1. Because Timer2 overflow and T2EX share the same interrupt vector address 002BH, it is the responsibility of
software programmer to check individual interrupt flag to see which one caused the interrupt.
14.2 Interrupt Enable Registers

Each of the interrupt sources can be individually enabled or disabled by setting its enable/disable bit in the Interrupt
Enable Registers (SFR IE), located at A8 (hex) of the SFR map. All interrupts can be globally disabled by clearing the
EA bit of SFR IE.
The Interrupt Enable Register is described in Table 28 and Table 29.
V1 2008 Jul 09 53
Table 28 Interrupt Enable Register SFR IE
INTERRUPT ENABLE REGISTER ( SFR IE ), LOCATED AT A8H OF THE SFR MAP

Mnemonics EA ET2 ES0 ET1 EX1 ET0 EX0
Reset value 0 0 0 0 0 0 0 0
Table 29 Description of Interrupt Enable Register SFR IE

EA IE.7 Global enable or disable of all interrupts.
When IE.7 = 0, all interrupts are globally disabled.
When IE.7 = 1, all interrupt sources are globaly enabled.
Please refer to Fig.26 for an overview of the interrupt system.
IE.6 Not implemented.
EX2 IE.5 Enable or disable interrupt due to Timer 2 overflow, or T2EX pin (shared with
P1.1) interrupt.
When IE.5 = 1, external interrupt 2 is enabled.
When IE.5 = 0, external interrupt 2 is disabled.
ES0 IE.4 Enable or disable UART interrupt.
When IE.4 = 1, UART interrupt is enabled.
When IE.4 = 0, UART interrupt is disabled.
ET1 IE.3 Enable Timer 1 overflow interrupt.
When IE.3 = 1, Timer 1 overflow interrupt is enabled.
When IE.3 = 0, Timer 1 overflow interrupt is disabled.
EX1 IE.2 Enable External Interrupt 1.
When IE.2 = 1, External Interrupt 1 is enabled.
When IE.2 = 0, External Interrupt 1 is disabled.
ET0 IE.1 Enable Timer 0 overflow interrupt.
When IE.1 = 1, Timer 0 overflow interrupt is enabled.
When IE.1 = 0, Timer 0 overflow interrupt is disabled.
EX0 IE.0 Enable External Interrupt 0.
When IE.0 = 1, External Interrupt 0 is enabled.
When IE.0 = 0, External Interrupt 0 is disabled.
14.3 Interrupt Priority Register SFR IP

Each interrupt source can be assigned one of two priority levels: high and low. Interrupt priority is defined by the Interrupt
Priority Register (SFR IP, at B8 hex of the SFR map), which is described in Table 30 and Table 31.
Interrupt priority levels are as follows:
• logic 0 = low priority
• logic 1 = high priority.
A low priority interrupt may be interrupted by a high priority interrupt. A high priority interrupt cannot be interrupted by any
other interrupt source. If two requests of different priority occur simultaneously, the high priority level request is serviced.
If requests of the same priority are received simultaneously, an internal polling sequence determines which request is
serviced. Thus, within each priority level, there is a second priority structure determined by the polling sequence. This
second priority structure is shown in Table 27.
V1 2008 Jul 09 54
Table 30 Interrupt Priority Register SFR IP
SFR Interrupt Priority Register ( SFR IP ), located at B8 hex of the SFR map
Mnemonics PT2 PS0 PT1 PX1 PT0 PX0
Reset value 1 0 0 0 0 0 0 0
Table 31 Description of Interrupt Priority Register SFR IP

IP.7 not implemented, return a 1 when read.
IP.6 not implemented.
PT2 IP.5 Define the priority of Timer2 overflow interrupt, or T2EX-pin (shared with
P1.1) interrupt.
When IP.5 = 1, Timer 2 overflow is a high priority interrupt.
When IP.5 = 0, Timer 2 overflow is a low priority interrupt.
PS0 IP.4 Define the priority level of UART interrupt.
When IP.4 = 1, UART interrupt is a high priority interrupt.
When IP.4 = 0, UART interrupt is low priority interrupt.
PT1 IP.3 Define the interrupt level of Timer 1 overflow interrupt.
When IP.3 = 1, Timer 1 overflow interrupt is a high priority interrupt.
When IP.3 = 0, Timer 1 overflow interrupt is a low priority interrupt.
PX1 IP.2 Define the interrupt level of External Interrupt 1.
When IP.2 = 1, External Interrupt 1 is a high priority interrupt.
When IP.2 = 0, External Interrupt 1 is a low priority interrupt.
PT0 IP.1 Define the interrupt level of Timer 0 overflow interrupt.
When IP.1 = 1, Timer 0 overflow is a high priority interrupt.
When IP.1 = 0, Timer 0 overflow is a low priority interrupt.
PX0 IP.0 Define the interrupt level of External Interrupt 0.
When IP.0 = 1, External Interrupt 0 is a high priority interrupt.
When IP.1 = 0, External Interrupt 0 is a low priority level.
14.4 Interrupt Vectors

The vector indicates the Program Memory location where the appropriate interrupt service routine starts. Please refer to
Table 27 for interrupt vector addresses.
V1 2008 Jul 09 55
15 OVERALL VIEW OF THE INTERRUPT SYSTEM
High
Priority
Timer0 Overflow TF0
TCON.5 ET0 PT0
IE.1 IP.1 Low
Priority
Timer1 Overflow TF1
TCON.7 ET1 PT1
IE.3 IP.3
Timer2 overflow TF2
T2CON.7 OR
P1.1/PWM1/T2EX
EXF2
T2CON.6 EX2 PX2
EXEN2
IE.5 IP.5
T2CON.3
RI
UART SCON0.0 OR
TI ES PS
SCON0.1 IE.4 IP.4
P3.2/INT0
IE0
IT0 TCON.1 EX0 PX0
TCON.0 IE.0 IP.0
P3.3/INT1
IE1
TCON.3 EX1 PX1
TCON.2 IP.2
IE.7
= Low-level-triggered
= Falling-edge-triggered
Fig.26 Overall view of interrupt system.
V1 2008 Jul 09 56
16 UART0

The UART0 (Universal Asynchronous Receiver/Transmitter) is a full-duplex serial port. The word “full-duplex” means that
it can transmit and receive simultaneously. It has one receiver data pin (RXD) and one transmitter data pin (TXD). The
receiver data pin shares with port pin P3.0 and the transmitter data pin shares with port pin P3.1.
Two SFRs, SFR SCON0 and SFR SBUF0, are associated with the UART0.
• SFR SCON0, at 98H of the SFR memory space, is the control and status register of the UART0.
• SFR SBUF0, at 99H of the SFR memory space, is the data buffer for both transmission and reception.
From software point of view, data transmission and reception are both through the SFR SBUF0. Writing to SFR SBUF0
loads data to be transmitted to SFR SBUF0. Reading SFR SBUF0 reads received data.
But, physically, writing to SFR SBUF0 loads data to a physical Transmit Register and reading SFR SBUF0 reads a
physical Receive Register.
A programmer’s model of the UART0 is shown in Fig.27.
P3.1/TXD SFR SCON0

Full-duplex 8051 CPU
P3.0/RXD UART0
SFR SBUF0
Transmit Register
physical path Receive Register
Fig.27 Programmer’s model of the UART0
V1 2008 Jul 09 57
16.2 Operation modes

UART0 has 4 operation modes:
• Mode 0: 8-bit shift register,
• Mode 1: 10-bit data transmission/reception,
• Mode 2: 11-bit data transmission/reception, and
• Mode 3: 11-bit data transmission/reception.
Table 32 gives detailed description for each of the four operation modes.
The selection of operation modes depends on the setting of the SM0 bit and the SM1 bit of SFR SCON0.
Table 32 UART0 Operation Modes.

Mode SM0 SM1 Description
8-bit serial transmission or reception.
In this mode, 8 bits of data enters or exits through the P3.0/RXD pin. The P3.1/TxD pin
Mode 0 0 0 always outputs the shift clock.
The Least Significant Bit (LSB) is received or transmitted first.
The baud rate is either 1/4 or 1/12 of the XTAL1 frequency.
In this mode, 10 binary bits are transmitted (through P3.1/TXD) or received (through
Mode 1 0 1 P3.0/RXD). The 10 binary bits are composed of a start bit(1), 8 data bits (LSB first), and a
stop bit(1). On reception, the stop bit goes into bit RB8 of the SFR SCON0.
The baud rate comes from Timer 1 or Timer 2 overflow.
In this mode, 11 binary bits are transmitted (through P3.1/TXD) or received ( through
P3.0/RXD). The 11 binary bits are composed of a start bit(1), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit(1).
Mode 2 1 0
On transmission, the 9th data bit (TB8 in SCON0) can be programmed to be 1 or 0. For
example, in application, the parity bit P of SFR PSW can be moved into TB8 of SCON0.
On reception, the 9th data bit goes into RB8 of SFR SCON0, while the stop bit is ignored.
The baud rate is programmable to be 1/32 or 1/64 of XTAL1 frequency.
In this mode, 11 binary bits are transmitted (through P3.1/TXD) or received ( through
P3.0/RXD). The 11 binary bits are composed of a start bit(1), 8 data bits (LSB first), a
Mode 3 1 1 programmable 9th data bit, and a stop bit(1).
Actually, Mode 3 is a combination of Mode 2 protocol and Mode 1 baud rate.
The baud rate in Mode 3 comes from Timer 1 or Timer 2 overflow.
V1 2008 Jul 09 58
16.3 Serial Port Control/Status Register (SFR SCON0)

The Serial Port Control/Status Register is SFR SCON0, located at address 98H of the SFR memory space.
Table 33 Serial Port Control and Status Register (SFR SCON0, 98h)
Mnemonics SM0 SM1 SM2 REN0 TB8 RB8 TI0 RI0
Table 34 Description of SFR SCON0

Mnemonic Bit position Function
SM0 SCON0.7 These two bits are used to select an operation mode.
SM0 SM1 Modes
0 0 Mode 0
SM1 SCON0.6 0 1 Mode 1
1 0 M0de 2
1 1 Mode 3
Multiprocessor Communication Enable.

In Mode 0, SM2 decides the baud rate. When SM2 = 0, the baud rate is fxtal1 /12. When
SM2 = 1, the baud rate is fxtal1 /4.
In Mode 1:
SM2 SCON0.5 • if SM2=1, then RI0 will be set to high only when a HIGH stop bit has been received.
• if SM2=0, then RI0 will always be set to high without regard to the state of the received
stop bit.
In modes 2 and 3, SM2 enables the multiprocessor communication feature. SM2 is used
to disable interrupt to the un-addressed slave receivers, when data bytes are transmitted
from the master.
Reception Enable.
REN0 SCON0.4 When REN0=1, UART0 is enabled for reception.
When REN0=0, UART0 is disabled from reception.
TB8 is the 9th data bit that will be transmitted in Mode 2 or Mode 3. Set or cleared by
TB8 SCON0.3
software as desired.
In Mode 2 and Mode 3, RB8 is the 9th data bit received.
RB8 SCON0.2 In Mode 1, RB8 indicates the state of the received stop bit.
In Mode 0, RB8 is not used.
The Transmit Interrupt Flag. This flag can only be cleared by software.
In mode 0, this bit is set to a logic 1 by hardware at the end of the 8th bit time.
TI0 SCON0.1
In mode 1, mode 2, and mode 3, this bit is set to a logic 1 by hardware at the beginning
of the stop bit time.
The Receive Interrupt Flag. This flag can only be cleared by software.
In mode 0, this bit is set to a logic 1 by hardware at the end of the 8th bit time.
RI0 SCON0.0 In mode 1, this bit is set to logic 1 after the last sampling of the stop bit, subject to the
state of SM2.
In mode 2, and mode 3, this bit is set to a logic 1 by hardware at the last sampling of the
stop bit.
V1 2008 Jul 09 59
16.4 Mode 0
16.4.1 TRANSMISSION AND RECEPTION OF MODE 0

When operating in mode 0, the UART0 is an 8-bit data shift register. Eight bits of data can be shifted into or out from
SFR SBUF0, via the P3.0/RXD pin. The shifting clock always comes out from the P3.1/TXD pin, without regard to if the
data is shifted into or out from SFR SBUF0.
16.4.2 BAUD RATE OF MODE 0

In mode 0, the UART0’s baud rate is either fxtal1 /12 or fxtal1 /4, depending on the value of the SM2 bit. If SM2 = 1, the
baud rate (i.e., shifting clock frequency) is fxtal1 /4. If SM2 = 0, then the baud rate is fxtal1 /12.
16.4.3 TRANSMISSION TIMING OF MODE 0

Data transmission begins when an instruction writes to SFR SBUF0. That is, whenever an instruction with SFR SBUF0
as its destination operand is executed, data transmission will be initiated. The UART0 shifts the data out, LSB first, at the
selected baud rate, until all 8 bits of data have been shifted out.
Write to
SFR BUF0
P3.1/TXD
P3.0/ RXD D0 D1 D2 D3 D4 D5 D6 D7
TI0
RI0 always low
Fig.28 UART0 mode 0 transmission timing when baud rate is XTAL1/4.
16.4.4 RECEPTION TIMING OF MODE 0

To enable data reception, the REN0 bit must first be set to logic HIGH. Data reception begins when the RI0 bit is cleared.
Shifting clock is then sent out from the P3.1/TXD pin to shift in data, LSB first, until all 8 bits of external data have been
shifted in. Each bit of data is shifted in on the rising edge of the shifting clock. Four XTAL1 clocks after the 8th data bit
has been shifted in, the RI0 bit is set to logic HIGH. The RI0=1 indicates that 8 bits of data have been received.
Write to
SFR BUF0
P3.1/TXD
P3.0/RXD D0 D1 D2 D3 D4 D5 D6 D7
RI0
TI0 always low
Fig.29 UART0 mode 0 reception timing when baud rate is XTAL1/4.
V1 2008 Jul 09 60
16.5 Mode 1
16.5.1 OPERATION OF MODE 1

Mode 1 provides 10-bits, asynchronous, full-duplex transmission or reception. One transmission or reception word is
composed of the following bits:
• one start bit,
• eight data bits ( D0~D7 ), and
• one stop bit.
The 10-bits word format is shown below:
START D0 D1 D2 D3 D4 D5 D6 D7 STOP
The data bits are transmitted and received LSB first.

For receive operations, the received stop bit is stored to the RB8 bit of SFR SCON0.

Mode 1 baud rate can be from timer 1 overflow or timer 2 overflow.
Please refer to Section 16.8 “Baud Rate Generation for Mode 1 and Mode 3”
16.5.3 DATA TRANSMISSION TIMING IN MODE 1

A data transmission session in mode 1 involve two steps:
1. Application program issues a write to SFR SBUF0,
2. Transmission begins immediately after the first overflow of the divided-by-16 counter of the Baud Rate Generation
circuit (please refer to Fig.34).
3. The UART0 transmits data out from the P3.1/ TXD pin in the following order: START bit, data bits (D0~D7), and
STOP bit. The START bit is transmitted out first. The TI0 (SCON0.1) bit of SFR SCON0 is set to HIGH two XTAL1
clocks after the stop bit has been transmitted.
TX CLK
internal shift clock
P3.1/TXD START D0 D1 D2 D3 D4 D5 D6 D7 STOP
always high
P3.0/RXD
TI0
RI0 always low
Fig.30 UART0 mode 1 transmission timing
V1 2008 Jul 09 61
16.5.4 DATA RECEPTION TIMING IN MODE 1

A data reception session in mode 1 is as follows:
1. First, the reception function of the UART0 must be enabled by setting REN0=1 and then the UART0 starts detecting
if there is a falling edge on the P3.0/RXD input. For detecting this falling edge, UART0 samples the P3.0/RXD input
pin sixteen times per bit time for any baud rate.
2. When a falling edge on the P3.0/RXD pin is detected, the divided-by-16 counter of the baud rate generation circuit
is reset. The output of the divided-by-16 counter is the receiver clock, RX CLK. This action is for aligning Timer 1 or
Timer 2 overflow to bit boundaries. Please refer to Fig.34 for baud rate generation circuit.
3. For noise rejection, the UART0 decides the value of each received bit by majority decision of three consecutive
samples in the middle of each bit time. That is, if three consecutive sampled values are 110, then the received bit
value is regarded as HIGH. Similarly, if three consecutive sampled values are 101, then the received bit value is still
regarded as HIGH.
4. If the first received bit is not LOW, then the reception session is aborted and the UART0 waits for another falling edge
on the P3.0/RXD pin.
5. If the first received bit is LOW, then a reception session is initiated and the UART0 continues to receive the following
data bits (D0~D7). The bit value is decided by use of majority decision.
6. At the middle of the stop bit time, the UART0 checks the following conditions:
a) RI0 must be LOW,
b) if SM2 has been programmed to HIGH, then the received stop bit must also be HIGH. (If SM2 has been
programmed to LOW, the received stop bit can be LOW or HIGH.)
7. If the above conditions are met, then the UART0 moves the received data byte from the temporary Receive Register
(please refer to Fig.27) to SFR SBUF0, moves the received stop bit to the RB8 bit of SFR SCON0, and set RI0 bit to
HIGH, triggering an UART0 data reception interrupt. If the above conditions are not met, the received data is ignored
and the receive session is aborted.
8. After the middle of the stop bit time, the UART0 continues to wait for another high-to-low transition on the
P3.0/RXD pin.
RX CLK
(baud rate)
P3.0/RXD START D0 D1 D2 D3 D4 D5 D6 D7 STOP
Bit sampling
Data shift in clk

always high
P3.1/TXD
RI0
TI0 always low
Fig.31 UART0 mode 1 reception timing
V1 2008 Jul 09 62
16.6 Mode 2

Mode 2 provides 11-bits, asynchronous, full-duplex transmission or reception.
A transmission or reception word is composed of the following 11 bits:
• one start bit,
• eight data bits,
• one programmable 9th bit, and
• one stop bit.
The word format is shown below:
START D0 D1 D2 D3 D4 D5 D6 D7 TB8/RB8 STOP

For transmission, the 9th bit is determined by the value in TB8. To use the 9th bit as a parity bit, move the value of the
P bit of SFR PSW to TB8.

In Mode 2, the baud rate is decided by the value of the SMOD0 bit in the SFR PCON ( please refer to Table 36 ).
• If SMOD0=0, the default value of SMOD0 after reset, the baud rate is fxtal1 /64. That is, the duration of a bit time is 64
XTAL1 clocks.
• If SMOD0=1, the baud rate is fxtal1 /32. That is, the duration of a bit time is 32 XTAL1 clocks.
V1 2008 Jul 09 63
16.6.3 DATA TRANSMISSION TIMING IN MODE 2

A data transmission session in mode 2 involves the following steps:
1. Application program issues a write to SFR SBUF0,
2. Transmission begins immediately after the first overflow of the divided-by-16 counter of the Baud Rate Generation
circuit (please refer to Fig.34).
3. The UART0 transmits data out from the P3.1/ TXD pin in the following order: START bit, data bits (D0~D7), and
STOP bit. The START bit is transmitted out first.
4. The TI0 (SCON0.1) bit of SFR SCON0 is set to HIGH when the stop bit is placed on the P3.1/TXD pin.
Write to
SFR BUF0
TX CLK
Data shift out clk
P3.1/TXD START D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP
P3.0/ RXD always high
TI0
RI0 always low
Fig.32 UART0 mode 2 transmission timing
V1 2008 Jul 09 64
16.6.4 DATA RECEPTION TIMING IN MODE 2

A data reception session in mode 2 is as follows:
1. First, the reception function of the UART0 must be enabled by setting REN0=1 and then the UART0 starts detecting
if there is a falling edge on the P3.0/RXD input. For detecting this falling edge, UART0 samples the P3.0/RXD input
pin sixteen times per bit time for any baud rate.
2. When a falling edge on the P3.0/RXD pin is detected by UART0, the divided-by-16 counter of the baud rate
generation circuit is reset. The output of the divided-by-16 counter is the receiver clock, RX CLK. This action is for
aligning Timer 1 or Timer 2 overflow to bit boundaries. Please refer to Fig.34 for baud rate generation circuit.
3. For noise rejection, the UART0 decides the value of each received bit by majority decision of three consecutive
samples in the middle of each bit time. That is, if three consecutive sampled values are 110, then the received bit
value is regarded as HIGH. Similarly, if three consecutive sampled values are 101, then the received bit value is still
regarded as HIGH.
4. If the first received bit is not LOW, then the reception session is aborted and the UART0 waits for another falling edge
on the P3.0/RXD pin.
5. If the first received bit is LOW, then a reception session is initiated and the UART0 continues to receive the following
data bits (D0~D7). The bit value is decided by use of majority decision.
6. At the middle of the stop bit time, the UART0 checks the following conditions:
a) RI0 must be LOW,
b) if SM2 has been programmed to HIGH, then the received 9th bit must also be HIGH. (If SM2 has been
programmed to LOW, the received 9th bit can be LOW or HIGH.)
7. If the above conditions are met, then the UART0 moves the received data byte from the temporary Receive Register
(please refer to Fig.27) to SFR SBUF0, moves the received 9th bit to the RB8 bit of SFR SCON0, and set RI0 bit to
HIGH, triggering an UART0 data reception interrupt. If the above conditions are not met, the received data is ignored
and the receive session is aborted.
8. After the middle of the stop bit time, the UART0 continues to wait for another high-to-low transition on the
P3.0/RXD pin.
RX CLK
P3.0/RXD START D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP
Bit sampling
Data shift in clk

always high
P3.1/TXD
RI0
TI0 always low
Fig.33 UART0 mode 2 reception timing
V1 2008 Jul 09 65
16.7 Mode 3

Mode 3 provides 11-bits, asynchronous, full-duplex transmission or reception. Its transmission or reception word format
is composed of:
• one start bit,
• eight data bits,
• one programmable 9th bit, and
• one stop bit.
The word format is shown below. It is actually identical to that of Mode 2.
START D0 D1 D2 D3 D4 D5 D6 D7 TB8/RB8 STOP

Mode 3 operation is actually identical to Mode 2 operation, except baud rate. The Mode 3 baud rate generation is
identical to Mode 1. That is, Mode 3 is a combination of Mode 2 transmission/reception protocol and Mode 1 baud rate
generation.

Mode 3 baud rate can be from timer 1 overflow or timer 2 overflow. Please refer to Section 16.8 “Baud Rate Generation
for Mode 1 and Mode 3”
16.7.3 DATA TRANSMISSION IN MODE 3

Please refer to the description for mode 2.
16.7.4 DATA RECEPTION IN MODE 3

Please refer to the description for mode 2.
V1 2008 Jul 09 66
16.8 Baud Rate Generation for Mode 1 and Mode 3

In both Mode 1 and Mode 3, baud rate is derived from Timer 1 or Timer 2 overflow. Fig.34 gives the divider circuit used
to derive receiver baud rate and transmitter baud rate from Timer 1 overflow or Timer 2 overflow.

Note:
1⁄2
• RCLK = T2CON.5
0 1 • TCLK = T2CON.4
SMOD0
RCLK (PCON.7)
1 0
RX CLOCK (baud rate)

TCLK 1 ⁄ 16
1 0
TX CLOCK (baud rate)

1 ⁄ 16
Fig.34 baud rate generation from Timer 1 or Timer 2 overflow
16.8.1 USING TIMER 1 TO GENERATE BAUD RATES

When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1
overflow rate and the value of the SMOD0 bit of the SFR PCON, as follows:
SMOD
2
Baud rate = ----------------------
32
× Timer1 overflow rate
The Timer 1 interrupt should be disabled in this application.

The Timer 1 itself can be programmed for either timer or counter operation in any of its 3 running modes. In most typical
applications, it is programmed for timer operation, in the Auto-Reload mode (high nibble of TMOD=0010B). In this case
the baud rate is given by the formula:
SMOD
2 1
Baud rate = --------------------- × XTAL1 × ----------------------------------------------------
32 [ 12 × ( 256 – TH1 ) ]
By programming Timer 1 to run as a 16-bit timer (high nibble of TMOD=0001B), and using the Timer 1 interrupt to do a
16-bit software reload, very low baud rate can be achieved
Table 35 lists sample reload values for a variety of common serial port baud rate.
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Table 35 Timer 1 reload value for UART0 Mode 1 and Mode 3 baud rate.
Desired Baud SMOD0 C/T2 Timer 1 33 MHz 25 MHz 11.0592 MHz

rate (PCON.7) (TMOD.6) Mode XTAL1 XTAL1 XTAL1
57.6 Kb/s 1 0 2 FDh FEh FFh
19.2 Kb/s 1 0 2 F7h F9h FDh
9.6 Kb/s 1 0 2 EEh F2h FAh
4.8 Kb/s 1 0 2 DCh E5h F4h
2.4 Kb/s 1 0 2 B8h CAh E8h
1.2 Kb/s 1 0 2 71h 93h D0h
16.8.2 USING TIMER 2 TO GENERATE BAUD RATES

Please refer to Section 12.6 “Baud Rate Generator Mode” for detailed description of using Timer 2 to generate baud rate
for the UART0.
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16.9 Multiprocessor communications

Mode 2 supports multiprocessor communication, in which a master transmitter can send data to one or more slave
receivers. The 9th data bit is used to indicate an address byte or data byte. When the 9th data bit is HIGH, the transmitted
byte is an address byte. When the 9th data bit is LOW, the transmitted byte is a data byte.
1 2 3 4 5 6 7 8 9
D0 D1 D2 D3 D4 D5 D6 D7 address/
START data STOP
Fig.35 word format for multiprocessor communication
Master Slave Slave Slave

Transmitter Receiver Receiver Receiver
TX RX TX RX TX RX TX RX
Fig.36 UART0 multiprocessor communication
A typical session of multiprocessor communication is as follows:
1. Enable all slave receivers for reception by setting REN=1 and clearing RI=0.
2. Setting SM2=1 for all slave receivers. SM=1 indicates that only an address byte, which has its 9th data bit set to
HIGH, can be received by all slave receivers.
3. The master transmitter broadcasts an address byte out.
4. All the UART0s of all slave receivers receive this address byte and interrupt their respective CPU.
5. All slave receivers execute their UART0 interrupt subroutine.
6. In the interrupt subroutine, the received address is compared with the slave’s pre-assigned address. If the two
addresses match, then the SM2 bit is cleared to LOW. SM2=LOW indicates that the 9th bit data bit can be LOW or
HIGH. That is, the addressed slave can always receive next transmitted data bytes from the master transmitter.
7. If the received address does not match with the slave’s own pre-assigned address, the slave keeps its SM2 bit set
to HIGH, indicating that the slave will not be able to received the next transmitted data bytes.
8. A communication channel is therefore established between the master transmitter and the addressed slave receiver.
The master can continue to send data bytes to the addressed slave receiver. All other un-addressed slave receivers
can not receive the following data bytes, because their SM2 bits remain at HIGH.
9. Once the entire message has been received, the addressed slave sets its SM2 bit to HIGH to block further interrupt
and waits for the next address byte.
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17 POWER-SAVING MODES
The STK6032 provides two power-saving modes: Idle mode and Stop mode. The bits that control entry into Idle mode
and Stop modes are bits 0 (Idle mode) and bit 1 (Stop mode) of the Power Control Register (SFR PCON) at SFR
adddress 87(hex). Table 36 gives a description of the Power Control Register (SFR PCON).
Table 36 Power Control Register, SFR PCON at address 87(hex) of the SFR map
Bit Mnemonics Function
PCON.7 SMOD0 UART baud-rate doubler enable.
When SMOD0=1, the baud rate for the UART is doubled.
PCON. 6~4 Reserved.
PCON.3 GF1 General purpose flag 1.
Bit-addressable, general-purpose flag for software control.
PCON.2 GF0 General purpose flag 0.
Bit-addressable, general-purpose flag for software control.
PCON.1 STOP STOP mode select.
Setting the STOP=1 places the STK6032 in STOP mode.
PCON.0 IDLE IDLE mode select.
Setting the IDLE=1 places the STK6032 in IDLE mode.
If the STOP Mode and the Idle Mode are selected at the same time, the STOP Mode has higher priority, as can be
obviously seen in Fig.37
XTAL2 XTAL1
OSC
interrupts,
Clock
serial port,
timers
Generator
CPU
STOP
IDLE
Fig.37 Power-saving modes.
17.1 Idle Mode

Idle mode operation permits the interrupt, serial ports and timers to function while the CPU is halted. The functions that
are switched off when the microcontroller enters the Idle mode are:
• CPU (halted)
The functions that remain active during Idle mode are:
• Timer 0, Timer 1, Timer 2, and Watchdog Timer
• UART
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• External/Internal interrupts
• External reset or power-on-reset.
The instruction that sets PCON.0 (=1) is the last instruction executed in the normal operating mode before Idle mode is
activated.
Once in the Idle mode, the CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status
Word, Accumulator, RAM and all other registers maintain their current data during Idle mode. The status of external pins
during Idle mode is shown in Table 37.
There are three ways to terminate the Idle mode:
• Activation of any enabled interrupt from interrupt sources listed in Table 27 will cause PCON.0 to be cleared by
hardware, terminating Idle mode, but only if there is no interrupt in service with the same or higher priority. The interrupt
is serviced, and following return from interrupt instruction RETI, the next instruction to be executed will be the one
which follows the instruction that wrote a logic 1 to PCON.0.
The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or
during Idle mode.
For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits.
When Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits.
• The second way of terminating the Idle mode is with an external hardware reset. Since the oscillator is still running,
the hardware reset is required to be active for two instruction cycles to complete the reset operation.
• The third way of terminating the Idle mode is by internal watchdog reset.
17.2 Stop mode

The instruction that sets PCON.1 is the last executed, prior to going into the Stop mode. Once in Stop mode, the crystal
oscillator is stopped. The contents of the on-chip RAM (AUX Memory and Main Data Memory) and the SFRs are
preserved.
Note that the Stop mode can not be entered when the Watchdog Timer has been enabled.
The Stop mode can be terminated only by an external reset (RAM is saved, but SFRs are cleared due to reset).
The status of the external pins during Stop mode is shown in Table 37.
In the Stop mode, Vdd supplies to the CPU can be reduced to minimize power consumption. It must be ensured,
however, that Vdd is not reduced before the Stop mode is activated, and that the Vdd is restored to its normal operating
level before the Stop mode is terminated by hardware reset. The reset signal that terminates the Stop mode also restarts
the oscillator.The reset signal should not be activated before Vdd is restored to its normal operating level and must be
held active long enough to allow the oscillator to restart and stabilize( similar to power-on reset).
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17.3 Status of external pins during power-saving modes
Table 37 Status of external pins during Idle and Stop modes.

MODE Memory ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4
internal 1 1 port data port data port data port data port data
Idle
external 1 1 high-Z port data address port data port data
internal 0 0 port data port data port data port data port data
Stop
external 0 0 high-Z port data port data port data port data
17.4 Summary of Power-saving Modes
Table 38 .Summary of power-saving modes

Example for enabling
MODE TERMINATED BY REMARKS
the mode
• Enabled interrupt • CPU is gated off
• External hardware reset • CPU status registers maintain their data.
Idle ORL PCON, #01H
• Watchdog Timer • Peripherals are active.
overflow.
• Crystal oscillator is stopped.
• Contents of on-chip RAM and SFRs are
Stop ORL PCON, #02H External hardware reset maintained.
• However, leaving Power- Down mode
means redefinition of SFR contents.
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18 WATCHDOG TIMER
18.1 Functional Block Diagram

The Watchdog Timer is used to reset the STK6032 when it enters into an erroneous state, possibly due to disturbance
from external world.
Only one SFR (SFR WDT), at SFR map address E1hex) is associated with the Watchdog Timer.
Fig.38 gives the functional block diagram of the Watchdog Timer.
XTAL1
multiplexer
divided by 3 CPU CLK
X2
CPUCLK
CPURATE
÷ 256 3-bit
÷ 10000 Programmable RESET
Counter
CPU CLK
WDT0
EWDT WDTCLR
WDT1
WDT2
Assuming that XTAL1= 24 MHz and CPU CLK is programmed to be equal to XTAL1,
then the Watchdog Timer overflow period ∆t can be calculated from the following
equation. Please also refer to Table 40.
1
∆t = N × ------------ × 256 × 10000
24M
Fig.38 Watchdog Timer.
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18.2 Watchdog Timer Control Register

The Watchdog Timer Control Register (SFR WDT) is the only SFR associated with the Watchdog Timer. It can be written
to or read from, and is described in Table 39.
Table 39 Watchdog Timer Register
WATCHDOG TIMER REGISTER, SFR WDT, AT E1 (HEX) OF THE SFR MAP

Mnemonics EWDT WDTCLR not implemented WDT2 WDTI WDT0
RESET value 0 0 x 0 0 0
Table 40 Description of SFR WDT
MNEMONIC FUNCTION
EWDT (bit 7) Enable Watchdog Timer.
Setting EWDT=1 enables the Watchdog Timer. Setting EWDT=0 disables the Watchdog Timer.
WDTCLR (bit 6) Setting WDTCLR= 1 clears the Watchdog Timer Programmable Counter and the
divided-by-10000 prescaler.
The Watchdog Timer must be regularly cleared before it overflows.
WDT2, WDT1, These 3 bits decides the overflow period of the Watchdog Timer. The following table gives the
WDT0 (bits 2, 1, 0) overflow period versus the values of these 3 bits, assuming that XTAL1=24 MHz and CPU CLK
is programmed to be equal to XTAL1.
WDT2 WDT1 WDT0 Overflow interval Notes

0 0 0 8 x 0.107 seconds Assuming
0 0 1 1 x 0.107 seconds XTAL1=24 MHz and
CPU CLK is
0 1 0 2 x 0.107 seconds
programmed to be equal
0 1 1 3 x 0.107 seconds to XTAL1
1 0 0 4 x 0.107 seconds
1 0 1 5 x 0.107 seconds
1 1 0 6 x 0.107 seconds
1 1 1 7 x 0.107 seconds
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19 PWM (PULSE WIDTH MODULATED OUTPUT)
19.1 General description

The STK6032 contains 5 Pulse Width Modulated (PWM) outputs. These PWMs generate pulses of programmable length
within an interval of 256 CPU clocks.
Six SFRs are associated with the PWM. They are listed in Table 41.
Table 41 SFRs for PWM
Address(Hex
SYMBOL DESCRIPTION RESET VALUE
format)
P1_OTP Port 1 pin selection for PWM output or Port 1 one pin output. D1 xxx0 0000
When a PWM register (PWM0D ~ PWM4D) is loaded with a new value, the associated output is updated immediately. It
does not have to wait until the end of the current counter period. All PWMn output pins are driven by push-pull output
drivers.
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Fig.39 gives functional diagram of the PWM.
Pulse Width Register

(SFR PWM0D)
P1.0/PWM0
8-bit comparator output port
8-bit counter

(SFR PWM1D)
P1.1/PWM1
8-bit counter

(SFR PWM2D)
CPU_CLK P1.2/PWM2
Divided by 256 8-bit comparator output port
8-bit counter

(SFR PWM3D)
P1.3/PWM3
8-bit counter

(SFR PWM4D)
P1.4/PWM4
8-bit counter
Fig.39 PWM functional block diagram
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19.2 Port 1 Option Register (SFR P1_OPT)

The SFR P1_OPT is used to configure Port 1 pins to be Port 1 I/O pins or PWM output pins.
Table 42 Port 1 Option Register(address D1H)

Bit position 7 6 5 4 3 2 1 0
Mnemonics PWM4E PWM3E PWM2E PWM1E PWM0E
Reset value x x x 0 0 0 0 0
Table 43 Description of SFR P1_OPT bits

BIT SYMBOL DESCRIPTION
7, 6, 5 not implemented
4 to 0 PWM4E to PWM0E These bits are used to configure Port 4 pins to be an I/O pin or PWM
output pin.
When PWM4E=0, the P1.4/PWM4 pin works as an I/O pin.
When PWM4E=1, P1.4/PWM4 pin works as PWM 4 output pin.
Other bits can be configured in the same way.
19.3 Pulse Width Register 0 ~ 4 (PWM0D ~ PWM4D)
Table 44 Pulse width register (address D2 ~ D6 hex, R/W)

Register Address
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Name (hex)
PWM0D D2 Pulse width of PWM channel 0.
Reset
1 0 0 0 0 0 0 0
value
The value of a Pulse Width Register indicates the HIGH pulse width within an interval of 256 CPU clocks, as illustrated
in Fig.40.
0 1 2 3 127 128 254 254 255 0 1 2

CPU CLK
PWM interval
PWM SFR=1
PWM SFR=254
programmed value
Fig.40 value of a PWM SFR and the pulse width
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20 ANALOG-TO-DIGITAL CONVERTER (ADC)
20.1 ADC functional description

The STK6032 has a 6-bit successive approximation ADC, with 6 multiplexed analog input channels. ADC channel inputs
share Port 4 pins. Pins P4.0 ~ P4.5 can be programmed to be either as Port 4 pins or ADC analog input pins. Analog
input voltage range for each pin can be from 0 V to 5.0 V.
Three SFRs (P4_OPT, ADCSEL, and ADCVAL) perform the user software interface to the ADC; see Table 45 for an
overview of the ADC SFRs.
Figure 41 shows the relation between SFRs and the ADC.
P4.5/ADC5 enable ADC
P4.4/ADC4
P4.3/ADC3
SFR ADCSEL
SFR ADCVAL
SFR P4_OPT
P4.2/ADC2
6-bit ADC
P4.1/ADC1
P4.0/ADC0
Fig.41 ADC SFRs
20.2 ADC during Idle and Stop mode

The analog-to-digital converter is active only when the microcontroller is in normal operating mode. If the Idle or
Stop mode is activated, then the ADC is switched off and put into a power saving idle state - a conversion in progress is
aborted. The conversion result register (SFR ADCVAL) is not affected.
20.3 ADC SFRs and their reset value

Three SFRs (P4_OPT, ADCSEL, and ADCVAL) are associated with ADC. An overview of these three registers is given
in Table 45.
Table 45 ADC Special Function Registers overview

ADDRESS NAME R/W DESCRIPTION
D9(hex) P4_OPT R/W Selection of Port 4 pin function.
DA(hex) ADCSEL R/W Channel selection.
DB(hex) ADCVAL R/W ADC value.
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20.3.1 P4_OPT REGISTER

The P4_OPT SFR has only 6 bits. It is used to configure Port 4 pins to be a port I/O pin or an analog input pin for the
6-bit ADC.
Table 46 P4_OPT register (address D9 hex)
Bit Number BIT 7 BIT 6 BIT 5 BIT 5 BIT 3 BIT 2 BIT 1 BIT 0
Bit Name not implemented ADC5E ADC4E ADC3E ADC2E ADC1E ADC0E
Rest Value x x 0 0 0 0 0 0
Table 47 Description of P4_OPT Register bits

BIT SYMBOL Description
ADC5E=1 configures pin P4.5/ADC5 as an analog input pin.
5 ADC5E
ADC5E=0 configures pin P4.5/ADC5 as a port pin (P4.5)
4 ADC4E
3 ADC3E
2 ADC2E
1 ADC1E
0 ADC0E
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20.3.2 THE ADCSEL REGISTER

The ADCSEL Register is used to select an input channel for conversion. For proper conversion of the input analog
voltage, do the following:
1. Select a channel for analog signal input,
2. Then, enable the ADC by setting the EADC bit to HIGH.
Table 48 ADCSEL Register (address DA hex)

Bit Number BIT 7 BIT 6 BIT 5 4 BIT BIT 3 BIT 2 BIT 1 BIT 0
Bit Name EADC x SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
Reset Value 0 x 0 0 0 0 0 0
Table 49 Description of ADC Register bits

BIT SYMBOL DESCRIPTION
7 EADC Enable the ADC.
6 not implemented
SADC5=1 selects analog signal from P4.5/ADC5 pin for conversion.
5 SADC5
SADC5=0 un-selects this pin.
4 SADC4
SADC4=0 un-selects this pin for conversion.
3 SADC3
SADC3=0 un-selects this pin.
2 SADC2
1 SADC1
0 SADC0
20.3.3 ADCVAL REGISTERS

The binary result code of the analog-to-digital conversions is stored in the ADCVAL Register.
Table 50 ADCVAL Register (address DB hex)

Bit
BIT 7 BIT 6 BIT 5 4 BIT BIT 3 BIT 2 BIT 1 BIT 0
Number
Bit Name x x Binary code of the ADC coversion.
Reset
x x 0 0 0 0 0 0
Value
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20.4 ADC resolution and characteristics

The analog input voltage should be stable when the ADC is enabled to perform conversion. An RC low pass filter may
be added to the analog input pins to filter out high frequency noises.The capacitor between an analog input pin and the
ground pin shall be placed as close to the pins as possible, in order to have maximum effect in minimizing input noise
coupling.
Fig.42 gives the converted digital value (given in decimal unit) versus input analog voltages. The X-coordinate is the input
voltage and the Y-coordinate is the output code.
ADC0 ADC1 ADC2 ADC3
70
60
50
40
30
20
10
0
0.03
0.34
0.64
0.95
1.25
1.56
1.87
2.18
2.49
2.8
3.11
3.42
3.73
4.04
4.35
4.66
Fig.42 Converted digital code versus analog input voltage.
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21 PIN CIRCUITS
21.1 Port 0 (P0.0 ~ P0.7) circuit (Bidirectional Input/Output)
Output_enable
Port 0 pins are push-pull
Data_out outputs. The output
Output
sinking and sourcing
capability is 4 mA (typ.).
Input_enable
Data_in
Fig.43 Port 0 pad
21.2 Port 1 (P1.0 ~ P1.7), Port 2 (P2.0 ~ P2.7), Port 3 (P3.0 ~ P3.7) circuit (Bidirectional I/O, with weak Pull-up)
VDD
Pins of Port 1, Port 2, and
Port 3 are push-pull outputs
Pull-up
with weak internal pull-up. The
output sinking and sourcing
Output_enable
capability is 4 mA (typ.). The
typical value of the equivalent
Data_out Output resistance of the pull-up PMOS
is 15K ohm.
Input_enable
Data_in
Fig.44 Pad of Port 1, Port 2, and Port 3
21.3 ALE and PSEN (Output)
Data_out Output
Fig.45 Pad for ALE and PSEN..
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21.4 EA (Input), with weak internal pull-up PMOS
VDD
Note: This pin is weakly
pulled up.
Data_in Input (EA)
Fig.46 EA pad
21.5 RST (Input), with weak internal pull-low NMOS.
Data_in Input (RST)

Note: This pin is weakly
pulled down.
VDD
VSS
Fig.47 RST pad
21.6 XTAL1, XTAL2
STOP
XTAL2
Please refer to Fig.24 for
detail.
IDLE
CLK XTAL1
Fig.48 XTAL1, XTAL2 pads
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21.7 Port 4 (P4.0/ADC0, P4.1/ADC1, P4.2/ADC2, P4.3/ADC3, P4.4/ADC4, P4.5/ADC5)
VDD Weak pull-up PMOS must be

turned off when used as ADC
SFR P4_OTP input.
Output_enable
Data_out Output
Input_enable
Data_in
Analog_In
ESD
Fig.49 Port 4 pad
V1 2008 Jul 09 84
22 ABSOLUTE MAXIMUM RATING
Table 51 Absolute Maximum Rating

SYMBOL PARAMETER MIN. MAX. UNIT
VDD voltage on VDD with respect to ground, and SCL, SDA to −0.3 +5.8 volts
ground.
VI (note 1) input voltage on any other pin with respect to ground. −0.3 VDD + 0.3 volts
II, IO input/output current on any I/O pin − ±15 mA
Itotal Absolute sum of all input currents during overload 100 mA
condition.
Ptot total power dissipation (note 2) − 1.5 W
Tstg storage temperature range −25 +125 °C
Tamb operating ambient temperature range. -40 + 85 °C
Notes
1. The following applies to the Absolute Maximum Ratings:
a) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only and functional operation of the device should refer to the normal DC and AC characteristics.
b) This product includes ESD-protection circuits, specifically designed for the protection of its internal circuit.
However, its suggested that conventional ESD precautions be taken.
c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect
to ground.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package, not on
device power consumption.
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23 DC/AC CHARACTERISTICS
Test condition: VDD = 5.0 V ±10%; VSS = 0 V; all voltages with respect to VSS , unless otherwise specified;
Tamb = -40 to +85 °C; fXTAL1 = 24 MHz.
Table 52 DC/AC Characteristics
SYMBOL PARAMETER CONDITIONS MIN. TYP MAX. UNIT

General
VDD Operating supply voltage. 4.5 5.5 V
Toperating Operating temperature range -40 +85 °C
Foperating Operating frequency range 4 MHz 24 MHz 30 MHz
IDD(NORMAL) Operating supply current in normal notes 1, 2
6.4 mA
mode, at CPU CLK= 12 MHz. and 3
IDD(NORMAL) Operating supply current in normal notes 1, 2
9.4 mA
mode, at CPU CLK= 27 MHz. and 3
IDD(IDLE) Supply current in Idle mode,at notes 1 ,2
3.6 mA
CPU CLK= 12 MHz. and 3
IDD(STOP) Supply current in Stop mode. notes 1 ,2
4.5 µA
and 3
Current sourcing/sinking capability of Ports 0, 1, 2, 3, 4, at VDD=5.0 volts
IP0_sink The open-drain NMOS sinking
19 mA
current of Port 0.
IP1_source The PMOS sourcing current of
170 µA
Port 1.
IP1_sink The NMOS sinking current of
19 mA
Port 1.
170 µA
Port 2.
19 mA
Port 2.
170 µA
Port 3.
19 mA
Port 3.
170 µA
Port 4.
19 mA
Port 4.
Current sourcing/sinking capability of the ALE pin and the PSEN pin, at VDD=5.0 volts
IALE_source The PMOS sourcing current of the 4 mA
ALE pin.
IALE_sink The NMOS sinking current of the 4 mA
ALE pin.
IPSEN_source The PMOS sourcing current of the 4 mA
PSEN pin.
IPSEN_sink The NMOS sinking current of the 4 mA
PSEN pin.
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SYMBOL PARAMETER CONDITIONS MIN. TYP MAX. UNIT

Inputs HIGH/LOW voltage, Output HIGH/LOW voltage at VDD=5.0 volts.
VOL_P0 Output LOW voltage of Port 0. IOL = 3.2 mA; 0.144 volts
note 5
VIL Input LOW voltage to Port 0, Port 1, 1.8 volts
Port 2, Port 3, and Port 4.
VIH Input HIGH voltage to Port 0, 2.3 volts
Port 1, Port 2, Port 3, and Port 4.
VOL Output LOW voltage of Port 1, IOL = 3.2 mA; 0.2 volts
Port 2, Port 3, and Port 4. note 5
VOH Output HIGH voltage of Port 0, IOH = -25 µA 4.8 volts
Port 1, Port 2, Port 3 and Port 4.
VIH_RST Input HIGH voltage to RESET pin. 2.54 volts
VIL_RST Input LOW voltage to RESET pin. 2.15 volts
VOL_ALE Output LOW voltage of ALE pin. IOL = 3.2 mA;
note 5
VOH_ALE Output HIGH voltage of ALE pin. IOH = -60 µA
VOL_PSEN Output LOW voltage of PSEN pin. IOL = 3.2 mA;
note 5
VOH_PSEN Output HIGH voltage of PSEN pin. IOH = -60 µA
CI/O I/O pin capacitance test − 10 pF
frequency = 1
MHz;
Tamb = 25 °C
Notes to the DC characteristics
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with
tr = tf = 5ns; VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; Port 0 = VDD; EA = VSS.
2. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns;
VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2 not connected; EA = Port 0 = VDD.
3. The Stop current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = VDD;
EA = XTAL1 = VSS.
4. Pins of Ports 1, 2, 3, and 4 source a transition current when they are being externally driven from HIGH to LOW. The
transition current reaches its maximum value when VIN is approximately 1.6 V.
5. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make
HIGH-to-LOW transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on
the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an
address latch with a Schmitt Trigger STROBE input.
6. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD ;
VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2 not connected; Port 0 = VDD; EA = XTAL1 = VSS.
V1 2008 Jul 09 87
24 EXTERNAL PROGARM MEMORY READ CYCLE
1 2 3 4
CPU CLK
Memory address
ALE
PSEN
Port 2 high byte address
low byte program ROM data

Port 0 address
Note:
For external program ROM read, the EA input pin
must be conntected to LOW before Power-On-Reset.
Fig.50 External program memory read cycle
Draft 2008 Jul 09 88

25 EXTERNAL AUX MEMORY READ/WRITE TIMING WITH STRETCH= 0
25.1 External AUX Memory Read timing with stretch= 0

25.2 External AUX Memory Write with stretch= 0

25.3 External AUX memory READ timing with Stretch= 1

25.4 External AUX memory write timing with stretch= 1

25.5 External AUX memory Write timing with Stretch= 2

26 INSTRUCTION SET
The STK6032’s instruction set is binary-code-compatible with industrial standard 80C51. It consists of 49 single byte,
45 two byte and 17 three byte instructions. Using a 16 MHz crystal, 64 of the instructions are executed in 200 ns, 45 in
375 ns and the multiply, divide instructions in 750 ns.
A summary of the instruction set is given in Table 54, Table 55, Table 56, Table 57 and Table 58.
26.1 Addressing modes

Most instructions have a destination, source field that specifies the data type, addressing modes and operands involved.
For all these instructions, except for MOVs, the destination operand is also the source operand (e.g. ADD A,R7).
There are five kinds of addressing modes:
• Register Addressing
– R0 to R7 (4 banks)
– A,B,C (bit), AB (2 bytes), DPTR (double byte)
• Direct Addressing
– lower 128 bytes of internal main RAM (including the four R0 to R7 register banks)
– Special Function Registers
– 128 bits in a subset of the internal main RAM
– 128 bits in a subset of the Special Function Registers
• Register-Indirect Addressing
– internal main RAM (@R0, @R1, @SP [PUSH/POP])
– internal auxiliary RAM (@R0, @R1, @DPTR)
– external auxiliary RAM (@R0, @R1, @DPTR)
• Immediate Addressing
– Program Memory (in-code 8 bit or 16 bit constant)
• Base-Register-plus-Index-Register-Indirect Addressing
– Program Memory look-up table (@DPTR+A, @PC+A).
The first three addressing modes are usable for destination operands.

26.2 80C51 family instruction set
Table 53 Instructions that affect flag settings; note 1
FLAG(2)
INSTRUCTION
C OV AC
ADD X X X
ADDC X X X
SUBB X X X
MUL 0 X
DIV 0 X
DA X X
RRC X
RLC X
SETB C 1
CLR C 0
CPL C X
ANL C, bit X
ANL C,/bit X
ORL C, bit X
ORL C,/bit X
MOV C, bit X
CJNE X
Note
1. Note that operations on SFR byte address 208 or bit addresses 209 to 215 (i.e. the PSW or bits in the PSW) will also
affect flag settings.
2. X = dont care.

26.3 Instruction set description

For the description of the Data Addressing Modes and Hexadecimal opcode cross-reference see Table 58.
Table 54 Instruction set: Arithmetic operations
OPCODE
MNEMONIC DESCRIPTION BYTES CYCLES
(HEX)
Arithmetic operations
ADD A,Rr Add register to A 1 1 2*
ADD A,direct Add direct byte to A 2 2 25
ADD A,@Ri Add indirect RAM to A 1 1 26, 27
ADD A,#data Add immediate data to A 2 2 24
ADDC A,Rr Add register to A with carry flag 1 1 3*
ADDC A,direct Add direct byte to A with carry flag 2 2 35
ADDC A,@Ri Add indirect RAM to A with carry flag 1 1 36, 37
ADDC A,#data Add immediate data to A with carry flag 2 2 34
SUBB A,Rr Subtract register from A with borrow 1 1 9*
SUBB A,direct Subtract direct byte from A with borrow 2 2 95
SUBB A,@Ri Subtract indirect RAM from A with borrow 1 1 96, 97
SUBB A,#data Subtract immediate data from A with borrow 2 2 94
INC A Increment A 1 1 04
INC Rr Increment register 1 1 0*
INC direct Increment direct byte 2 2 05
INC @Ri Increment indirect RAM 1 1 06, 07
DEC A Decrement A 1 1 14
DEC Rr Decrement register 1 1 1*
DEC direct Decrement direct byte 2 2 15
DEC @Ri Decrement indirect RAM 1 1 16, 17
INC DPTR Increment data pointer 1 3 A3
MUL AB Multiply A and B 1 5 A4
DIV AB Divide A by B 1 5 84
DA A Decimal adjust A 1 1 D4

Table 55 Instruction set: Logic operations
OPCODE
(HEX)
Logic operations
ANL A,Rr AND register to A 1 1 5*
ANL A,direct AND direct byte to A 2 2 55
ANL A,@Ri AND indirect RAM to A 1 1 56, 57
ANL A,#data AND immediate data to A 2 2 54
ANL direct,A AND A to direct byte 2 2 52
ANL direct,#data AND immediate data to direct byte 3 3 53
ORL A,Rr OR register to A 1 1 4*
ORL A,direct OR direct byte to A 2 2 45
ORL A,@Ri OR indirect RAM to A 1 1 46, 47
ORL A,#data OR immediate data to A 2 2 44
ORL direct,A OR A to direct byte 2 2 42
ORL direct,#data OR immediate data to direct byte 3 3 43
XRL A,Rr Exclusive-OR register to A 1 1 6*
XRL A,direct Exclusive-OR direct byte to A 2 2 65
XRL A,@Ri Exclusive-OR indirect RAM to A 1 1 66, 67
XRL A,#data Exclusive-OR immediate data to A 2 2 64
XRL direct,A Exclusive-OR A to direct byte 2 2 62
XRL direct,#data Exclusive-OR immediate data to direct byte 3 2 63
CLR A Clear A 1 1 E4
CPL A Complement A 1 1 F4
RL A Rotate A left 1 1 23
RLC A Rotate A left through the carry flag 1 1 33
RR A Rotate A right 1 1 03
RRC A Rotate A right through the carry flag 1 1 13
SWAP A Swap nibbles within A 1 1 C4

Table 56 Instruction set: Data transfer
OPCODE
(HEX)
Data transfer
MOV A,Rr Move register to A 1 1 E*
MOV A,direct (note 1) Move direct byte to A 2 2 E5
MOV A,@Ri Move indirect RAM to A 1 1 E6, E7
MOV A,#data Move immediate data to A 2 2 74
MOV Rr,A Move A to register 1 1 F*
MOV Rr,direct Move direct byte to register 2 2 A*
MOV Rr,#data Move immediate data to register 2 2 7*
MOV direct,A Move A to direct byte 2 2 F5
MOV direct,Rr Move register to direct byte 2 2 8*
MOV direct,direct Move direct byte to direct 3 2 85
MOV direct,@Ri Move indirect RAM to direct byte 2 2 86, 87
MOV direct,#data Move immediate data to direct byte 3 3 75
MOV @Ri,A Move A to indirect RAM 1 1 F6, F7
MOV @Ri,direct Move direct byte to indirect RAM 2 2 A6, A7
MOV @Ri,#data Move immediate data to indirect RAM 2 2 76, 77
MOV DPTR,#data 16 Load data pointer with a 16-bit constant 3 3 90
MOVC A,@A+DPTR Move code byte relative to DPTR to A 1 3 93
MOVC A,@A+PC Move code byte relative to PC to A 1 3 83
MOVX A,@Ri Move external RAM (8-bit address) to A 1 2~9 EB, E3
MOVX A,@DPTR Move external RAM (16-bit address) to A 1 2~9 E0
MOVX @Ri,A Move A to external RAM (8-bit address) 1 2~9 F2, F3
MOVX @DPTR,A Move A to external RAM (16-bit address) 1 2~9 F0
PUSH direct Push direct byte onto stack 2 2 C0
POP direct Pop direct byte from stack 2 2 D0
XCH A,Rr Exchange register with A 1 1 C*
XCH A,direct Exchange direct byte with A 2 2 C5
XCH A,@Ri Exchange indirect RAM with A 1 1 C6, C7
XCHD A,@Ri Exchange LOW-order digit indirect RAM with A 1 1 D6, D7
Note
1. MOV A,ACC is not permitted.

Table 57 Instruction set: Boolean variable manipulation, Program and machine control
OPCODE
(HEX)
Boolean variable manipulation
CLR C Clear carry flag 1 1 C3
CLR bit Clear direct bit 2 2 C2
SETB C Set carry flag 1 1 D3
SETB bit Set direct bit 2 2 D2
CPL C Complement carry flag 1 1 B3
CPL bit Complement direct bit 2 2 B2
ANL C,bit AND direct bit to carry flag 2 2 82
ANL C,/bit AND complement of direct bit to carry flag 2 2 B0
ORL C,bit OR direct bit to carry flag 2 2 72
ORL C,/bit OR complement of direct bit to carry flag 2 2 A0
MOV C,bit Move direct bit to carry flag 2 2 A2
MOV bit,C Move carry flag to direct bit 2 2 92
Branching
ACALL addr11 Absolute subroutine call 2 3 •1
LCALL addr16 Long subroutine call 3 4 12
RET Return from subroutine 1 4 22
RETI Return from interrupt 1 4 32
AJMP addr11 Absolute jump 2 3 ♦1
LJMP addr16 Long jump 3 4 02
SJMP rel Short jump (relative address) 2 3 80
JMP @A+DPTR Jump indirect relative to the DPTR 1 3 73
JZ rel Jump if A is zero 2 3 60
JNZ rel Jump if A is not zero 2 3 70
JC rel Jump if carry flag is set 2 3 40
JNC rel Jump if carry flag is not set 2 3 50
JB bit,rel Jump if direct bit is set 3 4 20
JNB bit,rel Jump if direct bit is not set 3 4 30
JBC bit,rel Jump if direct bit is set and clear bit 3 4 10
CJNE A,direct,rel Compare direct to A and jump if not equal 3 4 B5
CJNE A,#data,rel Compare immediate to A and jump if not equal 3 4 B4
CJNE Rr,#data,rel Compare immediate to register and jump if not equal 3 4 B*
CJNE @Ri,#data,rel Compare immediate to indirect and jump if not equal 3 4 B6, B7
DJNZ Rr,rel Decrement register and jump if not zero 2 3 D*
DJNZ direct,rel Decrement direct and jump if not zero 3 4 D5
NOP No operation 1 1 00
All mnemonics are copyright © Intel Corporation 1980.

Table 58 Description of the mnemonics in the Instruction set
MNEMONIC DESCRIPTION
Data addressing modes
Rr Working register R0-R7.
direct 128 internal RAM locations and any special function register (SFR).
@Ri Indirect internal RAM location addressed by register R0 or R1 of the actual register bank.
#data 8-bit constant included in instruction.
#data 16 16-bit constant included as bytes 2 and 3 of instruction.
bit Direct addressed bit in internal RAM or SFR.
addr16 16-bit destination address. Used by LCALL and LJMP.
The branch will be anywhere within the 64 kbytes Program Memory address space.
addr11 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes
page of Program Memory as the first byte of the following instruction.
rel Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps.
Range is −128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference
* 8, 9, A, B, C, D, E, F.
• 1, 3, 5, 7, 9, B, D, F.
♦ 0, 2, 4, 6, 8, A, C, E.
Draft 2008 Jul 09 100

Draft 2008 Jul 09 Table 59 Instruction map
Syntek Semiconductors
First hexadecimal character of opcode ← Second hexadecimal character of opcode →
↓ 0 1 2 3 4 5 6 7 8 9 A B C D E F
AJMP LJMP RR INC INC INC @Ri INC Rr
0 NOP
addr11 addr16 A A direct 0 1 0 1 2 3 4 5 6 7
JBC ACALL LCALL RRC DEC DEC DEC @Ri DEC Rr
1
bit,rel addr11 addr16 A A direct 0 1 0 1 2 3 4 5 6 7
JB AJMP RL ADD ADD ADD A,@Ri ADD A,Rr
2 RET
bit,rel addr11 A A,#data A,direct 0 1 0 1 2 3 4 5 6 7
JNB ACALL RLC ADDC ADDC ADDC A,@Ri ADDC A,Rr
3 RETI
bit,rel addr11 A A,#data A,direct 0 1 0 1 2 3 4 5 6 7
JC AJMP ORL ORL ORL ORL ORL A,@Ri ORL A,Rr
4
rel addr11 direct,A direct,#data A,#data A,direct 0 1 0 1 2 3 4 5 6 7
JNC ACALL ANL ANL ANL ANL ANL A,@Ri ANL A,Rr
5
JZ AJMP XRL XRL XRL XRL XRL A,@Ri XRL A,Rr
6
101
JNZ ACALL ORL JMP MOV MOV MOV @Ri,#data MOV Rr,#data
7
rel addr11 C,bit @A+DPTR A,#data direct,#data 0 1 0 1 2 3 4 5 6 7
SJMP AJMP ANL MOVC DIV MOV MOV direct,@Ri MOV direct,Rr
8
rel addr11 C,bit A,@A+PC AB direct,direct 0 1 0 1 2 3 4 5 6 7
MOV ACALL MOV MOVC SUBB SUBB SUBB A,@Ri SUB A,Rr
9
DTPR,#data16 addr11 bit,C A,@A+DPTR A,#data A,direct 0 1 0 1 2 3 4 5 6 7
ORL AJMP MOV INC MUL MOV @Ri,direct MOV Rr,direct
A
C,/bit addr11 bit,C DPTR AB 0 1 0 1 2 3 4 5 6 7
ANL ACALL CPL CPL CJNE CJNE CJNE @Ri,#data,rel CJNE Rr,#data,rel
B
C,/bit addr11 bit C A,#data,rel A,direct,rel 0 1 0 1 2 3 4 5 6 7
PUSH AJMP CLR CLR SWAP XCH XCH A,@Ri XCH A,Rr
C
Product specification
direct addr11 bit C A A,direct 0 1 0 1 2 3 4 5 6 7
STK6032
POP ACALL SETB SETB DA DJNZ XCHD A,@Ri DJNZ Rr,rel
D
direct addr11 bit C A direct,rel 0 1 0 1 2 3 4 5 6 7
Draft 2008 Jul 09
First hexadecimal character of opcode ← Second hexadecimal character of opcode →
↓ 0 1 2 3 4 5 6 7 8 9 A B C D E F
MOVX AJMP MOVX A,@Ri CLR MOV MOV A,@Ri MOV A,Rr
E
A,@DTPR addr11 0 1 A A,direct (1) 0 1 0 1 2 3 4 5 6 7
MOVX ACALL MOVX @Ri,A CPL MOV MOV @Ri,A MOV Rr,A
F
@DTPR,A addr11 0 1 A direct,A 0 1 0 1 2 3 4 5 6 7
Note
1. MOV A, ACC is not a valid instruction.
This is the end of this data sheet

102
Product specification
STK6032
Draft 2008 Jul 09 27 PLCC44 PACKAGE OUTLINE DWRAWING
103
STK6032
Fig.51 STK6032 PLCC44 Package Outline Drawing
Draft 2008 Jul 09 28 QFP44 PACKAGE OUTLINE DRAWING
104
STK6032
Fig.52 STK6032 QFP44 Package Outline Drawing
Draft 2008 Jul 09 29 LQFP48 PACKAGE OUTLINE DRAWING
105
STK6032
Fig.53 STK6032 LQFP48 Package Outline Drawing

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Table of Contents STK6032

Table of Contents STK6032

11.1 Sources of RESET

Table of Contents STK6032

19 PWM (PULSE WIDTH MODULATED OUTPUT)

List of Table STK6032

Table 1 Ordering information.....Page [10]

List of Table STK6032

Table 50 ADCVAL Register (address DB hex).....Page [80]

List of Figures STK6032

Fig. 1 Functional block diagram...Page 11

List of Figures STK6032

Fig. 42 Converted digital code versus analog input voltage....Page 81

Table 1 Ordering information

TYPE NUMBER PACKAGE OUTLINE DRAWING

3 FUNCTIONAL BLOCK DIAGRAM

Fig.1 Functional block diagram

Fig.2 Pin configuration of QFP44 package.

4.2 Pinning diagram(LQFP48 package)

Fig.3 Pin configuration of LQFP48 version.

4.3 Pinning diagram(PLCC44)

Fig.4 Pin configuration PLCC44 version.

4.4 Pin description

SYMBOL PIN TYPE DESCRIPTION

SYMBOL PIN TYPE DESCRIPTION

5 REDUCING ELECTROMAGNETIC EMISSION

5.2 Turning off ALE

6 CENTRAL PROCESSING UNIT (CPU)

6.1 Instruction Set and addressing modes

6.2 CPU clock and Chip Configuration Register (SFR CHIPCON)

CPU clock control

Fig.5 CPU clock

Table 3 Chip Configuration Register

Table 4 Description of Chip Configuration Register (CHIPCON)

MNEMONIC BIT POSITION FUNCTION

6.3 Instruciton Cycle

instruction n+1 n+2

Fig.6 CPU timing for single-cycle instruction.

6.4 Program Status Word

Table 5 Program Status Word

Table 6 Description of Program Status Word (PSW)

Internal External External

Program Memory on-chip Data Memory External Data

Fig.7 The overall memory space

7.1 Program Memory

7.1.1 PRORAM ROM SPACE

7.1.2 ON-CHIP PROGRAM MEMORY VERSUS EXTERNAL PROGRAM MEMORY

7.1.3 ISP PRGRAMMING FOR THE 64K FLASH MEMORY

7.1.4 ROM CODE PROTECTION

on-chip program memory Off-chip program memory,

Fig.8 Program Memory.

7.2 Main Data RAM and Special Function Register (SFR)

Lower 128 bytes

7.2.1 THE LOWER 128 BYTES OF THE MAIN DATA RAM

7.3 AUX Memory

7.3.1 AUX MEMORY SPACE

Read/write to this block

7.3.2 ON-CHIP AUX MEMORY

Table 7 Data Pointer 0, Data Pointer 1, and DPTR Select Register

Table 8 Instructions that use the DPTR

Table 9 Clock Control Register, SFR CKCON

Table 10 Description of the CKCON Register