LABORATORY MANUAL

ECE279

Name of the Student :……………………………………………….

Registration Number/Roll No:………………………………………
Section and Group……………………………………………………
Name of School: School of Computer Science and Engineering

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 Course Outcome Statements Applicable to
CO1 Learn to use basic electrical & electronics measuring instruments and All practical
component specific ratings.
CO2 Use basic electrical laws and theorems to analyse DC circuits P1 and P2
CO3 Build virtual applications with at least one sensor module by programming P6
microcontroller board.
CO4 Make use of various digital & analogue ICs and conduct their functionality test. P3, P4, P5, P7,
P8
CO5 Assemble various electrical & electronics components on the breadboard and P1 to P5, P7, P8
create circuit connections.
CO6 Design and analyse combinational and sequential circuits. P5, P7, P8

Table of Contents
Practical Title of Experiment Page
No.
1 Implement Kirchhoff voltage and current laws. 5
2 Apply Thevenin's theorem on DC circuits. 11
3 Analyse V-I characteristics of PN Junction 15
diode.
4 Understanding the truth table of Logic Gates 21
and implement these gates using Universal
gates.
5 Understanding the combinational logic by 29
implementing the Boolean function using a
multiplexer.
6 Virtual integration of IR sensor using Arduino 35
7 Understand JK Flip-Flop and implement T- 41
Flip Flop using NAND circuit of JK Flip Flop.
8 Implement Decade counter using IC-7490 and 47
seven segment display.

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 General Safety guidelines for the students

• Use only tools and equipment with non-conducting handles when working with electrical
devices.
• When checking an operating circuit, keep one hand either in a pocket or behind your back to
avoid making a closed circuit through the body.
• Never plug leads into power source unless they are connected to an established circuit.
• Avoid contacting circuits with wet hands or wet materials.
• All current transmitting parts of any electrical devices must be enclosed.
• Maintain a work space clear of extraneous material such as books, papers, and clothes.
• Never change wiring with circuit plugged into power source.
• Place the IC’s Properly in the bread board, don’t break the IC pins by forcefully inserting in
bread board.
• Switch off the power supply when not in use.
• Always cut wire leads so the clipped wire falls on table top and not towards others.
• Shoes must be worn at all times.
• Remove all loose conductive Jewelry and trinkets, including rings, which may come
in contact with exposed circuits. (Do not wear long loose ties, scarves, orother
loose clothing around machines.
• Don’t switch ON the power supply without confirming the connections from the lab
instructor.
• When making measurements, form the habit of using only one hand at a time. No part
of a live circuit should be touched by the bare hand.
• Keep the body, or any part of it, out of the circuit. Where interconnecting wires and
cables are involved, they should be arranged so people will not trip over them.
• Be as neat as possible. Keep the work area and workbench clear of items not used in
the experiment.

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 Evaluation Mechanism for the course

1. Continuous assessment: There will be 4 Continuous Assessment for Practical (CAP), two Written
Test Practical (WTP) Examinations during the term. Each evaluation will be for 30 marks. Both WTP
Examinations are compulsory; and in CAP: 3 best out of 4 will be considered. All CAP will be MCQ
based with 15 questions of two marks each. WTP1, WTP2 will be evaluated for performances and
write up.
Each CAP will be conducted after two practical are performed in the laboratory.

2. Mid Term Practical (MTP): No Mid-term exam is applicable for this course

3. End Term Practical (ETP): This may be conducted in last teaching week or after last teaching week
of the term, Student will get any one practical to perform in the ETP for being evaluated on Viva,
Written and Performance.

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 EXPERIMENT No.1

Aim: Implement Kirchhoff’s Voltage Law and Current Law.

Learning Objective: To use ammeter and voltmeter and verify implementation of KVL and KCL.
Apparatus required:

S. No. Items Specifications Quantity

1 DC Voltage source 0-20V 01
2 Resistors 330 ohms 05
3 Ammeter Digital/Analog 01
4 Voltmeter Digital/Analog 01
5 Connecting wires
As per requirements
1. Kirchhoff’s Voltage Law states that the algebraic sum of all the voltages around any
closed path (loop or mesh) is zero.
Applying Kirchhoff’s voltage law to the first ( loop with voltage source) and the second
loops (without voltage source) in the circuit of Figure 1:
Loop 1: -Vs +V1 +V2 +V5 = 0 (1),
Let I1 is loop-1 current and I2 is loop-2 current in clockwise direction, Vs=5V
=> -5+I1R1+(I1-I2) R2+ I1R5 = 0; =>I1*330+(I1-I2)*330+ I1*330—(2)
=> 990I1-330I2=5 ------- (3)
Loop 2: V2 +V3 +V4 = 0 (4)
=> (I2-I1) R2+I2R3+ I2R4 = 0; => (I2-I1)*330+I2*330+ I2*330---(5)
=> -330I1-990I2=0 ------- (6)
=> I1=15/2640A= 5.7mA A, I2= 1.9mA using these values of current =>
LOOP1 equation (2) becomes -5+ 5.7m*330+ (5.7-1.9)m*330+ 5.7m*330= -5 + 1.881 + 1.254
+1.881= -5+5.016 ≈ 0, hence KVL verified theoretically.
LOOP2 equation (5) becomes (1.9-5.7) m*330+1.9m*330+ 1.9m*330= -1.254+0.627+0.627≈ 0.
hence KVL verified theoretically.

2. Kirchhoff’s Current Law states that the algebraic sum of all the currents at any node is zero.
Applying Kirchhoff’s current law to the first four nodes in the circuit shown in Figure 2 yields the
following equations; In Figure 2 Clockwise Current: through voltage source is IV, through R1 is I1 ,
through R2 is I2 , through R3 is I3 , Current through R4 is I4 , and Current through R5 is I5 ,
Let’s consider that node e is a reference node and is chosen as GND. Va, Vb, Vc, Vd
are node voltages at points a, b, c and d respectively.
Node a: -Is + I1 = 0=>Vs = 5V= Va
Node b: I1 =I2 + I3 => (Vb-5)/R1 = (Vb- Va)/R3 + (Vb-Vd)/R2 =>
Node c: I3 = I4
Node d: I2 +I4 = I5
Let e as reference point or ground.
 Va = 5V----(1)
At node b: I1 = I2 + I3
(5 – Vb)/ R1 = (Vb – Vd)/R2 + (Vb – Vc)/R3
After putting values of Resistence, we get
3Vb -Vc-Vd = 5 ----(2)
At node C : I3 = I4
(Vb – Vc)/ R3 = (Vc – Vd)/ R4
(Vb – Vc) = (Vc – Vd)
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 2Vc – Vb - Vd = 0 ------(3)
At node D: I5 = I2 + I4
(Vd – 0)/ R5 = (Vb – Vd)/R2 + (Vc – Vd)/R4
Vc - Vd + Vc – Vd = Vd
Vb + Vc – 3Vd = 0 -----(4)
Now simplify equation 2, 3 and 4.
Add equation (2) and [(3) × 3], we get
5Vc – 4Vd = 5-----(5)
Add equation (3) and (4), we get
Vc = 4Vd/3 ------(6)
Put equation (6) in equation (5), we get
Vd = 15/8 V -------(7)
Put equation (7) in equation (6), we get
Vc = 2.5V ----(8)
Put equation (7) ad (8) in equation (3), we get
Vb = 25/8 -----(9)
Now to find I1 , I2 , I3 , I4 and I5 put the value of Va, Vb, Vc and Vd in
I1 = (5 – Vb)/ R1
I2 = (Vb – Vd)/R2
I3 = (Vb – Vc) /R3
I4 = (Vc – Vd)/R4
I5 = (Vd – 0)/R5
We get, I1 = 15/ (8×330) A, I2 = 10/ (8×330) A, I3 = 5/ (8×330) A, I4 = 5/ (8×330) A
and I5 = 15/ (8×330) A
Hence Equations below at nodes a, b , c and d are verified theoretically
-Is + I1 = 0
I1 =I2 + I3
I3 = I4
I2 +I4 = I5

3. Reading Resistor with color code:

The color code is used to specify the resistance value, the tolerance value, and sometimes the reliability
or failure rate. The number of bands varies from three to six. At a minimum, two bands indicate the
resistance value and one band serves as multiplier.
The four-band color code is the most common variation. These resistors have two bands for the
resistance value, one multiplier and one tolerance band. In the example shown here, the 4 bands are
green, blue, red and gold. By using the color code chart, one finds that green stands for 5 and blue for 6.
The third band is the multiplier, with red representing a multiplier value of 2 (10 2). Therefore, the value
of this resistor is 56x102 = 56x100 = 5600 Ω. The gold band means that the resistor has a tolerance of
5%. The resistance value lies therefore between 5320 and 5880 Ω (5560 ± 5%). If the tolerance band
is left blank, the result is a 3-band resistor. This means that the resistance value remains the same, but the
tolerance is 20%. For 5 band resistor, the first three bands indicate the significant digits, the fourth band is the
multiplication factor, and the fifth band represents the tolerance. Let us consider another example (say); brown (1),
yellow (4), violet (7), black (x100 = x1), green (0.5%) represents a resistor of 147 Ω with a tolerance of 0.5%. The
tolerance represents deviation from the normal value. It is measured at 25 0C with no load applied and is generally
expressed as ±%.
Resistance Value of 330ohm as Band1: Orange, Band2: Orange, Band3: Brown=> 33x10=330∓
tolerance (5% Gold, 10% Silver)

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Figure 1 Voltage measurement across circuit elements

Figure 2 Current Measurement across circuit elements

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4. Least count of Voltmeter and Ammeter:-
In the given figure 3 below, total range is up to 3V for voltmeter and 1000 mA for ammeter.
𝑇𝑜𝑡𝑎𝑙 𝒓𝒂𝒏𝒈𝒆 𝑜𝑓 𝑚𝑒𝑡𝑒𝑟
Least count =
𝑇𝑜𝑡𝑎𝑙 𝒏𝒖𝒎𝒃𝒆𝒓 𝑜𝑓 𝑑𝑖𝑣𝑖𝑠𝑖𝑜𝑛
Least count of voltmeter = 3/30 = 0.1 V
Least count of ammeter = 1/50 = 0.02 A
Reading of Voltmeter = Number of divisions scaled by the pointer * Least count of voltmeter = 21*0.1=2.1V
Reading of Ammeter = Number of divisions scaled by the pointer * Least count of Ammeter= 15 *0.02A=
0.3A=30mA

Figure 3: Measurement of Current and Voltage using Ammeter and Voltmeter

5. Half-Breadboard for circuit implementation:
Internally connected
W column Hole 1 to 25, vertically
X Column Hole 1 to 25, vertically
Y Column Hole 1 to 25, vertically
Z Column Hole 1 to 25, vertically
Internally connected
Row-1 Holes A B C D & E, horizontally
Row -1 Holes F G H I & J, horizontally
Row-2 Holes A B C D & E, horizontally
Row -2 Holes F G H I & J, horizontally
th
And so on till 30 row
Table 1: Internal connection of holes through a metal strip on backside of Half Breadboard

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 Figure 4: Front view and Back view of Half Breadboard
Procedure:
1. Construct the circuit shown in Figure using the values below: R1 = 330 Ω R2 = 330 Ω
R3 = 330 Ω R4 = 330 Ω R5 = 330 Ω,
2. Set the Variable Power Supply (Vs) to 5 Volts.
3. Accurately measure all voltages and currents in the circuit using the Digital/Analog
Meter.
4. Record the measurements in the observation and calculation table containing the
measured voltage and currentvalues.
5. Verify KVL for the loops in the circuit using equations of Results and Discussion section.
6. Verify KCL for the loops in the circuit using equations of Results and Discussion section.
7. %𝑎𝑔𝑒 𝐸𝑟𝑟𝑜𝑟 = ([𝑉_𝐶𝑎𝑙𝑐𝑢𝑙𝑎𝑡𝑒𝑑 − 𝑉_𝑀𝑒𝑎𝑠𝑢𝑟𝑒𝑑)/𝑉_𝐶𝑎𝑙𝑐𝑢𝑙𝑎𝑡𝑒𝑑]𝑥100

Observation and Calculations: Vs=5V, R=330ohm

Theoretical Value using KVL and KCL Practical value using Ammeter and Voltmeter
Equations
Resistance Voltage across Current in R Voltage %age error Current in %age
R across R R error
R1 1.881V 15/ (8×330) A=5.7mA
R2 1.254V 10/ (8×330) A= 3.8mA
R3 0.627V 5/ (8×330) A=1.9mA
R4 0.627V 5/ (8×330) A=1.9mA
R5 1.881V 15/ (8×330) A= 5.7mA

Results and Discussion:

1. Verify the KVL principle using measured values for the equations below:
LOOP-1: -Vs +V1 +V2 +V5 = 0,
LOOP-2: V2 +V3 +V4 = 0

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2. Verify the KCL principle using measured values for the equations below:
Node b: I1 =I2 + I3
Node c: I3 = I4
Node d: I2 +I4 = I5

Precautions:
1. All the connections should be perfectly tight.
2. Always connect ammeter in series and voltmeter in parallel
3. Use safety guards while working on live parts
4. Don’t touch the bare conductor when supply is ON.
5. Supply should not be switched ON until and unless the connections are checked by the
Faculty/Lab Instructor
6. Use proper wire for connections

Learning Outcome (expected):

1. Able to connect circuit on the breadboard.
2. Use voltmeter and ammeter on the breadboard and finding least count.
3. Read resistance values using formula “BB ROY of Great Britain Having Very Good Wife”.
4. Calculate I and V across any circuit element.

Learning Outcome (what I have learnt):

Breadboard Circuit Diagram:

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 EXPERIMENT No.2
Aim: Apply Thevenin's theorem on DC circuits.

Learning Objective:
1. To implement the circuit on the breadboard and verify Thevenin’s theorem.
2. To identify different sources of error in this practical.

Apparatus/Components required:
S No Apparatus Range Quantity
1 Regulated Power Supply (0-30V) 2
2 Ammeter (0-10mA) 1
3 Resistor 1Kohm,220ohm. 330ohm 1,3,1
4 Bread Board -- 1
5 Voltmeter (0-30V) 1
6 Digital Multimeter -- 1

Statement: If we wish to find I or V across any element (load resistance) in the linear bilateral circuit,
then we go for Thevenin’s theorem. Any complex circuit can be broken down to only three elements
such as VTH, RTH, and load resistance (RL) using Thevenin’s theorem. In this practical we will find I
across 1Kohm Load resistance of Circuit-1 using Thevenin’s equivalent Circuit-4. We will prove
that IL of Circuit-1 and Circuit-4 are same.

Procedure:
1. Connections are given as per the circuit diagram.
2. Set 5Vvalue of voltage using RPS and note down the correspondingammeter readings
as per Circuit-1.
3. To find VTH : Remove the load resistance and measure the open circuit voltage
using multimeter (VTH) as per Circuit-2.
4. To find RTH : Remove the RPS and short circuit it and find the RTH using multimeter in
Circuit -3.
5. Give the connections for equivalent circuit and set VTH and RTH and note the
corresponding Ammeter reading in Circuit -4.
6. Verify Thevenin’s theorem for theoretical and practical values using observation table and
identify sources of error (if any).
7. Also find percentage error.
Circuit Diagrams: Circuit - 1: To find load current

Supply Voltage =5V, I1 and I2 are in clockwise direction, I2 =IL

5=220 I1+ 220 (I1- I2) => 440 I1 - 220 I2 ------------(1)
0=220 I2 +1000 I2 + 220 (I2- I1); => -220 I1 + 1440 I2 ------------(2) => I2= 1.879mA= IL
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 Circuit 2: To find VTH

Since no current is passed through the resistance connected to point A, so it will not contribute to VTH
value, so using potential divider law in the circuit below, VTH = (220*5V)/440 =2.5V

Circuit 3: To find RTH

RTH = 220 ohm connected to point A + Parallel combination of other two resistances
Parallel combination of other two resistances = (220*220)/(220+220)=220*220/440=110ohm
 RTH =220+110=330ohm

Circuit-4: Thevenin’s Equivalent Circuit:

Current flowing through 1Kohm, IL= 2.5/(330+1000)= 1.879mA

Precautions:
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 1. All the connections should be perfectly tight.
2. Always connect ammeter in series and voltmeter in parallel
3. Use safety guards while working on live parts
4. Don’t touch the bare conductor when supply is ON.
5. Supply should not be switched ON until and unless the connections are checked by
theFaculty/Lab Instructor
6. Use proper wire for connections

Worksheet of the student

Observation table: for Input Voltage =5V

Power supply Thevenin’s Thevenin’s Load Current IL (mA)
Voltage Voltage VTH Resistance RTH Circuit -1 Thevenin’s
Circuit-2 Circuit-3 equivalent
Circuit-4
Calculated 5V 2.5V 330 ohm 1.879mA 1.879mA
value
Measured
value

%𝑎𝑔𝑒 𝐸𝑟𝑟𝑜𝑟 𝑓𝑜𝑟 𝑉 = ([𝑉_𝐶𝑎𝑙𝑐𝑢𝑙𝑎𝑡𝑒𝑑 − 𝑉_𝑀𝑒𝑎𝑠𝑢𝑟𝑒𝑑)/𝑉_𝐶𝑎𝑙𝑐𝑢𝑙𝑎𝑡𝑒𝑑]𝑋100

Calculation of %age Error:

1. %age Error for VTH =

2. %age Error for RTH =

3. %age Error for IL =

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Results and Discussion:

Learning Outcomes (expected):

1. Measure the values of Thevenin’s voltage and resistance.
2. Able to use ammeter and voltmeter
3. Identify different sources of error in this practical.
Learning Outcomes (what I have learnt):

Bread Board Circuit Diagram/ Connection Diagram

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 EXPERIMENT No. 3

Aim: Analysis of V-I characteristics of PN Junction diode.

Learning Objective(s):
1. To identify sources of error in this practical.
2. To measure diode current in forward biased condition.
3. To test the diode for functioning.
Instruments/Components: A p-n junction diode, 30V DC power supply, 1Kohm, 0-30V
voltmeter, 0−100mA ammeter and connecting wires.

Sr. No. Components/Instruments Range Quantity

1. PN Junction Diode Number : IN 4007 1
2. Regulated DC Variable Power Supply 0-30V 1
3. DC Voltmeter 0-1V/0-20V 1
4. DC Ammeter 0-30mA 1
5. Resistance * as per calculation 470 ohm* 1
6. One Bread Board and Connecting Wires
Single Strand 8-10 number

Theory: A semiconductor PN junction diode is a two terminal electronic device (Di-electrode →

Diode). The metal contacts taken out from p-region and n-region are called anode and cathode
respectively. There are three possible biasing conditions and two operating regions for the typical
PN-Junction Diode, they are: zero bias, forward bias and reverse bias.When no voltage is applied
across the PN junction diode then the electrons will diffuse to P-side and holes will diffuse to N-
side through the junction and they combine with each other. Therefore,the acceptor atom close to
the P-type and donor atom near to the N-side are left unutilized. An electronic field is generated by
these charge carriers. This opposes further diffusion of charge carriers. Thus, no movement of the
region is known as depletion region or space charge. Figure 1 shows the symbol diagram of diode
with its real appearance.

Fig. 1: Symbol of PN Diode

Zero Biased PN Junction Diode

Unbiased pn Junction: As the pn junction is formed, holes from p-region diffuse across the junction
and recombine with the electrons in the n-region near the junction resulting in formation of positive
ions in the n-region near the junction. Similarly, electrons from n-region diffuse across the junction
and recombine with the holes in p-region near the junction to form negative ions. Thus there exists a
narrow region extended in both the regions, that does not have any mobile charge carriers (neither
holes nor electrons) is called depletion region, the region depleted of charge carriers. After generating
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a depletion region a equilibrium state reaches in whichAt equilibrium, these two currents are equal and
opposite i. e. ID = IS. This condition is maintained by barrier potential. The built-in potential across the
junction is given by,
𝑵𝑨 𝑵 𝑫
VO=VT In( )
𝒏𝟐𝒊
where, VT = 𝑘𝑇/𝑞, called thermal voltage, NA, ND are doping concentrations of p side and n side.
Typically the value of V0 at room temperature ranges between 0.6 to 0.8V

Figure 2: Unbiased Diode current direction

Forward Bias Condition: On forward biasing, initially no current flows due to barrier potential. As
the applied potential exceeds the barrier potential the charge carriers gain sufficient energy to cross
the potential barrier and hence enter the other region. The holes, which are majority carriers in the P-
region, become minority carriers on entering the N-regions, and electrons, which are the majority
carriers in the N-region, become minority carriers on entering the P-region. This injection of minority
carriers results in the current flow, opposite to the direction of electron movement. (Resistance RS
calculation for maximum current flow through the diode i.e. at maximum DC supply 20 V/ 30V
and maximum forward current 50 mA given)

RS = V/I = 20 / 50 mA (Supply 20 V) or 30 /50 mA (supply 30 V)

Thus R = 400 to 600 ohm

What happens inside the pn junction diode when forward biased?

When we apply voltage to the terminals of diode, the width of depletion region slowly starts
decreasing. The reason for this is, in forward bias we apply voltage in a direction opposite to that of
barrier potential. So the electrons in n-side get pushed towards the junction (by force of repulsion)
and the holes in p-side get pushed towards the junction. As the applied voltage increases from 0
volts to 0.7 volts, the depletion region width reduces to zero. This means depletion region vanishes
at 0.7 volts of applied voltage.

Procedure:
1. Before connection of the diode in the circuit test that diode is working, for that connect the diode
the anode terminal with +ve probe of multimeter and cathode with –Ve probe and adjust the
multimeter knob at Diode symbol as sown in figure 3. If value on multimeter is zero then diode is
working fine and if lower voltage present in the diode it is due to charged capacitor.

16
 Fig: 3 Diode testing with multimeter.
1. Connect the circuit as shown in figure 4 using PN Junction diode
2. Before switch ‘On’ the supply, rotate power supply potentiometer fully in CCW (counter
clockwise direction) to start experiment from Zero voltage otherwise excessive voltage can
damage the diode and multimeter.
3. Connect Ammeter in series of Power supply positive terminal and anode of Diode to measure diode
current ID (mA)
4. Connect Voltmeter across diode to measure diode voltage VD.
5. Initially vary the Regulated Power Supply voltage, Vs from zero in steps of 0.1 V. Once the current
starts increasing vary Vs in steps of 0.5 V, Vary the DC power supply till the value of diode voltage
VF from 0 to 1V, (0.83V) in steps and Measure the corresponding values of diode Forward Current
IF in mA and note down in the Observation Table.
6. Plot a curve between diode voltage VF and diode current IF as shown in figure 5 (First quadrant)
using suitable scale, with the help of Observation Table. This curve is the required forward
characteristics of Si diode.
7. After complete the experiment, Switch ‘Off’ the supply with doing DC power supply to zero volts.

Fig. 4: Circuit diagram of Forward Bias diode.

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 Fig. 5: VI characteristic of Forward Bias diode.
Precautions:
Do not press the IC on breadboard until pins are aligned with pours.
1. Make connection properly.
2. There should not any short circuit in the circuit. Avoid the heating of IC. Provide
proper clock pulse.

Calculations from Graph: Cut in Voltage V (It is observed that Ge diode has smaller cut in voltage
when compared to Si diode. The reverse saturation current in Ge diode is larger in magnitude when
compared to Si diode)

Static forward Resistance RDC =Vf /If Ω

Dynamic Forward Resistance r ac = ∆ Vf / ∆ If Ω

In the above diode current equation, defines an exponential relationship between the diode current
(the dependent variable) and the diode voltage (the independent variable). This equation holds over
at least seven orders of magnitude of current and is truly valuable in defining the behaviors of
semiconductor diodes. Where I is the forward current, V is the forward voltage, IO is the reverse
saturation current, and VT = kT/q is the thermal Voltage. VT = T/11600, 26 mV at room temperature,
k is Boltzmann’s constant (1.38 x 10-23 j/⁰K, T is the absolute temperature in degree Kelvin (⁰K =
273 + the temperature in ⁰C) and q indicates the fundamental charge of electron (1.60 x 10-19
Coulombs (C=J/V). η is dependent on material, diode construction and operational considerations
and unless otherwise explicitly stated, the standard simplification of η =1 for Ge and 2 for Si will be
used for all examples and may be made for all analyses. Initially, the V vs I graph is linear but then
after reaching breakdown, it becomes exponential.

18
 Worksheet of the Students

Observation Table:
ɳ is the emission coefficient which is 1 for Ge and 2 for Si
Value of reverse saturation current (I0) varies with temperature, since forward current varies between
1mA to 10mA at VF=0.7V for Si and 0.3 V for Ge so approximate range of reverse saturation current
(Io) for Si is 1.22nA to 12.2nA, Ge is 8.52nA to 85.2nA. You can find the correct value from this
range. In this practical, For Si Diode assumed value is 0.53nA
Thermal Voltage VT= 298.15/11600= 0.0257V at room temp.
Forward Bias
Sr. VF I_Calculated Si diode I_Calculated)Ge diode I (Measured) %age
𝑉 𝑉
No. ( ) ( ) Using Error
I=Io[𝑒 ƞ𝑉𝑇 -1] (A) I=Io[𝑒 ƞ𝑉𝑇 -1] (A)
ammeter
0.1 0.1
1. 0.1 ( ) ( )
I= Io[𝑒 2∗0.0257 -1= I= Io [𝑒 1∗0.0257 -1]=
0.2 0.2
2. 0.2 I= Io [𝑒 (2∗0.0257) -1]= I= Io [𝑒 (1∗0.0257) -1]=
0.3 0.3
3. 0.3 I= Io [𝑒
(
2∗0.0257
)
-1]= I= Io [𝑒
(
1∗0.0257
)
-1]=
0.5 0.4
4. 0.4 I= Io [𝑒
(
2∗0.0257
)
-1]= I= Io [𝑒
(
1∗0.0257
)
-1]=
0.5 0.5
5. 0.5 ( ) ( )
I= Io [𝑒 2∗0.0257 -1]= I= Io [𝑒 1∗0.0257 -1]=
0.6 0.6
6. 0.6 I= Io [𝑒 (
2∗0.0257
)
-1]= I= Io [𝑒 (
1∗0.0257
)
-1]=
0.7 0.7
7. 0.7 I= Io [𝑒 (
2∗0.0257
)
-1] = I= Io [𝑒 (
1∗0.0257
)
-1]=
0.7 0.8
8. 0.8 I= Io [𝑒
(
2∗0.0257
)
-1] = I= Io [𝑒
(
1∗0.0257
)
-1]=
0.9 0.9
9. 0.9 I= Io [𝑒 (
2∗0.0257
)
-1]= I= Io [𝑒 (
1∗0.0257
)
-1]=
1.0 1.0
10. 1 ( ) ( )
I= Io [𝑒 2∗0.0257 -1]= I= Io [𝑒 1∗0.0257 -1]=

Calculations:
Find optimal value of Io, for which measured diode current is equal to theoretical value of current,
and using that optimal value find theoretical diode current, and hence calculate
%𝑎𝑔𝑒 𝐸𝑟𝑟𝑜𝑟 𝐼 = ([𝐼_𝐶𝑎𝑙𝑐𝑢𝑙𝑎𝑡𝑒𝑑 − 𝐼_𝑀𝑒𝑎𝑠𝑢𝑟𝑒𝑑)/𝐼_𝐶𝑎𝑙𝑐𝑢𝑙𝑎𝑡𝑒𝑑]𝑥100

19
Results and Discussion on Sources or Error:

Learning Outcomes (expected):

1. Leant to forward bias a diode
2. Know the minimum bias voltage for Si and Ge diode?
3. Identify sources of error in this practical

Learning Outcomes (what I have learnt):

Breadboard Connection Diagram:

20
 EXPERIMENT No.4

Aim: Understanding the truth table of Logic Gates and implement these gates using Universal
gates.
Learning Objectives: 1. To verify the functionality of Logic Gates
2. To implement Basic Logic gates using Universal gates and verify their function.
Instruments/Components required: IC-7404,7408,7432, 7400,7402, 7486, Digital Trainer
module,
Theory and verification
1. NOT GATE 7404

Figure1: NOT gate using a SWITCH

The NOT gate, also known as an inverter, produces the complement of its input. If the
input is high, the output is low, and vice versa. It can be represented by the Boolean
expression NOT A.

Input Output
0 1(LED GLOW)
1 0 (LED OFF)

Figure 2: IC diagram of 7404 and Truth Table

Truth Table Outputs taken at
Input Output PIN2(Y1) PIN4(Y2) PIN6(Y3) PIN8(Y4) PIN10(Y5) PIN12(Y6)
0 1
1 0
Table 1: Observation table for NOT gate (7404)

2. AND GATE 7408

Figure 3: AND Gate using switches

The AND gate produces a high output only when all of its inputs are high. It can be represented

21
by the Boolean expression A AND B, where A and B are the inputs.

Input1 Input2 Output

0 0 0
0 1 0
1 0 0
1 1 1

Figure 4: IC diagram of 7408 and Truth Table

Input Output PIN3, Y1 PIN6, Y2 PIN8, Y3 PIN11, Y4

0 0
0 1
1 0
1 1
Table 2: Observation table for AND gate (7408)

3. OR GATE 7432

Figure 5: OR gate using a SWITCH

The OR gate produces a high output if any of its inputs are high. It can be represented by the
Boolean expression A OR B.

Input A Input B Output

0 0 0
0 1 1
1 0 1
1 1 1

Figure 6: IC diagram of 7432 and Truth Table

Input Output PIN3, Y1 PIN6, Y2 PIN8, Y3 PIN11, Y4

0 0
0 1
1 0
1 1
Table 3: Observation table for OR gate (7432)

22
4. NOR Gate 7402

Figure 7: NOR gate using a SWITCH

NOR gate: The NOR gate is a combination of an OR gate followed by a NOT gate. It
produces the complement of the OR gate output. It can be represented by the Boolean
expression NOT (A OR B).

Input A Input B Output

0 0 1
0 1 0
1 0 0
1 1 0

Figure 8: IC diagram of 7402 and Truth Table

Input Output PIN1, Y1 PIN4, Y2 PIN10, Y3 PIN13, Y4

0 0
0 1
1 0
1 1
Table 4: Observation table for NOR gate (7402)
5. NAND Gate 7400

Figure 9: NAND gate using a SWITCH

The NAND gate is a combination of an AND gate followed by a NOT gate. It produces
the complement of the AND gate output. It can be represented by the Boolean expression
NOT (A AND B).

23
 Input A Input B Output
0 0 1
0 1 1
1 0 1
1 1 0

Figure 10: IC diagram of 7400 and Truth Table

Input Output PIN3, Y1 PIN6, Y2 PIN8, Y3 PIN11, Y4

0 0
0 1
1 0
1 1
Table 5: Observation table for NAND gate (7400)
6. XOR Gate 7486

Figure 11: XOR gate using a SWITCH

XOR gate: The XOR gate, also known as an exclusive OR gate, produces a high output
if the number of high inputs is odd. It can be represented by the Boolean expression A
Input A Input B Output
0 0 0
0 1 1
1 0 1
1 1 0

xor B
Figure 12: IC diagram of 7486 and Truth Table

Output PIN3, Y1 PIN6, Y2 PIN8, Y3 PIN11, Y4

Input
0 0
0 1
1 0
1 1
Table 6: Observation table for XOR gate (7486)

7. Implementation using Universal gates

24
7.1 Using NAND Gate:

NAND Gate as NOT Gate:

Input Output
0 1
1 0
Figure 13: NOT gate using NAND Gate and Truth table
Truth Table Outputs taken at

Input Output PIN3, Y1 PIN6, Y2 PIN8, Y3 PIN11, Y4

0 1
1 0

Table 7: Observation table for NOT gate using NAND Gate

NAND Gate as OR Gate:

Input A Input B Output

0 0 0
0 1 1
1 0 1
1 1 1
Figure 14: OR gate using NAND Gate and Truth table

Truth Table Output

taken at
Input-1 Input-2 Output PIN6, Y1
0 0 1
0 1 1
1 0 1
1 1 0
Table 8: Observation table for OR Gate using NAND Universal gate

NAND Gate as AND Gate:

Input1 Input2 Output

0 0 0
0 1 0
1 0 0
1 1 1
Figure 15: AND gate using NAND Gate and Truth table

25
 Truth Table Output
taken at
Input-1 Input-2 Output PIN6, Y1

0 0 1
0 1 1
1 0 1
1 1 0
Table 9: Observation table for AND Gate using NAND Universal gate

7.2 Using NOR Gate:

NOR Gate as NOT Gate:

Input Output
0 1
1 0

Figure 16: NOT gate using NOR Gate and Truth table
Truth Table Outputs taken at

Input Output PIN3, Y1 PIN6, Y2 PIN8, Y3 PIN11, Y4

0 1
1 0
Table 10: Observation table for NOT gate using NOR Gate

NOR Gate as OR Gate:

Input A Input B Output

0 0 0
0 1 1
1 0 1
1 1 1

Figure 17: OR gate using NOR Gate and Truth table

Truth Table Output
taken at
Input-1 Input-2 Output PIN6, Y1

0 0 0
0 1 1
1 0 1
1 1 1
Table 11: Observation table for OR Gate using NOR Universal gate

26
NOR Gate as AND Gate:
Input1 Input2 Output
0 0 0
0 1 0
1 0 0
1 1 1
Figure 18:
AND gate using NOR Gate and Truth table

Truth Table Output

taken at
Input-1 Input-2 Output PIN6, Y1

0 0 1
0 1 1
1 0 1
1 1 0
Table 12: Observation table for AND Gate using NOR Universal gate

Procedure:
1. Place the IC on the breadboard of digital trainer module.
2. Identify VCC and GND terminals of the trainer module and connect them to VCC and
GND pins of the IC.
3. Identify toggle switches on the trainer module and connect them as inputs to the IC.
4. Identify output LEDs on the trainer module. Connect output pins of the IC to those
LEDs.
5. Apply various combinations of inputs according to the truth table and observe behavior
of the logic gates of the IC.
6. Disconnect the inputs and outputs of the IC and replace this IC with a new one and go
to step 1.
7. Got to step 1, till all ICs are tested/verified.
8. Now implement NOT, OR, AND using NOR, NAND respectively and verify the
functionality of NOT, OR, AND Gates.

Precautions:
1. All the connections should be perfectly tight.
2. Always connect ammeter in series and voltmeter in parallel.
3. Use safety guards while working on live parts.
4. Don’t touch the bare conductor when supply is ON.
5. Supply should not be switched ON until and unless the connections are
checked by the Faculty/Lab Instructor.
6. Use proper wire for connections.

Viva Questions:
1. Define gates?
2. Define IC?
3. What is DE Morgan’s law?
4. (A+A) A =?

27
 5. Define Universal gates and draw their internal and external Pin Diagram.
6. Write the Boolean expression of the 2 inputs AND gate.
7. How many no. of input variables can a NOT Gate have?
8. Under what conditions the output of a two input AND gate is one?
9. Calculate 1+0 =?
10. When will the output of a NAND Gate be 0?

Learning Outcome (expected):

1. Understanding the breadboard and its usage.
2. Able to understand logic gates and universal gates.
3. Understand pin diagrams of Logic Gate IC’s.
4. Able to implement AND, OR, NOT, XOR gates using Universal gates.

Learning Outcome (what I have learnt):

IC Connection Diagram:

28
 Practical No: 05
Aim: Understanding the combinational logic by implementing the Boolean function using a
multiplexer.
Learning Objective: 1. To implement FA and FS using 4:1 MUX.
2. To verify the working of FA and FS using MUX.
Instruments/Components: 74153 IC, 7404 IC, Digital Trainer module, connecting probes
Theory: Multiplexer (MUX) is a device that connects one of the input lines to the output line
depending upon control signal as shown in Figure 1. Same is explained through a control
switch and internal circuit of 2:1 MUX.

Figure 1: Block diagram of 2:1Mux, 2:1 Mux implementation using control switch, Internal
circuit of 2:1 MUX
In case of 4:1 Mux, there are four input lines, I0, I1, I2 and I3, which are to be multiplexed on
a single line output line (Y). The four input lines are also known as the Data Inputs. Since there
are four inputs, there is need of two additional inputs to the multiplexer, known as the Select
Inputs. The purpose of select inputs is to select, which of the inputs is reflected at the output.
Call these select lines S1(A) and S0(B). The pin diagram of IC74153, which is dual 4:1
Multiplexer IC is shown below in Figure 2.

Figure 2: Pin diagram of IC 74153

Implementation of a Full Adder using 4:1 mux:
The full adder has three inputs and 2 outputs i.e. Sum and Carry. In order to realize full adder 2
multiplexers are required, one for implementation of Sum and another of realization of Carry. The
Sum (Sn) and Carry (Cn) are expressed following Boolean functions:
𝑆𝑢𝑚(𝐴, 𝐵, 𝐶𝑖𝑛 ) = ∑ 𝑚(1,2,4,7)---------1
𝐶𝑎𝑟𝑟𝑦(𝐴, 𝐵, 𝐶𝑖𝑛 ) = ∑ 𝑚(3,5,6,7)-------2

29
The given function has three variables, but 4:1 MUX can have only two select lines, so
one of the variables will be taken at the input. In this case we are taking
𝑪𝒏−𝟏 as 3rd variable that will be connected to input line of MUX. Table “Mux Map for
SUM” and “Mux Map for Carry” helps to identify input data line connections using
equations 1 and 2, wherein bracketed values in the table below indicate values of equation
1 and 2 respectively.
Mux map for Sum
Inputs I0 I1 I2 I3
̅ 𝒏−𝟏
𝑪 0 (2) (4) 6
𝑪𝒏−𝟏 (1) 3 5 (7)
𝑪𝒏−𝟏 ̅ 𝒏−𝟏
𝑪 ̅ 𝒏−𝟏
𝑪 𝑪𝒏−𝟏

Mux map for Carry

Inputs I0 I1 I2 I3
̅ 𝒏−𝟏
𝑪 0 2 4 (6)
𝑪𝒏−𝟏 1 (3) (5) (7)
0→ GND 𝑪𝒏−𝟏 𝑪𝒏−𝟏 1→ Vcc
MUX map for SUM is implemented in A part of MUX IC & MUX map for Carry is
implemented in B part of MUX IC, A & B are select lines as indicated in Figure 3:

Figure 3: Connection diagram of Full Adder using 74153

Implementation of a Full Subtractor using 4:1 mux:
The full subtractor has three inputs and 2 outputs i.e. Difference and Borrow. In order to realize
full subtractor, 2 multiplexers are required, one for implementation of Difference and another of
realization of Borrow. The Difference (Dn) and Borrow (Bn) are expressed following Boolean
functions:
𝐷𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑐𝑒 (𝐴, 𝐵, 𝐵𝑛−1 ) = ∑ 𝑚(1,2,4,7)--------3
𝐵𝑜𝑟𝑟𝑜𝑤(𝐴, 𝐵, 𝐵𝑛−1 ) = ∑ 𝑚(1,2,3,7)--------------4
The given function has three variables, but 4:1 MUX can have only two select lines, so
one of the variables will be taken at the input. In this case we are taking
𝑩𝒏−𝟏 as 3rd variable that will be connected to input line of MUX. Table “Mux Map for
Difference” and “Mux Map for Borrow” helps to identify input data line connections using
equations 1 and 2, wherein bracketed values in the table below indicate values of equation

30
3 and 4 respectively.

Mux map for Difference

Inputs I0 I1 I2 I3
̅
𝑩𝒏−𝟏 0 (2) (4) 6
𝑩𝒏−𝟏 (1) 3 5 (7)
𝑩𝒏−𝟏 ̅ 𝒏−𝟏
𝑩 ̅ 𝒏−𝟏
𝑩 𝑩𝒏−𝟏

MUX map for Borrow

Inputs I0 I1 I2 I3
̅ 𝒏−𝟏
𝑩 0 (2) 4 6
𝑩𝒏−𝟏 (1) (3) 5 (7)
𝑩𝒏−𝟏 1→ Vcc 0→ GND 𝑩𝒏−𝟏
MUX map for Difference is implemented in A part of MUX IC & MUX map for Borrow is
implemented in B part of MUX IC, A & B are select lines as indicated in Figure 4:

Figure 4: Connection diagram of Full Subtractor using 74153

Procedure:
1. Power ON the IC: Connect Vcc to Pin [16] and GND to Pin [8].
2. Enable the IC-74153: Initialize MUX ‘A’ and MUX ‘B ’ by connect i ng EA,
EB t o GND.
3. Select Lines: The inputs ‘A’ and ‘B’ are applied to Pin [2] and input Pin [14]
as select lines, respectively.
4. Data line inputs for FA: Make use of 7404 and create input connections to
MUX-A and MUX-B part of IC-74153 as shown in Figure 3
5. In full adder the outputs Sn and Cn are taken from pins [7] and [9], respectively.
Now, complete the observation Table.
6. Data line inputs for FS: Make use of 7404 and create input connections to
MUX-A and MUX-B part of IC-74153 as shown in Figure 4.
7. In full subtractor the outputs Dn and Bn are taken from pins [7] and [9],

31
 respectively, Now, complete the observation Table.
Precautions:
1. Do not press the IC on breadboard until pins are aligned with pours.
2. Make connection properly.
3. There should not any short circuit in the circuit. Avoid the heating of IC.

Observation Table:
Full Adder Full Subtractor
Inputs Outputs Inputs Outputs
A B Cn-1 Sn Cn A B Bn-1 Dn Bn
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 1 1 1

Worksheet of the student

PIN diagram of IC-74153 with other external connections such as 7404, inputs, outputs

32
Learning Outcomes (Expected):
1. Could differentiate between adder is HA and FA?
2. Able to connect the circuit diagram using breadboard.
3. Understand provision of input carry and Borrow in FA, FS respectively
Learning Outcomes (What I have learnt):

Viva Questions:
1. How many select lines are there in 4:1 mux?
2. How can you implement a function with multiplexer?
3. IC 74153 is which type of the IC?
4. In 74153 what is the purpose of Strobe pin?
5. In 74153 how many multiplexers are present?
6. Which pin is active low pin in 74153 IC.

33
34
 EXPERIMENT No. 6
Aim: Virtual Integration of IR sensor using Arduino.
Learning Objective (s):
1. To write a program code on Arduino for integration of IR sensor
2. To verify the working of the experiment using a circuit simulator.
Instruments/Components Required:

S.No. Items Quantity

1 Arduino Uno 1
2 LED-GREEN (or any color) 1
3 Analog Primitive Resistor (220-ohm) 1
4 Virtual Terminal 1
5 Logic Toggle 1
6 IR Obstacle Sensor 1
7 Battery (Cell) 1

Theory:
An object can be detected with an infrared system consisting of an infrared transmitter
and a receiver. More in detail an IR transmitter, also known as IR LED, sends an infrared
signal with a certain frequency compatible with an IR receiver which has the task to
detect it. There are different kind of IR sensors for different type of application. In this practical,
IR technology is used as a proximity sensor to detect a near object.
IR sensor principle of operation with/without object: The IR transmitter sends an infrared
signal that, in case of a reflecting surface (e.g., white color),
bounces off in some directions including that of the IR receiver that captures the signal detecting
the object. When the surface is absorbent (e.g., black color) the IR signal isn’t reflected and the
object cannot be detected by the sensor. Same result would occur with object absent.
IR transmitter and IR receiver:
The IR transmitter is a particular LED that emits radiation in the frequency range of infrared,
invisible to the naked eye as shown in Figure 1. An infrared LED just works as a simple LED with
a voltage of 3V DC and a current consumption of about 20mA. The IR receiver, such as a
photodiode or a phototransistor, is capable of detect infrared radiation emitted from the IR

35
transmitter. Aesthetically it is similar to a LED but the external capsule can be wrapped by a dark
color film.

Figure 1: working of IR transmitter Receive module

Circuit Diagram for IR sensor connected at pin no 2 and output led connected at pin no 13:

Figure 2: Connection Diagram of the Practical

Program File for IR sensor connected at pin no 2 and output led connected at pin no 13:
void setup() {
pinMode(13, OUTPUT);
pinMode(2, INPUT);
//Serial.begin(9600);

36
}
void loop() {
int SensorValue = digitalRead(2);
//Serial.print("SensorPin Value: ");
//Serial.println(SensorValue);
delay(100);
if (SensorValue==LOW){ // LOW MEANS Object Detected
digitalWrite(13, HIGH);
}
else
{
digitalWrite(13, LOW);
}
}

Procedure:
1. At first, write the program (code) as given above on Arduino Uno 1.8.19. Verify the code
and save it. Secondly, Go to Sketch → export compiled binary, and click on it to get
IR_sensor.ino.standard.hex, and IR_sensor.ino.with_bootloader.standard.hex in your
folder where Arduino program is saved.

2. For circuit simulation, Open simulation window and follow the path: File → Project
Name→ Create a schematic from Templates (Select Default) → Do not create a PCB
layout → No Firmware Project→ Schematic→ Press “finish”.
3. Double click on Arduino board (at simulation window) and place compiled binary files
IR_sensor.ino.standard.hex, and IR_sensor.ino.with_bootloader.standard.hex file at the
location of circuit simulator file.
4. Ensure that following library file are available at a place where circuit simulator file is
saved: “InfraredSensorsTEP.HEX”
5. If files not available as per step 4, then follow path follow path; C:://→ Program files (*86)
→ lab Centre electronics→ professional→ Data→ library → Copy “InfraredSensorsTEP
.HEX” and past at location of circuit simulator file.

37
6. Click on component mode (highlighted in red above) → P icon (highlighted in red) →
search component names as mentioned in “apparatus required” and place components as
per given above diagram with double click on the simulation window.

6.1 Get Arduino Board: Component mode→ P→ Search “Arduino UNO R3 V1.0”
6.2 Get Infrared Sensor: Component mode→ P→ Search “IR Obstacle Sensor”
6.3 Get Toggle Switch: Component mode→ P→ Search “LOGICTOGGLE”
6.4 Get Battery: Component mode→ P→ Search “CELL”→ Battery (single cell). Now edit
the value of battery (right click on the icon) and make it 5V.
6.5 Get Resistance: Component mode→ P→ Search “RESISTORS”→ 1K---10Watt. Now
edit the value of resistance (right click on the icon) and make it 220 ohm.
6.6 Get LED: Component mode→ P→ Search “LED”→ LED-GREEN
6.7 Get Virtual Terminal: Right click on the circuit creation space→ Place→ Virtual
Instrument→ Virtual Terminal.
6.8 Get Ground Terminal: Terminal Mode (as indicated below) and select Ground

7. Now Double click on Arduino board -→ open the folder highlighted in RED→ select the
IR_sensor.ino.standard.hex from circuit simulator file folder → Press “OK”.

38
 8. Repeat the same exercise IR sensor, Double click on IR Sensor → Open program file
folder → select “InfraredSensorsTEP.HEX” from circuit simulator file folder→ press
“OK”
9. Once the circuit diagram is completed as indicated in Figure 2, press the play button
available at bottom left corner of simulation window as shown below (highlighted in red).

Verification of circuit connections

The sensor input is at pin 2 and the output is taken from pin no 13 as per given code. The “glowing
LED” will detect the presence of object in the IR radiation path. On changing logic toggle to 0 &
1, the virtual terminal displays the presence or absence of object indicating communication through
serial port. The virtual terminal is used to display the content of print statements.
Precautions:
1. Carefully write the program to avoid syntax errors.
2. In the circuit simulator, bin files must be called before running the circuit.
Observation Table:
Proteus circuit Arduino Program code

Sensor Arduino Sensor Arduino Observation

I/P O/P I/P O/P
2 13 2 12
2 13 2 13
2 13 3 13

39
Viva Questions:
1. The function which repeatedly executes in the main program is?
2. How many buttons exist for reset and erase in Arduino Due?
3. What is the Importance Virtual terminal and logic toggle switch?

Learning outcomes (Expected)

1. Write a program on Arduino and simulate it
2. Use the Arduino binary file in circuit simulator
3. Learn to use TEP.HEX file in IR sensor module and its significance.
4. Connect other sensors and repeat the practical (home exercise)
Learning outcomes (what I have learnt)
1.

40
 Experiment No.- 7

AIM: Understand JK Flip-Flop and implement T-Flip Flop using NAND circuit of JK Flip Flop.

Learning Objectives:
1. To implement JK flip flop using NAND gates and verify of its functionality.
2. To implement T flip flop using NAND gates and verify its functionality.
Components & Instruments required: IC 7410, 7400, Power supply and LEDs.
Theory:
The logic circuits whose outputs at any instant of time depend not only on the present input but also on
the past outputs are called sequential circuits. The simplest kind of sequential circuit which is capable
of storing one bit of information is called latch. The operation of basic latch can be modified, by
providing an additional control input that determines, when the state of the circuit is to be changed. The
latch with additional control input is called the Flip-Flop. The additional control input is either the clock
or enable input. Flip flop is formed using logic gates. Flip flop are fundamental building blocks in the
memory of electronic devices. Each flip flop can store one bit of data. Based on their operations, flip
flops are basically 4 types. They are
1. S-R flip flop
2. D flip flop
3. J-K flip flop
4. T flip flop
J-K flip-flop: JK flip flop operates on sequential logic principle, where the output is dependent not only on
the current inputs but also on the previous state. There are two inputs in JK Flip Flop Set and Reset denoted
by J and K. It also has two outputs: Output and complement of Output denoted by Q and Q̅. The internal
circuitry of a JK Flip Flop consists of a combination of logic gates, usually NAND gates as shown in Figure
1.
JK flip flop comprises four possible combinations of inputs:
• J=0, K=0: In this state, flip flop retains its preceding state. It neither sets nor resets itself, making it stable.
• J=0, K=1: This input combination forces flip flop to reset, resulting in Q=0 and Q̅=1. It is often referred to
as the “reset” state.
• J=1, K=0: Here, flip flop resides in the set mode, causing Q=1 and Q̅=0. It is known as the “set” state.
• J=1, K=1: This combination toggles flip flop. If the previous state is Q=0, it switches to Q=1 and vice versa.
This makes it valuable for frequency division and data storage applications.

Figure 1: J-K Flip flop using NAND gate, Truth Table (here Qn=Q)

41
 Characteristic Table: Excitation table:

Qn Qn+1 J K
0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0

Characteristic Equation:

=>
T flip-flop: T flip flop or to be precise is known as Toggle Flip Flop because it can able to toggle its output depending
upon on the input. T, here stands for Toggle. Toggle basically indicates that the bit will be flipped i.e., either from 1
to 0 or from 0 to 1. The toggle or T-type flip-flop gets its name from the fact that its two outputs Q and Q invert
from their previous state as it toggles back and forth every time it is triggered (T = 1). That is,
the Q and Q outputs change to a “1” if it was “0”, and “0” if it was previously a “1” but only when the “T” input
changes HIGH, otherwise they do not change. Same is shown in Figure 2

Clk T Qn+1 Operation

0 × Qn Memory
1 0 Qn Memory
1 1 Qn’ Toggle

Figure 2: NAND implementation of T-FF and Truth Table

Characteristic Table: Excitation Table:

Clk T Qn Qn+1
0 × × ×
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

42
 Characteristic equation:

̅̅̅𝑛̅ + 𝑇
Qn+1 = 𝑇𝑄 ̅ 𝑄𝑛 = T xor Qn
Procedure:
1. Make the connections using IC 7400 and 7410 as given below

2. Power on the IC-7410 and 7400 by connecting VCC at pin 14 and GND at PIN 7.
3. Connect the "Clock 1Hz" button or pulse button as a CLK.
4. Apply the inputs as per characteristic table of JK FF and note the outputs in Figure 1, Update
the observation table of JK FF.
5. Verify the practical and theoretical values of JK-FF as per entries in observation table of
JK FF.
6. Similarly repeat step 4 and 5 for T FF of Figure 2.
7. Identify different sources of error in this practical.

IC Diagram of JK-FF using NAND Gates:

43
IC Diagram of T-FF using NAND Gates

Precautions:
1. Do not press the IC on breadboard until pins are aligned with pours.
2. Make connection properly.
3. There should not any short circuit in the circuit. Avoid the heating of IC. Provide
proper clock pulse.

Learning Outcomes:
1. To learn the working of flip flops.
2. To test the IC of gates used.
3. To learn that how the present inputs and previous outputs effects present output.

Viva Questions:
1. What is the function of clock pulse?
2. What do you mean by race around condition?
3. How the race around condition can be removed?
4. How to convert JK to T-FF.

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 Worksheet of the student
Observation Table for J-K Flip Flop
J K Qn Qn+1 (Calculated using Characteristic equation) Q(n+1) (Observed using LED
display of Digital trainer kit)

0 0 0 ̅̅̅𝑛̅ + 𝐾
𝐽𝑄 ̅𝑄𝑛 =0. 0
̅+0
̅ . 0=0.1+1.0=0+0 = 0

0 0 1 ̅̅̅𝑛̅ + 𝐾
𝐽𝑄 ̅𝑄𝑛 =0. 1
̅+0
̅ . 1=0.0+1.1=0+1 = 1

0 1 0 ̅̅̅𝑛̅ + 𝐾
𝐽𝑄 ̅𝑄𝑛 =0. 0
̅+0
̅ . 0=0.1+1.0=0+0 = 0

0 1 1 ̅̅̅𝑛̅ + 𝐾
𝐽𝑄 ̅𝑄𝑛 =0. 1
̅+1
̅ . 1=0.0+0.1=0+0 = 0

1 0 0 ̅̅̅𝑛̅ + 𝐾
𝐽𝑄 ̅𝑄𝑛 =1. 0
̅+0
̅ . 0=1.1+1.0=1+0 = 1

1 0 1 ̅̅̅𝑛̅ + 𝐾
𝐽𝑄 ̅𝑄𝑛 =1. 1
̅+0
̅ . 1=1.0+1.1=0+1 = 1

1 1 0 ̅̅̅𝑛̅ + 𝐾
𝐽𝑄 ̅𝑄𝑛 =1. 0
̅+1
̅ . 0=1.1+0.0=1+0 = 1

1 1 1 ̅̅̅𝑛̅ + 𝐾
𝐽𝑄 ̅𝑄𝑛 =1. 1
̅+1
̅ . 1=1.0+0.1=0+0 = 0

Observation Table for T Flip Flop

T Qn Qn+1 (Calculated using Characteristic equation) Q(n+1) (Observed using LED
display of Digital trainer kit)
0 0 ̅̅̅𝑛̅ + 𝑇
𝑇𝑄 ̅ 𝑄𝑛 = 0. 0
̅+0
̅ . 0=0.1+1.0=0+0 =0

0 1 ̅̅̅𝑛̅ + 𝑇
𝑇𝑄 ̅ 𝑄𝑛 = 0. 1
̅+0
̅ . 1=0.0+1.1=0+1 =1

1 0 ̅̅̅𝑛̅ + 𝑇
𝑇𝑄 ̅ 𝑄𝑛 = 1. 0
̅+1
̅ . 0=1.1+0.0=1+0 =1

1 1 ̅̅̅𝑛̅ + 𝑇
𝑇𝑄 ̅ 𝑄𝑛 = 1. 1
̅+1
̅ . 1=1.0+0.1=0+0 =0

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Learning Outcomes (expected):
1. To implement JK and T-FF on the breadboard
2. To verify JK and T FF.
3. To identify different sources of error in this practical.

Learning Outcomes (what I have learnt?):

46
 Practical No 8
Aim: Implement Decade counter using IC-7490 and seven segment display.

Learning Objective: To use IC-7490 as MOD-2, MOD-5 and MOD-10 counter, and display
IC-7490 output value on 7 segment display through decoder circuit.
Instruments/Components required: IC 7490, IC 7447 Decoder, Seven Segment display,
digital trainer module with 1Hz clock and 5V Power terminal, breadboard.

Theory: A decade counter resets to zero when the output count reaches the decimal value of
9, i.e. when 1001. A counter with a count sequence from binary 0000 through to 1001 is
generally referred as a BCD binary code decimal counter because its ten state sequences ie
0,1,2,3,4,5,6,7,8,9, are Binary Coded Decimal (BCD) Numbers.
The design of the experiment requires three ICs i.e. 7490, 7447 and seven segment display.
The outputs of 7490 acts as input to 7447 (BCD to seven segment decoder). There are 7 output
PIN from 7447 which acts as inputs to seven segment display IC as shown in Figure 1.

Figure 1: Block Diagram of the Experiment

1. IC 7490 BCD Decade Counter: It is a 14 pin IC, which can output the binary numbers
from 0000 to 1001. After 1001 it gets resets and again starts counting from zero, as shown
in Figure 3 & 4. Since, IC 7490 gets reset after counting ten numbers, it is called MOD-
10 or Decade Counter. This IC takes 10 clock pulses to generates BCD code
corresponding to each clock pulse. The outputs QA, QB, QC and QD are four bits of the
BCD code.

Figure 2: PIN diagram of IC-7490

The IC 7490 consists of MOD-2 and MOD-5 counters. MoD-2 counter has output QA and
MOD-5 counter has output QD, QC and QB (QD is MSB and QB is LSB of MOD-5 counter).
Count sequence of MOD-5 counter is 0→1→2→3→4→0 and so on. The count sequence of
MOD-2 counter is 0→1→0 and so on. It should be noted that external CLK signal is applied
at MOD-2 counter and its output QA acts as clock for MOD-5 counter. This is shown in Figure
7. The state diagram for decade counter is as:

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 Figure 3: State diagram of MoD-10 Counter

Truth table of Decade Counter

Clock Output Bit Pattern for IC - Output of decade counter in decimal
Count 7490 value
QD Qc QB QA
1 0 0 0 0 0
2 0 0 0 1 1
3 0 0 1 0 2
4 0 0 1 1 3
5 0 1 0 0 4
6 0 1 0 1 5
7 0 1 1 0 6
8 0 1 1 1 7
9 1 0 0 0 8
10 1 0 0 1 9
Figure 4: Truth table of Decade Counter

2. IC 7447 BCD to seven segment decoder/driver IC: It is a 16 pin IC, which accepts a
binary coded decimal as input and converts it into a pattern to drive a seven-segment for
displaying digits 0 to 9. BCD is an encoding method in which each digit of a number is
represented by its own binary sequence (usually of four bits). It accepts four lines of BCD
(8421) input data and generates their complements internally. The outputs correspond to
common anode (CA) configuration of seven segment as shown in Figure 5.

Figure 5: PIN diagram of IC-7447 and 7 segment display

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Truth table and internal circuit of IC-7447:

K-Map Simplification

The below figures show the k-map simplification for the common cathode seven-segment
decoder in order to design the combinational circuit.

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 3. Seven Segment Display: Seven segment displays are 10 pin output display device that
provides a way to display information in the form of images or text or decimal numbers,
which is an alternative to the more complex dot matrix displays. It is widely used in digital
clocks, basic calculators, electronic meters, and other electronic devices that displays
numerical information. It consists of seven segments of light-emitting diodes (LEDs),
which are assembled like numerical 8. According to the type of application, there are two
types of configurations of seven-segment displays: common anode display and common
cathode display as shown in Figure 6.
In common cathode seven segment displays, all the cathode connections of LED segments
are connected together to logic 0 or ground. We use logic 1 through a current limiting
resistor to forward bias the individual anode terminals a to g (we may also connect without
using a resistance). Whereas all the anode connections of the LED segments are connected
together to logic 1 in a common anode seven segment display. We use logic 0 through a
current limiting resistor to the cathode of a particular segment a to g (we may also connect
without using a resistance).

Common anode seven segment display Common cathode seven segment display
(LED will glow with input LOW) (LED will glow with input HIGH)

Figure 6: Common Anode, Common Cathode Display

7 Procedure:

7.1 Power On the ICs: IC-7490: PIN 5 to Vcc and PIN 10 to GND, IC-7447: PIN 15 to
Vcc and PIN 8, 7-Segment display: PIN 8 and or 3 to Vcc through a resistance to
provide less than 5V to power on display IC.
7.2 Connection diagram: - The output of IC-7490 is connected to IC7447 decoder and
decoder output to 7-segment display unit. Make the connections as shown in Figure 7,
as per case-2 of observation table.
7.3 Case-1 of Observation table:
7.3.1 Master CLK of 1Hz taken from Trainer module is connected at PIN -14 of IC-
7490.
7.3.2 PIN-12 is not connected to PIN-1 of IC-7490
7.4 Case-2 of Observation table:
7.4.1 Master CLK of 1Hz taken from Trainer module is connected at PIN -14 of IC-
7490.

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 7.4.2 PIN-12 is connected to PIN-1 of IC-7490.
7.5 Case-3 of Observation table:
7.5.1 Master CLK of 1Hz taken from Trainer module is not connected at PIN -14 of IC-
7490.
7.5.2 PIN-12 is not connected to PIN-1 of IC-7490
7.5.3 Master CLK of 1Hz taken from Trainer module is connected at PIN -1 of IC-7490
Observation Table
Sr No Changes in connection diagram of Figure 7 Expected Observed
sequence Sequence
1) Master CLK of 1Hz taken from Trainer module
is connected at PIN -14 of IC-7490 and 0→ 1→0
Case: 1 2) PIN-12 is not connected to PIN-1 of IC-7490
1) Master CLK of 1Hz taken from Trainer module
Case: 2 is connected at PIN -14 of IC-7490 and 0→1→2→3→4
2) PIN-12 is connected to PIN-1 of IC-7490 →5→6→7→8
→9→0
1) Master CLK of 1Hz taken from Trainer module
Case: 3 is not connected at PIN -14 of IC-7490 and 0→1→2→3→4
2) PIN-12 is not connected to PIN-1 of IC-7490 →0
3) Master CLK of 1Hz taken from Trainer module
is connected at PIN -1 of IC-7490

Figure 7: Connection diagram as per CASE-2

8 Precautions:
8.1 Do not press the IC on breadboard until pins are aligned with pours.
8.2 Make connection properly.
8.3 There should not any short circuit in the circuit.
8.4 Avoid the heating of IC.
8.5 Provide proper clock pulse.

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9 Viva Questions:
9.1Which type of seven segment display IC is used in this experiment?
9.2What should be the value of a, b, c, d, e, f and g, if we have to display 6?
9.3What do you understand by MOD-10 counter?

10. Learning Outcomes (expected):

10.1 Connect the circuit diagram using breadboard, and Digital Trainer module.
10.2 Use IC7490 as MoD-2. MoD-5 and MoD-10 Counter.
10.3 Identify Common anode and common cathode display.
10.4 Identify faults in the connection diagram.

11. Learning Outcomes (What I have learnt):

IC Connection Diagram:

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